Active region structure and method for forming the active region structure

Abstract

The present disclosure provides an active region structure and a method for forming the active region structure. The active region structure includes an active region disposed on the active layer. Among them, the active region is a closed structure, and the active region includes a plurality of first active lines arranged at intervals along a preset direction, second active lines spaced apart from and alternating with the first active lines, a first closed boundary, and a second closed boundary. Both ends of the first active line intersect with the first closed boundary. The first active line includes a plurality of first device units arranged at intervals, the second active line includes a plurality of second device units arranged at intervals, and the first device units and the second device units are arranged alternately. This structure can balance the stress between the active device units and their boundaries, preventing the device units from being damaged due to uneven stress. Moreover, the second closed boundary is formed simultaneously with the device units, which can reduce the number of mask plates, simplify the process flow, and reduce costs.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and particularly to an active region structure and a method for forming the active region structure. Background Art

[0002] In recent years, for the design of electronic products, they generally have multifunctional and fast processing capabilities. To increase the processing power, for example, a computer system or a multifunctional electronic product, it requires a large-capacity dynamic random access memory (DRAM). In order to increase the memory capacity, the size of the memory cells of the memory needs to be reduced. However, after the size of the memory cells is greatly reduced, other problems will be caused, making the operation of the memory cells unstable or damaged, especially the device damage caused by the uneven stress between the active device cells and their boundaries.

[0003] In the preparation process of existing semiconductor devices, the active layer units (device units) are usually defined on the substrate and used as the basis for forming the required device structures thereon. Taking the memory cells of DRAM as an example, multiple memory cells are regularly arranged in a predetermined device area to form an array (active region), and the device units finally form the memory cells. In addition, for the memory cells that can work, some peripheral circuits are arranged around the memory cells to control the memory cells. The peripheral circuits are also formed based on the peripheral active regions, but usually the peripheral circuits are different from the device active region where the device units are located, and the peripheral circuits are formed separately by photolithography etching, which makes the entire preparation process complicated, difficult, and increases the preparation cost. Summary of the Invention

[0004] In view of the above problems, the present disclosure provides an active region structure and a method for forming the active region structure, which solve the technical problems of device damage caused by uneven stress between the active device cells and their boundaries in the prior art, and the complication, high difficulty, and increased cost of the preparation process caused by separate etching of the device active region and the peripheral circuits.

[0005] In a first aspect, the present disclosure provides an active region structure, including:

[0006] A semiconductor substrate;

[0007] An active layer located above the substrate;

[0008] An active region disposed on the active layer;

[0009] Wherein, the active region is a closed structure, and the active region includes a plurality of first active lines arranged at intervals along a preset direction, second active lines spaced from and alternating with the first active lines, a first closed boundary surrounding all the first active lines and the second active lines, and a second closed boundary surrounding the periphery of the first closed boundary; both ends of the first active line intersect with the first closed boundary, and the second active line does not contact the first closed boundary; the first active line includes a plurality of first device units arranged at intervals, the second active line includes a plurality of second device units arranged at intervals, and the first device units and the second device units are arranged in an interleaved manner.

[0010] According to an embodiment of the present disclosure, preferably, both ends of the first active line extend beyond the range of the first closed boundary.

[0011] According to an embodiment of the present disclosure, preferably,

[0012] The first device unit close to the first closed boundary intersects with the first closed boundary;

[0013] The second device unit does not contact the first closed boundary.

[0014] According to an embodiment of the present disclosure, preferably, the lengths of all the first device units intersecting with the first closed boundary are different.

[0015] According to an embodiment of the present disclosure, preferably, each device unit is isolated by a first shallow trench, and the first closed boundary and the second closed boundary are isolated by a second shallow trench.

[0016] According to an embodiment of the present disclosure, preferably, the line width of the first active line is the same as the line width of the second active line.

[0017] In a second aspect, the present disclosure provides a method for forming an active region structure, including:

[0018] Providing a semiconductor substrate and forming an active layer above the substrate;

[0019] Forming a sacrificial layer above the active layer and performing a patterning process on the sacrificial layer to form a sacrificial layer pattern above the active layer; wherein, the sacrificial layer pattern includes a plurality of spaced-apart separation pattern units along a preset direction, and a closed first boundary pattern unit surrounding all the separation pattern units, and both ends of the separation pattern unit intersect with the first boundary pattern unit;

[0020] Forming spacers on the sidewalls of each pattern unit of the sacrificial layer pattern;

[0021] Fill the space between the spacers to form a filling layer covering the sacrificial layer pattern, and remove the spacers in the filling layer to form a filling layer pattern above the active layer; wherein, the filling layer pattern includes filling pattern units spaced and alternating with the separation pattern units, and a closed second boundary pattern unit surrounding the periphery of the first boundary pattern unit, and the filling pattern units do not contact the first boundary pattern unit;

[0022] Pattern the separation pattern units and the filling pattern units to obtain the patterned separation pattern units and the filling pattern units;

[0023] Using the first boundary pattern unit, the second boundary pattern unit, the patterned separation pattern units and the filling pattern units as etching masks, etch the active layer to form a plurality of first active lines arranged at intervals along the preset direction, second active lines spaced and alternating with the first active lines, a first closed boundary surrounding all the first active lines and the second active lines, and a second closed boundary surrounding the periphery of the first closed boundary on the active layer, thereby forming an active region;

[0024] Wherein, both ends of the first active line intersect with the first closed boundary, and the second active line does not contact the first closed boundary; the first active line includes a plurality of first device units arranged at intervals, the second active line includes a plurality of second device units arranged at intervals, and the first device units and the second device units are arranged alternately.

[0025] According to an embodiment of the present disclosure, preferably,

[0026] The separation pattern units extend beyond the range of the first boundary pattern unit;

[0027] Both ends of the first active line extend beyond the range of the first closed boundary.

[0028] According to an embodiment of the present disclosure, preferably,

[0029] The first device units close to the first closed boundary intersect with the first closed boundary;

[0030] The second device units do not contact the first closed boundary.

[0031] According to an embodiment of the present disclosure, preferably, the lengths of all the first device units intersecting with the first closed boundary are different.

[0032] According to an embodiment of the present disclosure, preferably, the second boundary pattern unit does not contact the first boundary pattern unit.

[0033] According to an embodiment of the present disclosure, preferably, each device unit is isolated by a first shallow trench isolation, and the first closed boundary and the second closed boundary are isolated by a second shallow trench isolation.

[0034] According to an embodiment of the present disclosure, preferably, the line widths of the separation pattern unit and the filling pattern unit are the same.

[0035] According to an embodiment of the present disclosure, preferably, patterning the separation pattern unit and the filling pattern unit to obtain the patterned separation pattern unit and filling pattern unit includes the following steps:

[0036] Form a photoresist layer over the sacrificial layer pattern and the filling layer pattern;

[0037] Pattern the photoresist layer through a mask to form a photoresist pattern over the sacrificial layer pattern and the filling layer pattern; wherein, the photoresist pattern includes a third boundary pattern unit covering the first boundary pattern unit, a fourth boundary pattern unit covering the second boundary pattern unit, a plurality of first device pattern units arranged at intervals above the separation pattern unit, and a plurality of second device pattern units arranged at intervals above the filling pattern unit, and the first device pattern units and the second device pattern units are staggered;

[0038] Using the photoresist pattern as a mask, etch the separation pattern unit and the filling pattern unit to truncate the separation pattern unit into a plurality of third device pattern units arranged at intervals, and truncate the filling pattern unit into a plurality of fourth device pattern units arranged at intervals, so as to obtain the patterned separation pattern unit and filling pattern unit; wherein, the third device pattern units and the fourth device pattern units are staggered;

[0039] Remove the photoresist pattern.

[0040] According to an embodiment of the present disclosure, preferably, the third device pattern unit close to the first boundary pattern unit intersects with the first boundary pattern unit.

[0041] According to an embodiment of the present disclosure, preferably, using the first boundary pattern unit, the second boundary pattern unit, the patterned separation pattern unit, and the filling pattern unit as an etching mask, the active layer is etched to form a plurality of first active lines arranged at intervals along the preset direction, second active lines spaced apart from and alternating with the first active lines, a first closed boundary surrounding all the first active lines and the second active lines, and a second closed boundary surrounding the outer periphery of the first closed boundary on the active layer, thereby forming an active region, including the following steps:

[0042] Using the first boundary pattern unit, the second boundary pattern unit, the third device pattern unit, and the fourth device pattern unit as an etching mask, the active layer is etched to form a plurality of first active lines arranged at intervals along the preset direction, second active lines spaced apart from and alternating with the first active lines, a first closed boundary surrounding all the first active lines and the second active lines, and a second closed boundary surrounding the outer periphery of the first closed boundary on the active layer, thereby forming an active region.

[0043] Compared with the prior art, one or more embodiments in the above solution may have the following advantages or beneficial effects:

[0044] The present disclosure provides an active region structure and a method for forming the active region structure. The active region structure includes an active region disposed on the active layer. Wherein, the active region is a closed structure, and the active region includes a plurality of first active lines arranged at intervals along a preset direction, second active lines spaced apart from and alternating with the first active lines, a first closed boundary surrounding all the first active lines and the second active lines, and a second closed boundary surrounding the outer periphery of the first closed boundary. The second closed boundary does not contact the first closed boundary, both ends of the first active line intersect with the first closed boundary, and the second active line does not contact the first closed boundary. The first active line includes a plurality of first device units arranged at intervals, the second active line includes a plurality of second device units arranged at intervals, and the first device units and the second device units are arranged in an interleaved manner. This structure can balance the stress between the active device units and their boundaries, preventing the device units from being damaged due to uneven stress. And the second closed boundary is used to form the peripheral region, and the second closed boundary and the device units are formed simultaneously, which can reduce the number of mask plates, simplify the process flow, and reduce costs. Description of the Drawings

[0045] The drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. They are used to explain the present disclosure together with the following specific embodiments, but do not constitute a limitation to the present disclosure. In the drawings:

[0046] Figure 1 is a front top view schematic diagram of an active region structure shown in an exemplary embodiment of the present disclosure;

[0047] Figure 2 is a cross-sectional structure schematic diagram of an active region structure shown in an exemplary embodiment of the present disclosure;

[0048] Figure 3 is a front top view schematic diagram of another active region structure shown in an exemplary embodiment of the present disclosure;

[0049] Figure 4 is a schematic flow diagram of a method for forming an active region structure shown in an exemplary embodiment of the present disclosure;

[0050] Figures 5 - 17 are a front top view schematic diagram and a cross-sectional structure schematic diagram formed by related steps of a method for forming an active region structure shown in an exemplary embodiment of the present disclosure;

[0051] Figure 18 is a front top view schematic diagram formed by related steps of another method for forming an active region structure shown in an exemplary embodiment of the present disclosure;

[0052] In the drawings, like reference numerals are used for like components, and the drawings are not drawn to actual scale.

[0053] 101 - Substrate; 102 - Active layer; 1021 - First device unit; 1022 - Second device unit; 1023 - First closed boundary; 1024 - Second closed boundary; 103 - First shallow trench; 104 - Second shallow trench; 105 - Sacrificial layer pattern; 1051 - Separation pattern unit; 1052 - First boundary pattern unit; 1053 - Third device pattern unit; 106 - Spacer; 107 - Filling layer; 108 - Filling layer pattern; 1081 - Filling pattern unit; 1082 - Second boundary pattern unit; 1083 - Fourth device pattern unit. Detailed implementation manners

[0054] The following will describe in detail the implementation manners of the present disclosure in conjunction with the drawings and embodiments, so as to fully understand how the present disclosure uses technical means to solve technical problems and the implementation process of achieving corresponding technical effects and implement accordingly. The embodiments of the present disclosure and each feature in the embodiments can be combined with each other on the premise of not conflicting, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0055] It should be understood that although terms such as "first", "second", "third", etc. may be used to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be denoted as a second element, component, region, layer, or section without departing from the teachings of the present disclosure.

[0056] It should be understood that spatial relationship terms such as "above", "on top of", "below", "beneath", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0057] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0058] Embodiments of the present disclosure are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions shown herein but include shape deviations due to, for example, manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic in nature, and their shapes are not intended to show the actual shape of regions of the device and are not intended to limit the scope of the present disclosure.

[0059] To thoroughly understand the present disclosure, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0060] Example 1

[0061] As Figure 1 and 2 shown, an active region structure is provided in an embodiment of the present disclosure, including a semiconductor substrate 101, an active layer 102, and an active region (not labeled in the figure).

[0062] The substrate 101 may include at least one of, for example, a single crystal silicon substrate and a silicon epitaxial layer.

[0063] The active layer 102 is located above the substrate 101. The material of the active layer 102 includes at least one of silicon oxide, silicon nitride, and silicon.

[0064] The active region (not labeled in the figure) is disposed on the active layer 102. The active region is a closed structure, and the active region includes a first active line (not labeled in the figure, i.e., the active line where the first device unit 1021 is located), a second active line (not labeled in the figure, i.e., the active line where the second device unit 1022 is located), a first closed boundary 1023, and a second closed boundary 1024.

[0065] A number of first active lines along a preset direction are spaced apart on the active layer 102. The first active line includes a number of spaced-apart first device units 1021, that is, each first active line is truncated into a number of spaced-apart first device units 1021.

[0066] A number of second active lines along a preset direction are spaced apart on the active layer 102 (i.e., the direction of the second active line is the same as that of the first active line). The second active line is spaced and alternating with the first active line, and the line width of the first active line is the same as that of the second active line. The second active line includes a number of spaced-apart second device units 1022, that is, each second active line is truncated into a number of spaced-apart second device units 1022. The first device unit 1021 and the second device unit 1022 are staggered, and this structure is more conducive to the realization of the electrical performance of the device.

[0067] The first closed boundary 1023 surrounds all the first active lines and the second active lines. Both ends of the first active line intersect with the first closed boundary 1023, and the second active line does not contact the first closed boundary 1023. That is, the first device unit 1021 close to the first closed boundary 1023 intersects with the first closed boundary 1023, and all the second device units 1022 do not contact the first closed boundary 1023.

[0068] In this embodiment, both ends of the first active line intersect with the first closed boundary 1023, but neither end of the first active line extends beyond the range of the first closed boundary 1023. This structure can balance the stress between the active device unit and its boundary, preventing the device unit from being damaged due to uneven stress.

[0069] The lengths of all the first device units 1021 (all the first device units 1021 close to the first closed boundary 1023) intersecting with the first closed boundary 1023 are different, and this structure can make the stress between the device unit and its boundary more balanced.

[0070] The second closed boundary 1024 surrounds the periphery of the first closed boundary 1023. The second closed boundary 1024 does not contact the first closed boundary 1023, and the second active line does not contact the first closed boundary 1023. That is to say, all the first device units 1021 and the second device units 1022 do not contact the second closed boundary 1024. The second closed boundary 1024 is used to form an external circuit, and this external circuit does not contact the first closed boundary 1023, the first device units 1021, and the second device units 1022.

[0071] Between each device unit (including between the first device units 1021, between the second device units 1022, and between the first device units 1021 and the second device units 1022), it is isolated by the first shallow trench 103 (Shallow Trench Isolation, STI), and between the first closed boundary 1023 and the second closed boundary 1024, it is isolated by the second shallow trench 104.

[0072] Isolation structures such as insulating layers can be provided in the first shallow trench 103 and the second shallow trench 104.

[0073] The present disclosure provides an active region structure, which includes an active region disposed on the active layer 102; wherein, the active region is a closed structure, and the active region includes a plurality of first active lines arranged at intervals along a preset direction, second active lines spaced and alternating with the first active lines, a first closed boundary 1023 surrounding all the first active lines and the second active lines, and a second closed boundary 1024 surrounding the periphery of the first closed boundary 1023; the second closed boundary 1024 does not contact the first closed boundary 1023, both ends of the first active line intersect with the first closed boundary 1023, and the second active line does not contact the first closed boundary 1023; the first active line includes a plurality of first device units 1021 arranged at intervals, the second active line includes a plurality of second device units 1022 arranged at intervals, and the first device units 1021 and the second device units 1022 are arranged alternately. This structure can balance the stress between the active device unit and its boundary, preventing the device unit from being damaged due to uneven stress.

[0074] Example 2

[0075] like Figure 3 As shown, the embodiment of the present disclosure provides another active region structure, including a semiconductor substrate 101, an active layer 102 and an active region (not marked in the figure).

[0076] The substrate 101 may include, for example, at least one of a single crystal silicon substrate and a silicon epitaxial layer.

[0077] The active layer 102 is located above the substrate 101. The material of the active layer 102 includes at least one of silicon oxide, silicon nitride, and silicon.

[0078] The active region (not marked in the figure) is disposed on the active layer 102. The active region is a closed structure, and includes a first active line (not marked in the figure, i.e., an active line where the first device unit 1021 is located), a second active line (not marked in the figure, i.e., an active line where the second device unit 1022 is located), a first closed boundary 1023 and a second closed boundary 1024.

[0079] A plurality of first active lines are arranged at intervals on the active layer 102 along a preset direction. The first active lines include a plurality of first device units 1021 arranged at intervals. That is, each first active line is cut into a plurality of first device units 1021 arranged at intervals.

[0080] A plurality of second active lines along a preset direction are arranged at intervals on the active layer 102 (i.e., the direction of the second active lines is consistent with that of the first active lines), the second active lines are spaced and alternate with the first active lines, and the line width of the first active lines is the same as that of the second active lines. The second active lines include a plurality of second device units 1022 arranged at intervals, i.e., each second active line is cut into a plurality of second device units 1022 arranged at intervals. The first device units 1021 and the second device units 1022 are arranged alternately, and this structure is more conducive to the realization of the electrical performance of the device.

[0081] The first closed boundary 1023 is arranged around all the first active lines and the second active lines, both ends of the first active lines intersect with the first closed boundary 1023, and the second active lines do not contact with the first closed boundary 1023. That is, the first device unit 1021 close to the first closed boundary 1023 intersects with the first closed boundary 1023, and all the second device units 1022 do not contact with the first closed boundary 1023.

[0082] In this embodiment, both ends of the first active line intersect with the first closed boundary 1023, and both ends of the first active line extend beyond the scope of the first closed boundary 1023, but both ends of the first active line do not contact the second closed boundary 1024. This structure can balance the stress between the active device unit and its boundary, prevent the device unit from being damaged due to uneven stress, and in particular, can compensate for the uneven stress at the ends of the first active line, further avoiding the damage of the device unit.

[0083] The lengths of all the first device units 1021 (all the first device units 1021 close to the first closed boundary 1023) intersecting with the first closed boundary 1023 are different, and this structure can make the stress between the device unit and its boundary more balanced.

[0084] The second closed boundary 1024 surrounds the first closed boundary 1023, the second closed boundary 1024 does not contact the first closed boundary 1023, and the second active line does not contact the first closed boundary 1023. That is to say, all the first device units 1021 and the second device units 1022 do not contact the second closed boundary 1024. The second closed boundary 1024 is used to form a peripheral circuit, and this peripheral circuit does not contact the first closed boundary 1023, the first device units 1021, and the second device units 1022.

[0085] Between each device unit (including between the first device units 1021, between the second device units 1022, and between the first device units 1021 and the second device units 1022), it is isolated by the first shallow trench 103, and between the first closed boundary 1023 and the second closed boundary 1024, it is isolated by the second shallow trench 104.

[0086] Insulating layers and other isolation structures can be arranged in the first shallow trench 103 and the second shallow trench 104.

[0087] The present disclosure provides an active region structure, which includes an active region disposed on an active layer 102; wherein, the active region is a closed structure, and the active region includes a plurality of first active lines arranged at intervals along a preset direction, second active lines spaced apart from and alternating with the first active lines, a first closed boundary 1023 surrounding all the first active lines and the second active lines, and a second closed boundary 1024 surrounding the periphery of the first closed boundary 1023; the second closed boundary 1024 does not contact the first closed boundary 1023, both ends of the first active line intersect with the first closed boundary 1023, and the second active line does not contact the first closed boundary 1023; the first active line includes a plurality of first device units 1021 arranged at intervals, the second active line includes a plurality of second device units 1022 arranged at intervals, and the first device units 1021 and the second device units 1022 are arranged in an interleaved manner. This structure can block the stress generated by the peripheral region on the device units and prevent the device units from being damaged due to stress.

[0088] Example 3

[0089] Based on Embodiment 1, this embodiment provides a method for forming an active region structure. Figure 4 FIG. is a schematic flowchart of a method for forming an active region structure shown in an embodiment of the present disclosure. Figures 5 - 17 FIGS. are a front top view and a cross-sectional structure view formed by related steps of a method for forming an active region structure shown in an embodiment of the present disclosure. Next, with reference to Figure 4 and Figures 5 - 17 the detailed steps of an exemplary method for forming an active region structure proposed in an embodiment of the present disclosure will be described.

[0090] As Figure 4 shown, the method for forming an active region structure in this embodiment includes the following steps:

[0091] Step S101: Provide a semiconductor substrate 101 and form an active layer 102 above the substrate 101.

[0092] The substrate 101 may include at least one of, for example, a single crystal silicon substrate and a silicon epitaxial layer. The material of the active layer 102 includes at least one of silicon oxide, silicon nitride, and silicon.

[0093] Step S102: As Figure 5 and 6As shown, a sacrificial layer (not labeled in the figure) is formed above the active layer 102, and the sacrificial layer is patterned to form a sacrificial layer pattern 105 above the active layer 102. Among them, the sacrificial layer pattern 105 includes a plurality of spaced-apart partition pattern units 1051 along a preset direction, and a closed first boundary pattern unit 1052 surrounding all the partition pattern units 1051. Both ends of the partition pattern unit 1051 intersect with the first boundary pattern unit 1052.

[0094] The material of the sacrificial layer includes at least one of silicon oxide, silicon oxynitride, polysilicon, and amorphous carbon. The sacrificial layer serves as an auxiliary film layer in subsequent processes, is used to form device units and closed boundaries, and is removed after formation.

[0095] In this embodiment, both ends of the partition pattern unit 1051 intersect with the first boundary pattern unit 1052, but do not extend beyond the range of the first boundary pattern unit 1052.

[0096] Specifically, step S102 includes the following steps:

[0097] S102a: A first photoresist layer (not shown in the figure) is formed above the sacrificial layer (not labeled in the figure);

[0098] S102b: The first photoresist layer (not shown in the figure) is patterned through a first mask (not shown in the figure) to form a photoresist pattern (not shown in the figure);

[0099] S102c: The sacrificial layer (not labeled in the figure) is etched through the photoresist pattern (not shown in the figure) to form a sacrificial layer pattern 105 above the active layer 102;

[0100] S102d: The photoresist pattern is removed.

[0101] Step S103: As Figure 7 and 8 shown, spacers 106 are formed on the sidewalls of each pattern unit of the sacrificial layer pattern 105.

[0102] Specifically, step S103 includes the following steps:

[0103] S103a: An oxide layer (not labeled in the figure) is formed above and on the sidewalls of each pattern unit of the sacrificial layer pattern 105 by atomic layer deposition;

[0104] S103b: An etch-back process is performed on the oxide layer (not labeled in the figure) to form spacers 106 on the sidewalls of each pattern unit of the sacrificial layer pattern 105.

[0105] The oxide layer prepared by the atomic layer deposition method has good step coverage and can completely cover each pattern unit of the sacrificial layer pattern 105.

[0106] The oxide layer can have an etching selectivity with respect to the sacrificial layer, and thus can have an etching rate faster than that of the sacrificial layer pattern 105. Therefore, after the etch-back process, only the portions of the oxide layer located on the sidewalls of each pattern unit of the sacrificial layer pattern 105, i.e., the spacers 106, remain. The etch-back process can include: a dry etch process, a chemical mechanical polishing (CMP) process, or a wet stripping process. And in the etch-back process, the oxide layer above each pattern unit of the sacrificial layer pattern 105 is removed to expose the upper surface of each pattern unit.

[0107] The oxide layer material can be formed of silicon oxide, silicon oxynitride, or silicon nitride.

[0108] Step S104: As Figure 9 and 10 shown, the space between the spacers 106 is filled to form a filling layer 107 covering the sacrificial layer pattern 105. As Figure 11 and 12 shown, the spacers 106 in the filling layer 107 are removed to form a filling layer pattern 108 above the active layer 102. Among them, the filling layer pattern 108 includes filling pattern units 1081 spaced apart and alternating with the separation pattern units 1051, and a closed second boundary pattern unit 1082 surrounding the periphery of the first boundary pattern unit 1052. The filling pattern units 1081 do not contact the first boundary pattern unit 1052.

[0109] Among them, the first boundary pattern unit 1052 does not contact the second boundary pattern unit 1082, and the thickness of the filling layer 107 is less than or equal to the thickness of the sacrificial layer pattern 105 and the spacers 106. The filling layer 107 fills the gaps between the spacers 106 and exposes the tops of the sacrificial layer pattern 105 and the spacers 106. Then, by removing the spacers 106, a number of filling pattern units 1081 spaced apart and alternating with the separation pattern units 1051 can be formed.

[0110] The material of the filling layer 107 can be the same as that of the sacrificial layer. The line width of the separation pattern units 1051 is the same as the line width of the filling pattern units 1081 to form a fine pattern with a consistent line width.

[0111] Step S105: As Figure 13 and 14 shown, the separation pattern units 1051 and the filling pattern units 1081 are patterned to obtain the patterned separation pattern units 1051 and filling pattern units 1081.

[0112] The material of the mask layer is photoresist, and step S105 includes the following steps:

[0113] S105a: Form a photoresist layer (not shown in the figure) above the sacrificial layer pattern 105 and the filling layer pattern 108;

[0114] S105b: Pattern the photoresist layer through a mask plate to form a photoresist pattern (not shown in the figure) above the sacrificial layer pattern 105 and the filling layer pattern 108; wherein, the photoresist pattern includes a third boundary pattern unit (not shown in the figure) covering the first boundary pattern unit 1052, a fourth boundary pattern unit (not shown in the figure) covering the second boundary pattern unit 1082, a plurality of first device pattern units (not shown in the figure) arranged at intervals above the partition pattern unit 1051, and a plurality of second device pattern units (not shown in the figure) arranged at intervals above the filling pattern unit 1081, and the first device pattern units and the second device pattern units are arranged in an interleaved manner;

[0115] S105c: Use the photoresist pattern as a mask to etch the partition pattern unit 1051 and the filling pattern unit 1081, so as to truncate the partition pattern unit 1051 into a plurality of third device pattern units 1053 arranged at intervals, and truncate the filling pattern unit 1081 into a plurality of fourth device pattern units 1083 arranged at intervals, thereby obtaining the patterned partition pattern unit 1051 and filling pattern unit 1081; wherein, the third device pattern units 1053 and the fourth device pattern units 1083 are arranged in an interleaved manner;

[0116] S105d: Remove the photoresist pattern.

[0117] Among them, the third device pattern unit 1053 close to the first boundary pattern unit 1052 intersects with the first boundary pattern unit 1052, and the lengths of all the third device pattern units 1053 (all the third device pattern units 1053 close to the first boundary pattern unit 1052) intersecting with the first boundary pattern unit 1052 are different. This structure can make the subsequently formed device units intersect with the corresponding closed boundaries, and can balance the stress between the active device units and their boundaries, preventing the device units from being damaged due to uneven stress.

[0118] Step S106: As Figures 15 - 17As shown, using the first boundary pattern unit 1052, the second boundary pattern unit 1082, the patterned separation pattern unit 1051, and the fill pattern unit 1081 as etching masks, the active layer 102 is etched to form a plurality of first active lines (not labeled in the figure) arranged at intervals along a preset direction, second active lines (not labeled in the figure) spaced from and alternating with the first active lines, a first closed boundary 1023 surrounding all the first and second active lines, and a second closed boundary 1024 surrounding the periphery of the first closed boundary 1023 on the active layer 102, thereby forming an active region. The two ends of each first active line intersect with the first closed boundary 1023, and the second active lines do not contact the first closed boundary 1023. The first active lines include a plurality of first device units 1021 arranged at intervals, the second active lines include a plurality of second device units 1022 arranged at intervals, and the first device units 1021 and the second device units 1022 are arranged in an interleaved manner.

[0119] The first device units 1021 close to the first closed boundary 1023 intersect with the first closed boundary 1023, and the second device units 1022 do not contact the first closed boundary 1023. The lengths of all the first device units 1021 (all the first device units 1021 close to the first closed boundary 1023) that intersect with the first closed boundary 1023 are different. This structure can make the stress between the device units and their boundaries more balanced and prevent the device units from being damaged due to uneven stress.

[0120] The first closed boundary 1023 does not contact the second closed boundary 1024. Each device unit (including between the first device units 1021, between the second device units 1022, and between the first device units 1021 and the second device units 1022) is isolated by a first shallow trench 103, and the first closed boundary 1023 and the second closed boundary 1024 are isolated by a second shallow trench 104.

[0121] The first device units 1021 and the second device units 1022 are arranged in an interleaved manner, and this structure is more conducive to the realization of the electrical performance of the device.

[0122] Step S106 specifically includes the following steps:

[0123] Using the first boundary pattern unit 1052, the second boundary pattern unit 1082, the third device pattern unit 1053, and the fourth device pattern unit 1083 as etching masks, the active layer 102 is etched to form a plurality of first active lines arranged at intervals along a preset direction, second active lines spaced from and alternating with the first active lines, a first closed boundary 1023 surrounding all the first and second active lines, and a second closed boundary 1024 surrounding the periphery of the first closed boundary 1023 on the active layer 102, thereby forming an active region (not labeled in the figure).

[0124] This structure can balance the stress between the active device unit and its boundary, preventing the device unit from being damaged due to uneven stress.

[0125] The present disclosure provides a method for forming an active region structure. The second closed boundary 1024 is formed simultaneously with the device unit. The second closed boundary 1024 is used to form the peripheral region, which can reduce the number of masks, simplify the process flow, and reduce costs.

[0126] Example 4

[0127] Based on Embodiment 2, the present embodiment provides a method for forming an active region structure. Figure 18 It is a front top view schematic diagram formed by the relevant steps of another method for forming an active region structure shown in the embodiments of the present disclosure.

[0128] In this embodiment, except for step S102, the other steps are the same as those in Embodiment 3. The steps of step S102 are as follows: As Figure 18 shown, a sacrificial layer is formed above the active layer 102, and the sacrificial layer is patterned to form a sacrificial layer pattern 105 above the active layer 102. The sacrificial layer pattern 105 includes a plurality of spaced-apart partition pattern units 1051 along a preset direction, and a closed first boundary pattern unit 1052 surrounding all the partition pattern units 1051. Both ends of the partition pattern unit 1051 intersect with the first boundary pattern unit 1052 and the partition pattern unit 1051 extends beyond the range of the first boundary pattern unit 1052.

[0129] Since the partition pattern unit 1051 extends beyond the range of the first boundary pattern unit 1052, both ends of the finally formed first active line intersect with the first closed boundary 1023 and extend beyond the range of the first closed boundary 1023, but both ends of the first active line do not contact the second closed boundary 1024. This structure can balance the stress between the active device unit and its boundary, preventing the device unit from being damaged due to uneven stress, and in particular can compensate for the uneven stress at the ends of the first active line, further avoiding the damage of the device unit.

[0130] The other steps are the same as those in Embodiment 3 and will not be described in detail here.

[0131] The present disclosure provides a method for forming an active region structure. The second closed boundary 1024 is formed simultaneously with the device unit. The second closed boundary 1024 is used to form the peripheral region, which can reduce the number of masks, simplify the process flow, and reduce costs.

[0132] Although the embodiments disclosed in the present invention are as described above, the content therein is only an embodiment adopted for the convenience of understanding the present invention and is not intended to limit the present invention. Any person skilled in the art within the technical field to which the present invention pertains may make any modifications and changes in the form of implementation and details without departing from the spirit and scope disclosed by the present invention. However, the protection scope of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. An active region structure, characterized in that, Comprising: A semiconductor substrate; An active layer located above the substrate; An active region disposed on the active layer; Wherein, the active region is a closed structure, and the active region includes a plurality of first active lines arranged at intervals along a preset direction, second active lines spaced apart from and alternating with the first active lines, a first closed boundary surrounding all the first active lines and the second active lines, and a second closed boundary surrounding the periphery of the first closed boundary; both ends of the first active line intersect with the first closed boundary, and the second active line does not contact the first closed boundary; the first active line includes a plurality of first device units arranged at intervals, the second active line includes a plurality of second device units arranged at intervals, and the first device units and the second device units are arranged in an interleaved manner; The first device units are isolated from each other by a first shallow trench, and an insulating layer is disposed in the first shallow trench.

2. The active region structure according to claim 1, wherein Both ends of the first active line extend outside the range of the first closed boundary.

3. The active region structure according to claim 1, wherein: The first device units close to the first closed boundary intersect with the first closed boundary; The second device units do not contact the first closed boundary.

4. The active region structure according to claim 3, wherein The lengths of all the first device units intersecting with the first closed boundary are different from each other.

5. The active region structure according to claim 1, characterized in that, The second device units are isolated from each other by a first shallow trench, and the first closed boundary and the second closed boundary are isolated from each other by a second shallow trench.

6. The active region structure according to claim 1, wherein The line width of the first active line is the same as the line width of the second active line.

7. A method for forming an active region structure, characterized in that, Comprising: Providing a semiconductor substrate and forming an active layer above the substrate; Forming a sacrificial layer above the active layer and performing a patterning process on the sacrificial layer to form a sacrificial layer pattern above the active layer; wherein, the sacrificial layer pattern includes a plurality of partition pattern units arranged at intervals along a preset direction, and a closed first boundary pattern unit surrounding all the partition pattern units, and both ends of the partition pattern unit intersect with the first boundary pattern unit; Forming spacers on the sidewalls of each pattern unit of the sacrificial layer pattern; Filling between the spacers to form a filling layer covering the sacrificial layer pattern, and removing the spacers in the filling layer to form a filling layer pattern above the active layer; wherein, the filling layer pattern includes filling pattern units spaced apart from and alternating with the partition pattern units, and a closed second boundary pattern unit surrounding the periphery of the first boundary pattern unit, and the filling pattern units do not contact the first boundary pattern unit; Performing a patterning process on the partition pattern units and the filling pattern units to obtain the patterned partition pattern units and filling pattern units; Using the first boundary pattern unit, the second boundary pattern unit, the patterned separation pattern unit, and the filling pattern unit as an etching mask, etch the active layer to form a plurality of first active lines arranged at intervals along the preset direction, second active lines spaced and alternating with the first active lines, a first closed boundary surrounding all the first active lines and the second active lines, and a second closed boundary surrounding the periphery of the first closed boundary on the active layer, thereby forming an active region; Wherein, both ends of the first active line intersect the first closed boundary, and the second active line does not contact the first closed boundary; the first active line includes a plurality of first device units arranged at intervals, the second active line includes a plurality of second device units arranged at intervals, and the first device units and the second device units are arranged in an interleaved manner.

8. The method according to claim 7, wherein, The separation pattern unit extends beyond the range of the first boundary pattern unit; Both ends of the first active line extend beyond the range of the first closed boundary.

9. The method according to claim 7, wherein, The first device unit close to the first closed boundary intersects the first closed boundary; The second device unit does not contact the first closed boundary.

10. The method according to claim 9, characterized in that The lengths of all the first device units intersecting the first closed boundary are different.

11. The method according to claim 7, wherein The second boundary pattern unit does not contact the first boundary pattern unit.

12. The method according to claim 11, wherein The first device units are isolated by first shallow trench isolation, the second device units are isolated by first shallow trench isolation, and the first closed boundary and the second closed boundary are isolated by second shallow trench isolation.

13. The method according to claim 7, wherein The separation pattern unit and the filling pattern unit have the same line width.

14. The method according to claim 7, wherein Performing a patterning process on the separation pattern unit and the filling pattern unit to obtain the patterned separation pattern unit and the filling pattern unit includes the following steps: Forming a photoresist layer above the sacrificial layer pattern and the filling layer pattern; Performing a patterning process on the photoresist layer through a mask to form a photoresist pattern above the sacrificial layer pattern and the filling layer pattern; wherein, the photoresist pattern includes a third boundary pattern unit covering the first boundary pattern unit, a fourth boundary pattern unit covering the second boundary pattern unit, a plurality of first device pattern units arranged at intervals above the separation pattern unit, and a plurality of second device pattern units arranged at intervals above the filling pattern unit, and the first device pattern units and the second device pattern units are arranged in an interleaved manner; Using the photoresist pattern as a mask, etch the partition pattern units and the filling pattern units to truncate the partition pattern units into a plurality of third device pattern units arranged at intervals, and truncate the filling pattern units into a plurality of fourth device pattern units arranged at intervals, so as to obtain the patterned partition pattern units and the filling pattern units; wherein, the third device pattern units and the fourth device pattern units are arranged alternately. Remove the photoresist pattern.

15. The method according to claim 14, wherein The third device pattern unit adjacent to the first boundary pattern unit intersects with the first boundary pattern unit.

16. The method according to claim 14, wherein Using the first boundary pattern unit, the second boundary pattern unit, the patterned partition pattern units and the filling pattern units as an etching mask, etch the active layer to form a plurality of first active lines arranged at intervals along the preset direction, second active lines spaced apart from and alternating with the first active lines, a first closed boundary surrounding all the first active lines and the second active lines, and a second closed boundary surrounding the outside of the first closed boundary on the active layer, thereby forming an active region, including the following steps: Using the first boundary pattern unit, the second boundary pattern unit, the third device pattern units and the fourth device pattern units as an etching mask, etch the active layer to form a plurality of first active lines arranged at intervals along the preset direction, second active lines spaced apart from and alternating with the first active lines, a first closed boundary surrounding all the first active lines and the second active lines, and a second closed boundary surrounding the outside of the first closed boundary on the active layer, thereby forming an active region.

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