Instruction cache coherency

Abstract

The present disclosure relates to instruction cache coherency. A data processing apparatus is provided comprising a cache for storing operations generated by decoding instructions fetched from a memory. The cache is indexed by virtual addresses of the instructions in the memory. Receive circuitry receives an incoming invalidate request, the incoming invalidate request referencing a physical address in the memory. Invalidate circuitry invalidates an entry in the cache whose virtual address corresponds to the physical address. Thus, coherency can be achieved when using a cache indexed using virtual addresses.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to data processing. More specifically, the present disclosure relates to instruction caching. BACKGROUND

[0002] In a data processing apparatus, instructions to be executed are fetched from a memory device and then decoded to produce one or more operations. The decoding process can be speeded up (or even circumvented) by caching the operations. It is desirable for such a cache to be indexed by virtual addresses rather than physical addresses, as this saves the need to perform translations between virtual and physical addresses. However, invalidation requests used to invalidate a local cache's copy of an instruction or an operation related to that instruction index entries using physical addresses. As multiple virtual addresses can reference the same physical address, such invalidation requests tend not to use virtual addresses. Thus, by invalidating only one virtual address, other copies of the same instruction (provided at other virtual addresses) can not be invalidated. SUMMARY

[0003] From a first example configuration, there is provided a data processing apparatus comprising: a cache to store operations produced by decoding instructions fetched from a memory, wherein the cache is indexed by virtual addresses of the instructions in the memory; a receiving circuitry to receive an incoming invalidation request, wherein the incoming invalidation request references a physical address in the memory; and an invalidation circuitry to invalidate an entry in the cache whose virtual address corresponds to the physical address.

[0004] From a second example configuration, there is provided a data processing method comprising: decoding instructions fetched from a memory to produce operations; storing the operations in a cache indexed by virtual addresses of the instructions; receiving an incoming invalidation request referencing a physical address in the memory; and invalidating an entry in the cache whose virtual address corresponds to the physical address.

[0005] From a third example configuration, there is provided a data processing apparatus comprising: means for decoding instructions fetched from a memory to produce operations; means for storing the operations in a cache indexed by virtual addresses of the instructions; means for receiving an incoming invalidation request referencing a physical address in the memory; and means for invalidating an entry in the cache whose virtual address corresponds to the physical address. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will be further described, by way of example only, with reference to the accompanying drawings in which:

[0007] Figure 1 A system comprising two data processing apparatuses according to some embodiments is schematically illustrated;

[0008] Figure 2 A data processing apparatus is shown in accordance with some embodiments;

[0009] Figure 3 A flow diagram showing a method of handling invalidation requests in accordance with some embodiments is shown.

[0010] Figure 4 A data processing apparatus is shown in accordance with some embodiments;

[0011] Figure 5 A data processing apparatus is shown in accordance with some embodiments; and

[0012] Figure 6 A flow diagram showing a data processing method in accordance with some embodiments is shown. DETAILED DESCRIPTION

[0013] Before any embodiments of the application are explained in detail, the following description of embodiments provides a general overview of the application.

[0014] According to one example configuration, a data processing apparatus is provided comprising: a cache to store operations resulting from decoding instructions fetched from a memory, wherein the cache is indexed by virtual addresses of the instructions in the memory; a receive circuit to receive an incoming invalidation request, wherein the incoming invalidation request references a physical address in the memory; and an invalidation circuit to invalidate an entry in the cache having a virtual address corresponding to the physical address in the invalidation request.

[0015] The data processing apparatus receives an invalidation request for an instruction, the operations of which can reside within the cache. The invalidation request references a particular physical address in a physical domain in the memory. The invalidation circuit invalidates an entry in the cache having a virtual address corresponding to the physical address in the invalidation request, thereby providing coherency while enabling the cache to be indexed using virtual addresses.

[0016] In some embodiments, the data processing apparatus comprises correspondence table storage circuitry for storing indications of physical addresses of instructions fetched from memory. The correspondence table storage circuitry can be populated when instructions are passed to the decode circuitry, where the instructions can be fetched directly from memory or indirectly from memory via an instruction cache. In some embodiments, the correspondence table storage circuitry functions as a fully-associative cache, such that each entry of the correspondence table can be looked up simultaneously. In other embodiments, the correspondence table storage circuitry is set-associative, such that only certain entries can be stored in a limited number of locations, thereby reducing the search time for a particular entry. By using the correspondence table in the correspondence table storage circuitry, the entries corresponding to the provided physical addresses can be located in the cache. Those entries can then be invalidated, while leaving the other entries intact. Thus, by providing a correspondence table, invalidation can be achieved without simply invalidating all entries in the cache. In particular, at least some entries in the cache are not invalidated in response to an incoming invalidation request. In some embodiments, those entries having a virtual address that does not correspond to the provided physical address are not invalidated. By inhibiting (or eliminating) unwanted invalidations, any performance loss that would occur due to simply invalidating the entire cache can be reduced.

[0017] In some embodiments, in response to an incoming invalidation request, the invalidation circuitry is adapted to determine a correspondence table index in the correspondence table storage circuitry that corresponds to the physical address referenced in the incoming invalidation request. Thus, the correspondence table can store a list of physical addresses, each at a different index or location. Upon receiving an incoming invalidation request, the correspondence table is searched for an entry that corresponds to the physical address included in the incoming invalidation request. If such an entry is found, the index of the correspondence table at which the entry was found (the correspondence table index) is returned. If no entry is found, the data processing apparatus has not recently fetched the instruction in question, and thus no invalidation needs to be performed.

[0018] In some embodiments, the cache is adapted to store one of the operations in association with one of the correspondence table indices of the correspondence table storage circuitry, the one correspondence table index containing one of the indications of physical addresses, the physical address being that of one of the instructions decoded as the one operation. In this way, the correspondence table and the cache collectively associate the indications of physical addresses with the respective operations generated from the instructions at that physical address.

[0019] In some embodiments, the indication of the physical address stored in the correspondence table storage circuit comprises a hash of at least a portion of the physical address. Thus, the indication of the physical address can be a hash of the portion of the physical address, or a hash of the physical address. A hash function can be used to map an input domain to a smaller output domain. Thus, the amount of storage space required by the correspondence table can be reduced compared to the case where the physical address (portion) is stored. As a result, because the output domain is smaller than the input domain, it is possible for two physical addresses (or portions of physical addresses) to yield the same hash value. Thus, when a physical address is received in a pass-in invalidate request, this can cause some entries in the cache to be invalidated other than the subject of the invalidate request. However, it is worth noting that even in these cases, the number of unwanted invalidations should be small, and thus any performance loss that occurs due to invalidating some unintended entries should be small. Because the cache stores copies of data held in memory, if the data is invalidated and needed at a later stage, the data can be retrieved again.

[0020] In some embodiments, the at least a portion of the physical address comprises the most significant bits of the physical address. In this way, the entries in the correspondence table can refer to blocks of instructions, rather than individual instructions.

[0021] In some embodiments, the at least a portion of the physical address refers to a page in memory. For example, if the page size in the data processing device is 4kB, then bits 0-11 of the physical address can not be considered, such that the entries of the correspondence table refer to pages.

[0022] In some embodiments, the cache comprises: operation storage circuitry for storing operations; and tag determination circuitry for storing an operation storage index in the operation storage circuitry at which one of the operations corresponding to the received virtual address is located. Thus, by performing a lookup using the tag determination circuitry, the index at which a particular operation is located in the operation storage circuitry can be obtained.

[0023] In some embodiments, the operations are macro-operations. Thus, in such embodiments, the operations are not the result of a direct decode of the instructions, but can be the result of decoding the instructions into operations and then degenerating the operations into macro-operations, which can be executed by the execution units, where multiple macro-operations can be generated for multiple execution units. In some embodiments, the macro-operations are further degenerated into micro-operations, which are executed by the execution units. In some embodiments, the execution units can operate on micro-operations and / or macro-operations and / or operations.

[0024] In some embodiments, a data processing apparatus comprises fetch circuitry to fetch an instruction from a physical address in a memory; decode circuitry to receive the instruction and decode the instruction to produce an operation; and populate circuitry to insert the physical address into a correspondence table circuitry, wherein the cache is adapted to store the operation in association with a correspondence table index in the correspondence table circuitry, wherein the physical address is located at the correspondence table index in the correspondence table circuitry. The fetch circuitry and the decode circuitry can together form part of a pipeline. By storing the physical address in the correspondence table circuitry and by storing the index of the correspondence table circuitry (i.e. the location at which the physical address is stored) in association with the operation, it is possible to locate the operation corresponding to a particular physical address in the cache. This can be achieved even if the cache is indexed using virtual addresses (e.g. even if the cache provides an association between virtual addresses and the respective operations of the instructions stored at those virtual addresses).

[0025] There are a number of ways in which the correspondence table storage circuitry can be populated, and in which the process of populating the correspondence table can be used to provide a mapping between physical addresses in the correspondence table and the operations produced by the instructions stored at those physical addresses.

[0026] In some embodiments, the physical address is provided to the populate circuitry by the fetch circuitry; and the populate circuitry inserts the physical address into the correspondence table circuitry at the correspondence table index. Thus, the correspondence table index provides an index (e.g. a location number) at which a particular physical address is stored in the correspondence table.

[0027] In some embodiments, the populate circuitry returns the correspondence table index at which the physical address is inserted in the correspondence table circuitry; and the correspondence table index is passed to the decode circuitry by the fetch circuitry to insert the correspondence table index into the cache. Thus, in such embodiments, the correspondence table index is passed along the pipeline together with the virtual address (e.g. program counter value) of the instruction in question. Once the instruction has been decoded, the resulting operation can be stored in association with the program counter value (e.g. virtual address) of the instruction and in association with the correspondence table index.

[0028] In some other embodiments, the data processing apparatus comprises: a fetch queue circuit to store a virtual address of an instruction in the memory at a fetch queue index, wherein the fetch queue index is provided by the fetch circuit to the fill circuit along with the physical address; the fill circuit causes the corresponding table index to be stored in the fetch queue circuit in association with the virtual address; the fetch queue index is passed by the fetch circuit to the cache circuit; and the cache circuit uses the fetch queue index to retrieve the physical address and the corresponding table index to insert the corresponding table index into the cache. The fetch queue provides the virtual address (program counter value) of the instruction to be fetched. Each virtual address in the fetch queue is passed to the fetch circuit along with the index (e.g., location) in the fetch queue circuit where that virtual address is located. In these embodiments, the fetch queue index is also provided to the fill circuit, rather than just the physical address to the fill circuit. The fill circuit then inserts the physical address into the corresponding table (as described previously) and then stores the index where this insertion occurred in association with the virtual address at the provided fetch queue index. Thus, the fetch queue stores the virtual address (e.g., program counter value) in association with the index in the corresponding table circuit where the equivalent physical address is located. Meanwhile, the fetch circuit passes the fetch queue index to the cache circuit (in some embodiments, via the decode circuit) and the cache circuit uses the fetch queue index to retrieve the corresponding table index and program counter value from the fetch queue circuit. The cache can then be filled using the operations in association with the program counter value / virtual address and the corresponding table index where the equivalent physical address is stored. Because the program counter value is not passed by the fetch circuit to the decode circuit and then to the cache circuit, but only the index of the fetch queue is passed, the amount of data that needs to pass through the pipeline can be reduced. Thus, the amount of circuitry required is reduced compared to if the program counter value was passed through the pipeline, and thus power consumption is reduced.

[0029] In some embodiments, the incoming invalidate request is a snoop invalidate request received from another data processing apparatus. The snoop invalidate request can be issued by the other data processing apparatus in response to data being modified at the other data processing apparatus. To maintain consistency, multiple versions of the same data cannot be stored. Thus, other versions of the data that are not modified are invalidated, and the invalidate request is used to cause those versions to be invalidated (e.g., deleted).

[0030] In some embodiments, a data processing apparatus comprises instruction modification circuitry to perform a modification to an old instruction in a memory; and in response to the modification, the data processing apparatus issues an outgoing invalidate request to another data processing apparatus, wherein the outgoing invalidate request references a physical address at which the old instruction is located in the memory. The modification of the instruction can occur, for example, in Just In Time (JIT) compilation. In these cases, because the instruction in the instruction cache can be overwritten with the revised version of the instruction, it is necessary to invalidate other copies of the instruction (which can be located elsewhere). This can be achieved by issuing an outgoing invalidate request which references the physical address at which the old instruction is located. The outgoing invalidate request can then be sent to other locations where the instruction can be found, for example, other data processing apparatuses containing caches.

[0031] Particular embodiments will now be described with reference to the drawings.

[0032] Figure 1 A system 100 is schematically illustrated, the system 100 comprising a first data processing apparatus 105, a second data processing apparatus 110 and a memory 115 connected via a bus 155. In this example, the second data processing apparatus 110 uses instruction modification circuitry 120 to modify an operation corresponding to an instruction held in a second level data cache 125 of the second data processing apparatus 110. As a result of this modification, the operation corresponding to the instruction (which can be held in other caches of other data processing apparatuses in the system 100, such as the first data processing apparatus 105) must be invalidated. This invalidation ensures that multiple different versions of the operation relating to the same instruction are not held within the system 100, which would result in uncertainty as to which version is correct. Therefore, the second data processing apparatus 110 issues a snoop invalidate request which is sent to the first data processing apparatus 105. The snoop invalidate request contains the physical address (PA) of the instruction for which the modification has been performed.

[0033] The snoop invalidation request is received by a receive circuit 130 of the first data processing device 105. If the first data processing device 105 comprises a data cache such as a level two data cache 135, the physical address can be used to directly invalidate any copy of the instruction (or operation thereof) stored within the level two data cache 135. In this example, the first data processing device comprises a macro operation (MOP) cache 145 which is indexed using virtual addresses. The MOP cache 145 forms part of an instruction cache 160 and stores macro operations resulting from the decoding of instructions fetched from the memory 115. Because the MOP cache 145 is indexed using virtual addresses, the physical address received in the snoop invalidation request cannot be used directly to look up a corresponding entry. Therefore, in these embodiments, the receive circuit 130 sends the physical address to an invalidate circuit 140 of the instruction cache 160. By consulting a correspondence table (PACT) 150, the invalidate circuit 140 is able to determine the location of the entry in the MOP cache 145 relating to the instruction referenced in the snoop invalidation request.

[0034] Thus, even though the MOP cache 145 is indexed using virtual addresses, it can still respond to snoop invalidation requests received from other data processing devices 110 in which the reference in the snoop invalidation request is a physical address. Thus, such a system can take advantage of a virtually indexed cache while also being used in a coherent system.

[0035] Figure 2 An example of one of the data processing devices 200 is shown schematically. In the data processing device 200, a fetch queue 205 lists a series of virtual addresses (VAs) or program counter values at which instructions are to be fetched. From here, the virtual addresses output from the fetch queue 205 can take two different paths. In a first path, a translation lookaside buffer (TLB) 210 uses the virtual addresses to translate the virtual addresses into physical addresses. The TLB 210 uses a memory management unit (MMU) 215 to obtain this information. The corresponding physical address and program counter value (e.g. virtual address) provided by the TLB 210 are provided to an instruction cache 220 containing instructions which have been fetched from memory. In this embodiment, the TLB is tagged using a virtual address and an execution context comprising an address space identifier (ASID), a virtual machine identifier (VMID) and an exception level / privilege level (EL). Here, an instruction tag circuit 225 uses the physical address to reference a location in an instruction data buffer 230. This results in an opcode of the fetched instruction. The opcode is provided to a decode circuit 235 by a queue. The decode circuit 235 produces one or more macro operations. These macro operations can then be cached in a MOP cache 250 to save the need to perform the decode again.

[0036] In the second path, which can be taken from fetch queue 205, the virtual address is used to index into macro op cache tag circuit 255 of MOP cache 250. If a hit occurs, this provides a reference to macro op cache data buffer 270 storing the corresponding macro op. The macro op is then provided to decompressor 275 through a queue. Thus, the second path reduces the extent of decoding required and enables faster retrieval of macro ops relevant to the instruction.

[0037] Regardless of which of the two paths is taken, either decode circuit 235 or decompression circuit 275 provides its output to multiplexer 280. The output of the multiplexer can then be provided to, for example, a renaming circuit or other stage of a pipeline.

[0038] Note that in this example, macro op cache tag circuit 255 is composed of two separate circuits. First, virtual address correspondence table (VACT) 260 relates an execution context including an address space identifier (ASID), a virtual machine identifier (VMID), and an exception level / privilege level (EL) to the high bits of a virtual address ([48:12]). Thus, the entries of the VACT contain data corresponding to tags used in a TLB. The entries of this table are referenced by tag circuit 265, which also provides the low bits of the virtual address ([11:2]). This use of two separate tables 260, 265 recognizes that there is a large amount of redundancy in the virtual address. Specifically, the most significant bits of the virtual address are least likely to change and are more likely to be the same among multiple addresses accessed in a short time. Thus, only a small number of entries (e.g., 16 in this example) are provided in VACT 260, which represent the high bits of the virtual address, while a larger number of entries (e.g., 256 in this example) are provided in tag circuit 265.

[0039] As previously discussed, the data processing apparatus 200 in these examples includes a correspondence table (PACT) 240 for providing an indication of the most recently accessed physical address. These are for the purpose of invalidating the appropriate operations in response to an invalidate request. In particular, in this example, a fill circuit 245 is provided with the physical address from the instruction tag circuit 225. The fill circuit 245 then inserts the bits of the physical address into the correspondence table (PACT) 240. The fill circuit 245 then provides an index to where the entry in the correspondence table (PACT) 240 was generated. This index is provided to the decode circuit 235 along with the program counter value (virtual address). When the decode circuit 235 provides a macro-operation to the macro-operation cache 250 to create a new entry, the macro-operation is provided with the program counter value (virtual address) and the index to the correspondence table (PACT) 240. The program counter value is used to fill the VACT 260 and the tag circuit 265 (the bits of the program counter value are divided between each of these two circuits 260, 265 as previously discussed). At the same time, the index to the correspondence table (PACT) 240 is provided with the high bits of the program counter value / virtual address in the VACT 260.

[0040] In this way, when a physical address relating to an instruction(s) / operation(s) is received, the correspondence table (PACT) 240 can be searched. If an entry is found that matches the physical address, the index of that entry can be searched for in the VACT 260. Thus, even in the case where the invalidate request references a physical address and the MOP cache 250 references a virtual address, the relevant entry of the MOP cache 250 can be located and invalidated if necessary.

[0041] Figure 3 A flowchart 300 is shown that illustrates, for example, using the correspondence table (PACT) 240, how the VACT 260 and the tag circuit 265 are filled. The flowchart 300 is shown in relation to a program counter value (virtual address) and an index to the correspondence table (PACT) 240. The program counter value is divided between the VACT 260 and the tag circuit 265. The index to the correspondence table (PACT) 240 is provided with the high bits of the program counter value / virtual address in the VACT 260. Figure 2The process shown in the circuit to respond to a snoop invalidation request. At step 310, a snoop invalidation request is received, for example by the receive circuit 130. At step 320, the index at the location in the correspondence table (PACT) 240 where the physical address is listed is determined. The correspondence table (PACT) 240 can be fully associative, such that every entry of the PACT table can be searched simultaneously. In this example, the correspondence table (PACT) 240 lists only the high bits of the physical address. Specifically, each address in the correspondence table (PACT) 240 references a page in memory (each page representing 4kB of memory). Thus, the search of the correspondence table (PACT) 240 only considers the same number of high bits of the physical address. For example, if the snoop invalidation request contains a full physical address of length 40 bits, only bits 12 to 40 are used to search the correspondence table (PACT) 240 (as the correspondence table (PACT) 240 does not store bits 0-11). If no match is found, no invalidation operation is performed. Alternatively, if a match is to be found, at step 330, the index of the matching correspondence table (PACT) 240 is determined. At step 340, the entry in the VACT 260 containing the index that has been retrieved from the correspondence table (PACT) 240 is searched. The entry in the VACT 260 containing such an index is then determined. The high bits of the virtual address stored in this entry are then determined at step 340. At step 350, using the index of this entry, any entry in the tag table 265 containing this index is searched. This in turn provides the low bits of the virtual address. The low and high bits are then combined in order to provide an index to the MOP cache data circuit 270. Any data stored at the relevant index is then invalidated.

[0042] For example, consider the case where a physical address PA[40:2] is received in an invalidation request. In this example, PA[40:12] is searched in all entries of the correspondence table (PACT) 240. A match is found at index 7. The entry in the VACT 260 with PACT index 7 is then searched. One entry is at index 12, which has a PACT index of 7 (as required) and lists the high bits of the virtual address VA[48:12]. The entry in the tag index 265 with VACT index 12 is then searched. Again, one entry is found, which provides the low bits of the virtual address VA[11:2] (in fact, because the page size here is 4kB, the low bits of the physical address received in the request - PA[11:2] - will be the same as VA[11:2]). These two sets of bits are then combined together to form the virtual address (most of) - VA[48:2]. This is then used to identify the entry in the macro-operation cache data 270 to be invalidated. Note that the lower two bits of the virtual address VA([1:0]) are not required because the instruction is considered to occupy four bytes of memory.

[0043] Figure 4 An alternative embodiment is shown in which the data processing apparatus 400 uses a correspondence table (PACT) 240 to store the hash of the physical address or part of the physical address. In this way, the size of the correspondence table (PACT) 240 can be reduced. The data processing apparatus 400 works in a similar way to the apparatus 200 shown. Note that because the hash of the physical address is stored in the correspondence table (PACT) 240, it is possible that as a result of an incoming snoop invalidation request, a different entry in the expected MOP cache 250 can be invalidated because that different entry of the MOP cache 250 resolves to the same hash value. It is expected that this will occur rarely and the performance penalty associated with occasionally invalidating a small number of additional entries of the MOP cache 250 (rather than invalidating all entries of the MOP cache 250) will be small. Figure 2 The apparatus 200 shown works in a similar way to the apparatus 200 shown. Note that because the hash of the physical address is stored in the correspondence table (PACT) 240, it is possible that as a result of an incoming snoop invalidation request, a different entry in the expected MOP cache 250 can be invalidated because that different entry of the MOP cache 250 resolves to the same hash value. It is expected that this will occur rarely and the performance penalty associated with occasionally invalidating a small number of additional entries of the MOP cache 250 (rather than invalidating all entries of the MOP cache 250) will be small.

[0044] Figure 5 A data processing apparatus 500 according to some embodiments is shown. In these embodiments, in addition to providing the virtual address, the fetch queue 205 also provides the index in the fetch queue where the virtual address currently being fetched is located. This is provided to the TLB 210 and from there to the instruction cache 220. Here, the tag circuit 225 provides the physical address and the fetch queue index number to the fill circuit 245. Again, the fill circuit 245 inserts the entry into the correspondence table (PACT) 240. Furthermore, rather than returning the index of the correspondence table (PACT) 240 to the tag circuit 225, the fill circuit 245 inserts the index of the correspondence table (PACT) 240 at the specified index of the fetch queue 205. Thus, rather than providing the correspondence table index to the tag circuit 225, the correspondence table index is stored in the corresponding entry of the fetch queue 205. The tag circuit 225 also provides the fetch queue index to the instruction data buffer 230 which provides the fetch queue index along with the operation code to the decode circuit 235. When a new entry is generated, the decode circuit 235 provides the fetch queue index to the MOP cache circuit 250. Here, the MOP cache circuit 250 uses the fetch queue index to access the specified entry of the fetch queue 205 to provide the corresponding virtual address / program counter value and correspondence table (PACT) index. These are then stored in the MOP cache tag circuit 255 as before.

[0045] In this way, the amount of data transferred from the instruction cache to the decode circuitry and from the decode circuitry to the MOP cache 250 is greatly reduced. In particular, rather than providing a program counter value and a corresponding table (PACT) index through the pipeline, this data is stored at the index of the fetch queue and the index at which the data is stored is passed through the pipeline. Thus, the number of bits to be transferred is significantly reduced. Once the fetch queue index is provided to the MOP cache 250, a lookup can be performed using the fetch queue 205 to retrieve the data required to populate the MOP cache 250.

[0046] Figure 6 A flowchart 600 showing a data processing method according to some embodiments is shown. At step 610, instructions are fetched. At step 620, the instructions are decoded so as to produce operations. At step 630, the operations are cached in a VIVT cache such as the MOP cache 250. Such a cache is indexed using virtual addresses. At step 640, an invalidate request is received, the invalidate request referencing a particular physical address. At step 650, entries in the cache having a virtual address corresponding to the physical address received by the invalidate request are then invalidated. This can be achieved, for example, with the aid of a correspondence table (PACT) 240 which is used to provide a correspondence between physical addresses and virtual addresses. The virtual address can then be used to look up the relevant operations in the MOP cache 250, thereby determining which entries of the MOP cache 250 should be invalidated in accordance with the invalidate request.

[0047] Thus, from the above, it can be appreciated that the advantages of a MOP cache 250 using virtual indexing can be obtained, which eliminates the need for virtual address translation, whilst still enabling coherency with respect to invalidate requests received from other data processing devices in the system (e.g. snoop invalidate requests).

[0048] In this application, the word "configured" is used to mean that an element of an apparatus has a configuration able to perform the defined operation. In this context, a "configuration" means an arrangement or manner of interconnection of hardware or software. For example, the apparatus can have dedicated hardware which provides the defined operational behaviour, or a processor or other processing device can be programmed to perform the function. "Configured" does not imply that the apparatus element has to be changed in any way in order to provide the defined operation.

[0049] While illustrative embodiments of the application have been described herein with reference to the accompanying drawings, it is to be understood that the application is not limited to those precise embodiments, and that various changes, additions and modifications can be made to the embodiments without departing from the scope and spirit of the application defined in the appended claims. For example, features of one claim can be combined with features of another claim while not departing from the scope or spirit of the application.

Claims

1. A data processing apparatus comprising: a cache to store operations produced by decoding instructions fetched from a memory, wherein the cache is indexed by virtual addresses of the instructions in the memory; a receive circuit to receive an incoming invalidate request, wherein the incoming invalidate request references a physical address in the memory; an invalidate circuit to invalidate an entry in the cache that has a virtual address corresponding to the physical address; a correspondence table storage circuit to store an indication of a physical address of the instructions fetched from the memory; a fetch circuit to fetch the instructions from the physical address in the memory; a decode circuit to receive the instructions and decode the instructions to produce the operations; and a populate circuit to insert the physical address into the correspondence table circuit, wherein the cache is adapted to store the operations in association with a correspondence table index, wherein the physical address is at the correspondence table index in the correspondence table circuit.

2. The data processing apparatus of claim 1, wherein: in response to the incoming invalidate request, the invalidate circuit is adapted to determine a correspondence table index in the correspondence table storage circuit that corresponds to the physical address referenced in the incoming invalidate request.

3. The data processing apparatus of claim 2, wherein: the cache is adapted to store one of the operations in association with one of the correspondence table indexes of the correspondence table storage circuit, the one of the correspondence table indexes containing one of the indications of physical addresses, the physical address being a physical address of one of the instructions decoded into the one of the operations.

4. The data processing apparatus of claim 1, wherein: the indication of the physical address stored in the correspondence table storage circuit comprises a hash of at least a portion of the physical address.

5. The data processing apparatus of claim 4, wherein: the at least a portion of the physical address comprises a most significant bit of the physical address.

6. The data processing apparatus of claim 5, wherein: the at least a portion of the physical address references a page in the memory.

7. The data processing apparatus of claim 1, wherein: the cache comprises: an operation storage circuit to store the operations; and a tag determination circuit to store an operation storage index in the operation storage circuit at which one of the operations corresponding to a received virtual address is located.

8. The data processing apparatus of claim 1, wherein: the operations are macro operations.

9. The data processing apparatus of claim 1, wherein: the physical address is provided to the populate circuit by the fetch circuit; and the populate circuit inserts the physical address into the correspondence table circuit at the correspondence table index.

10. The data processing apparatus of claim 9, wherein: the populate circuit returns the correspondence table index at which the physical address is inserted in the correspondence table circuit; and the invalidate circuit invalidates the entry in the cache at the correspondence table index returned by the populate circuit. The correspondence table index is passed by the fetch circuit to the decode circuit to insert the correspondence table index into the cache.

11. The data processing device of claim 1, comprising: a fetch queue circuit to store the virtual address of the instruction in memory at a fetch queue index, wherein, the fetch queue index is provided by the fetch circuit to the fill circuit along with the physical address; the fill circuit causes the correspondence table index to be stored in the fetch queue circuit in association with the virtual address; the fetch queue index is passed by the fetch circuit to the cache circuit; and the cache circuit uses the fetch queue index to retrieve the physical address and the correspondence table index to insert the correspondence table index into the cache.

12. The data processing device of claim 1, wherein, the incoming invalidation request is a snoop invalidation request received from another data processing device.

13. The data processing device of claim 1, comprising: an instruction modification circuit to perform a modification to an old instruction in the memory; and in response to the modification, the data processing device issues an outgoing invalidation request to another data processing device, wherein the outgoing invalidation request references a physical address in the memory at which the old instruction is located.

14. A data processing method, comprising: decoding an instruction fetched from a memory to produce an operation; storing the operation in a cache, the cache being indexed by a virtual address of the instruction; receiving an incoming invalidation request referencing a physical address in the memory; invalidating an entry in the cache having a virtual address corresponding to the physical address; storing an indication of the physical address of the instruction fetched from the memory in a correspondence table; fetching the instruction from the physical address in the memory; receiving the instruction and decoding the instruction to produce the operation; and inserting the physical address into the correspondence table, wherein the cache is adapted to store the operation in association with a correspondence table index, wherein the physical address is located at the correspondence table index in the correspondence table.

15. A data processing device, comprising: means for decoding an instruction fetched from a memory to produce an operation; means for storing the operation in a cache, the cache being indexed by a virtual address of the instruction; means for receiving an incoming invalidation request referencing a physical address in the memory; means for invalidating an entry in the cache having a virtual address corresponding to the physical address; means for storing an indication of the physical address of the instruction fetched from the memory in a correspondence table; means for fetching the instruction from the physical address in the memory; means for receiving the instruction and decoding the instruction to produce the operation; and means for inserting the physical address into the correspondence table, wherein the cache is adapted to store the operation in association with a correspondence table index, wherein, the physical address is located at the correspondence table index in the correspondence table.

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