Display device and method of manufacturing the same

Abstract

A display device and a manufacturing method thereof. The display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes a plurality of first electrodes and a driving element layer. The plurality of first electrodes are arranged in the pixel region and the plurality of first electrodes are electrically connected to the driving element layer. The isolation layer is arranged on the semiconductor substrate. The isolation layer includes a first isolation pattern arranged in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is arranged on the isolation layer and the plurality of first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is arranged on the light-emitting layer.

Description

Technical Field

[0001] The disclosed embodiments relate to a display device and a manufacturing method thereof. Background Art

[0002] In recent years, with the rapid development of semiconductor technology, near-eye displays have become popular. Due to the limitations in current manufacturing technology, it is difficult to reduce the spacing between light-emitting elements of display devices. Development of manufacturing technology for display devices in wafer-level near-eye displays is underway to meet the demand for size reduction and high resolution. Summary of the invention

[0003] According to an embodiment of the present invention, a display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region, wherein the semiconductor substrate includes a plurality of first electrodes and a driving element layer. The plurality of first electrodes are arranged in the pixel region and the plurality of first electrodes are electrically connected to the driving element layer. The isolation layer is arranged on the semiconductor substrate, wherein the isolation layer includes a first isolation pattern arranged in the peripheral region, the first isolation pattern having a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is arranged on the isolation layer and the plurality of first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is arranged on the light-emitting layer.

[0004] According to an embodiment of the present invention, a display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region around the pixel region, wherein the semiconductor substrate includes a plurality of first electrodes and a driving element layer. The plurality of first electrodes are arranged in the pixel region, and the plurality of first electrodes are electrically connected to the driving element layer. The isolation layer is arranged on the semiconductor substrate, wherein the isolation layer includes a first opening in the peripheral region and a plurality of second openings in the pixel region. The light-emitting layer is arranged on the isolation layer and in the first opening and the plurality of second openings. The second electrode is arranged on the light-emitting layer.

[0005] According to an embodiment of the present invention, a method for manufacturing a display device includes at least the following steps. A semiconductor substrate having a plurality of device units is provided, wherein each of the plurality of device units has a pixel region and a peripheral region located around the pixel region, and the semiconductor substrate includes a plurality of first electrodes and a driving element layer. The plurality of first electrodes are arranged in the pixel region, and the plurality of first electrodes are electrically connected to the driving element layer. An isolation layer is formed on the semiconductor substrate. The isolation layer is patterned to form a first opening in the peripheral region and a plurality of second openings in the pixel region, wherein the plurality of second openings expose the plurality of first electrodes. A light-emitting layer is formed on the patterned isolation layer and in the first opening and the plurality of second openings. A second electrode is formed on the light-emitting layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure.

[0008] Figure 2 is a simplified top view of a display device according to some embodiments of the present disclosure.

[0009] FIG. 3A to FIG. 3F are schematic cross-sectional views of various stages in a method for manufacturing a display device according to some embodiments of the present disclosure.

[0010] Figure 4 is a simplified top view of an intermediate stage in a method of manufacturing a display device according to some embodiments of the present disclosure.

[0011] Figure 5 is a schematic cross-sectional view of a display device according to some alternative embodiments of the present disclosure.

[0012] Description of Figure Numbers

[0013] 10, 20: Display devices

[0014] 100: Semiconductor substrate

[0015] 102: Substrate

[0016] 104: Driving element layer

[0017] 106: Internal connection structure

[0018] 108a: first electrode

[0019] 108b: Common electrode

[0020] 110, 110': Isolation layer

[0021] 110p: Partial

[0022] 112: First isolation pattern

[0023] 114: Second isolation pattern

[0024] 114a: first pattern portion

[0025] 114b: Second pattern portion

[0026] 120: Luminous layer

[0027] 130: Second electrode

[0028] 140: Dielectric Encapsulation

[0029] A: Pixel area

[0030] B: Outer area

[0031] D, D2: minimum distance

[0032] DU: Device Unit

[0033] H: Height

[0034] I-I', II-II': line

[0035] M1: First mask

[0036] M2: Second mask

[0037] O1: First opening

[0038] O2: Second opening

[0039] OP1: First opening pattern

[0040] OP2: Second opening pattern

[0041] S1: First side surface

[0042] S2: Second side surface

[0043] S3: Third side surface

[0044] S4: Fourth side surface

[0045] S5: Fifth side surface

[0046] S6: Sixth side surface

[0047] SL1, SL2: Cutting path

[0048] X, Y: direction

[0049] Z: thickness direction DETAILED DESCRIPTION

[0050] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The following describes specific examples of components, values, operations, materials, arrangements, etc. to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. It is expected that there are other components, values, operations, materials, arrangements, etc. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact with each other by forming a first feature on or on the second feature, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact with each other. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0051] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature illustrated in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0052] In addition, for ease of description, terms such as "first", "second", "third", "fourth", etc. may be used herein to describe similar elements or features or different elements or features shown in the figures, and may be used interchangeably according to the order of existence or context of the description.

[0053] Figure 1 is a schematic cross-sectional view of a display device 10 according to some embodiments of the present disclosure. Figure 2 is a simplified top view of a display device 10 according to some embodiments of the present disclosure. Specifically, Figure 1 is along Figure 2 The cross-sectional view taken along the line II' is shown. Figure 2 The simplified top view only shows a few elements of the display device 10 , such as a semiconductor substrate, an isolation layer, a first electrode, and a second electrode, and these elements are not necessarily in the same plane.

[0054] Reference Figure 1 and Figure 2, the display device 10 includes a semiconductor substrate 100, an isolation layer 110, a light-emitting layer 120 and a second electrode 130. In some embodiments, the display device 10 may further include a dielectric encapsulant 140. In some embodiments, the display device 10 is a self-luminescent display device. In some embodiments, the display device 10 is an organic light-emitting diode (OLED) display device. In some alternative embodiments, the display device 10 also includes other required elements, such as a cover plate, glass and / or a transparent shielding. That is, the display device 10 of the present disclosure is not limited to Figure 1 . In some embodiments, the cover plate and the semiconductor substrate 100 are disposed opposite to each other. In some embodiments, the cover plate may be a flexible substrate, such as a polymer substrate or a plastic substrate. However, the present disclosure is not limited thereto. In some alternative embodiments, the cover plate is a rigid substrate, such as a glass substrate, a quartz substrate, or a silicon substrate.

[0055] In some embodiments, the semiconductor substrate 100 has a pixel region A and a peripheral region B located around the pixel region A. Figure 2 As shown in , in the top view, the peripheral region B has a ring shape. In some embodiments, the semiconductor substrate 100 includes a substrate 102, a driving element layer 104, an internal wiring structure 106, a plurality of first electrodes 108a and a common electrode 108b. In some embodiments, the substrate 102 is made of the following materials: an elemental semiconductor material, such as crystalline silicon, diamond or germanium; a compound semiconductor material, such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide; or an alloy semiconductor material, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide or gallium indium phosphide. In some embodiments, the substrate 102 is a bulk semiconductor material. For example, the substrate 102 may be a bulk silicon substrate, such as a bulk substrate formed of single crystal silicon, a doped silicon substrate, an undoped silicon substrate or a silicon-on-insulator (SOI) substrate, wherein the dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant or a combination thereof.

[0056] In some embodiments, the driving element layer 104 is disposed on the substrate 102. In some embodiments, the driving element layer 104 includes active components (e.g., transistors, etc.) and / or passive components (e.g., resistors, capacitors, inductors, etc.) formed in the driving element layer 104. In some embodiments, the driving element layer 104 is a complementary metal-oxide-semiconductor (CMOS) circuit layer.

[0057] In some embodiments, the interconnect structure 106 is used to connect to active components (not shown) and / or passive components (not shown) in the driver element layer 104. In some embodiments, the interconnect structure 106 includes an insulating layer (not shown) and a plurality of metal features (not shown) disposed in the insulating layer. In some embodiments, the insulating layer includes an inter-layer dielectric (ILD) layer located on the driver element layer 104 and at least one inter-metal dielectric (IMD) layer located on the inter-layer dielectric layer. In some embodiments, the material of the insulating layer includes silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material, or a combination thereof. The insulating layer may be a single-layer or multi-layer structure. In some embodiments, the metal features include metal lines and vias (not shown). In some embodiments, the material of the metal features includes tungsten (W), copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or a combination thereof. In some embodiments, the interconnect structure 106 is formed by a dual damascene process. In an alternative embodiment, the interconnect structure 106 is formed by a plurality of single damascene processes. In yet other alternative embodiments, the interconnect structure 106 is formed by an electroplating process.

[0058] In some embodiments, the plurality of first electrodes 108a are disposed in the pixel region A. In some embodiments, some of the plurality of first electrodes 108a are disposed in the pixel region A and further extend into the peripheral region B, such as Figure 1 As shown in . However, the present disclosure is not limited to this. In some alternative embodiments, no first electrode 108a is disposed in the peripheral region B. In some embodiments, the first electrode 108a is electrically connected to active components (not shown) and / or passive components (not shown) in the driving element layer 104 through the interconnect structure 106. That is, the driving signal can be transmitted to the first electrode 108a through the active components (not shown) in the driving element layer 104 and the interconnect structure 106. In some embodiments, the material of the first electrode 108a includes a transparent conductive material. In some embodiments, the transparent conductive material may include a metal oxide conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, other suitable oxides, or a stacked layer formed by at least two of the above materials. However, the present disclosure is not limited to this. In some alternative embodiments, the material of the first electrode 108a includes an opaque conductive material. In some embodiments, the opaque conductive material includes a metal. In some embodiments, the first electrode 108a is disposed above the exemplary top surface of the interconnect structure 106, such as Figure 1As shown in . However, the present disclosure is not limited to this. In some alternative embodiments, the first electrode 108a is embedded in the interconnect structure 106. In some embodiments, the first electrode 108a is formed by a photolithography process and an etching process. For example, the method of forming the first electrode 108a may include: forming a conductive material layer completely on the interconnect structure 106 by a suitable manufacturing technology (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or evaporation); and then performing a photolithography process and an etching process to pattern the conductive material layer. In the display device 10, the number of first electrodes 108a may be less than or more than Figure 2 The number shown in the figure can be specified based on requirements and / or design layout; the present disclosure is not particularly limited thereto.

[0059] In some embodiments, the common electrode 108b is disposed in the peripheral region B. In some embodiments, the common electrode 108b is electrically grounded (e.g., 0 V). In some embodiments, the material of the common electrode 108b includes a transparent conductive material. In certain embodiments, the transparent conductive material includes a metal oxide conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, other suitable oxides, or a stacked layer formed by at least two of the foregoing materials. However, the present disclosure is not limited thereto. In some alternative embodiments, the material of the common electrode 108b includes an opaque conductive material. In certain embodiments, the opaque conductive material includes a metal. In certain embodiments, the material of the common electrode 108b is the same as that of the first electrode 108a. In certain embodiments, the material of the common electrode 108b is different from that of the first electrode 108a. In some embodiments, the common electrode 108b is disposed above the exemplary top surface of the interconnect structure 106, such as Figure 1As shown in . However, the present disclosure is not limited to this. In some alternative embodiments, the common electrode 108b is embedded in the interconnect structure 106. In some embodiments, the common electrode 108b is formed by a photolithography process and an etching process. The method of forming the common electrode 108b may include: forming a conductive material layer completely on the interconnect structure 106 by a suitable manufacturing technology (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or evaporation); then performing a photolithography process and an etching process to pattern the conductive material layer. In some embodiments, the common electrode 108b and the first electrode 108a are formed in the same process. That is, the common electrode 108b and the first electrode 108a are both derived from the same conductive material layer. However, the present disclosure is not limited to this. In some alternative embodiments, the common electrode 108b and the first electrode 108a are formed in separate processes. As Figure 2 As shown in FIG. 1 , one common electrode 108 b is provided in the peripheral region B, but the present disclosure is not limited thereto. The number of common electrodes 108 b may be more than Figure 2 The number shown in and can be specified based on requirements and / or design layout.

[0060] In some embodiments, the isolation layer 110 is disposed on the semiconductor substrate 100. In some embodiments, the material of the isolation layer 110 includes silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In some embodiments, the isolation layer 110 is an oxide-nitride-oxide (ONO) layer. In some embodiments, the isolation layer 110 is formed by a photolithography process and an etching process.

[0061] In some embodiments, the isolation layer 110 includes a first isolation pattern 112 and a second isolation pattern 114, and the first isolation pattern 112 is located around the second isolation pattern 114. In some embodiments, the first isolation pattern 112 is disposed in the peripheral region B. Figure 2 As shown in FIG. 1 , in a top view, the first isolation pattern 112 has a ring shape. In some embodiments, the first isolation pattern 112 has a first side surface S1 and a second side surface S2 opposite to the first side surface S1. The second side surface S2 of the first isolation pattern 112 faces the second isolation pattern 114. Figure 2 The second side surface S2 is closer to the pixel area A than the first side surface S1. Figure 1 In some embodiments, as shown in Figure 1 As shown in , the cross-sectional profile of the first side surface S1 and the cross-sectional profile of the second side surface S2 are substantially symmetrical to each other. The cross-sectional profile of the first side surface S1 and the cross-sectional profile of the second side surface S2 may be mirror images of each other. With this configuration, the cross-sectional profile of the first side surface S1 and the cross-sectional profile of the second side surface S2 may be considered to be substantially the same.

[0062] In some embodiments, the second isolation pattern 114 is disposed in the pixel region A. In some embodiments, the second isolation pattern 114 has a plurality of first pattern portions 114a and a plurality of second pattern portions 114b. Figure 2 As shown in , a plurality of first pattern portions 114a are arranged along a direction X perpendicular to the thickness direction Z of the semiconductor substrate 100, and a plurality of second pattern portions 114b are arranged along a direction Y perpendicular to the thickness direction Z, wherein the direction X is perpendicular to the direction Y. In some embodiments, each first pattern portion 114a extends along the direction Y, and each second pattern portion 114b extends along the direction X. Figure 2 As shown in Figure 2 As shown in FIG. 1 , the plurality of first pattern portions 114 a are connected to the plurality of second pattern portions 114 b to constitute a mesh structure.

[0063] In some embodiments, each first pattern portion 114a has a third side surface S3 and a fourth side surface S4 opposite to the third side surface S3, and each second pattern portion 114b has a fifth side surface S5 and a sixth side surface S6 opposite to the fifth side surface S5. Figure 1 As shown in , the cross-sectional profile of the third side surface S3 and the cross-sectional profile of the fourth side surface S4 are substantially symmetrical to each other. The cross-sectional profile of the third side surface S3 and the cross-sectional profile of the fourth side surface S4 may be mirror images of each other. With this configuration, the cross-sectional profile of the third side surface S3 and the cross-sectional profile of the fourth side surface S4 may be considered to be substantially the same. Similarly, as Figure 1 As shown in , the cross-sectional profile of the fifth side surface S5 and the cross-sectional profile of the sixth side surface S6 are substantially symmetrical to each other, so the cross-sectional profile of the fifth side surface S5 and the cross-sectional profile of the sixth side surface S6 can be considered to be substantially the same. In addition, in some embodiments, as Figure 1 As shown in , the cross-sectional profile of the third side surface S3 is substantially the same as the cross-sectional profile of the fifth side surface S5. That is, in the second isolation pattern 114, the first pattern portion 114a and the second pattern portion 114b have substantially the same cross-sectional profile of the side surface. In some embodiments, as Figure 1 As shown in , the cross-sectional profile of the first side surface S1 is substantially the same as the cross-sectional profile of the third side surface S3. That is, in the isolation layer 110, the first isolation pattern 112 and the second isolation pattern 114 have substantially the same cross-sectional profile of the side surface. In some embodiments, the difference in profile size between the cross-sectional profile of the side surface of the first isolation pattern 112 and the cross-sectional profile of the side surface of the second isolation pattern 114 is less than about 10%.

[0064] In some embodiments, the isolation layer 110 has a first opening O1 located in the peripheral region B and a plurality of second openings O2 located in the pixel region A. In some embodiments, some of the plurality of second openings O2 are disposed in the pixel region A and further extend into the peripheral region B, such as Figure 1 However, the present disclosure is not limited thereto. In some alternative embodiments, no second opening O2 is disposed in the peripheral region B.

[0065] Specifically, refer to Figure 1 and Figure 2 , the first opening O1 is an unclosed opening having a single sidewall defined by the isolation layer 110. The first side surface S1 of the first isolation pattern 112 can be regarded as a sidewall of the first opening O1. Figure 1 As shown in , the vertical projection of the common electrode 108b on the substrate 102 along the thickness direction Z of the semiconductor substrate 100 falls within the span of the vertical projection of the first opening O1 on the substrate 102 along the thickness direction Z of the semiconductor substrate 100. That is, during the process of manufacturing the display device 10, the common electrode 108b may be exposed by the first opening O1 in some stages.

[0066] In addition, refer to Figure 1 and Figure 2 , each second opening O2 is a closed opening, and the vertical projection of the closed opening along the thickness direction Z on the substrate 102 is rectangular. In other words, each second opening O2 has four sidewalls. However, the present disclosure is not limited to this. In some alternative embodiments, the vertical projection of each second opening O2 along the thickness direction Z on the substrate 102 may present a polygonal shape or any suitable shape in a top view. In some embodiments, the sidewalls of each second opening O2 are defined by the isolation layer 110. In detail, as Figure 2 As shown in , the sidewall of each of the plurality of second openings O2 located at the edge of the pixel region A is defined by both the first isolation pattern 112 and the second isolation pattern 114, and the sidewall of each of the plurality of second openings O2 located at the center of the pixel region A is defined only by the second isolation pattern 114. That is, the second side surface S2 of the first isolation pattern 112, the third side surface S3 and the fourth side surface S4 of the first pattern portion 114a, and the fifth side surface S5 and the sixth side surface S6 of the second pattern portion 114b can be regarded as the sidewalls of the second opening O2. Figure 1 and Figure 2 The second side surface S2 of the first isolation pattern 112, the third side surface S3 of the first pattern portion 114a, and the fifth side surface S5 of the second pattern portion 114b can be regarded as Figure 1The sidewall of the second opening O2 shown in the example on the left side, the second side surface S2 of the first isolation pattern 112, the third side surface S3 of the first pattern portion 114a, the fourth side surface S4 of the other first pattern portion 114a, and the fifth side surface S5 of the second pattern portion 114b can be regarded as Figure 1 The side wall of the exemplary central second opening O2 shown in FIG. 1 , and the third side surface S3 of the first pattern portion 114a, the fourth side surface S4 of another first pattern portion 114a, the fifth side surface S5 of the second pattern portion 114b, and the sixth side surface S6 of another second pattern portion 114b can be regarded as Figure 1 The side wall of the second right opening O2 is shown in FIG.

[0067] In some embodiments, Figure 1 and Figure 2 As shown in FIG. 1 , the plurality of second openings O2 are arranged corresponding to the plurality of first electrodes 108a underlying thereunder. Figure 1 and Figure 2 As shown in FIG. 1 , the vertical projection of the first electrode 108a on the substrate 102 along the thickness direction Z of the semiconductor substrate 100 partially overlaps the span of the vertical projection of the corresponding second opening O2 on the substrate 102 along the thickness direction Z of the semiconductor substrate 100. That is, during the process of manufacturing the display device 10, in the stage of forming the second opening O2, the first electrode 108a is partially exposed by the second opening O2. As described above, the number of the first electrodes 108a is not limited to Figure 2 Therefore, the number of the second openings O2 corresponding to the first electrode 108a is not limited to Figure 2 The number shown in and can be specified based on requirements and / or design layout.

[0068] In some embodiments, the light-emitting layer 120 is disposed on the isolation layer 110 and the plurality of first electrodes 108a. In some embodiments, the light-emitting layer 120 may be any light-emitting layer that can be used in a display device and is well known to those of ordinary skill in the art. In some embodiments, the material of the light-emitting layer 120 may include an organic light-emitting material in red, green, blue, white, other suitable colors, or a combination of the light-emitting materials. For example, in some embodiments, the light-emitting layer 120 includes a white organic light-emitting material. In some embodiments, the light-emitting layer 120 further includes other organic functional layers, such as an electron transport layer, an electron injection layer, a hole transport layer, a hole injection layer, or a combination of the functional layers.

[0069] In some embodiments, the light emitting layer 120 is discontinuously disposed on the isolation layer 110 and the plurality of first electrodes 108a. Figure 1Specifically, during the process of forming the light emitting layer 120, the light emitting layer 120 is cut by the isolation layer 110 due to the cross-sectional profile of the side surface. That is, the isolation layer 110 is configured to discontinuously arrange the light emitting layer 120. As long as the isolation layer 110 can discontinuously arrange the light emitting layer 120, the configuration of the cross-sectional profile of the side surface of the isolation layer 110 may not be limited to Figure 1 The configuration shown in and can be specified based on requirements and / or design layout.

[0070] In some embodiments, some portions of the light emitting layer 120 are disposed in the plurality of second openings O2. Figure 1 As shown in FIG. 1 , some portions of the light emitting layer 120 disposed in the plurality of second openings O2 directly contact the plurality of first electrodes 108a underlying and exposed by the second openings O2. Figure 1 As shown in FIG. 1 , some portions of the light emitting layer 120 disposed in the plurality of second openings O2 cover sidewalls of the plurality of second openings O2 defined by the isolation layer 110. That is, the second side surface S2 of the first isolation pattern 112, the third side surface S3 and the fourth side surface S4 of the first pattern portion 114a, and the fifth side surface S5 and the sixth side surface S6 of the second pattern portion 114b are covered by the light emitting layer 120.

[0071] In some embodiments, a portion of the light emitting layer 120 is disposed in the first opening O1. Figure 1 As shown in , the portion of the light emitting layer 120 disposed in the first opening O1 covers the sidewall of the first opening O1 defined by the isolation layer 110 (i.e., the first side surface S1 of the first isolation pattern 112) and a portion of the exemplary top surface of the semiconductor substrate 100 exposed by the first opening O1. That is, the portion of the light emitting layer 120 disposed in the first opening O1 extends from the first side surface S1 of the first isolation pattern 112 to the exemplary top surface of the semiconductor substrate 100 in the peripheral region B that is not covered by the first isolation pattern 112. In addition, as shown in Figure 1 As shown in , the minimum distance D between the outer edge of the portion of the light emitting layer 120 disposed in the first opening O1 and the first side surface S1 of the first isolation pattern 112 (i.e., the sidewall of the first opening O1) is equal to or greater than half of the height H of the isolation layer 110. That is, the outer edge of the portion of the light emitting layer 120 disposed in the first opening O1 protrudes toward the first side surface S1 of the first isolation pattern 112 by the minimum distance D. In other words, the semiconductor substrate 100 is covered by the portion of the light emitting layer 120 disposed in the first opening O1. Figure 1As shown in the figure, along the direction X perpendicular to the thickness direction Z of the semiconductor substrate 100, in the vertical projection on the illustrated top surface of the semiconductor substrate 100, the projection position of the outermost edge of the entire light emitting layer 120 is located at the minimum distance D next to the projection position of the outermost edge of the entire isolation layer 110.

[0072] In some embodiments, the second electrode 130 is disposed on the light emitting layer 120. In some embodiments, the second electrode 130 extends from the pixel region A toward the peripheral region B. Figure 2 In addition, in some embodiments, the second electrode 130 is disposed in the first opening O1 and the plurality of second openings O2, as shown in FIG. Figure 1 As shown in . In some embodiments, the second electrode 130 directly contacts the underlying common electrode 108b to be electrically connected to the semiconductor substrate 100. As described above, the common electrode 108b can be electrically grounded so that the second electrode 130 can also be electrically grounded. In some embodiments, the material of the second electrode 130 includes a transparent conductive material. In certain embodiments, the transparent conductive material includes or is a metal oxide conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, other suitable oxides, or a stacked layer formed by at least two of the above materials. However, the present disclosure is not limited to this. In some alternative embodiments, the material of the second electrode 130 includes an opaque conductive material. In certain embodiments, the opaque conductive material includes a metal.

[0073] In some embodiments, the first electrode 108a, the portion of the light emitting layer 120 disposed in the second opening O2 and directly contacting the underlying first electrode 108a, and the portion of the second electrode 130 overlapping the portion of the light emitting layer 120 along the thickness direction Z constitute a light emitting element. In the display device 10, a plurality of light emitting elements are disposed in the pixel area A. Since the number of the first electrode 108a is not limited to Figure 2 Therefore, the number of light-emitting elements in the display device 10 is not limited to Figure 2, and can be specified based on demand and / or design layout. In some embodiments, the light-emitting element may be an OLED element. In detail, the light-emitting layer 120 of the light-emitting element is driven to emit light by the voltage difference generated between the first electrode 108a and the second electrode 130. Since the drive signal can be transmitted to the first electrode 108a through the active components (not shown) in the driving element layer 104, the light-emitting element in the display device 10 can be controlled by the active components (not shown) in the driving element layer 104. In some embodiments, the first electrode 108a acts as an anode of the light-emitting element, and the second electrode 130 acts as a cathode of the light-emitting element. However, the present disclosure is not limited to this. In some alternative embodiments, according to design requirements, the first electrode 108a acts as a cathode of the light-emitting element, and the second electrode 130 acts as an anode of the light-emitting element.

[0074] In some embodiments, the second electrode 130 is continuously disposed on the light emitting layer 120 and the common electrode 108b. Figure 1 . Specifically, since the side surfaces of the isolation layer 110 (e.g., the first side surface S1 and the second side surface S2 of the first isolation pattern 112, the third side surface S3 and the fourth side surface S4 of the first pattern portion 114a, and the fifth side surface S5 and the sixth side surface S6 of the second pattern portion 114b) are covered by the light-emitting layer 120, the second electrode 130 is raised by the underlying light-emitting layer 120, so that the second electrode 130 is away from the side surface of the isolation layer 110 that will make the layer (e.g., the light-emitting layer 120) discontinuous. In addition, when the minimum distance D between the outer edge of the portion of the light-emitting layer 120 disposed in the first opening O1 and the first side surface S1 of the first isolation pattern 112 is equal to or greater than half of the height H of the isolation layer 110, the second electrode 130 raised by the underlying light-emitting layer 120 can avoid being cut by the isolation layer 110. In this way, the second electrode 130 has good continuity, and thus the electrical yield of the display device 10 can be ensured.

[0075] In some embodiments, the dielectric encapsulant 140 encapsulates and covers the second electrode 130. In some embodiments, the dielectric encapsulant 140 is filled into the first opening O1 to encapsulate the second electrode 130 in the lateral direction. In some embodiments, the dielectric encapsulant 140 encapsulates the light emitting element in the display device 10 to isolate the light emitting element from moisture, impurities, etc. In some embodiments, the material of the dielectric encapsulant 140 includes silicon oxide, silicon nitride, aluminum oxide, silicon carbonitride (SiCN), silicon oxynitride, acrylic resin, hexamethyl disiloxane (HMDSO) or glass, but the present invention is not limited thereto.

[0076] The following will refer to FIG. 3A to FIG. 3F as well as Figure 4 A method of manufacturing the display device 10 is explained in detail. FIG. 3A to FIG. 3F are schematic cross-sectional views of various stages in a method for manufacturing a display device 10 according to some embodiments of the present disclosure. Figure 4 is a simplified top view of an intermediate stage in a method of manufacturing a display device 10 according to some embodiments of the present disclosure. Specifically, Figure 3A is along Figure 4 A cross-sectional view taken along line II-II' is shown.

[0077] Reference Figure 3A and Figure 4 , provide a semiconductor substrate 100. In some embodiments, the semiconductor substrate 100 may be a semiconductor wafer. FIG. 3A to FIG. 3F The manufacturing method of the display device 10 illustrated in FIG. 1 can be regarded as a wafer level process. Figure 4 As shown in FIG. 1 , the semiconductor substrate 100 has a plurality of device units DU arranged in an array. Each device unit DU corresponds to a portion of the semiconductor wafer. Figure 4 As shown in , a plurality of device units DU are defined by a plurality of cutting lanes SL1 and a plurality of cutting lanes SL2. Figure 4 As shown in , a plurality of scribe lines SL1 are arranged along a direction X perpendicular to the thickness direction Z of the semiconductor substrate 100, and a plurality of scribe lines SL2 are arranged along a direction Y perpendicular to the thickness direction Z, wherein the direction X is perpendicular to the direction Y. In some embodiments, each scribe line SL1 extends along the direction Y, and each scribe line SL2 extends along the direction X. Figure 4 In addition, Figure 4 As shown in FIG, a plurality of scribe lines SL1 cross a plurality of scribe lines SL2 to provide a plurality of columns and a plurality of rows. The number of device units DU, the number of scribe lines SL1, and the number of scribe lines SL2 may be less than or greater than Figure 4 The number shown in the figure can be specified based on requirements and / or design layout; the present disclosure is not particularly limited thereto.

[0078] In some embodiments, Figure 4 As shown in FIG. 1 , each of the plurality of device units DU has a pixel region A and a peripheral region B inside. Figure 3A At the stage shown, the semiconductor substrate 100 may have a plurality of pixel regions A arranged in an array. The details of the pixel region A and the peripheral region B have been described above and will not be repeated herein. Figure 3A As shown in , each of the plurality of device units DU may include a substrate 102, a driving element layer 104, an interconnect structure 106, a plurality of first electrodes 108a and a common electrode 108b. Figure 3AAt the stage shown, the substrates 102 of the plurality of device units DU are connected to each other. Similarly, in some embodiments, Figure 3A At the stage shown, the driving element layers 104 of the plurality of device units DU are connected to each other, and the interconnect structures 106 of the plurality of device units DU are connected to each other. The details of the substrate 102, the driving element layer 104, the interconnect structure 106, the first electrode 108a and the common electrode 108b have been described above and will not be repeated herein.

[0079] Reference Figure 3B , an isolation layer 110' is formed on the semiconductor substrate 100 to cover the first electrode 108a and the common electrode 108b. In some embodiments, the material of the isolation layer 110' includes silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In some embodiments, the isolation layer 110' is an oxide-nitride-oxide (ONO) layer. In some embodiments, the isolation layer 110' is formed by chemical vapor deposition (CVD) or any other suitable film deposition method.

[0080] Reference Figure 3C , the isolation layer 110' is patterned to form the isolation layer 110. In some embodiments, the isolation layer 110 is formed by performing a photolithography process and an etching process. In some embodiments, the isolation layer 110 is formed by at least the following steps. First, a photoresist layer (not shown) is formed on the isolation layer 110'. In some embodiments, the photoresist layer can be formed by spin coating or other suitable methods. Thereafter, the photoresist layer is patterned to form a patterned photoresist layer, and the isolation layer 110' is etched using the patterned photoresist layer as a mask to form the isolation layer 110. The patterned photoresist layer is then removed or stripped. In some embodiments, the isolation layer 110' is etched by a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the patterned photoresist layer can be removed or stripped by, for example, etching, ashing, or other suitable removal processes.

[0081] In some embodiments, Figure 3C As shown in FIG. 1 , the isolation layer 110 includes a first isolation pattern 112 and a second isolation pattern 114, and the second isolation pattern 114 has a plurality of first pattern portions 114a and a plurality of second pattern portions 114b. Figure 3C In the figure, for the sake of simplicity, a first pattern portion 114a and a second pattern portion 114b are shown. Figure 1 and Figure 2 As described above, those skilled in the art can understand that a plurality of first pattern portions 114a and a plurality of second pattern portions 114b can be formed to provide a grid structure.

[0082] In some embodiments, Figure 3C As shown in , the cross-sectional profile of the first side surface S1 of the first isolation pattern 112 and the cross-sectional profile of the second side surface S2 of the first isolation pattern 112 are substantially symmetrical to each other. The cross-sectional profile of the third side surface S3 of the first pattern portion 114a and the cross-sectional profile of the fourth side surface S4 of the first pattern portion 114a are substantially symmetrical to each other. The cross-sectional profile of the fifth side surface S5 of the second pattern portion 114b and the cross-sectional profile of the sixth side surface S6 of the second pattern portion 114b are substantially symmetrical to each other. The cross-sectional profile of the first side surface S1, the cross-sectional profile of the third side surface S3, and the cross-sectional profile of the fifth side surface S5 are substantially the same as each other. The cross-sectional profile of the second side surface S2, the cross-sectional profile of the fourth side surface S4, and the cross-sectional profile of the sixth side surface S6 are substantially the same as each other. In this way, the cross-sectional profile of the first side surface S1, the cross-sectional profile of the second side surface S2, the cross-sectional profile of the third side surface S3, the cross-sectional profile of the fourth side surface S4, the cross-sectional profile of the fifth side surface S5, and the cross-sectional profile of the sixth side surface S6 can be considered to be substantially the same as each other. In view of this, the isolation layer 110 may be formed by performing a photolithography process using a single mask. As a result, the isolation layer 110 may be formed in a simple and low-cost process.

[0083] Furthermore, in some embodiments, Figure 3C As shown in FIG. 1 , after the isolation layer 110 ′ is patterned, a first opening O1 and a plurality of second openings O2 are formed in the isolation layer 110 . Figure 3C As shown in FIG. 1 , the common electrode 108 b is exposed by the first opening O1 , and some portions of the plurality of first electrodes 108 a are exposed by the plurality of second openings O2 . Other details of the isolation layer 110 have been described above and will not be repeated herein.

[0084] Reference Figure 3D , a light emitting layer 120 is formed on the isolation layer 110 and in the first opening O1 and the plurality of second openings O2. The light emitting layer 120 is disposed in both the pixel region A and the peripheral region B. In some embodiments, the light emitting layer 120 is formed by evaporation or any other suitable film deposition method. Figure 3D As shown in FIG. 1 , the light emitting layer 120 is formed using a first mask M1 having a first opening pattern OP1. Figure 3D In the figure, for the sake of simplicity, a first opening pattern OP1 is shown. Figure 3A and Figure 4 As described above, those skilled in the art can understand that a plurality of first opening patterns OP1 corresponding to a plurality of device units DU are formed in the first mask M1.

[0085] In some embodiments, the first opening pattern OP1 is provided to define the position of the light emitting layer 120. In some embodiments, the first opening pattern OP1 exposes the isolation layer 110 in the thickness direction Z of the semiconductor substrate 100. Figure 3D As shown in , due to the cross-sectional profile of the side surface of the isolation layer 110, the light emitting layer 120 is discontinuously formed on the isolation layer 110. That is, even if the entire isolation layer 110 is exposed by the first opening pattern OP1, some portions 110p of the isolation layer 110 are still not covered by the light emitting layer 120. In some embodiments, the minimum distance D2 between the boundary of the first opening pattern OP1 and the first side surface S1 of the first isolation pattern 112 is equal to or greater than half of the height H of the isolation layer 110. Using such a positional relationship between the first mask M1 and the isolation layer 110, the minimum distance D between the outer edge of the portion of the light emitting layer 120 disposed in the first opening O1 and the first side surface S1 of the first isolation pattern 112 is equal to or greater than half of the height H of the isolation layer 110. Other details of the light emitting layer 120 have been described above and will not be repeated herein.

[0086] Reference Figure 3E , forming a second electrode 130 on the light emitting layer 120. In some embodiments, the second electrode 130 is formed by evaporation, chemical vapor deposition (CVD), physical vapor deposition (PVD) or any other suitable film deposition method. Figure 3E As shown in FIG. , the second electrode 130 is formed using a second mask M2 having a second opening pattern OP2. Figure 3E In the figure, for the sake of simplicity, a second opening pattern OP2 is shown. Figure 3A and Figure 4 As illustrated in FIG. 1 and described above, a plurality of second opening patterns OP2 corresponding to the plurality of device units DU may be formed in the second mask M2 .

[0087] In some embodiments, the second opening pattern OP2 is provided to define the position of the second electrode 130. In some embodiments, the second opening pattern OP2 exposes the light emitting layer 120 in the thickness direction Z of the semiconductor substrate 100. Figure 3EAs shown in , the second electrode 130 is formed to extend continuously from the pixel region A to the peripheral region B over the semiconductor substrate 100. Specifically, the second electrode 130 is elevated by the underlying light emitting layer 120, so that the second electrode 130 is away from the side surface of the isolation layer 110 that causes discontinuity of the layer (e.g., the light emitting layer 120). In addition, in some embodiments, the minimum distance D of the light emitting layer 120 extending to the illustrated top surface of the semiconductor substrate 100 in the peripheral region B is equal to or greater than half of the height H of the isolation layer 110, so that the second electrode 130 elevated by the underlying light emitting layer 120 can avoid being cut by the isolation layer 110. In this way, the second electrode 130 is formed to have good continuity, and thus the electrical yield of the display device 10 can be ensured. By arranging the minimum distance D to be equal to or greater than half of the height H of the isolation layer 110, even if the isolation layer 110 is formed using a single mask so that all side surfaces have a consistent cross-sectional profile that would destroy the layers formed on the isolation layer 110, the second electrode 130 can be continuously formed on the semiconductor substrate 100 to ensure the electrical yield of the display device 10. Therefore, the complexity and cost of manufacturing the display device 10 are reduced, and the yield and performance of the display device 10 are improved.

[0088] In some embodiments, the second opening pattern OP2 exposes the common electrode 108b in the thickness direction Z of the semiconductor substrate 100. The second electrode 130 formed using the second mask M2 directly contacts the underlying common electrode 108b to provide electrical connection with the semiconductor substrate 100. Other details of the second electrode 130 have been described above and will not be repeated herein.

[0089] Reference Figure 3F , a dielectric encapsulation body 140 is formed on the second electrode 130. In some embodiments, as Figure 3F As shown in , the dielectric encapsulant 140 is completely formed on the semiconductor substrate 100. In some embodiments, the dielectric encapsulant 140 is formed by chemical vapor deposition (CVD), evaporation, or any other suitable fabrication technique. Other details of the dielectric encapsulant 140 have been described above and will not be repeated herein.

[0090] After the dielectric encapsulation body 140 is formed, a singulation process is performed to cut the semiconductor substrate 100 and the dielectric encapsulation body 140 to provide a plurality of display devices 10. For example, by Figure 4The display device 10 is cut by cutting the plurality of cutting lanes SL1 and the plurality of cutting lanes SL2 arranged between the plurality of device units DU as shown in the figure to perform a singulation process to separate the individual display devices 10. The singulation process may be a laser cutting process, a mechanical cutting process, or other suitable processes. In some embodiments, the singulation process is performed by cutting by a rotating blade or a laser beam. In some embodiments, the display device 10 is suitable for near-eye display applications.

[0091] Although each process is shown and described as a series of actions or events, it should be understood that the illustrated order of such actions or events is not to be interpreted as having a limiting meaning. In addition, not all illustrated processes are required to implement one or more embodiments of the present disclosure.

[0092] exist FIG. 3A to FIG. 3F In the manufacturing method of the display device 10 shown in , the light emitting layer 120 is formed to cover the semiconductor substrate 100 in the peripheral area B within the range of the minimum distance D, and the first isolation pattern 112 of the isolation layer 110 is formed not to directly contact the common electrode 108b. The formation of the isolation layer 110 can be completed by using a mask pull-back process. In some embodiments, the mask pull-back process includes widening the opening pattern in the mask for defining the first opening O1 of the isolation layer 110. However, the present disclosure is not limited to this. In the following, reference will be made to Figure 5 Other embodiments are described.

[0093] Figure 5 is a schematic cross-sectional view of a display device according to some alternative embodiments of the present disclosure. Figure 5 and Figure 1 , Figure 5 The display device 20 is shown with the example being Figure 2 The cross section taken along line II' is Figure 1 The display device 20 is similar to the display device 10. Therefore, the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. The differences between the display device 20 and the display device 10 are described below.

[0094] Reference Figure 5 In the display device 20, the light emitting layer 120 covers the semiconductor substrate 100 in the peripheral region B within the range of the minimum distance D, and the first isolation pattern 112 of the isolation layer 110 is formed to directly contact the common electrode 108b. In this case, the formation of the light emitting layer 120 can be completed by using a mask pull-back process. In the mask pull-back process for forming the light emitting layer 120, the first opening pattern OP1 (such as the first opening pattern OP2 of the first mask M1) for defining the position of the light emitting layer 120 is formed. Figure 3D ) may be widened to expose both the isolation layer 110 and the common electrode 108b.

[0095] According to some embodiments, a display device includes a semiconductor substrate, an isolation layer, a light-emitting layer, and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region, wherein the semiconductor substrate includes a plurality of first electrodes and a driving element layer. The plurality of first electrodes are arranged in the pixel region and the plurality of first electrodes are electrically connected to the driving element layer. The isolation layer is arranged on the semiconductor substrate, wherein the isolation layer includes a first isolation pattern arranged in the peripheral region, the first isolation pattern having a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is arranged on the isolation layer and the plurality of first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is arranged on the light-emitting layer.

[0096] In some embodiments, the second side surface is closer to the pixel region than the first side surface, and a minimum distance between an outer edge of the light emitting layer and the first side surface is equal to or greater than half a height of the isolation layer.

[0097] In some embodiments, the isolation layer also includes a second isolation pattern arranged in the pixel area, the second isolation pattern having a plurality of first pattern portions and a plurality of second pattern portions, the plurality of first pattern portions being arranged along a first direction, the plurality of second pattern portions being arranged along a second direction, the first direction being perpendicular to the second direction, and each of the plurality of first pattern portions having a third side surface and a fourth side surface opposite to the third side surface.

[0098] In some embodiments, a cross-sectional profile of the first side surface, a cross-sectional profile of the second side surface, a cross-sectional profile of the third side surface, and a cross-sectional profile of the fourth side surface are substantially the same.

[0099] In some embodiments, the semiconductor substrate further includes a common electrode disposed in the peripheral region and electrically connected to the second electrode.

[0100] In some embodiments, the light-emitting layer is discontinuously disposed on the isolation layer and the plurality of first electrodes, and the second electrode is continuously disposed on the light-emitting layer.

[0101] In some embodiments, the first isolation pattern has a ring shape.

[0102] In some embodiments, the display device further includes a dielectric encapsulant encapsulating and covering the second electrode.

[0103] According to some embodiments, a display device includes a semiconductor substrate, an isolation layer, a light-emitting layer, and a second electrode. The semiconductor substrate has a pixel region and a peripheral region around the pixel region, wherein the semiconductor substrate includes a plurality of first electrodes and a driving element layer. The plurality of first electrodes are arranged in the pixel region, and the plurality of first electrodes are electrically connected to the driving element layer. The isolation layer is arranged on the semiconductor substrate, wherein the isolation layer includes a first opening in the peripheral region and a plurality of second openings in the pixel region. The light-emitting layer is arranged on the isolation layer and in the first opening and the plurality of second openings. The second electrode is arranged on the light-emitting layer.

[0104] In some embodiments, the light emitting layer covers a sidewall of the first opening defined by the isolation layer and a plurality of sidewalls of the plurality of second openings defined by the isolation layer.

[0105] In some embodiments, the light emitting layer disposed in the plurality of second openings contacts the plurality of first electrodes.

[0106] In some embodiments, a minimum distance between an outer edge of the light emitting layer disposed in the first opening and the sidewall of the first opening defined by the isolation layer is equal to or greater than half a height of the isolation layer.

[0107] In some embodiments, a cross-sectional profile of the sidewall of the first opening defined by the isolation layer is substantially the same as a cross-sectional profile of each of the plurality of sidewalls of the plurality of second openings defined by the isolation layer.

[0108] In some embodiments, the display device further includes a dielectric encapsulation body encapsulating the second electrode and filling the first opening.

[0109] According to some embodiments, a method for manufacturing a display device includes at least the following steps. A semiconductor substrate having a plurality of device units is provided, wherein each of the plurality of device units has a pixel region and a peripheral region located around the pixel region, and the semiconductor substrate includes a plurality of first electrodes and a driving element layer. The plurality of first electrodes are arranged in the pixel region, and the plurality of first electrodes are electrically connected to the driving element layer. An isolation layer is formed on the semiconductor substrate. The isolation layer is patterned to form a first opening in the peripheral region and a plurality of second openings in the pixel region, wherein the plurality of second openings expose the plurality of first electrodes. A light-emitting layer is formed on the patterned isolation layer and in the first opening and the plurality of second openings. A second electrode is formed on the light-emitting layer.

[0110] In some embodiments, patterning the isolation layer includes performing a photolithography process on the isolation layer using a single mask.

[0111] In some embodiments, forming the light-emitting layer includes: providing a first mask having a first opening pattern; and performing a first deposition process to form the light-emitting layer on the patterned isolation layer corresponding to the first opening pattern of the first mask, wherein the first opening pattern exposes the patterned isolation layer in a thickness direction of the semiconductor substrate.

[0112] In some embodiments, during the first deposition process, a minimum distance between a boundary of the first opening pattern of the first mask and a sidewall of the first opening defined by the patterned isolation layer is equal to or greater than half a height of the patterned isolation layer.

[0113] In some embodiments, forming the second electrode includes: providing a second mask having a second opening pattern; and performing a second deposition process to form the second electrode on the light-emitting layer corresponding to the second opening pattern of the second mask, wherein the second opening pattern exposes the light-emitting layer in the thickness direction of the semiconductor substrate.

[0114] In some embodiments, the method for manufacturing the display device further includes: forming a dielectric encapsulation body on the second electrode; and performing a singulation process to cut the semiconductor substrate and the dielectric encapsulation body.

[0115] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: A semiconductor substrate having a pixel region and a peripheral region around the pixel region, wherein the semiconductor substrate comprises a plurality of first electrodes and a driving element layer, the plurality of first electrodes are disposed in the pixel region, and the plurality of first electrodes are electrically connected to the driving element layer; an isolation layer disposed on the semiconductor substrate, wherein the isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface; a light-emitting layer, disposed on the isolation layer and the plurality of first electrodes, and covering the first side surface and the second side surface of the first isolation pattern, wherein the second side surface is closer to the pixel region than the first side surface, and a minimum distance between an outer edge of the light-emitting layer and the first side surface is equal to or greater than half a height of the isolation layer; as well as The second electrode is arranged on the light-emitting layer.

2. The display device according to claim 1, wherein the isolation layer further comprises a second isolation pattern arranged in the pixel area, the second isolation pattern having a plurality of first pattern portions and a plurality of second pattern portions, the plurality of first pattern portions being arranged along a first direction, the plurality of second pattern portions being arranged along a second direction, the first direction being perpendicular to the second direction, and each of the plurality of first pattern portions having a third side surface and a fourth side surface opposite to the third side surface. 3 . The display device according to claim 2 , wherein the cross-sectional profile of the first side surface, the cross-sectional profile of the second side surface, the cross-sectional profile of the third side surface, and the cross-sectional profile of the fourth side surface pixel are substantially the same. 4 . The display device according to claim 1 , wherein the semiconductor substrate further comprises a common electrode disposed in the peripheral region and electrically connected to the second electrode. 5 . The display device according to claim 1 , wherein the light emitting layer is discontinuously disposed on the isolation layer and the plurality of first electrodes, and the second electrode is continuously disposed on the light emitting layer. The display device according to claim 1 , wherein the first isolation pattern has a ring shape. 7 . The display device according to claim 1 , further comprising a dielectric encapsulant encapsulating and covering the second electrode.

8. A display device comprising: A semiconductor substrate having a pixel region and a peripheral region around the pixel region, wherein the semiconductor substrate comprises a plurality of first electrodes and a driving element layer, the plurality of first electrodes are disposed in the pixel region, and the plurality of first electrodes are electrically connected to the driving element layer; an isolation layer disposed on the semiconductor substrate, wherein the isolation layer comprises a first opening located in the peripheral region and a plurality of second openings located in the pixel region; a light-emitting layer disposed on the isolation layer and in the first opening and the plurality of second openings, wherein a minimum distance between an outer edge of the light-emitting layer disposed in the first opening and a sidewall of the first opening defined by the isolation layer is equal to or greater than half a height of the isolation layer; as well as The second electrode is arranged on the light-emitting layer. 9 . The display device according to claim 8 , wherein the light emitting layer covers a sidewall of the first opening defined by the isolation layer and a plurality of sidewalls of the plurality of second openings defined by the isolation layer. 10 . The display device according to claim 8 , wherein the light emitting layer disposed in the plurality of second openings contacts the plurality of first electrodes. 11 . The display device according to claim 9 , wherein a cross-sectional profile of the sidewall of the first opening defined by the isolation layer is substantially the same as a cross-sectional profile of each of the plurality of sidewalls of the plurality of second openings defined by the isolation layer. 12 . The display device according to claim 8 , further comprising a dielectric encapsulation body encapsulating the second electrode and filling in the first opening.

13. A method for manufacturing a display device, comprising: Providing a semiconductor substrate having a plurality of device units, wherein each of the plurality of device units has a pixel region and a peripheral region located around the pixel region, the semiconductor substrate comprising a plurality of first electrodes and a driving element layer, the plurality of first electrodes being disposed in the pixel region and the plurality of first electrodes being electrically connected to the driving element layer; forming an isolation layer on the semiconductor substrate; patterning the isolation layer to form a first opening in the peripheral region and a plurality of second openings in the pixel region, wherein the plurality of second openings expose the plurality of first electrodes; Forming a light-emitting layer on the patterned isolation layer and in the first opening and the plurality of second openings, wherein forming the light-emitting layer comprises: providing a first mask having a first opening pattern; and performing a first deposition process to form the light emitting layer on the patterned isolation layer corresponding to the first opening pattern of the first mask, wherein the first opening pattern exposes the patterned isolation layer in a thickness direction of the semiconductor substrate; and A second electrode is formed on the light emitting layer.

14. The method for manufacturing a display device according to claim 13, wherein patterning the isolation layer comprises: A photolithography process is performed on the isolation layer using a single mask.

15. The method for manufacturing a display device according to claim 13, wherein during the first deposition process, a minimum distance between a boundary of the first opening pattern of the first mask and a sidewall of the first opening defined by the patterned isolation layer is equal to or greater than half a height of the patterned isolation layer.

16. The method for manufacturing a display device according to claim 13, wherein forming the second electrode comprises: providing a second mask having a second opening pattern; as well as A second deposition process is performed to form the second electrode on the light emitting layer corresponding to the second opening pattern of the second mask, wherein the second opening pattern exposes the light emitting layer in the thickness direction of the semiconductor substrate.

17. The method for manufacturing a display device according to claim 13, further comprising: forming a dielectric encapsulation over the second electrode; as well as A singulation process is performed to cut the semiconductor substrate and the dielectric encapsulation.

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