Chip-level GaAs etching temperature control method

Abstract

The invention discloses a chip-level GaAs etching temperature control method, which comprises the following steps: detecting the upper surface temperature of a GaAs wafer in the etching process in real time to obtain first temperature data; and according to a partition structure in the electrostatic chuck and the first temperature data, determining a to-be-adjusted electrostatic chuck partition and determining a second temperature of the upper surface of the carried GaAs wafer corresponding to the to-be-adjusted electrostatic chuck partition. And on the basis of the second temperature data and the target temperature, power adjustment is carried out on the heating unit of the to-be-adjusted electrostatic chuck partition through the partition temperature PID control module, and the second temperature data is adjusted to the target temperature. According to the invention, the power of the local heating unit is adjusted according to the wafer surface temperature data obtained in real time by using the partition temperature PID control module, and the temperature of each area is ensured to be uniform and stable. The control coefficient of the PID controller is optimized in an auxiliary mode through the neural network, and the self-adaptive capacity and the control precision of the system are improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a chip-level GaAs etching temperature control method. Background Art

[0002] In the current field of microelectronics manufacturing and nanotechnology, the etching process plays a vital role. It is the core step in the preparation of precision structures such as integrated circuits (ICs), thin film devices, and quantum chips. Traditional etching methods usually use dry etching or wet etching technology to accurately remove materials on the surface of semiconductor wafers to form a predetermined microscopic geometric structure.

[0003] Among them, the non-uniformity of temperature distribution during the etching process is a particularly prominent problem. Although traditional etching equipment can control the overall temperature to a certain extent, in actual operation, different locations on the wafer surface may experience different degrees of temperature changes due to factors such as heat conduction efficiency, gas flow, and local heat source effects. This temperature non-uniformity will directly lead to differences in etching rates in different areas of the wafer surface, the so-called "hot spots" and "cold spots" phenomenon, thereby affecting the consistency of etching depth and the verticality of the sidewall profile, and further affecting the precise control of the final circuit component size and the stability of electrical performance.

[0004] At present, it is difficult to accurately compensate for the uneven heat distribution and temperature changes caused by material removal during GaAs chip etching by controlling the temperature of the internal partitions of the electrostatic chuck. Especially for etching tasks of GaAs chips with large areas, high aspect ratios or three-dimensional structures, the heat conduction efficiency and thermal response time between the wafer surface and the electrostatic chuck below limit the effectiveness of this local temperature control. Summary of the invention

[0005] In order to solve at least one of the technical problems mentioned above, the present invention provides a chip-level GaAs etching temperature control to solve the problems of insufficient temperature control accuracy, local temperature unevenness and inability to adaptively adjust PID control parameters in real time during chip-level GaAs etching.

[0006] On the one hand, a chip-level GaAs etching temperature control method is provided, comprising:

[0007] Real-time detection of the upper surface temperature of the GaAs wafer during the etching process to obtain first temperature data;

[0008] According to the partition structure inside the electrostatic chuck and the first temperature data, the electrostatic chuck partition to be adjusted and the second temperature data are determined. The second temperature data is the temperature of the upper surface of the GaAs wafer carried by the electrostatic chuck partition to be adjusted.

[0009] Based on the second temperature data and the preset target temperature, the power of the heating unit of the partition of the electrostatic chuck to be adjusted is adjusted through the partition temperature PID control module to adjust the second temperature data to the target temperature.

[0010] Preferably, the method further comprises:

[0011] According to the first temperature data, a maximum temperature value of the upper surface of the GaAs wafer is obtained;

[0012] When the maximum temperature value of the upper surface of the GaAs wafer is greater than a preset maximum temperature threshold, the RF power is adjusted by the RF power PID control module based on the first temperature data until the maximum temperature value of the upper surface of the GaAs wafer is less than or equal to the preset maximum temperature threshold.

[0013] Preferably, the method further comprises:

[0014] Obtaining etching layer parameters of each etching layer of the GaAs wafer, wherein the etching layer parameters include the number of etching layers, the thickness of the etching layer, and the cross-sectional area of ​​the etching layer;

[0015] Acquire the temperature of the lower surface of the GaAs wafer carried by the partition of the electrostatic chuck to be adjusted, obtain third temperature data, and obtain the temperature difference between the upper and lower surfaces of the GaAs wafer according to the second temperature data and the third temperature data;

[0016] The temperature difference between the upper and lower surfaces of the GaAs wafer and the etching layer parameters are input into a heat transfer model to obtain adjustment heat data, and the initial adjustment power of the electrostatic chuck partition to be adjusted is determined according to the adjustment heat data.

[0017] Preferably, the heat transfer model is expressed as follows:

[0018]

[0019] Where Q is the heat provided by the electrostatic chuck partition to be adjusted, R is the number of etching layers of the GaAs wafer, and h r represents the thickness of the rth etched layer of the GaAs wafer, k r represents the thermal conductivity of the rth etched layer of the GaAs wafer, S r Represents the cross-sectional area of ​​the rth etched layer of the GaAs wafer, S represents the average cross-sectional area of ​​the etched layer of the GaAs wafer, ΔT represents the temperature difference between the upper and lower surfaces of the GaAs wafer, and r∈[1,R] is a natural number.

[0020] Preferably, the partition temperature PID control module and the RF power PID control module respectively use a neural network model for real-time optimization, specifically including: using a neural network model to dynamically calculate and update in real time the proportional coefficient, integral coefficient and differential coefficient of their PID controllers.

[0021] Preferably, the neural network model is expressed as:

[0022]

[0023]

[0024] Where I(t) is the input of the neural network model, T(t) represents the second temperature data at time t, e(t) represents the temperature error at time t, j is the number of nodes in the hidden layer of the neural network model, O j is the output result of the jth node in the hidden layer of the neural network model, M p (t) is the proportional coefficient of the PID controller, M i (t) is the integral coefficient of the PID controller, M d (t) is the differential coefficient of the PID controller, and is the weight coefficient from the neural network input layer to the hidden layer, and is the weight coefficient from the hidden layer to the output layer of the neural network model, f(x) is the hidden layer activation function, and g(x) is the output layer characteristic function.

[0025] Preferably, the neural network model uses mean square error as the loss function.

[0026] Preferably, the real-time detection of the upper surface temperature of the GaAs wafer during the etching process to obtain the first temperature data includes:

[0027] The upper surface temperature of the GaAs wafer is monitored in real time using a non-contact infrared temperature sensor to obtain a temperature distribution matrix.

[0028] Preferably, the method of using a non-contact infrared temperature sensor to monitor the upper surface temperature of the GaAs wafer in real time and obtaining a temperature distribution matrix further includes preprocessing the temperature distribution matrix. The specific process is expressed as follows:

[0029] Filter out abnormal temperature points, as shown below:

[0030] |T ij -μ|>θ·σ T ,

[0031] Among them, T ijrepresents the abnormal temperature value, i and j represent the row index and column index of the temperature distribution matrix respectively, μ represents the average temperature in the chip area, σ T represents the standard deviation of the temperature in the chip area, and θ represents the threshold coefficient;

[0032] For abnormal temperature value T ij Replace it as follows:

[0033]

[0034] Among them, T ′ (x) represents the abnormal temperature value T ij The replacement value, N represents the number of sampling points, x represents the coordinates of the target point to be replaced, c n represents the coordinates of the nth sampling point, ω n represents the weight coefficient, ||xc n || represents the Euclidean distance from the target point to the nth sampling point, and σ represents the standard deviation of the Gaussian kernel.

[0035] Preferably, when it is detected that the maximum temperature value of the upper surface of the GaAs wafer is greater than a preset maximum temperature threshold, the chip in the corresponding area is recorded as an etching temperature abnormality chip, and the test weight of the etching temperature abnormality chip is calculated based on the difference between the maximum temperature value and the maximum temperature threshold.

[0036] The beneficial effects of the present invention are:

[0037] (1) Compared with the prior art that only relies on monitoring the temperature of the back of the electrostatic chuck for indirect control, this solution ingeniously sets the temperature feedback point directly on the surface of the GaAs wafer, and uses high-precision sensors to collect and analyze the surface temperature data of each partition in real time, ensuring accurate perception and real-time monitoring of temperature changes during the etching process. The present invention adopts a partition temperature PID control module, which can realize accurate dynamic adjustment of the power of the local heating unit according to the surface temperature distribution of the GaAs wafer in different regions. When it is detected that the actual temperature of one or some areas deviates from the preset target temperature range, the module will respond immediately and adjust the heating power of the corresponding electrostatic chuck partition, thereby effectively ensuring the consistency and stability of the surface temperature of the entire wafer, and reducing process deviations and product defects caused by uneven temperature.

[0038] (2) The present invention introduces a radio frequency power PID control module. When the system detects that the maximum temperature on the surface of the GaAs wafer exceeds the preset maximum threshold, an advanced neural network algorithm is used to predict the optimal radio frequency power parameters, and the output power of the radio frequency source is adjusted accordingly to reduce the etching rate, thereby controlling the temperature rise during the entire etching process, avoiding overheating problems, and ensuring the quality and production safety of semiconductor devices.

[0039] (3) The present invention utilizes a neural network model to learn and update the proportional coefficient, integral coefficient, and differential coefficient of the PID controller in real time, so that the control system can better adapt to various complex working conditions and environmental changes, improve the system's adaptability and control performance, and make temperature control more accurate, stable, and robust, laying a solid foundation for improving the yield and reliability of semiconductor device manufacturing processes.

[0040] (4) The present invention determines the initial adjustment amount based on the heat transfer model, so that the etching temperature of the GaAs wafer can be quickly stabilized within the ideal range, which significantly improves the accuracy and response speed of temperature control.

[0041] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0043] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to illustrate the technical solutions disclosed in the present invention.

[0044] Figure 1 A schematic flow chart of a chip-level GaAs etching temperature control method provided by an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of a work flow of a zone temperature PID control module provided in an embodiment of the present invention;

[0046] Figure 3 A schematic diagram of the working process of a radio frequency power PID control module provided in an embodiment of the present invention;

[0047] Figure 4 A schematic diagram of a neural network model structure provided by another embodiment of the present invention;

[0048] Figure 5 A schematic structural diagram of a chip-level GaAs etching temperature control system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0051] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0052] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0053] In addition, in order to better illustrate the present invention, numerous specific details are provided in the following specific embodiments. It should be understood by those skilled in the art that the present invention can be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0054] At present, there are problems in the chip-level GaAs etching process, such as insufficient temperature control accuracy, uneven local temperature, and inability to adaptively adjust PID control parameters in real time.

[0055] Example 1

[0056] This application provides a chip-level GaAs etching temperature control method, referring to Figure 1 , including the steps of:

[0057] S100, detecting the upper surface temperature of the GaAs wafer during the etching process in real time to obtain first temperature data;

[0058] In this embodiment, a high-precision, non-contact infrared thermal imager system is installed in the etching chamber of the semiconductor etching equipment to perform real-time and continuous temperature monitoring of the GaAs wafer, and the acquired continuous temperature signal is converted into first temperature data in a digital format to ensure that the temperature distribution of each point on the wafer surface can be accurately reflected.

[0059] The first temperature data includes, but is not limited to, a temperature distribution matrix.

[0060] In one possible embodiment, the first temperature data acquired in real time is converted into a two-dimensional or three-dimensional temperature distribution matrix, and the matrix is ​​presented as an intuitive temperature distribution thermal imaging diagram in a color-coded manner. On the thermal imaging diagram, different colors represent different temperature ranges, thereby clearly showing the precise temperature state and distribution trend of each area on the surface of the GaAs wafer. The technician can monitor this thermal imaging diagram in real time during the etching process. Once an abnormal temperature area is found, the electrostatic chuck partition to be adjusted can be quickly located, and based on the problems reflected in the thermal imaging diagram, combined with professional knowledge and experience, the relevant parameters of the etcher are manually adjusted at the first time, including but not limited to the power allocation of the heating unit, PID controller parameter optimization, etc., to ensure the temperature consistency of the entire GaAs wafer during the etching process, and effectively improve the process accuracy and yield rate.

[0061] S200, determining the electrostatic chuck partition to be adjusted and determining second temperature data according to the partition structure inside the electrostatic chuck and the first temperature data, wherein the second temperature data is the temperature of the upper surface of the GaAs wafer carried by the electrostatic chuck partition to be adjusted;

[0062] The electrostatic chuck has multiple independently controllable heating areas (partitions). Each partition can independently adjust its temperature according to the input control command. Assume that the internal partition of the electrostatic chuck is in the form of a two-dimensional matrix of M×N, denoted by P=[P ij ], where i = 1, 2, ..., M and j = 1, 2, ..., N. The first temperature data is denoted as matrix T first , the first temperature data of the upper surface of each electrostatic chuck partition are averaged to obtain the temperature distribution matrix T that integrates the electrostatic chuck partition structure tem ,in Indicates electrostatic chuck partition P ij The average temperature of the wafer surface temperature corresponding to the area carried. Then each electrostatic chuck partition Pij The difference between the average temperature of the wafer surface temperature corresponding to the carrying area and the target temperature is expressed as ΔT ij , set the threshold ∈, if |ΔT ij |>∈|, then the electrostatic chuck is partitioned into P ij Determine the electrostatic chuck partition to be adjusted. That is the electrostatic chuck partition P to be adjusted ij The second temperature data corresponds to the upper surface of the carrier.

[0063] S300, based on the second temperature data and the preset target temperature, the power of the heating unit of the partition to be adjusted of the electrostatic chuck is adjusted by the partition temperature PID control module to adjust the second temperature data to the preset target temperature.

[0064] The specific process of adjusting the power of the heating unit of the electrostatic chuck partition based on the second temperature data and the preset target temperature is as follows:

[0065] The PID (proportional-integral-differential) control algorithm is used to establish the partition temperature PID control module. For each electrostatic chuck partition P to be adjusted ij , according to P ij Average temperature in the zone And the corresponding target temperature Calculate the output signal U of the partition temperature PID control module ij :

[0066]

[0067] Among them, K p , K i and K d They are proportional coefficient, integral coefficient and differential coefficient respectively. In this embodiment, K is obtained by neural network training. p , K i and K d Then the output signal U of the partition temperature PID control module is ij The temperature data is continuously collected and the input of the zone temperature PID control module is updated to form a closed-loop control system, which ensures that the temperature of each zone of the GaAs wafer can be accurately controlled within the set target range during the etching process, thereby optimizing the etching effect and improving the product yield.

[0068] Preferably, the method further comprises:

[0069] According to the first temperature data, a maximum temperature value of the upper surface of the GaAs wafer is obtained;

[0070] When the maximum temperature value of the upper surface of the GaAs wafer is greater than the preset maximum temperature threshold, the RF power is adjusted by the RF power PID control module based on the first temperature data until the maximum temperature value of the upper surface of the GaAs wafer is less than or equal to the preset maximum temperature threshold.

[0071] The first temperature data is collected by a high-precision infrared thermal imager or distributed temperature sensor array integrated in the etching chamber. These data are quickly analyzed and processed to identify and determine the highest temperature value on the surface of the GaAs wafer. Assume the maximum temperature threshold is When detected When the RF power PID control module is started, the overall etching rate of the GaAs chip is controlled, thereby reducing the etching temperature of the GaAs chip as a whole, so that the upper surface temperature of the GaAs wafer is reduced to below the maximum temperature threshold at the fastest speed.

[0072] According to the current high maximum temperature value and target maximum temperature threshold The temperature difference between the two is calculated and used as the input error of the PID controller. The PID controller makes a comprehensive judgment based on the error value, historical cumulative error, and temperature change trend (differential term), and generates an adjustment value to output to the RF power supply. The RF power PID control module dynamically adjusts the energy provided by the RF source based on the adjustment value, such as reducing the RF power to slow down the heat generated during the etching process. After adjusting the RF power, the temperature changes on the upper surface of the GaAs wafer are continuously monitored, especially the cooling of the previously high temperature area. When the highest temperature value detected in real time is Drops to a value less than or equal to the preset maximum temperature threshold , it indicates that the RF power has been successfully adjusted to the appropriate range. At this time, the PID controller will maintain the current RF power setting unchanged until the next temperature control cycle.

[0073] By real-time monitoring of the maximum temperature on the upper surface of the GaAs wafer and using the RF power PID control module for dynamic adjustment, the RF power is reduced when the temperature exceeds the preset threshold. This method not only ensures the safety and stability of the etching process, but also brings significant beneficial effects in many aspects. First, precise control of RF power helps to optimize the temperature distribution during the etching process, improve etching uniformity, and ensure the consistency of semiconductor device performance. Secondly, moderately slowing down the etching rate can avoid problems such as over-etching of materials and edge effects caused by excessively high etching speeds. At the same time, it is conducive to maintaining a suitable overall etching temperature and protecting the crystal structure and electrical properties of sensitive materials such as GaAs from being affected by high temperatures. In addition, the reasonable reduction of RF power is also conducive to energy conservation and consumption reduction, reducing equipment losses, and reducing safety risks caused by high temperatures, thereby achieving green and sustainable production.

[0074] Preferably, the method further comprises:

[0075] Obtaining etching layer parameters of each etching layer of the GaAs wafer, the etching layer parameters including the number of etching layers, the thickness of the etching layer and the cross-sectional area of ​​the etching layer;

[0076] Acquire the temperature of the lower surface of the GaAs wafer carried by the electrostatic chuck partition to be adjusted, obtain third temperature data, and obtain the temperature difference between the upper and lower surfaces of the GaAs wafer according to the second temperature data and the third temperature data;

[0077] The temperature difference between the upper and lower surfaces of the GaAs wafer and the etching layer parameters are input into the heat transfer model to obtain the adjustment heat data, and the initial adjustment power of the electrostatic chuck partition to be adjusted is determined according to the adjustment heat data;

[0078] Preferably, the heat transfer model is expressed as follows:

[0079]

[0080] Where Q is the heat provided by the electrostatic chuck partition to be adjusted, R is the number of etching layers of the GaAs wafer, and h r represents the thickness of the rth etched layer of the GaAs wafer, k r represents the thermal conductivity of the rth etched layer of the GaAs wafer, S r Represents the cross-sectional area of ​​the rth etched layer of the GaAs wafer, S represents the average cross-sectional area of ​​the etched layer of the GaAs wafer, ΔT represents the temperature difference between the upper and lower surfaces of the GaAs wafer, and r∈[1,R] is a natural number.

[0081] By comprehensively analyzing the temperature difference between the upper and lower surfaces of the GaAs wafer and the etching layer parameters (such as the number of etching layers, etching layer thickness and cross-sectional area), and inputting them into a precise heat transfer model, it is possible to accurately simulate and predict the heat distribution of each etching layer during the etching process of the wafer. The adjusted heat data calculated in this way provides a scientific basis for accurately setting the initial adjustment power of each partition, thereby achieving refined control of the local temperature of the wafer. It effectively avoids problems such as uneven etching and device performance degradation caused by local overheating, improves the process stability and yield rate in the semiconductor manufacturing process, and also provides a more flexible and efficient temperature management strategy for the preparation of complex structures and high-precision semiconductor devices.

[0082] Preferably, the partition temperature PID control module and the RF power PID control module respectively use a neural network model for real-time optimization, specifically including: using a neural network model to dynamically calculate and update in real time the proportional coefficient, integral coefficient and differential coefficient of their PID controllers.

[0083] See also Figure 2 and Figure 3 , the traditional PID controller parameters (proportional coefficient M p , integral coefficient M i and the differential coefficient M d ) as the learning target of the neural network, by constructing a deep learning or recursive neural network model adapted to the complex characteristics of the etching process, the first temperature data obtained in real time and the process parameters related to the RF power control are used as input information. During operation, the neural network model continuously receives temperature data and RF power and other variables under the actual working state, and dynamically calculates and updates the coefficient values ​​of the PID controller based on these real-time feedback information. This dynamic adjustment mechanism enables the controller to automatically find the optimal control parameter combination under different etching stages and different working conditions, thereby achieving more accurate, sensitive and efficient closed-loop control of the surface temperature and RF power of the GaAs wafer. For example, in terms of partition temperature control, when it is detected that the actual temperature of a partition exceeds the preset threshold, the neural network model will quickly optimize and calculate the new PID parameters based on the current temperature change trend and historical data, and then guide the heating unit to adjust the power output to ensure that the surface temperature of the wafer is stable within the set range. In the RF power control link, the neural network is also used to monitor the maximum temperature in real time. When it exceeds the maximum allowable value, the parameters of the RF power PID controller are intelligently adjusted to effectively reduce the overall etching rate and prevent overheating, while ensuring the quality and stability of the etching process. Through the neural network dynamic optimization of PID controller parameters, not only the accuracy and response speed of temperature and power control are improved, but also the system's adaptability and long-term stability are greatly enhanced, which is conducive to the realization of efficient, precise and green sustainable development of semiconductor device manufacturing process.

[0084] Preferably, the neural network model is represented as:

[0085]

[0086] Where I(t) is the input of the neural network model, T(t) represents the second temperature data at time t, e(t) represents the temperature error at time t, j is the number of nodes in the hidden layer of the neural network model, O j is the output result of the jth node in the hidden layer of the neural network model, M p (t) is the proportional coefficient of the PID controller, M i (t) is the integral coefficient of the PID controller, M d (t) is the differential coefficient of the PID controller, and is the weight coefficient from the neural network input layer to the hidden layer, and is the weight coefficient from the hidden layer to the output layer of the neural network model, f(x) is the hidden layer activation function, and g(x) is the output layer characteristic function.

[0087] In one possible embodiment, see Figure 4 The neural network model is divided into input layer, hidden layer and output layer. The input layer uses two input nodes, T(t) and e(t). The hidden layer uses three nodes to map the relationship between input and PID control coefficient. The output layer is M p (t) is the proportional coefficient of the PID controller, M i (t) is the integral coefficient of the PID controller, M d (t) is the differential coefficient of the PID controller.

[0088] In this embodiment, the neural network configured as above is used to optimize the PID controller parameters (proportional, integral, differential coefficients). The advantage is that it has strong self-learning and adaptability, can capture and model the complex nonlinear relationship between input parameters, and realize the refined dynamic adjustment of PID coefficients. It simplifies the traditional manual parameter adjustment process, improves the response speed and control accuracy of the control system, and the model obtained through training has good generalization performance and robustness, which helps to improve the stability of the entire system and its adaptability to unknown working conditions.

[0089] Preferably, the neural network model uses mean square error as the loss function.

[0090] Mean Squared Error (MSE) is a widely used and intuitive evaluation index that can effectively quantify the difference between the model prediction output and the actual target value, prompting the neural network to continuously reduce the gap between the predicted value of the PID coefficient and the optimal coefficient value during the training process, thereby improving the accuracy of the control system. The mean square error loss function has consistent sensitivity to various types of errors, which can ensure that the weight adjustment of each coefficient is fair and reasonable during the optimization process, and help to achieve balanced optimization of the proportional, integral and differential coefficients, so that the PID controller can maintain good dynamic performance and stability under different working conditions. Since the mean square error loss function is easy to calculate and has gradient differentiability, it is conducive to the use of optimization algorithms such as gradient descent for rapid convergence, so that the neural network can quickly find a set of optimal PID controller parameters suitable for the current working environment, thereby enhancing the real-time and adaptive capabilities of the chip-level GaAs etching temperature control method.

[0091] Preferably, real-time detection of the upper surface temperature of the GaAs wafer during the etching process to obtain first temperature data includes:

[0092] The upper surface temperature of the GaAs wafer is monitored in real time using a non-contact infrared temperature sensor to obtain a temperature distribution matrix.

[0093] Preferably, the upper surface temperature of the GaAs wafer is monitored in real time using a non-contact infrared temperature sensor. After obtaining the temperature distribution matrix, the temperature distribution matrix is ​​preprocessed. The specific process is expressed as follows:

[0094] Filter out abnormal temperature points, as shown below:

[0095] |T ij -μ|>θ·σ T ,

[0096] Among them, T ij represents the abnormal temperature value, i and j represent the row index and column index of the temperature distribution matrix respectively, μ represents the average temperature in the chip area, σ T represents the standard deviation of the temperature in the chip area, and θ represents the threshold coefficient;

[0097] For abnormal temperature value T ij Replace it as follows:

[0098]

[0099] Among them, T ′ (x) represents the abnormal temperature value T ij The replacement value, N represents the number of sampling points, represents the coordinates of the target point to be replaced, c n represents the coordinates of the nth sampling point, ω n represents the weight coefficient, ||xc n || represents the Euclidean distance from the target point to the nth sampling point, and σ represents the standard deviation of the Gaussian kernel.

[0100] In this embodiment, data with large deviations from the average value are screened out as abnormal temperature points, and a method based on a Gaussian kernel function is used to replace these abnormal values. The sampling points are randomly composed of N non-abnormal temperature points in the vicinity of the abnormal temperature point. In this embodiment, 5 random sampling points are used. The main benefit of this preprocessing method is that it can effectively reduce the influence of noise and errors, and improve the accuracy and stability in subsequent analysis or control processes. Since the replacement operation is performed by weighted summing of normal temperature points adjacent to the abnormal temperature point, some information characteristics of the original data are retained to a certain extent, which helps to maintain the consistency of the overall trend.

[0101] Preferably, when it is detected that the highest temperature value on the upper surface of the GaAs wafer is greater than a preset maximum temperature threshold, the chip in the corresponding area is recorded as an etching temperature abnormality chip, and the test weight of the etching temperature abnormality chip is calculated based on the difference between the highest temperature value and the maximum temperature threshold.

[0102] When the detection system identifies that the maximum temperature value on the surface of the GaAs wafer exceeds the preset maximum allowable temperature threshold, the corresponding area where the overheating phenomenon occurs will be specially marked and defined as an abnormal etching temperature chip. Not only is the chip location information of potential quality problems recorded, but the difference between the actual maximum temperature and the maximum temperature threshold is also calculated by precise measurement, further quantifying the test weight of the abnormal etching temperature chip. The calculation of this test weight is based on the degree of overheating, and is intended to reflect the severity of the negative impact that temperature abnormalities may have on chip performance and yield. The larger the test weight, the higher the risk of process failure due to excessive temperature, which will help to analyze and optimize process parameters, adjust etching equipment control strategies, and grade abnormal batches of products to ensure the controllability and consistency of semiconductor production quality. At the same time, through detailed tracking and evaluation of temperature abnormality chips, the problem location and resolution speed can be accelerated, and the overall manufacturing efficiency and cost-effectiveness can be improved.

[0103] Example 2

[0104] The present application also provides a chip-level GaAs etching temperature control system, referring to Figure 5 ,include:

[0105] The data detection module 100 is used to detect the upper surface temperature of the GaAs wafer during the etching process in real time to obtain first temperature data;

[0106] The first data processing module 200 is used to determine the second temperature data of the electrostatic chuck partition to be adjusted and the upper surface corresponding to the electrostatic chuck partition to be adjusted by comparative analysis according to the partition structure inside the electrostatic chuck and the first temperature data;

[0107] The second data processing module 300 is used to adjust the power of the heating unit of the electrostatic chuck partition to be adjusted through the partition temperature PID control module based on the second temperature data and the target temperature, so that the upper surface temperature of the GaAs wafer carried by the electrostatic chuck partition to be adjusted is adjusted to the target temperature.

[0108] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A chip-level GaAs etching temperature control method, characterized in that: include: Real-time detection of the upper surface temperature of the GaAs wafer during the etching process to obtain first temperature data; Determine the partition of the electrostatic chuck to be adjusted and determine the second temperature data according to the partition structure inside the electrostatic chuck and the first temperature data, wherein the second temperature data is the temperature of the upper surface of the GaAs wafer carried by the partition of the electrostatic chuck to be adjusted; Based on the second temperature data and the preset target temperature, the power of the heating unit of the partition of the electrostatic chuck to be adjusted is adjusted through the partition temperature PID control module to adjust the second temperature data to the preset target temperature.

2. A chip-level GaAs etching temperature control method according to claim 1, characterized in that: The method further comprises: According to the first temperature data, a maximum temperature value of the upper surface of the GaAs wafer is obtained; When the maximum temperature value of the upper surface of the GaAs wafer is greater than a preset maximum temperature threshold, the RF power is adjusted by the RF power PID control module based on the first temperature data until the maximum temperature value of the upper surface of the GaAs wafer is less than or equal to the preset maximum temperature threshold.

3. A chip-level GaAs etching temperature control method according to claim 1, characterized in that: The method further comprises: Obtaining etching layer parameters of each etching layer of the GaAs wafer, wherein the etching layer parameters include the number of etching layers, the thickness of the etching layer, and the cross-sectional area of ​​the etching layer; Acquire the temperature of the lower surface of the GaAs wafer carried by the partition of the electrostatic chuck to be adjusted corresponding to obtain third temperature data, and obtain the temperature difference between the upper and lower surfaces of the GaAs wafer according to the second temperature data and the third temperature data; The temperature difference between the upper and lower surfaces of the GaAs wafer and the etching layer parameters are input into a heat transfer model to obtain adjustment heat data, and the initial adjustment power of the electrostatic chuck partition to be adjusted is determined according to the adjustment heat data.

4. A chip-level GaAs etching temperature control method according to claim 3, characterized in that: The heat transfer model is expressed as follows: Where Q is the heat provided by the electrostatic chuck partition to be adjusted, R is the number of etching layers of the GaAs wafer, and h r represents the thickness of the rth etched layer of the GaAs wafer, k r represents the thermal conductivity of the rth etched layer of the GaAs wafer, S r Represents the cross-sectional area of ​​the rth etched layer of the GaAs wafer, S represents the average cross-sectional area of ​​the etched layer of the GaAs wafer, ΔT represents the temperature difference between the upper and lower surfaces of the GaAs wafer, and r∈[1,R] is a natural number.

5. The chip-level GaAs etching temperature control method according to claim 2, characterized in that: The partition temperature PID control module and the radio frequency power PID control module respectively use a neural network model for real-time optimization, specifically including: using a neural network model to dynamically calculate and update in real time the proportional coefficient, integral coefficient and differential coefficient of their PID controllers.

6. A chip-level GaAs etching temperature control method according to claim 5, characterized in that: The neural network model is expressed as: I(t)=T(t)+e(t), Where I(t) is the input of the neural network model, T(t) represents the second temperature data at time t, e(t) represents the temperature error at time t, j is the number of nodes in the hidden layer of the neural network model, O j is the output result of the jth node in the hidden layer of the neural network model, M p (t) is the proportional coefficient of the PID controller, M i (t) is the integral coefficient of the PID controller, M d (t) is the differential coefficient of the PID controller, and is the weight coefficient from the neural network input layer to the hidden layer, and is the weight coefficient from the hidden layer to the output layer of the neural network model, f(x) is the hidden layer activation function, and g(x) is the output layer characteristic function.

7. A chip-level GaAs etching temperature control method according to claim 6, characterized in that: The neural network model uses mean square error as the loss function.

8. The chip-level GaAs etching temperature control method according to claim 1, characterized in that: The real-time detection of the upper surface temperature of the GaAs wafer during the etching process to obtain first temperature data includes: The upper surface temperature of the GaAs wafer is monitored in real time using a non-contact infrared temperature sensor to obtain a temperature distribution matrix.

9. A chip-level GaAs etching temperature control method according to claim 8, characterized in that: The method of using a non-contact infrared temperature sensor to monitor the upper surface temperature of the GaAs wafer in real time and obtain a temperature distribution matrix also includes preprocessing the temperature distribution matrix. The specific process is as follows: Filter out abnormal temperature points, as shown below: |T ij -μ|>θ·σ T , Among them, T ij represents the abnormal temperature value, i and j represent the row index and column index of the temperature distribution matrix respectively, μ represents the average temperature in the chip area, σ T represents the standard deviation of the temperature in the chip area, and θ represents the threshold coefficient; For abnormal temperature value T ij Replace it as follows: Where T′(x) represents the abnormal temperature value T ij The replacement value, N represents the number of sampling points, x represents the coordinates of the target point to be replaced, c n represents the coordinates of the nth sampling point, ω n represents the weight coefficient, ||xc n || represents the Euclidean distance from the target point to the nth sampling point, and σ represents the standard deviation of the Gaussian kernel.

10. The chip-level GaAs etching temperature control method according to claim 2, characterized in that: When it is detected that the maximum temperature value of the upper surface of the GaAs wafer is greater than a preset maximum temperature threshold, the chip in the corresponding area is recorded as an etching temperature abnormality chip, and the test weight of the etching temperature abnormality chip is calculated according to the difference between the maximum temperature value and the maximum temperature threshold.

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