Method and system for manufacturing vertical fin-based field effect transistors

Abstract

A transistor includes: a substrate having a first surface and a second surface opposite to the first surface; a drift region having a doped region on the first surface of the substrate and a gradient doped region on the doped region; a semiconductor fin protruding from the gradient doped region and including a metal compound layer at an upper portion of the semiconductor fin; a source metal contact on the metal compound layer; a gate layer having a bottom portion directly in contact with the gradient doped region; and a drain metal contact on the second surface of the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 877,224, filed on July 22, 2019, entitled “Method and System for Fabrication of a Vertical Fin-Based Field Effect Transistor,” the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] The present invention relates to vertical fin-based field effect transistor (FET) devices having combined improvements in leakage current, maximum electric field, and on-resistance for a given threshold voltage. Background Art

[0004] Power electronic devices are widely used in various applications, including power conversion, motor drive, switching power supply, lighting, etc. Power electronic devices such as transistors are often used in these power switching applications. The operation of the current generation of power transistor devices, especially those with high voltage (>600V) handling capabilities, is hampered by slow switching speeds and high specific on-resistance.

[0005] Therefore, there is a need in the art for a power transistor device that exhibits low capacitance, low positive threshold voltage, low specific on-resistance, and high breakdown voltage. Summary of the invention

[0006] Embodiments of the present invention provide novel vertical fin-based FET devices and methods of manufacturing such FET devices having improved specific on-resistance, leakage current, and breakdown voltage.

[0007] In one embodiment, a transistor includes: a substrate having a first surface and a second surface opposite to the first surface; a drift region having a doped region on the first surface of the substrate and a gradient doped region on the doped region; a semiconductor fin protruding from the gradient doped region and including a metal compound layer at an upper portion of the semiconductor fin; a source metal contact on the metal compound layer; a gate layer having a bottom portion directly in contact with the gradient doped region; and a drain metal contact on the second surface of the substrate.

[0008] In another embodiment, a method for manufacturing a vertical fin-based field effect transistor (FET) is provided, the method may include: providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type; epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a gradient doping layer on the drift layer; epitaxially growing a second semiconductor layer (also referred to as a fin conductive layer) having the first conductivity type on the gradient doping layer, forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal layer and the second semiconductor layer (i.e., the fin conductive layer) using the patterned hard mask layer as a mask, and exposing the surface of the gradient doping layer to form a plurality of fins surrounded by grooves. The method also includes: epitaxially growing a third semiconductor layer having a second conductivity type opposite to the first conductivity type in the trench; etching back the third semiconductor layer and planarizing the third semiconductor layer and exposing a sidewall portion of the fin, forming a first dielectric layer on the planarized third semiconductor layer and covering the patterned hard mask layer and the sidewall portion of the fin; forming a second dielectric layer on the first dielectric layer, forming a third dielectric layer on the second dielectric layer, and etching back the third dielectric layer to form a spacer on the sidewall of the second dielectric layer.

[0009] In one embodiment, the method may further include: removing a portion of the second dielectric layer not covered by the spacer to expose an upper surface portion of the first dielectric layer above the planarized third semiconductor layer; and removing the spacer and the patterned hard mask.

[0010] In one embodiment, the first dielectric layer comprises Si 3 N 4 , the second dielectric layer includes SiO 2 , and the third dielectric layer includes Si 3 N 4 In one embodiment, the first dielectric layer has a thickness of about 100 nm, the second dielectric layer has a thickness of about 100 nm, and the third dielectric layer has a thickness of about 400 nm.

[0011] Compared with conventional techniques, many benefits can be obtained through the present invention. For example, embodiments of the present invention provide methods and systems that utilize: (1) a gradient doping region as a landing zone for etching vertical fins, thereby minimizing the effect of etch depth variation during the etching process on the on-resistance and gate-source capacitance of the FET, (2) a self-aligned source contact to reduce or eliminate alignment issues in forming the contact and thereby minimize parasitic capacitance, and (3) an epitaxially regrown gate layer on a gradient doping region with a ternary III-V compound on a binary III-V compound substrate.

[0012] The difference between the lattice constant and the induced stress of the ternary III-V compound gate layer and the binary III-V compound substrate generates polarization charge, which generates a two-dimensional electron gas (2DEG) at the interface with the gate layer. The 2DEG enables the current to flow in the horizontal direction first substantially along the lateral bottom surface of the gate layer, and then through the drift region in the vertical direction, thereby reducing the diffusion resistance in the device and reducing the specific on-resistance of the device. By controlling the etching depth in the gradient doping region, the drain-source on-resistance, threshold voltage, electric field and drain-source leakage current can be kept within the desired range. In addition, some embodiments include applications for hybrid pin / Schottky (MPS) diodes and vertical MOSFETs. In particular, using epitaxially regrown ternary III-V compounds as P-type regions in MPS diodes can reduce the on-voltage of the diode. For vertical MOSFETs, the gradient doping region landing area has similar advantages to vertical JFETs, and the self-aligned source contact can also be applied to vertical MOSFET structures. These and other embodiments of the present invention and many of its advantages and features are described in more detail in conjunction with the following disclosure and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following drawings form a part of the present invention and illustrate exemplary embodiments of the present invention. Together with the description, these drawings will explain the principles of the present invention.

[0014] Figure 1 is a cross-sectional view of a vertical fin-based field effect transistor (FET) device according to an embodiment of the present invention.

[0015] Figure 2 is a simplified cross-sectional view of a vertical fin-based FET device illustrating current flow from a lateral direction along a two-dimensional electron gas (2DEG) to a vertical direction toward a substrate in accordance with an embodiment of the present invention.

[0016] Figure 3is a simplified flow chart of a method for fabricating a vertical fin-based FET device according to an embodiment of the present invention.

[0017] 4A to 4D is a cross-sectional view illustrating an intermediate stage of a method of fabricating a vertical fin-based FET device according to an embodiment of the present invention.

[0018] FIG. 5A to FIG. 5E is a cross-sectional view showing an intermediate stage of a method of manufacturing a vertical fin-based FET device according to a first embodiment of the present invention.

[0019] FIG. 6A to FIG. 6D is a cross-sectional view showing an intermediate stage of a method of manufacturing a vertical fin-based FET device according to a second embodiment of the present invention.

[0020] 7A to 7H is a cross-sectional view showing an intermediate stage of a method of manufacturing a vertical type fin-based FET device, which can be applied to the first and second embodiments of the present invention.

[0021] Fig. 8A The simulated structure of a vertical fin-based FET device with a fin thickness of 0.2 μm.

[0022] Figure 8B is a graph illustrating the change in threshold voltage (V) of a vertical fin-based FET device as a function of etch offset (μm).

[0023] Figure 8C is a graph illustrating the variation of the electric field E (MV / cm) of a vertical fin-based FET device with the etch offset (μm).

[0024] Fig.8D is a graph illustrating the variation of channel leakage (A) of a vertical fin-based FET device with etching offset (μm).

[0025] Fig. 9A is a graph illustrating current density for normal etching. Fig. 9B is a graph illustrating current density for 0.1 μm overetch. Fig. 9C is a graph illustrating current density for a 0.2 μm overetch.

[0026] Fig. 10A is a graph illustrating the electric field at the gate corner for normal etching. Fig. 10B is a graph illustrating the electric field at the gate corner for a 0.1 μm under-etch. Fig. 10C is a graph showing the current density for 0.2 μm under-etching. Fig. 10B and Fig. 10CThe ellipse in FIG. 4 represents the gate corner with the fin.

[0027] Fig.11 is a graph illustrating the on-resistance Ron as a function of etching variation (μm) for a 0.2 μm graded epitaxial layer.

[0028] Fig.12 is a graph illustrating the threshold voltage Vt (V) as a function of etch variation (μm) for a 0.2 μm graded epitaxial layer.

[0029] Fig.13 is a graph illustrating the maximum electric field (MV / cm) as a function of etch variation (μm) for a 0.2 μm graded epitaxial layer.

[0030] Fig.14 is a graph illustrating the high voltage drain leakage current Idss (A) at 1200V as a function of etch variation (μm) for a 0.2 μm graded epitaxial layer.

[0031] Fig.15 is a graph showing the on-resistance Ron (mΩ) of the epitaxial layer for a 0.3 μm grade as a function of etching variation (μm).

[0032] Fig.16 FIG. 4 is a graph illustrating the change in threshold voltage Vt (V) with etching change (μm) for a 0.3 μm graded epitaxial layer.

[0033] Fig.17 is a graph illustrating the variation of electric field (MV / cm) with etch variation (μm) for a 0.3 μm graded epitaxial layer.

[0034] Fig.18 is a graph illustrating the high voltage drain leakage current Idss (A) at 1200V as a function of etch variation (μm) for a 0.3 μm graded epitaxial layer.

[0035] Fig.19A It is a diagram showing the prediction in the c-plane In 0.15 Ga 0.85 Plot of the effect of the absence of polarization charges on the current density generated at the N / GaN interface.

[0036] Fig.19B is a diagram illustrating the prediction of the c-plane In according to some embodiments of the present invention. 0.15 Ga 0.85 Diagram of the effect of polarization charges generated at the N / GaN interface.

[0037] Fig. 20A It is a diagram showing the prediction in the c-plane In 0.15Ga 0.85 Diagram of the effect of the electric field generated at the interface between the N gate layer and the GaN drift layer.

[0038] Fig. 20B is a diagram illustrating the prediction of the c-plane In according to some embodiments of the present invention. 0.15 Ga 0.85 Figure 2. Effect of the electric field generated at the N / GaN interface. The figure shows that in the off state a relatively high electric field is formed due to polarization.

[0039] Fig. 20C is a graph illustrating the off-state amplitude of the electric field in the absence of polarization and in the presence of polarization.

[0040] Fig.21A and Fig. 21B is a graph illustrating the current density through the channel of a baseline FET compared to the current density through the channel of a non-polar FET at 150°C. DETAILED DESCRIPTION

[0041] Embodiments of the present invention will be described more fully below with reference to the accompanying drawings. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided so that the present invention will be close and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Some features may not be drawn to scale, and for clarity, some details may be exaggerated relative to other elements. The same number always represents the same element.

[0042] It should be understood that when an element, such as a layer, region, or substrate, is referred to as being "on another element" or "extending onto another element," the element may be directly on the other element or directly extending onto the other element, or there may be intermediate elements. Conversely, when an element is referred to as being "directly on another element" or "extending directly onto another element," there are no intermediate elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0043] As used herein, relative terms such as "below," "above," "upper," "lower," "horizontal," "lateral," or "vertical" may be used to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation of the device depicted in the figures.

[0044] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "said" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", and "includes" when used herein specifically refer to the presence of stated features, numbers, steps, operations, elements, and / or parts, and do not exclude the presence or additional one or more other features, numbers, steps, operations, elements, and / or parts.

[0045] Embodiments of the present invention are described herein with reference to schematic cross-sectional illustrations of idealized embodiments (and intermediate structures) of the present invention. For clarity, the thickness of the layers and regions in the drawings may be magnified relative to other layers and regions. In addition, as a result of, for example, manufacturing technology and / or tolerances, variations in the shapes shown in the drawings are expected. Therefore, embodiments of the present invention should not be interpreted as being limited to the specific regional shapes illustrated herein, but should include shape deviations, for example, caused by manufacturing. For example, an implanted region illustrated as a rectangle generally has rounded or curved features at its edges and / or has a gradient of implant concentration, rather than a discrete change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface (through which the implantation is performed). Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the device region, nor are they intended to limit the scope of the present invention.

[0046] Embodiments of the present invention will now be described more fully below with reference to the accompanying drawings, in which embodiments of the present invention are shown. However, the present invention may be implemented in many different forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided so that the present invention will be close and complete, and the scope of the present invention will be fully conveyed to those skilled in the art.

[0047] The techniques, methods and devices known to those of ordinary skill in the relevant art will not be discussed in detail, but in the case where these techniques, methods and devices are applied, these techniques, methods and devices should be considered as part of this specification. In addition, similar reference numerals and letters are used to refer to similar items in the following figures, and once an item is defined in one of the figures, no further explanation of the item is required in the subsequent figures.

[0048] Embodiments of the present invention relate to vertical fin-based field effect transistor (FET) devices. More specifically, the present invention relates to such vertical fin-based FET devices having improved leakage current, maximum electric field and on-resistance for a given threshold voltage. By way of example only, the present invention relates to a method and a vertical transistor device having a gradient doping region in a doped drift region, and a regrowth of an epitaxial gate layer in direct contact with the gradient doping region. By having an epitaxially regrown gate layer on the gradient doping region, a number of advantages can be obtained, such as improved on-resistance, maximum electric field, and current that flows preferentially in the lateral direction of the bottom interface layer of the gate layer rather than in the vertical direction through the drift layer toward the substrate.

[0049] Figure 1 is a cross-sectional view of a vertical fin-based field effect transistor device 100 according to an embodiment of the present invention. The terms "FET", "FinFET", and "vertical fin-based FET" may be used interchangeably herein. Figure 1 , the FET device 100 may include a semiconductor substrate 101, a drift layer 102, and a plurality of fins 103, the drift layer 102 including a uniform doping region 102a on the semiconductor substrate 101 and a gradient doping region 102b on the uniform doping region 102a, and the plurality of fins 103 protrude from the gradient doping region 102b. In one embodiment, each fin 103 may include: a heavily doped layer 104 disposed in an upper portion of the fin, and a refractory metal, refractory metal compound, or refractory metal alloy layer (e.g., a TiN layer) 105 disposed on the heavily doped layer 104. The FET device 100 may also include: a source contact structure 106 on the metal layer (TiN) 105. The source contact structure 106 may include a titanium (Ti) layer 106a on the metal layer (TiN) 105, an aluminum (Al) layer 106b on the titanium (Ti) layer 106a, and a barrier metal layer (eg, molybdenum (Mo), titanium (Ti), tantalum (Ta), or the like) 106c on the aluminum (Al) layer 106b.

[0050] The FET device 100 may further include: a gate layer 110 having a bottom portion directly contacting the graded doped region 102 b, a dielectric (e.g., silicon dioxide or silicon nitride) layer 111 disposed on the gate layer 110 and surrounding the fin 103, a gate contact structure 112 disposed on the gate layer 110, a first interlayer dielectric layer 113 disposed on the dielectric layer 111 and the gate contact structure 112, and a second interlayer dielectric layer 114 disposed on the first interlayer dielectric layer 113. In one embodiment, the gate contact structure 112 may include: a nickel (Ni) layer 112 a disposed on the gate layer 110, a first gold (Au) layer 112 b disposed on the nickel (Ni) layer 112 a, a barrier metal (e.g., molybdenum (Mo), titanium (Ti), tantalum (Ta), or the like) layer 112 c disposed on the first gold (Au) layer 112 b, and a second gold (Au) layer 112 d disposed on the barrier layer 112 c.

[0051] The FET device 100 may further include: a first via contact 115 extending through the first interlayer dielectric layer 113 and the second interlayer dielectric layer 114 and contacting the source contact structure 106, a second via contact 116 extending through the first interlayer dielectric layer 113 and the second interlayer dielectric layer 114 and contacting the gate contact structure 112, and a drain metal contact 117 on the bottom surface of the semiconductor substrate 101. As used herein, the terms "drift layer" and "drift region" may be used interchangeably, the terms "doped layer" and "doped region" may be used interchangeably, and the terms "gradient doped region" and "gradient doped layer" may be used interchangeably.

[0052] In some embodiments, the semiconductor substrate 101 may include an N+ doped Group III nitride material, the fin 103 may include an N-doped Group III nitride material having a first dopant concentration, the uniformly doped region 102a of the drift region 102 may include an N-doped Group III nitride material having a second dopant concentration lower than the first dopant concentration, and the gradient doped region 102b has a third dopant concentration that increases (e.g., linearly increases) from the second dopant concentration to the first dopant concentration.

[0053] In one embodiment, the first dopant concentration is about 7.5×10 16 Atom / cm 3 , the second dopant concentration is about 1×10 16 Atom / cm 3 .

[0054] In one embodiment, the drift region has a thickness of about 12 μm (micrometers), the graded doping region has a thickness of about 0.3 μm, the semiconductor fin has a height in the range of about 0.7 μm to about 0.8 μm, and a width of about 0.2 μm.

[0055] In one embodiment, the gate layer 110 may include In x Ga 1-x N layer, where 0 < x < 1, that is, x is between 0 and 1 and not equal to 0 or 1. In one embodiment, the gate layer 110 is disposed in a recessed area between two adjacent fins and has a portion 110a in contact with the graded doping region 102b. The depth (or thickness) of the portion 110a of the gate layer will affect the threshold voltage, conductance, and maximum electric field of the FET device. The influence of the depth (or thickness) of the portion 110a embedded in the graded doping region will be described in more detail below.

[0056] In one embodiment, the FET device 100 may include: a substrate 101 that may include an N+ GaN material layer, a drain metal layer 117 disposed on the bottom surface of the substrate, an N-GaN drift layer 102 having a uniform doping region 102a disposed on the substrate 101 and a graded doping region 102b disposed on the uniform doping region, and an epitaxial GaN layer disposed on the graded doping region and including a recessed area for forming a plurality of fins 103. The FET device may further include: a P-type GaN gate layer filling the recessed area. The graded doping region 102b may be used as a landing pad to ensure sufficient contact of the gate layer 110. In one embodiment, the gate layer may include a ternary compound semiconductor layer (e.g., In x Ga 1-xN layers, where 0 < x < 1). In one embodiment, the portion 110a of the gate layer 110 may have a depth (or thickness) of about 0.1 μm (+ / - 0.1 μm) extending into the graded doping region 102b. Each fin may have a width of about 0.2 μm and be spaced apart from each other by about 2.0 μm, i.e., the recessed region between two adjacent fins or the gate layer filling the recessed region has a lateral width of about 2.0 μm. The FET device may further include: a two-dimensional electron gas (2DEG) layer 120 formed at the interface between the gate layer 110 and the graded doping region 102b. The surface area of the gate layer 110 is large such that the current flows laterally along the 2DEG layer 120 before flowing vertically in the substrate direction towards the drain metal layer 117, thereby improving the conductance (reducing the on-resistance) of the FET device. In other words, the channel FET device has two parts: the first part is the lateral channel that controls the current flowing through the 2DEG layer, which effectively distributes the current in the drift region, and the second part is the vertical channel that carries the current passing vertically through the drift region towards the substrate 101 and the drain metal layer 117.

[0057] In one embodiment, each fin may include: a metal layer 105 made of TiN, and a multi-layer source metal structure (such as a stack of Ti / Al or Ti / TiN / Al, where Ti is in contact with the metal layer 105). The FET device may further include an insulating layer 111, for example, a silicon dioxide or silicon nitride layer on the gate layer 110, which may also be referred to as a dielectric layer. The insulating layer 111 includes an opening at which a gate contact structure (gate electrode) 112 in contact with the gate layer 110 is formed. The gate contact structure (gate electrode) 112 has a multi-layer metal structure, such as Pd (palladium) / Pt (platinum) / Au (gold), where Pd is in contact with the gate layer 110, or Ni (nickel) and Au, where Ni is deposited in contact with the gate layer 110. Other embodiments may include other gate electrode metal structures known to those skilled in the art.

[0058] In one embodiment, each fin may include an upper part and a lower part. The upper part has sidewalls that are parallel to each other and substantially perpendicular to the substrate surface, and the lower part has sidewalls that are not parallel to each other and form an angle other than 90 degrees with the substrate surface. The parallel sidewalls may define a non-polar plane, such as the m-plane.

[0059] In one embodiment, the 2DEG layer is caused by the polarization between the gate layer and the drift region in the c-plane, and the current flowing vertically through the drift region is along the m-plane.

[0060] Figure 2is a simplified cross-sectional view of a vertical FET device 20 according to an embodiment of the present invention, which illustrates the current flow from the lateral direction along the 2DEG to the vertical direction toward the substrate. Figure 2 , the vertical FET device 20 may include: a substrate 201, a drift layer 202 covering the substrate 201, a plurality of fins 203 protruding from the surface of the drift layer 202, and a gate layer 210 on the drift layer 202 and surrounding the fins. The FET device 20 may also include: a gate electrode 212 on the gate layer 210, and a dielectric layer (e.g., silicon dioxide) 211 on the gate layer 210 and surrounding the fins 203 and the gate electrode 212. The FET device 20 may also include: a two-dimensional electron gas 220, wherein the gate layer 220 contacts the drift layer 202 along the polar plane direction. The FET device 20 may also include: a source electrode 206 coupled to the fins 203. When no potential is applied to the gate electrode 212, the FET device 20 is in an off state.

[0061] When a potential is applied to the gate electrode 212, a continuous two-dimensional electron gas (2DEG) 220 electrically connected to the drain electrode is modulated. A source current 231 flows laterally under the gate layer 210 and vertically into the drain electrode 217. In one embodiment, each fin has a width of about 0.2 μm and the fins are spaced apart at a distance of about 2.0 μm. A 2DEG 220 caused by polarization is formed in the interface between the gate layer and the graded doping region of the drift region, thereby distributing current in the drift region to improve the conductance of the FET device.

[0062] The embodiments of the present invention also provide a method for manufacturing a vertical FET device. Figure 3 is a simplified flow chart of a method 300 for fabricating a vertical FET device with a regrown gate layer according to an embodiment of the present invention. Figure 3 , providing a III-nitride substrate (310). In one embodiment, the III-nitride substrate is an N+GaN substrate having a resistivity in the range of about 0.020 ohm-cm (ohm-centimeter). In one embodiment, the resistivity of the N+GaN substrate can be from about 0.001 ohm-cm to about 0.018 ohm-cm, preferably less than 0.016 ohm-cm, and more preferably less than 0.012 ohm-cm. Method 300 also includes: forming a first III-nitride epitaxial layer, for example, forming a 12 μm thick first III-nitride epitaxial layer (for example, an N-GaN epitaxial layer deposited on the III-nitride substrate) (312). The first III-nitride epitaxial layer is epitaxially grown on the III-nitride substrate at a temperature of 950° C. to 1100° C. and is characterized by a first dopant concentration, for example, having a dopant concentration of about 1×10 16 Atom / cm3 In some embodiments, the first III-nitride epitaxial layer is a drift layer, which includes: a uniform doping region (layer) on a III-nitride substrate and a gradient doping region (layer) on the uniform doping region. In one embodiment, the uniform doping region has a thickness of about 12 μm and the gradient doping region has a thickness of about 0.3 microns. In one embodiment, the surface of the substrate 310 deviates from the c-plane at a certain angle to facilitate high-quality epitaxial growth for high-voltage operation of the drift layer.

[0063] The method 300 further includes forming a second III-nitride epitaxial layer (314) on the first III-nitride epitaxial layer. In one embodiment, the second III-nitride epitaxial layer is epitaxially grown on the first III-nitride epitaxial layer with a thickness of about 0.7 μm and is characterized by a second dopant concentration (e.g., N-type doped). In some embodiments, the second dopant concentration is higher than the first dopant concentration. In one embodiment, the second dopant concentration is about 1.3×10 17 Atom / cm 3 . Method 300 also includes: forming a metal layer on the second III-nitride epitaxial layer and forming a patterned hard mask layer (316) on the metal layer, and patterning the metal layer using the patterned hard mask layer as a mask. Method 300 also includes: forming a recessed region (318) in the second III-nitride epitaxial layer using the patterned hard mask layer through an etching process (e.g., a reactive ion etching (RIE) process). Method 300 also includes: regrowing a third III-nitride epitaxial layer (320) in the recessed region. The regrown III-nitride epitaxial layer can form a gate layer. In one embodiment, the regrown III-nitride epitaxial layer has a conductivity type opposite to the conductivity type of the first and second III-nitride epitaxial layers.

[0064] The method 300 also includes: forming a first dielectric layer on the regrown III-nitride epitaxial layer and on the patterned hard mask layer, and forming a second dielectric layer on the first dielectric layer (322). The method 300 also includes: removing a portion of the second dielectric layer to form a spacer on the sidewall of the first dielectric layer on the opposite side of the upper portion of the fin (324). The method 300 also includes: removing a portion of the first dielectric layer to expose a surface portion of the regrown III-nitride epitaxial layer, while retaining a portion of the first dielectric layer on the opposite side of the fin (326). The method 300 also includes: removing the isolation and the hard mask layer, while exposing the surface of the metal layer and retaining a portion of the first dielectric layer on the opposite side of the fin (328).

[0065] The method 300 further includes: forming a source mask layer (330) on the exposed surface portion of the regrown epitaxial III-nitride layer. The method 300 further includes: forming a source contact structure on the surface of the metal layer and removing the source mask layer (332). The method 300 further includes: forming a gate mask layer covering the source contact structure while exposing the surface portion of the regrown III-nitride epitaxial layer, forming a gate contact structure on the exposed surface portion of the regrown III-nitride epitaxial layer, and removing the gate mask layer (334). The method 300 further includes: forming an interlayer dielectric layer covering the source contact structure and the gate contact structure, forming a patterned mask layer on the interlayer dielectric layer, etching the interlayer dielectric layer to form a through hole extending to the source contact structure, and filling the through hole with a conductive material to form a via (336). It should be noted that the through hole and via to the gate contact structure and the through hole and via to the source contact structure can be formed simultaneously.

[0066] It should be understood that according to the embodiments of the present invention, Figure 3 The specific steps illustrated in the figure provide a specific method for manufacturing a vertical FET device with a regrown gate layer. According to alternative embodiments, these steps may also be performed in other orders. For example, alternative embodiments of the present invention may perform the steps listed above in a different order. In addition, Figure 3 The illustrated individual steps may include multiple sub-steps, which may be performed in different orders according to the individual steps. In addition, additional steps may be added or removed depending on the specific application. A person of ordinary skill in the art may appreciate multiple variations, modifications, and substitutions.

[0067] Reference again Figure 3 And refer to 4A to 4D, which describes a method of manufacturing a vertical FET device according to some embodiments of the present invention. Figure 4A , providing an N+ doped III-nitride substrate 401 (block 310). A first N-doped semiconductor (drift) layer 402 is epitaxially grown on the substrate 401 at a temperature of 950°C to 1200°C, preferably at a temperature of 1000°C to 1150°C, and more preferably at about 1100°C (block 312), and a second N-doped semiconductor layer 403 is epitaxially grown on the first semiconductor layer 402 at a temperature of 950°C to 1200°C, preferably at a temperature of 1000°C to 1150°C, and more preferably at a temperature of about 1100°C (block 314). Figure 4B , forming a metal layer 405 on the second semiconductor layer 403, and forming a patterned hard mask layer 406 on the metal layer 405 (block 316). In one embodiment, the hard mask layer may include Si 3 N 4 , and formed by PECVD at about 300° C. to a thickness of about 400 nm. In one embodiment, the patterned hard mask layer 406 may be formed using RIE based on a fluorine (F-based) chemistry. In one embodiment, the metal layer 405 is omitted.

[0068] In one embodiment, the dopant concentration is about 5×10 17 Atom / cm 3 To about 1×10 19 Atom / cm 3 The N+ doped III-nitride substrate 401 is heavily doped with an N-type dopant having a resistivity in the range of 0.001 ohm-cm and less than 0.020 ohm-cm. In one embodiment, the resistivity of the N+ doped III-nitride substrate may be about 0.001 ohm-cm to 0.018 ohm-cm, preferably less than 0.016 ohm-cm, and more preferably less than 0.012 ohm-cm. The first semiconductor layer 402 has a thickness of about 12 μm and has a resistivity of about 1×10 16 Atom / cm 3 The second semiconductor layer 403 is a fin conductive layer having a uniform doping region with a dopant concentration of about 1.3×10 17 Atom / cm 3 The graded doping region 4023 having a thickness of about 0.3 μm is disposed between the first semiconductor layer and the second semiconductor layer and has a thickness of about 1×10 16 Atom / cm 3 increases (e.g., linearly) to 1.3×10 17Atom / cm 3 The dopant concentration of the second semiconductor layer 403 is linearly increased from the first semiconductor layer to the second semiconductor layer. The metal layer 405 may include TiN, and the hard mask layer 406 may include silicon nitride. In one embodiment, a heavily N+ doped layer 404 may be present between the second semiconductor layer 403 and the metal layer 405 to improve the contact resistance between the second semiconductor layer and the metal layer. For clarity, the gradient doping region 4023 and the heavily N+ doped layer 404 are omitted in the following drawings and illustrations.

[0069] refer to Figure 4C , an etching process is performed using a patterned hard mask 406 as a mask to form a plurality of fins 403' and patterned metal contacts 405' (box 318). In some embodiments, each fin has a width of about 0.2μm, a height in the range of about 0.7μm to 0.8μm, and the fins are spaced apart from each other at intervals of about 2μm, i.e., the fin pitch is about 2μm. In order to have a uniform fin height, good controllability of the depth of the etching process is utilized. According to the present invention, the etching process may include a chlorine-based (Cl-based) chemical process using RIE, and the etching process is performed to remove a portion of the second semiconductor layer 403, thereby forming a recessed area 408. In one embodiment, the etching process may be stopped when the gradient doping region 4023 of about 0.1μm is removed. As described in further detail below, it is critical to use a gradient doping region to mitigate the electrical effects of etching process variations or tolerances.

[0070] It should be noted that after the etching process, the bottom portion of the fin may have a Figure 4C Shapes different from the shapes shown. Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. For clarity, the thicknesses of the layers and regions in the drawings may be exaggerated. In addition, variations in the shapes shown are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present invention should not be interpreted as limited to the specific regional shapes illustrated herein, but should include shape deviations caused by, for example, manufacturing. In the following figures, the bottom portion of the fin is shown as being at an angle of 90 degrees to the surface of the gradient doped region, that is, the fin is shown as having a rectangular shape in cross section. It will be understood that the bottom portion of the fin may have rounded or curved features. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the device region, nor are they intended to limit the scope of the present invention.

[0071] In one embodiment, after the trench is formed, a cleaning process is performed using a TMAH solution with a weight percentage of about 25% at a temperature of about 85° C. for about 30 minutes. In another embodiment, before the TMAH solution is used for cleaning, a H solution with a volume ratio of 2:1 may be used. 2 SO 4 :H 2 Perform a 2 min pre-wash with O Piranha wash.

[0072] refer to Figure 4D After cleaning, a third semiconductor layer 407 is epitaxially grown in the recessed region 408 (block 320). In one embodiment, the third semiconductor layer 407 may include a P-type GaN layer that is non-conformally grown in the trench at a temperature of about 950° C. to a thickness that is substantially flat with the bottom of the patterned metal contact 405′ (or hard mask 406 if the patterned metal contact 405′ is omitted). In one embodiment, the thickness of the third semiconductor layer 407 is about 840 nm. The P-type GaN layer may be doped with a dopant concentration of about 1×10 19 Atom / cm 3 The p-type GaN layer may be doped with a dopant concentration of about 1×10 19 Atom / cm 3 Thereafter, thermal annealing (for example, at 850°C in N 2 The Mg dopant atoms are then activated by rapid thermal annealing (RTA) for 5 minutes. The Mg atoms in the P-type GaN layer are then activated in an amount greater than 10% by weight. In one embodiment, the heavily N+ doped layer (e.g. Figure 4B ) may exist between the fin 403' and the patterned metal contact 405' to improve the contact resistance between the second semiconductor layer and the metal layer.

[0073] In the first embodiment, reference Figure 5A A planarization process may be performed on the third semiconductor layer 407. In one embodiment, the planarization process includes removing an upper portion of the third semiconductor layer 407 by etching. In one embodiment, the planarization process includes removing approximately 0.2 μm of the upper portion of the third semiconductor layer 407.

[0074] Thereafter, a first dielectric layer 410a is formed on at least the planarized surface of the fourth dielectric semiconductor layer 407, and the first dielectric layer 410a is substantially conformal with the sidewalls of the fin, the patterned metal contact 405', and the hard mask 406. In one embodiment, the first dielectric layer 410a has a thickness of about 100 nm and may include Si 3 N 4, and may be deposited by PECVD at about 300° C. A second dielectric layer 410 b is formed on the first dielectric layer 410 a. In one embodiment, the second dielectric layer 410 b has a thickness of about 100 nm and may include SiO 2 , and may be deposited by PECVD at about 300° C. A third dielectric layer 410c is formed on the second dielectric layer 410b. In one embodiment, the third dielectric layer 410c has a thickness of about 400 nm and may include Si 3 N 4 , and can be deposited by PECVD at about 300°C.

[0075] refer to Figure 5B , the third dielectric layer 410c is etched back to form a spacer 412a on the sidewall of the second dielectric layer 410b. In one embodiment, the spacer 412a has a width of about 300 nm at its lower portion.

[0076] refer to Figure 5C , the second dielectric layer 410b is etched using a substantially isotropic etch to expose the top of the first dielectric layer 410a above the planarization region 407 and above the hard mask 406. In one embodiment, the etching uses a wet etchant, such as buffered HF. In another embodiment, the etching uses a fluorine-based plasma etch. After etching, the remaining portion of the second dielectric layer 410b adjacent to the spacer 412a is represented as 410b'.

[0077] refer to Figure 5D , the third dielectric layer 410c (spacer 412a), the first dielectric layer 410a and the hard mask 406 are etched to expose the contact region above the patterned metal contact 405'. In one embodiment, the patterned metal contact 405' is omitted and the contact region is the top of the fin 403'.

[0078] refer to Figure 5E , the remaining portion of the second dielectric layer 410b' is etched to expose the remaining surface of the first dielectric layer 410a.

[0079] FIG. 6A to FIG. 6D is a cross-sectional view illustrating an intermediate stage of a method for manufacturing a vertical fin-based FET device according to a second embodiment of the present invention. Fig. 6A, a planarization process may be performed on the third semiconductor layer 407. In one embodiment, the planarization process includes removing an upper portion of the third semiconductor layer 407 by etching. In one embodiment, the planarization process includes removing about 0.2 μm of the upper portion of the third semiconductor layer 407. Thereafter, a first dielectric layer 410 is formed on the planarized surface of the fourth semiconductor layer 407, and a second dielectric layer 411 is formed on the first dielectric layer 410 (block 322). In one embodiment, the first dielectric layer 410 may include SiO 2 The second dielectric layer 411 may include Si 3 N 4 And the deposition was performed by PECVD at about 300°C.

[0080] refer to Figure 6B , the second dielectric layer 411 is etched back to form a spacer 412 having a thickness of about 2000 angstroms on the sidewalls of the first dielectric layer 410 (block 324). In one embodiment, the first dielectric layer 410 is also etched back to a depth such that the upper surface of the first dielectric layer 410 is within the thickness of the hard mask layer 406, as shown in FIG. Figure 6B shown.

[0081] refer to Figure 6C The first dielectric layer 410 is further etched back and exposes the upper surface of the fourth semiconductor layer 407 (block 326). In one embodiment, the first dielectric layer 410 may be overetched by 50% to expose a portion of the upper surface and sidewalls of the hard mask layer 406.

[0082] refer to Fig.6D , the hard mask layer 406 and the spacers 412 are removed, while remaining portions of the first dielectric layer 410 remain (block 328).

[0083] 7A to 7H 1 is a cross-sectional view showing an intermediate stage of a method for manufacturing a vertical fin-based FET that can be applied to the first embodiment and the second embodiment. For illustrative purposes, 7A to 7H The application to the second embodiment is shown, and a person skilled in the art can easily apply the same intermediate stages to the first embodiment. Fig. 7AA source mask layer 415 is formed on the exposed upper surface of the fourth semiconductor layer 407 and has an opening 415a exposing a portion of the first dielectric layer 410 and the upper surface of the fin 403' (block 330). The source mask layer 415 also has a protrusion 415b extending above the opening 415a. In one embodiment, the source mask layer 415 has a lift-off capability and has a bottom CD of 0.65 μm and a top CD of 0.55 μm.

[0084] refer to Figure 7B , forming a source metal contact structure 416 by deposition on the exposed upper surface of the fin 403' at a temperature of about 150°C (box 332). In one embodiment, the source metal contact structure 416 may include a stacked structure including a first source metal layer 416a on the metal layer 405 on the upper surface of the fin 403', a second source metal layer 416b on the first source metal layer 416a, and a third source metal layer 416c on the second source metal layer 416b. In one embodiment, the first source metal layer 416a includes Ti (titanium) having a thickness of about 25nm, the second source metal layer 416b includes Al (aluminum) having a thickness of about 100nm, and the third source metal layer 416c includes Mo (molybdenum) having a thickness of about 40nm. In another embodiment, the second source metal layer 416b includes TiN (titanium nitride) and the third source metal layer 416c includes Al. In another embodiment, the second source metal layer 416b includes TiN and the third source metal 416c is omitted. After forming the source metal contact structure, the source mask layer 415 is dissolved to peel off the metal layer deposited thereon, while the metal layer deposited on the upper surface of the fin remains intact. In another embodiment, after depositing the source metal contact structure 416, the mask layer 415 is coated with a reverse tone, and the source metal contact structure 416 is etched (e.g., using RIE) until the mask layer 415 of the reverse tone is presented. The mask layer 415 is then removed. The source metal contact structure 416 formed below the opening 415a will have a width of approximately 0.65 μm corresponding to the width of the opening. In one embodiment, the source metal contact structure 416 can be etched at 850°C at N 2 A rapid thermal annealing (RTA) process is performed for 5 minutes in the process. After the RTA process, the source metal contact structure will have a thickness of less than about 10 -5 ohm-cm 2 Resistivity.

[0085] In some embodiments, a junction-terminated edge (JTE) structure is formed outside the active region of the FET device by implantation (eg, implantation of nitrogen (N) or argon (Ar)) to achieve stable high voltage operation of the device.

[0086] refer to Figure 7C A gate metal mask layer 420 is formed on the exposed upper surface of the source metal structure, and the gate metal mask layer 420 has an opening 420a that exposes a surface portion of the fourth semiconductor layer 407 (block 334). The gate metal mask layer 420 also has a protrusion 420b extending above the opening 420a. In one embodiment, the gate metal mask layer 420 has a lift-off capability and has a bottom CD of 0.9 μm and a top CD of 0.8 μm.

[0087] refer to Fig.7D , a gate metal contact structure 421 is formed on an exposed surface portion of the fourth semiconductor layer 407 through the opening 420a by deposition. In one embodiment, the gate metal contact structure 421 may include a stacked structure including a first gate metal layer 421a on a surface portion of the fourth semiconductor layer 407, a second gate metal layer 421b on the first gate metal layer 421a, a third gate metal layer 421c on the second gate metal layer 421b, and a fourth gate metal layer 421d on the third gate metal layer 421c. In one embodiment, the first gate metal layer 421a includes Ni, the second gate metal layer 421b includes Au, the third gate metal layer 421c includes Mo, and the fourth gate metal layer 421d includes Au. In another embodiment, the gate metal layers 421c and 421d are omitted, and the first gate metal layer 421a includes Ni, and the second gate metal layer 421b includes Au. In another embodiment, the gate metal layer 421d is omitted, and the first gate metal layer 421a includes Pd, the second gate metal layer 421b includes Pt, and the third gate metal layer 421c includes Au. After forming the gate metal contact structure, the gate mask layer 420 is dissolved to peel off the metal layer deposited on the gate mask layer, while the metal layer deposited on the surface portion of the fourth semiconductor layer 407 remains intact.

[0088] refer to Fig. 7E , remove the gate metal mask layer 420 (block 334) and perform a thermal anneal to provide a stable low contact resistance. In one embodiment, the gate metal mask layer 420 may be removed at 500°C in an oven at 0 2 A 10-minute rapid thermal annealing (RTA) process is performed in the embodiment of the present invention. After the thermal treatment, the gate metal contact structure will have a thickness of less than about 10 -3 ohm-cm 2 specific resistance.

[0089] refer to Figure 7F , a first interlayer dielectric layer 425 covering the gate metal contact structure, the source metal contact structure and the surface of the fourth semiconductor layer is deposited using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of 300° C. The first interlayer dielectric layer 425 is relatively conformal. In one embodiment, layer 425 has a thickness of approximately 50 nm and may include a nitride (e.g., silicon nitride). Next, a second interlayer dielectric layer 426 is deposited on the first interlayer dielectric layer 425 using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of 300° C. (block 336). The second interlayer dielectric layer 426 has a thickness of approximately 50 nm and may include an oxide (e.g., silicon oxide).

[0090] refer to Figure 7G , a patterned photoresist layer 427 is formed over the second interlayer dielectric layer 426, and the photoresist layer 427 may be planarized or non-planarized. , the photoresist layer 427 is formed and patterned using a known photolithography process to define the location where the via 428 will be formed. Next, the first interlayer dielectric layer 425 and the second interlayer dielectric layer 426 are etched until the upper surface of the source metal contact structure is exposed. In some embodiments, the via to the gate metal contact structure may also be formed simultaneously with the via 428 for the source metal contact structure. In one embodiment, the via has a CD of approximately 0.45 μm.

[0091] Next, the patterned photoresist layer 427 is removed. Figure 7H , forming a conductive material 429 filling the via 428, and performing pad metal deposition on the filled via by evaporation to a thickness of about 4 μm (block 336). The above method of manufacturing a vertical fin-based FET has the advantage of forming a metal, metal alloy or metal compound layer (e.g., TiN) on the fin epitaxial layer and subsequently forming a hard mask layer.

[0092] Fig. 8A Figure 2 is a cross-section of a simulated cell structure using a 0.2μm fin thickness. The nominal etch depth below the bottom of the fin layer is 0.1μm (0.1μm into the gradient region). Etch depth variations of + / -0.1μm around the nominal value are simulated, as well as gradient region thicknesses of 0.2μm for the second run and 0.3μm for the third run.

[0093] FIG6 is a graph illustrating the threshold voltage (V) of a vertical fin-based FET device as a function of the etch offset (μm) for a 0.3μm fin and an ungraded epitaxial layer. The "0" on the x-axis represents the epitaxial layer between the fin and the drift region. The right side of "0" represents over-etching into the drift region below the fin layer, while the left side of "0" represents under-etching. The y-axis represents the voltage threshold (V). Reference Figure 8C , over-etching into the drift region below the fin layer results in a significant increase in the voltage threshold. Figure 8B and Figure 8C , the inventors found that the acceptable limit for conductance and threshold voltage is about 0.1 μm.

[0094] Figure 8C It is a graph illustrating the electric field E (MV / cm) of a vertical fin-based FET device as a function of the etching offset (μm) of a 0.3μm fin and an ungraded epitaxial layer. The "0" on the x-axis represents the epitaxial layer between the fin and the drift region. The right side of "0" represents over-etching into the drift region below the fin layer, while the left side of "0" represents under-etching. The y-axis represents the electric field E (MV / cm). Under-etching of the epitaxial layer (i.e., above the interface with the drift layer) results in a significant increase in the maximum electric field E. That is, the risk of breakdown increases with under-etching of 0.1μm or more.

[0095] Fig.8D is a graph illustrating the channel leakage (A) of a vertical fin-based FET device as a function of etch offset (μm) for a 0.3μm fin and an ungraded epitaxial layer. The "0" on the x-axis represents the epitaxial layer between the fin and the drift region. The right side of "0" represents over-etching into the drift region below the fin layer, while the left side of "0" represents under-etching. The y-axis represents the drain-source leakage current Idss (A). Reference Fig.8D , the etching variation has no significant effect on the leakage current.

[0096] 9A to 9C is a graph illustrating the current density (A / cm2) versus position relative to the fin for a normal etch of a 0.3μm fin and an ungraded epitaxial layer. The fin is located on the right. The solid horizontal line is the nominal etch depth, while the dashed yellow line 1001 represents the fin / drift region interface. The x-axis represents the current density relative to the position of the fin in μm, where "1" is the middle of the fin. The y-axis represents the position of the etched drift region relative to the gate layer, where "0" is the top surface of the gate layer and "0.8" is the nominal bottom position of the gate layer. Reference Fig. 9A , for the nominal etch (also the bottom of the gate layer), i.e. the etch depth at the interface with the drift region is 0.8 μm, the high current density is around the interface between the bottom of the gate layer and the bottom of the fin, and the threshold voltage is within the nominal range. Fig. 9Bis a graph illustrating the current density for a 0.1 μm over-etch. The interface with the bottom of the gate layer is 0.9 μm. The threshold voltage is high, as shown by band 1002. Fig. 9C is a graph illustrating current density for a 0.2 μm over-etch. The threshold voltage is even worse as shown by band 1003. The results are also confirmed in FIG. 6, which shows a significant increase in threshold voltage at a 0.2 μm over-etch.

[0097] FIG. 10A to FIG. 10C Plots of the electric field at the gate corner for different etching conditions are illustrated. The nominal etching condition is represented by the box denoted "N / N-Interface". Fig. 10A is a graph illustrating the electric field 1101 with nominal value at the gate corner for normal etching. The double arrow 1102 shows the heavily doped region below the interface with the gate layer. Fig. 10B is a graph illustrating the electric field 1103 at the gate corner for 0.1 μm under-etch. The double arrow 1104 shows that a portion of the heavily doped region (indicated by the double arrow 1104) is disposed between the gate layer and the under-etched region, which will induce a high electric field at the gate corner. Fig. 10C is a graph illustrating the ab electric field for a 0.2 μm under-etch. The heavily doped region (indicated by double arrow 1106) is completely disposed in the under-etched region. The results are also shown in Fig.8D middle.

[0098] 0.2μm fin with 0.2μm graded epitaxial layer (epi)

[0099] Fig.11 is a graph illustrating the drain-source on-resistance Ron as a function of etch change (μm) for a 0.2μm graded epitaxial layer. “0” is the middle of the 0.2μm graded epitaxial layer between the fin and drift region. Ron increases significantly with 0.1μm over-etch. Reference Fig.11 , the upper limit "USL" (specified upper limit) of Ron is reached at about 0.05μm over-etching. That is, when the etching variation is within the range of + / -0.1μm, the on-resistance value will exceed the specified upper limit.

[0100] Fig.12 is a graph illustrating the threshold voltage Vt (V) versus etch change (μm) for a 0.2μm graded epitaxial layer. “0” is the middle of the 0.2μm graded epitaxial layer between the fin and the drift region. Similar to Ron, the threshold voltage Vt increases significantly with 0.1μm over-etching. That is, when the graded doping region is over-etched, the threshold will increase to an unacceptable value. See Appendix Fig.11 and Fig.12 , under-etching does provide improvements in on-resistance and threshold voltage. Fig.13 and Fig.14 As shown, the under-etching also provides improvements to the electric field and leakage current.

[0101] Fig.13 is a graph illustrating the maximum electric field (MV / cm) for a 0.2μm graded epilayer as a function of etch variation (μm). The 0.2μm graded epilayer does provide an improvement over the electric field with an under-etch by having the nominal etch end in the graded doped layer. In the first round of simulations, the 0.1μm under-etch case is now similar to the nominal case, with a slight increase in the electric field due to the additional charge in the graded doped layer.

[0102] Fig.14 is a graph illustrating the high voltage drain leakage current Idss (A) at 1200V as a function of etch variation (μm) for a 0.2 μm graded epitaxial layer. Fig.14 , the high voltage drain leakage current Idss remains well controlled by using the graded epitaxial layer. That is, over-etching or under-etching does not affect the leakage current.

[0103] 0.2μm fin with 0.3μm graded epitaxial layer

[0104] The inventors performed a third round of simulations using a 0.2 μm fin with a 0.3 μm thick linearly graded epitaxial layer inserted between the fin epilayer and the drift region. In the third round of simulations, the nominal etch depth was maintained at 0.1 μm below the bottom of the fin epilayer, and the results were Figure 16 to Figure 1 9 is shown.

[0105] Fig.15 is a graph showing the on-resistance Ron (mΩ) of the epitaxial layer with 0.3 μm grading as a function of etching variation (μm). Fig.15 , the on-resistance Ron is well controlled within the range of + / -1μm. Fig.15 , with 0.1 μm overetching the on-resistance Ron increases by about 10%, which is acceptable and much smaller than the 0.2 μm graded epitaxial layer used in the second set of simulations (see Fig.11 ).

[0106] Fig.16 Graph showing the threshold voltage Vt(V) of the epitaxial layer with a gradient of 0.3μm as a function of etching change (μm). Fig.16 , the threshold voltage Vt is well controlled within the range of + / -1μm. With 0.1μm overetching, the threshold voltage Vt increases by about 10%, which is acceptable and much smaller than Fig.12The threshold voltage Vt of the structure illustrated in FIG. 5 using a 0.2 μm graded epitaxial layer used in the second set of simulations.

[0107] Fig.17 is a graph illustrating the electric field (MV / cm) versus etch change (μm) for a 0.3 μm graded epitaxial layer. Fig.17 , the electric field is higher in the gradient region of 0.3μm. Under the under-etching condition of 0.1μm, the electric field is about 3.15MV / cm (at the boundary line), that is, the maximum electric field is marginal at the minimum etching depth. The boundary or marginal conditions will require some additional optimization, either by changes in the grading or re-centering of the nominal etching depth.

[0108] Fig.18 is a graph illustrating the high voltage drain leakage current Idss (A) at 1200V as a function of etch variation (μm) for a 0.3 μm graded epitaxial layer. Fig.18 , the high voltage drain leakage current Idss is well controlled within the simulated etching range.

[0109] In summary, the inventors have determined that with a prominent fin epitaxial layer to drift region doping transition, the expected fin etch depth process variation will result in unacceptable variations in drain-source on-resistance Ron, threshold voltage Vt, and breakdown voltage. Inserting a gradient doping region as a transition layer between the fin epitaxial region and the drift region significantly improves the parameter variation with etching process variations. The linearly gradient 0.3μm transition region achieves good control of the drain-source on-resistance Ron and Vt variations. For high electric fields, through embodiments of the present invention, the grading (or etching depth) is optimized to reduce the electric field level to about 3MV / cm.

[0110] In one embodiment, an existing Silvaco TCAD model for a FET device is modified to use In in the gate region. 0.15 Ga 0.85 N material. Use material models and strain calculations to calculate In 0.15 Ga 0.85 Expected polarization charge at the N / GaN interface.

[0111] Table 1 shows the 0.15 Ga 0.85 Calculated charge content of the N / GaN interface.

[0112]

[0113] Table 1

[0114] This polarization charge is assumed to occur on the c-planes but not on the channel sidewalls (m-planes), following the typical behavior of III-N heterointerfaces on these planes.

[0115] Fig.19A It is a diagram showing the prediction in the c-plane In 0.15 Ga 0.85 A plot of the effect of the absence of polarization charges on the current density generated at the N / GaN interface. The figure shows a 2D cross-section of the total current density without including polarization. Fig.19A , the current 2001 flows from the channel region between the fin and the gate region to the drift region, but does not pass horizontally through In 0.15 Ga 0.85 The interface between the N gate region and the GaN drift region is fully diffused. Fig.19B is a diagram illustrating the prediction of the c-plane In according to some embodiments of the present invention. 0.15 Ga 0.85 Figure 2. Effect of polarization charges generated at the N / GaN interface. The figure shows a 2D cross section of the total current density including polarization. The net positive fixed charge at the interface due to polarization is expected to attract equal and opposite mobile charges (2D electron gas). The 2DEG at this location results in greater current spreading at the channel opening to the drift layer. Reference Fig.19B , the current 2003 flows horizontally along the lateral surface of the bottom portion of the gate layer via a two-dimensional electron gas (2DEG) and then flows vertically through the drift region in a direction toward the substrate and the drain metal contact, wherein the two-dimensional electron gas is composed of In in the c-plane. 0.15 Ga 0.85 This is caused by polarization of the N / GaN interface, which can provide significant advantages of smaller device size and lower cost compared to existing devices that do not include polarization.

[0116] Fig. 20A It is a diagram showing the prediction in the c-plane In 0.15 Ga 0.85 Diagram of the effect of the electric field generated at the interface between the N gate layer and the GaN drift layer. In the off state, a relatively low electric field is uniformly formed between the gate layer (region) and the drift layer (region). Fig. 20B is a diagram illustrating the prediction of the c-plane In according to some embodiments of the present invention. 0.15 Ga 0.85 Figure 2. Effect of the electric field generated at the N / GaN interface. The figure shows that in the off state a relatively high electric field is formed due to polarization.

[0117] Fig. 20C 2 is a graph illustrating the off-state amplitude of the electric field in the absence of polarization 2111 and in the presence of polarization 2112. Fig. 20C , which illustrates a vertical cut line 2113 through the non-channel (PN junction region). The presence of 2DEG due to polarization results in a high electric field at the interface in the off state.

[0118] Table 2 shows the baseline GaN finFET and the In 0.15 Ga 0.85 Comparison of simulated electrical parameters of N-gate fin FET.

[0119] Baseline FinFET Polar InGaN FinFET I channel 0.8 0.8 N-channel 1.30E+17 1.30E+17 Gradient landing yes yes Fin width (μm) 0.2 0.2 Vth(V) 1.23 1.15 IDSS@1200V(A) 8.70E-12 7.10E-12 Maximum E(MV / cm) 2.92 4.5 Maximum E||(MV / cm) 2.4 2.4 Conductivity / unit channel (S / cm) 6.55E-08 6.60E-0.8

[0120] Table 2

[0121] like Fig.19A , Fig.19B , FIG. 20A to FIG. 20C As shown in Table 2 above, using 15% InGaN is shown to provide the expected benefits (lower threshold voltage Vth 1.15V vs. 1.23V), but with the tradeoff of increased electric field in the off state (4.5MV / cm vs. 2.92MV / cm). It is suggested to use a lower percentage of In, which results in lower polarization charge, or even negligible polarization. Therefore, the simulation results of a non-polar InGaN fin FET structure are shown below.

[0122] Table 3 shows the simulated electrical parameters comparison of the baseline GaN FinFET and the non-polar InGaN gate FinFET.

[0123] Baseline FinFET InGaN FinFET Non-Polar I channel 0.8 0.8 N-channel 1.30E+17 1.30E+17 Gradient landing yes yes Fin width (μm) 0.2 0.2 Vth(V) 1.23 1.15 IDSS@1200V(A) 8.70E-12 7.10E-12 Maximum E(MV / cm) 2.92 2.6 Maximum E||(MV / cm) 2.4 2.4 Conductivity / unit channel (S / cm) 6.55E-08 6.60E-0.8

[0124] Table 3

[0125] Referring to Table 3, the use of InGaN results in a -0.08V threshold voltage shift (1.15V vs. 1.23V) with low electric field (2.6MV / cm vs. 2.92MV / cm). The channel doping can be readjusted to return to the baseline threshold voltage, resulting in very small electrical differences between the structures. The advantages of InGaN will be lower temperature growth and better ohmic contact and P-type doping.

[0126] Fig.21A and Fig. 21B is a graph showing the current density through the channel of a FET ( Fig.21A ) and the associated strip diagrams of the gate and drift regions adjacent to the channel of the FET ( Fig. 21B ). In both figures, the characteristics of the baseline FET (curve 2411) are compared to the characteristics of the non-polar FET (curve 2412) at 150°C. Fig.21A , showing the vertical cut lines of current density through the channel, and Fig. 21BA band diagram of a vertical cross section under the gate in the drift region in the non-channel area adjacent to the FET channel is shown.

[0127] According to an embodiment of the present invention, a fin FET having a P-type gate region utilizing InGaN (e.g., instead of GaN) is provided. The use of InGaN for the P-type gate material provides many benefits that are not available using conventional techniques. For example, some process flows described herein utilize lower InGaN growth temperatures compared to GaN, which are used to protect the regrowth hard mask applied during the regrowth process. In addition, some embodiments utilize magnesium doping, where the Mg dopant is shallower in the InGaN layer, resulting in higher ionization of the dopant at the same temperature. In addition, the lower band gap of InGaN helps to form an ohmic contact to the P-type region.

[0128] It has been described that embodiments of the present invention take into account the effects of polarization to achieve a desired compromise between current spreading and high electric fields.

[0129] The embodiments disclosed herein are not limited in scope by the specific embodiments described herein. In addition to the embodiments described herein, various modifications of these embodiments of the present invention will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. In addition, although some embodiments of the present invention have been described in the context of being specifically implemented in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that their applicability is not limited thereto, and embodiments of the present invention may be advantageously implemented in any environment for any purpose.

Claims

1. A transistor, include: a substrate having a first surface and a second surface opposite to the first surface; a drift region having a doped region on the first surface of the substrate and a graded doped region on the doped region; a semiconductor fin comprising a lower portion and an upper portion, wherein the lower portion protrudes from the graded doping region and includes a portion of the graded doping region, and wherein a metal compound layer is disposed in the upper portion of the semiconductor fin; a source metal contact on the upper portion of the semiconductor fin; a gate layer having a bottom portion directly contacting the graded doping region; as well as A drain metal contact is on the second surface of the substrate.

2. The transistor according to claim 1, in: The semiconductor fin comprises a first dopant concentration; The doped region of the drift region has a second dopant concentration lower than the first dopant concentration; and The graded doping region of the drift region has a third dopant concentration that increases linearly from the second dopant concentration to the first dopant concentration.

3. The transistor according to claim 2, in: The first dopant concentration is about 7.5×10 16 Atom / cm 3 , and the second dopant concentration is about 1×10 16 Atom / cm 3 .

4. The transistor according to claim 1, in: The substrate includes an N+GaN layer; The doped region of the drift region includes an N-GaN layer; The semiconductor fin includes an N GaN layer; and The gate layer includes In x Ga 1-x N layers, where 0 <x<1。 5. The transistor according to claim 4, in: The current first flows horizontally along the lateral surface of the bottom portion of the gate layer via the two-dimensional electron gas and then vertically through the drift region in the direction toward the drain metal contact, the two-dimensional electron gas being composed of the In in the c-plane. x Ga 1-x Caused by the polarization of the N layer.

6. The transistor according to claim 1, further comprising: include: A polar c-plane interface between the gate layer and the graded doped region.

7. The transistor according to claim 1, in: The source metal contact includes a TiN / Ti / Al / Mo stacked structure arranged from bottom to top.

8. The transistor according to claim 1, in: The drift region has a thickness of about 12 μm, the graded doping region has a thickness of about 0.3 μm, and the semiconductor fin has a thickness of about 0.7 μm and a width of about 0.2 μm.

9. The transistor according to claim 1, further comprising: include: A gate contact is provided on the surface of the graded doping region, wherein the gate contact comprises a Ni / Au / Mo / Au stacked structure arranged from bottom to top.

10. The transistor according to claim 1, in: The upper portion of the semiconductor fin includes sidewalls that are substantially parallel to each other.

11. The transistor according to claim 10, in: The upper portion of the semiconductor fin is substantially perpendicular to the substrate.

12. The transistor according to claim 1, in: The lower portion of the semiconductor fin includes sidewalls that are not parallel to each other.

13. The transistor according to claim 12, in: The sidewall of the lower portion of the semiconductor fin forms an angle different from 90 degrees with the substrate.

14. The transistor according to claim 1, in: The gate layer surrounds the semiconductor fin.

15. A method of manufacturing a vertical fin-based field effect transistor (FET), the method include: Providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type; epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, wherein the first semiconductor layer has the first conductivity type and includes a drift layer and a graded doping layer on the drift layer; epitaxially growing a second semiconductor layer having the first conductivity type on the graded doped layer; forming a metal compound layer on the second semiconductor layer; forming a patterned hard mask layer on the metal compound layer; as well as The metal compound layer and the second semiconductor layer are etched using the patterned hard mask layer as a mask to expose a surface of the graded doping layer to form a plurality of fins surrounded by trenches.

16. The method according to claim 15, further comprising: include: epitaxially growing a third semiconductor layer in the trench, the third semiconductor layer having a second conductivity type opposite to the first conductivity type; Etching back the third semiconductor layer to expose a sidewall portion of the fin; forming a silicon dioxide layer on the etched-back third semiconductor layer and covering the patterned hard mask layer and the sidewall portion of the fin, wherein the silicon dioxide layer has a raised portion near the fin; forming a silicon nitride layer on the silicon dioxide layer; isotropically etching the silicon nitride layer and the silicon dioxide layer to expose an upper surface of the silicon dioxide layer and to form silicon nitride spacers on sidewalls of the elevated portions of the silicon dioxide layer; removing a portion of the silicon dioxide layer not covered by the silicon nitride spacer to expose a first surface portion of the third semiconductor layer; as well as The silicon nitride spacers and the patterned hard mask layer are removed.

17. The method according to claim 16, further comprising: include: forming a patterned source mask covering the exposed surface of the second semiconductor layer and exposing the surface of the metal compound layer; forming a source stack structure including Ti, Al and Mo from bottom to top on the metal compound layer; as well as The patterned source mask is removed.

18. The method according to claim 17, further comprising: include: forming a gate mask on the source stack structure and the elevated portion of the silicon dioxide layer to expose a second surface portion of the second semiconductor layer; forming a gate structure on the exposed second surface portion of the second semiconductor layer; as well as The gate mask is removed.

19. The method according to claim 18, in: The second semiconductor layer includes In x Ga 1-x N, where 0 <x<1。 20. The method according to claim 19, further comprising: include: forming a nitride interlayer dielectric layer covering the source stack structure, the gate structure and the exposed surface of the second semiconductor layer; forming an oxide interlayer dielectric layer covering the nitride interlayer dielectric layer; forming a patterned photoresist layer on the oxide interlayer dielectric layer; Etching the oxide interlayer dielectric layer and the nitride interlayer dielectric layer using the patterned photoresist layer to form a via extending to the source stack structure; as well as The via is filled with a conductive material.

21. The method according to claim 20, in: The via has a diameter of about 0.45 μm.

22. The method according to claim 19, in: The gate structure includes a metal stack including Ni, Au, Mo, and Au arranged from bottom to top.

23. The method according to claim 15, further comprising: include: A drain electrode is formed on the second surface of the semiconductor substrate.

24. The method according to claim 15, in: The semiconductor substrate includes N+GaN having a first dopant concentration, the second semiconductor layer includes N GaN having a second dopant concentration lower than the first dopant concentration, the drift layer of the first semiconductor layer includes N-GaN having a third dopant concentration lower than the second dopant concentration, and the graded doping layer of the first semiconductor layer includes a fourth dopant concentration that linearly increases from the third dopant concentration to the second dopant concentration.

25. The method according to claim 15, in: The drift layer has a thickness of about 12 μm, the graded doping layer has a thickness of about 0.3 μm, each of the fins has a thickness of about 0.7 μm and a width of about 0.2 μm, and the fins are spaced apart from each other at intervals of about 2 μm.

26. The method according to claim 15, further comprising: include: epitaxially growing a third semiconductor layer in the trench, the third semiconductor layer having a second conductivity type opposite to the first conductivity type; Etching back the third semiconductor layer, and planarizing the upper surface of the third semiconductor layer and exposing the sidewall portion of the fin; forming a first dielectric layer on the planarized third semiconductor layer and covering the patterned hard mask layer and the sidewall portion of the fin; forming a second dielectric layer on the first dielectric layer; forming a third dielectric layer on the second dielectric layer; etching back the third dielectric layer to form spacers on sidewalls of the second dielectric layer; removing a portion of the second dielectric layer not covered by the spacer to expose a portion of an upper surface of the first dielectric layer above the planarized third semiconductor layer; as well as The spacers and the patterned hard mask layer are removed.

27. The method according to claim 26, in: The first dielectric layer includes Si 3 N 4 , the second dielectric layer includes SiO 2 , and the third dielectric layer includes Si 3 N 4 .

28. The method according to claim 27, in: The first dielectric layer has a thickness of about 100 nm, the second dielectric layer has a thickness of about 100 nm, and the third dielectric layer has a thickness of about 400 nm.

29. The method according to claim 26, in: Each of the first dielectric layer, the second dielectric layer, and the third dielectric layer is formed by PECVD at a temperature of about 300°C.

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