Detector Chip Assembly for High-Speed Optical Signal Reception

Abstract

The present invention discloses a detector chip assembly for high-speed optical signal reception, comprising: a detector chip; a TIA; at least two leads connected to the output end of the TIA for connecting to an external circuit; a capacitor located between the detector chip and the TIA; one end of the capacitor being grounded together with the detector chip; the capacitor being connected in parallel with the TIA; and at least two sections of gold wires, a first gold wire connecting the detector chip and the capacitor, and a second gold wire connecting the capacitor and the TIA. The detector chip of the present invention converts the received high-speed modulated optical signal into an electrical signal, and the electrical signal is input to the TIA through an inductor and a capacitor and then input to the external circuit through the leads after being amplified by the TIA. By selecting appropriate inductors and capacitors, the present invention can greatly increase the effective reception bandwidth of the detector chip, thereby realizing the reception of high-speed optical signals by using low-cost and low-bandwidth detector chips.

Description

Technical Field

[0001] The present invention relates to a signal transmission device in the field of communications, and particularly to a detector chip assembly for high-speed optical signal reception. Background Art

[0002] With the explosive growth of information brought about by the applications of technologies such as high-definition video, 5G mobile communications, and the popularization of the Internet of Things, communication networks are facing increasing pressure for bandwidth growth. The traditional 10G transmission technology is no longer sufficient to meet the current bandwidth requirements, and the development of 100G / 400G / 800G transmission technologies has become inevitable. However, during the upgrade process from the traditional 10G network to above 100G, many challenges are faced, and one of them is the demand for a detector chip for high-bandwidth, low-cost, and reliable high-speed optical signal reception.

[0003] The bandwidth of a semiconductor photodiode detector is mainly limited by the junction capacitance and parasitic capacitance of the chip. Therefore, to increase the reception bandwidth of a semiconductor photodiode detector chip, the most direct method is to reduce the light-receiving area to lower the junction capacitance and parasitic capacitance of the detector chip, thereby increasing the 3dB bandwidth of the receiving chip. However, reducing the light-receiving area will greatly increase the difficulty of coupling the signal light from the optical fiber to the detector chip and the packaging manufacturing cost. For example, expensive aspherical lenses need to be used, and the coupling accuracy and stability need to reach sub-microns. These not only increase the material cost, but also greatly reduce the manufacturing efficiency and yield. If a low-bandwidth detector chip can be used to increase the reception bandwidth of the detector through the peripheral circuit without significantly reducing the light-receiving area, it will have great practical significance.

[0004] The packaging structure of a traditional detector chip is as Figure 1 shown, including a detector chip 1, a transimpedance amplifier (TIA) 2, and leads 4 for outputting high-speed electrical signals connected to an external circuit. The detector chip 1 and the TIA 2 are directly connected by a gold wire 3 ( Figure 1 the external drive voltage lead of the TIA 2 and the decoupling capacitor that may be required are not shown in Figure 2 ). Generally, to minimize the parasitic effects introduced by the packaging as much as possible, the gold wire 3 connecting the detector chip 1 and the TIA 2 needs to be as short as possible to reduce the self-inductance generated by the gold wire itself. As Figure 2 shown, it is the small-signal S21 curve simulated based on a detector chip with a junction capacitance and parasitic capacitance of 0.075 pF (picofarad); this figure is based on the equivalent circuit of the detector chip (the TIA 2 is replaced by a 50-ohm load), and the bandwidth of the detector chip can be calculated;

[0005] However, research has found that adding a certain inductance between the detector chip 1 and the TIA 2 can increase the receiving bandwidth of the detector. Based on this idea, a packaging structure of the detector chip as shown in Figure 3 can be adopted. An inductance 5 is added between the detector chip 1 and the TIA 2 in this packaging structure to increase the receiving bandwidth of the detector chip. Among them, the detector chip 1 is connected to the inductance 5 through a gold wire 3, and the inductance 5 and the signal electrode of the TIA 2 are also connected through a gold wire 3. After testing, adding an inductance can generally increase the bandwidth of the detector chip by about 50%. As shown in Figure 4 , when the inductance 5 is 0.1 nH (nanohenry), the 3dB bandwidth increases from 20.4 GHz without inductance to 26.2 GHz; when the inductance increases to 0.2 nH, the 3dB bandwidth increases to 29.1 GHz; when the inductance is 0.3 nH, the 3dB bandwidth no longer increases and returns to 28 GHz. Although the detector bandwidth can be increased from 20.4 GHz to 29.1 GHz by introducing inductance, to receive a 50 Gbps optical signal, generally, the 3dB bandwidth of the detector is required to reach above 33 GHz. Therefore, simply adding an inductance is still not sufficient to ensure the reception of 50 Gbps signals and cannot be applied to 50 Gbps networks. SUMMARY OF THE INVENTION

[0006] The technical problem to be solved by the present invention is to provide a detector chip assembly for high-speed optical signal reception, which can increase the receiving bandwidth of the photodiode detector, so that a detector chip with a low bandwidth can be applied to the reception of high-speed optical signals without reducing the light-receiving area.

[0007] To solve the above technical problem, the technical solution of the detector chip assembly for high-speed optical signal reception of the present invention is as follows:

[0008] It includes: a detector chip; a TIA; at least two leads connected to the output end of the TIA for connecting to an external circuit; a capacitor located between the detector chip and the TIA; one end of the capacitor is grounded with the detector chip; the capacitor is connected in parallel with the TIA; and at least two gold wires, the first gold wire connects the detector chip and the capacitor, and the second gold wire connects the capacitor and the TIA.

[0009] In another embodiment, the length of the first gold wire is greater than 0.1 mm.

[0010] In another embodiment, the self-inductance generated by the first gold wire is between 0.01 nH and 1 nH; and / or the self-inductance generated by the second gold wire is between 0.01 nH and 0.5 nH.

[0011] In another embodiment, the detector chip, the capacitor, and the TIA are packaged in a TO-CAN.

[0012] In another embodiment, the detector chip assembly further includes an inductor. One end of the inductor is connected to the first gold wire, and the other end of the inductor is connected to the capacitor. The inductor and the capacitor are located between the detector chip and the TIA chip. The inductor is in series with the detector chip. The series-connected inductor and detector chip are in parallel with the capacitor. The length of the first gold wire is not greater than 0.1 mm.

[0013] In another embodiment, the detector chip, the inductor, the capacitor, and the TIA are packaged in a TO-CAN.

[0014] In another embodiment, the inductor and the capacitor are integrated on the same substrate. There is a metal thin film on the substrate.

[0015] In another embodiment, the detector chip is located on the substrate where the inductor and the capacitor are located; or, the detector chip is located on a substrate different from the substrate where the inductor and the capacitor are located.

[0016] In another embodiment, the inductance value is between 0.01 nH and 1 nH.

[0017] In another embodiment, the capacitance value is between 0.001 pF and 0.2 pF.

[0018] In another embodiment, the substrate is an aluminum nitride, alumina, quartz, or silicon-based substrate.

[0019] In another embodiment, the detector chip is a semiconductor photodiode detector chip.

[0020] The technical effects that the present invention can achieve are:

[0021] By adding a parallel capacitor, the present invention further improves the bandwidth of the detector chip, so that a 25G detector can be applied to the reception of 50G signals, realizing an increase in the bandwidth of the detector chip assembly at low cost and conveniently.

[0022] The detector chip of the present invention converts the received high-speed modulated optical signal into an electrical signal. The electrical signal is input to the TIA through the inductor and capacitor, and after being amplified by the TIA, it is input to the external circuit through the lead. By selecting appropriate inductors and capacitors, the detector chip assembly of the present invention can greatly increase the effective reception bandwidth of the detector chip, thereby realizing the reception of high-speed optical signals using low-cost and low-bandwidth detector chips.

[0023] The present invention utilizes a circuit based on thin-film technology and a low-bandwidth detector chip with low cost and large light-receiving area to achieve the improvement of the detector bandwidth and the reception of high-speed optical signals, without the need to develop a high-bandwidth detector chip with great technical difficulty, which will solve the limitation of the shortage of high-bandwidth detector chips in the current market.

[0024] The present invention can be compatible with the existing detector chip packaging technology, without the need to develop a new packaging process and increase the chip packaging size, and can be applied to all optical devices and optical modules. Therefore, the technical solution of the present invention can ensure mass production, and at the same time, compared with high-bandwidth detector chips, it has lower cost and better reliability.

[0025] The present invention can overcome the defects of existing semiconductor optoelectronic detector chips applied to the reception of optical signals of 25G and above, and can use low-bandwidth optoelectronic detector chips for the reception of high-speed optical signals of 25G and above, so as to utilize the existing mature low-cost and high-reliability detector chips and assembly manufacturing processes to achieve the reception of high-speed signals of 25G and above. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following will further elaborate on the present invention in conjunction with the drawings and specific embodiments, in order to more clearly understand its structure and working principle, but the protection scope of the present invention cannot be limited thereby.

[0027] Those skilled in the art should understand that the following description only schematically illustrates the principle of the present invention, and the principle can be applied in various ways to achieve many different alternative embodiments. These descriptions are only used to show the general principle of the teaching content of the present invention, and do not mean to limit the inventive concept disclosed herein.

[0028] The drawings incorporated in this specification and constituting a part of this specification illustrate embodiments of the present invention and, together with the general description above and the detailed description of the following drawings, are used to explain the principle of the present invention.

[0029] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments:

[0030] Figure 1 is a schematic structural diagram of a detector chip assembly in the prior art;

[0031] Figure 2 is Figure 1 the intrinsic small-signal response curve graph of the shown chip, where the abscissa in the graph is frequency (unit: GHz) and the ordinate is small-signal response (unit: dB);

[0032] Figure 3 is a schematic structural diagram of a detector chip assembly with an inductor in the prior art;

[0033] Figure 4 is Figure 3 The small-signal response curve diagram simulated after adding different inductors to the shown chip;

[0034] Figure 5 is the structural schematic diagram of Embodiment 1 of the detector chip assembly for high-rate optical signal reception of the present invention;

[0035] Figure 6 is the small-signal response curve diagram after adding different capacitors when the inductance value in Embodiment 1 is 0.2 nH;

[0036] Figure 7 is the small-signal response curve diagram after adding different capacitors when the inductance value in Embodiment 1 is 0.3 nH;

[0037] Figure 8 is the structural schematic diagram of Embodiment 2 of the detector chip assembly for high-rate optical signal reception of the present invention, which replaces the inductor with a gold wire;

[0038] Figure 9 is the small-signal response curve diagram in Embodiment 2 when considering the inductance introduced by the gold wire connecting the capacitor and the TIA.

[0039] Explanation of the reference numerals in the figure:

[0040] 1 is the detector chip, 2 is the transimpedance amplifier (TIA),

[0041] 3 is the first gold wire, 4 is the lead,

[0042] 5 is the inductor, 6 is the capacitor,

[0043] 7 is the substrate, 8 is the second gold wire. Detailed implementation manners

[0044] The core idea of the present invention is to combine an externally added circuit based on inductance and capacitance with a detector chip to increase the optical signal reception bandwidth of the detector chip. The semiconductor detector chip generates electrons and holes by absorbing photons, converting the high-speed optical signal into a high-speed electrical signal. Although theoretically, the bandwidth of the chip can be increased by reducing the size of the chip to meet the requirements of 50G or even 100G bandwidth. However, due to the limitations of semiconductor materials and chip manufacturing processes, the physical size cannot be infinitely reduced. A more serious problem is that the reduction of the light-receiving area will make it increasingly difficult to couple the optical signal from the optical fiber to the detector chip. When the light-receiving area is reduced to about 20 microns, an aspherical lens is required to achieve low-loss coupling between the optical fiber and the detector chip; when it is reduced to less than 10 microns, even with an aspherical lens, the coupling loss increases significantly, and the production efficiency and device reliability are also greatly reduced because the requirement for coupling accuracy reaches the sub-micron level. In addition, due to the reduction of the light spot, the detector absorption surface is near the focus. If a traditional packaging structure is used, it is extremely difficult to control the return loss of the device. All these will increase the packaging and manufacturing costs of high-bandwidth detector chips.

[0045] With the externally added inductance and capacitance, the present invention can appropriately adjust the overall performance of the circuit to increase the reception bandwidth of the detector chip assembly without significantly reducing the light-receiving area of the detector. Hereinafter, taking a 50G detector chip assembly as an example, the present invention will be described in detail on how to use a low-bandwidth detector chip to achieve high-speed 50Gbps signal reception. The technical solution of the present invention is also applicable to the bandwidth improvement of detector chips with high speeds above 25G.

[0046] Based on the above invention idea, the present invention combines a detector chip with a compensation circuit composed of capacitance and inductance to form a detector chip assembly. The high-speed optical signal is not directly connected to the TIA or other loads, but first passes through the compensation circuit and then enters the TIA to output a high-speed electrical signal, thereby achieving the reception of high-speed signals.

[0047] The detector chip assembly of the present invention for receiving high-speed optical signals mainly includes a detector chip, capacitance and inductance, a TIA, and leads for connecting to an external circuit. The leads are used to output high-speed electrical signals; among them, one end of the inductance is connected to the detector chip, the other end is connected to the capacitance, and is connected to the TIA through the capacitance; the capacitance is in parallel with the inductance and the TIA.

[0048] After the detector chip of the present invention converts the received optical signal into an electrical signal, it will first pass through a circuit composed of inductance and capacitance and then be added to the TIA. By selecting appropriate values of inductance and capacitance, the frequency response of the entire circuit can be modulated to increase the reception bandwidth of the entire detector chip assembly.

[0049] To achieve the above object of realizing high-speed optical signal reception based on a low-bandwidth detector chip, the present invention is described by the following embodiments.

[0050] Embodiment 1

[0051] As Figure 5 shown, the detector chip assembly for high-speed optical signal reception of the present invention includes a detector chip 1, a TIA 2, an inductor 5, a capacitor 6, and a lead 4 connecting to an external circuit. The detector chip 1, TIA 2, inductor 5, and capacitor 6 are pasted on the same substrate 7; there is a metal thin film on the substrate 7; the detector chip 1 is connected to one end of the inductor 5 through a first gold wire 3, the other end of the inductor 5 is connected to one end of the capacitor 6, and this end of the capacitor 6 is connected to the TIA 2 through a second gold wire; the other end of the capacitor 6 is grounded; the capacitor 6 forms a parallel connection with the inductor 5 and the TIA 2; the lead 4 can output high-speed electrical signals.

[0052] As a preferred embodiment, the inductor 5 and capacitor 6 can be made by a thin film process and integrated on the substrate 7 to facilitate packaging and save costs;

[0053] The inductance value of the inductor 5 is controlled by the size of the metal thin film;

[0054] The capacitor 6 can adopt a planar capacitor, and its capacitance value is controlled by the area and / or the thickness of the dielectric layer;

[0055] The specific values of the inductor 5 and capacitor 6 can be optimized based on the performance of the detector chip 1; preferably, the value of the inductor 5 is between 0.01 nH and 1 nH; the value of the capacitor 4 is between 0.001 pF and 0.2 pF.

[0056] The following takes an example to illustrate how the present invention uses the inductor 5 and capacitor 6 to use a 25G low-bandwidth detector chip for 50Gbps optical signal reception. The intrinsic bandwidth of this 25G detector chip is 20.4 GHz; when an inductor with an inductance value of 0.2 nH is added, the reception bandwidth will increase to 29.1 GHz, but still cannot fully meet the reception of 50Gbps signals; when the LC circuit in Embodiment 1 is added, by selecting appropriate inductors and capacitors, the reception bandwidth of the detector chip assembly can be further improved.

[0057] As Figure 6 shown are the corresponding small-signal bandwidths when the inductor is 0.2 nH and the capacitor is 0.01 pF, 0.03 pF, 0.05 pF, 0.07 pF, and 0.09 pF. Figure 6 It is shown that when the inductor 5 is 0.2 nH, after adding a capacitor 6, the 3dB bandwidth is not improved, but the flatness of the small-signal response is significantly improved, so the quality of the received signal will be improved.

[0058] As Figure 7 shown, the corresponding small-signal response curves are for an inductor of 0.3 nH and capacitors of 0, 0.02, 0.04, 0.06, 0.08, 0.1, 0.12, and 0.15 pF respectively, and their corresponding bandwidths are 28, 29, 30.6, 33.1, 35.3, 36.2, 36.3, and 35.8 GHz respectively. Figure 7 It is shown in that when the inductor is 0.3 nH, adding capacitor 6 will increase the bandwidth. When the capacitance value is from 0.1 to 0.13 pF, the receiving bandwidth can increase from 28 GHz to greater than 36 GHz, which is sufficient to meet the receiving requirements of 50 Gbps signals. Therefore, adding capacitor 6 will suppress the original low-frequency resonance caused by the inductor, increase the high-frequency response, thus making the frequency response flat and increasing the bandwidth of the detector chip assembly.

[0059] In Embodiment 1, inductor 5 is made by a thin-film process and is located on the same substrate 7 as capacitor 6; the laser chip 1 is connected to inductor 2 by a gold wire 3. Since the diameter of the gold wire used for chip connection is generally about 25 microns and will generate self-inductance itself, inductor 2 in Embodiment 1 can be replaced by a gold wire to form Embodiment 2 of the present invention.

[0060] Embodiment 2

[0061] As Figure 8 shown, the original inductor 5 located on the same substrate 7 as capacitor 6 is replaced by a first gold wire 3 of a certain length; the first gold wire 3 not only provides the connection between capacitor 6 and the detector chip 1, but also acts as the inductor 5. Compared with Embodiment 1, replacing inductor 2 with a gold wire in Embodiment 2 can not only reduce costs, but also since the length of the gold wire can be adjusted during chip packaging and the inductance value changes accordingly, gold wires of different lengths will be able to act as adjustable inductors. Since the parameters of detector chips from different suppliers are different, adjusting the inductance value by changing the length of the first gold wire will greatly facilitate adjusting the resonance characteristics for different detector chips to obtain the best response performance. The size of the first gold wire 3 is adjusted according to the performance of the detector chip to obtain the best receiving bandwidth.

[0062] In Embodiment 2, capacitor 6 is connected to TIA2 by a second gold wire 8; this second gold wire 8 will also generate self-inductance and acts as a second inductor to improve the small-signal response curve of the detector assembly and further improve the quality of the received signal. Simulation shows that although the second gold wire 8 cannot increase the bandwidth, it can improve the flatness of the small-signal response curve.

[0063] Figure 9The bandwidth is simulated after adding the inductance (inductance values of 0.01, 0.1, 0.15, 0.2 nH) introduced by the second gold wire 8 in Embodiment 1; when the inductance value is less than 0.2 nH, the change in bandwidth is less than 1 GHz, but the small-signal low-frequency response is improved, and the original high-frequency overshoot is reduced. Therefore, the quality of the received signal will be greatly improved. Figure 9 The illustration in Figure 9 . The left side corresponds to the received eye diagram of 0.01 nH, and the right side corresponds to the received eye diagram of 0.15 nH. It can be seen that the splitting and jitter of the original eye diagram caused by the uneven high- and low-frequency responses are significantly improved after adding the inductance caused by the gold wire 8.

[0064] In the above embodiments, the detector chip 1 and the TIA 2 are located on the substrate 7 where the inductor 5 and the capacitor 6 are located, but this is not necessary. The TIA 2 can also be placed on another substrate and then connected to the components on the substrate 7 through gold wires. The detector chip assemblies of the above Embodiment 1 and Embodiment 2 can be encapsulated in a standard TO-CAN (diode package module), and the drive source and output signal of the TIA can be directly connected to the pins of the TO through gold wires.

[0065] Obviously, those skilled in the art can make various changes and deformations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these changes and deformations.

Claims

1. A detector chip assembly for high-speed optical signal reception, characterized in that, Comprising: A detector chip; A TIA; At least two leads connecting the output of the TIA for connection to an external circuit; A capacitor located between the detector chip and the TIA; one end of the capacitor is grounded with the detector chip; the capacitor is in parallel with the TIA; And At least two gold wires, the first gold wire connecting the detector chip and the capacitor, and the second gold wire connecting the capacitor and the TIA; The detector chip assembly further includes an inductor, one end of the inductor is connected to the first gold wire, and the other end of the inductor is connected to the capacitor; the inductor and the capacitor are located between the detector chip and the TIA chip; the capacitor and the inductor form a compensation circuit.

2. The detector chip assembly for high-rate optical signal reception according to claim 1, wherein: The length of the first gold wire is greater than 0.1 mm.

3. The detector chip assembly for high-speed optical signal reception according to claim 1, characterized in that: The self - inductance generated by the first gold wire is between 0.01 nH and 1 nH; and / or the self - inductance generated by the second gold wire is between 0.01 nH and 0.5 nH.

4. The detector chip assembly for high-rate optical signal reception according to claim 1, wherein: The detector chip, the capacitor and the TIA are encapsulated in a TO - CAN.

5. The detector chip component for high-rate optical signal reception according to claim 1, wherein The inductor is in series with the detector chip; the series - connected inductor and detector chip are in parallel with the capacitor.

6. The detector chip assembly for high-speed optical signal reception according to claim 5, wherein: The detector chip, the inductor, the capacitor and the TIA are encapsulated in a TO - CAN.

7. The detector chip assembly for high-rate optical signal reception according to claim 5, wherein: The inductor and the capacitor are integrated on the same substrate; there is a metal thin film on the substrate.

8. The detector chip assembly for high-speed optical signal reception according to claim 7, characterized in that: The detector chip is located on the substrate where the inductor and the capacitor are located; or, the detector chip is located on a substrate different from the substrate where the inductor and the capacitor are located.

9. The detector chip assembly for high-speed optical signal reception according to claim 5, characterized in that: The inductance value is between 0.01 nH and 1 nH.

10. The detector chip assembly for high-rate optical signal reception according to claim 1 or 9, characterized in that: The capacitance value is between 0.001 pF and 0.2 pF.

11. The detector chip assembly for high-rate optical signal reception according to any one of claims 1 to 9, characterized in that: The substrate is an aluminum nitride, alumina, quartz or silicon - based substrate.

12. The detector chip assembly for high-rate optical signal reception according to any one of claims 1 to 9, characterized in that: The detector chip is a semiconductor photodiode detector chip.

Images