A phase-locked loop circuit capable of fast locking

Abstract

The present invention discloses a phase-locked loop circuit capable of fast locking, comprising: a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider connected in sequence to form a loop, and also comprising: a fast charging circuit, wherein the two output ends of the phase frequency detector respectively output a digital signal UP and a digital signal DN to the fast charging circuit; and the fast charging circuit outputs a current signal to the loop filter. The present invention effectively reduces the locking time while maintaining the performance index and power consumption index of low output jitter.

Description

Technical Field

[0001] The present invention relates to a phase-locked loop circuit. Background Art

[0002] Phase-locked loop (PLL) technology is often used to meet the clock requirements of subsystems or I / O devices in the growing number of mobile devices and consumer electronics. These mobile devices are often battery-powered. To conserve power, system design requires that the clock generator, the PLL, possess fast locking capabilities so that the operating system can quickly switch from sleep mode to normal operation. Therefore, a PLL circuit with fast locking capabilities is an essential component of low-power mobile devices.

[0003] like Figure 2 As shown in the figure, a traditional phase-locked loop circuit primarily consists of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a divider. The PFD operates by detecting the frequency and phase difference between the input reference clock (REFCLK) and the feedback clock (FBCLK). The charge pump converts this difference into a charge and discharge current, which then passes through the loop filter to output the voltage control signal VCTRL for the voltage-controlled oscillator. The VCO then generates a clock signal CKOUT based on the loop parameters based on the input voltage signal.

[0004] The existing technology mainly adopts the method of increasing the small signal bandwidth to shorten the locking time. However, the increase of the small signal bandwidth will worsen the phase noise of the entire phase-locked loop output, thereby causing the output jitter performance of the entire circuit to deteriorate. Summary of the Invention

[0005] The object of the present invention is to provide a phase-locked loop circuit capable of fast locking, effectively reducing the locking time while maintaining the performance index of low output jitter and power consumption index.

[0006] The technical solution to achieve the above purpose is:

[0007] A phase-locked loop circuit capable of fast locking comprises: a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider which are connected in sequence to form a loop, and also comprises: a fast charging circuit,

[0008] The two output terminals of the phase and frequency detector respectively output a digital signal UP and a digital signal DN to the fast charging circuit;

[0009] The fast charging circuit outputs a current signal to the loop filter.

[0010] Preferably, the two output terminals of the phase frequency detector are connected to the two input terminals of the charge pump;

[0011] The output end of the charge pump is connected to the input end of the loop filter and the input end of the voltage controlled oscillator;

[0012] The output end of the voltage-controlled oscillator serves as a circuit signal output end and is connected to the input end of the frequency divider;

[0013] The output end of the frequency divider outputs a feedback clock to one input end of the phase frequency detector, and the other input end of the phase frequency detector receives a reference clock.

[0014] Preferably, the loop filter includes a resistor, a first capacitor and a second capacitor which are connected in series to form a loop, wherein the connected ends of the first capacitor and the second capacitor are grounded; and the connected ends of the resistor and the first capacitor are connected to the output end of the fast charging circuit.

[0015] Preferably, the fast charging circuit includes: a first OR gate circuit, a second OR gate circuit, an AND gate circuit, a first D flip-flop, a second D flip-flop, a third D flip-flop, a latch and a switch, wherein:

[0016] The clock terminal of the first D flip-flop receives the digital signal UP, the D input terminal is connected to the output terminal of the first OR gate circuit, and the Q non-output terminal is connected to the first input terminal of the first OR gate circuit;

[0017] The second input terminal of the first OR gate circuit is connected to the Q output terminal of the second D flip-flop;

[0018] A first input terminal of the second OR gate circuit is connected to the Q output terminal of the second D flip-flop, a second input terminal of the second OR gate circuit is connected to the Q output terminal of the first D flip-flop, and an output terminal of the second OR gate circuit is connected to the D input terminal of the second D flip-flop;

[0019] The clock terminal of the second D flip-flop receives the digital signal UP, and the Q non-output terminal receives the digital signal DN;

[0020] The first input terminal of the AND gate circuit is connected to the Q output terminal of the second D flip-flop, the second input terminal of the AND gate circuit is connected to the Q output terminal of the first D flip-flop, and the output terminal of the AND gate circuit is connected to the D input terminal of the third D flip-flop;

[0021] The clock terminal of the third D flip-flop receives the digital signal UP, and the Q non-output terminal receives the digital signal DN;

[0022] The Q output terminal of the third D flip-flop is connected to the input terminal of the latch, and the output terminal of the latch is connected to the control terminal of the switch;

[0023] One end of the switch is connected to a power supply, and the other end is connected to the loop filter.

[0024] Preferably, the first D flip-flop, the second D flip-flop, the third D flip-flop and the latch all receive a reset signal.

[0025] The beneficial effects of the present invention are as follows: Based on the traditional phase-locked loop circuit architecture, the present invention combines a digitally assisted quick-charge circuit to charge the loop filter (LPF) to expand the large signal bandwidth, thereby reducing the lock time. This control method can achieve a reduction of lock time by more than 50%, while maintaining the performance indicators of low output jitter and power consumption indicators. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a structural diagram of a phase-locked loop circuit in the prior art;

[0027] Figure 2 It is a structural diagram of the phase-locked loop circuit in the present invention;

[0028] Figure 3 1. It is a comparison diagram of the locking process of the traditional phase-locked loop circuit and the phase-locked loop circuit of the present invention;

[0029] Figure 4 It is a structural diagram of the fast charging circuit in the present invention. DETAILED DESCRIPTION

[0030] The present invention will be further described below with reference to the accompanying drawings.

[0031] See also Figure 1 The phase-locked loop circuit capable of fast locking of the present invention comprises: a phase frequency detector 1, a charge pump 2, a loop filter 3, a voltage-controlled oscillator 4, a frequency divider 5, and a fast charging circuit 6, which are connected in sequence to form a loop.

[0032] The two output terminals of the phase frequency detector 1 respectively output digital signals UP and DN to the fast charge circuit 6. The fast charge circuit 6 outputs a current signal to the loop filter 3. The two output terminals of the phase frequency detector 1 are connected to the two input terminals of the charge pump 2. The output terminal of the charge pump 2 is connected to the input terminal of the loop filter 3 and the input terminal of the voltage-controlled oscillator 4. The output terminal of the voltage-controlled oscillator 4 serves as the circuit signal output terminal and is connected to the input terminal of the frequency divider 5. The output terminal of the frequency divider 5 outputs the feedback clock FBCLK to one input terminal of the phase frequency detector 1. The other input terminal of the phase frequency detector 1 receives the reference clock REFCLK.

[0033] The loop filter 3 includes a resistor R1, a first capacitor C1 and a second capacitor C2 connected in series to form a loop, wherein the connecting end of the first capacitor C1 and the second capacitor C2 is grounded; the connecting end of the resistor R1 and the first capacitor C1 is connected to the output end of the fast charging circuit 6.

[0034] like Figure 4 As shown, the fast charging circuit 6 includes: a first OR gate circuit 61 , a second OR gate circuit 62 , an AND gate circuit 63 , a first D flip-flop 64 , a second D flip-flop 65 , a third D flip-flop 66 , a latch 67 and a switch 68 .

[0035] The clock terminal of the first D flip-flop 64 receives the digital signal UP, its D input terminal is connected to the output terminal of the first OR circuit 61, and its Q NOT output terminal is connected to the first input terminal of the first OR circuit 61. The second input terminal of the first OR circuit 61 is connected to the Q output terminal of the second D flip-flop 65. The first input terminal of the second OR circuit 62 is connected to the Q output terminal of the second D flip-flop 65, the second input terminal of the second OR circuit 62 is connected to the Q output terminal of the first D flip-flop 64, and the output terminal of the second OR circuit 62 is connected to the D input terminal of the second D flip-flop 65. The clock terminal of the second D flip-flop 65 receives the digital signal UP, and the Q NOT output terminal receives the digital signal DN. The first input terminal of the AND circuit 63 is connected to the Q output terminal of the second D flip-flop 65, the second input terminal of the AND circuit 63 is connected to the Q output terminal of the first D flip-flop 64, and the output terminal of the AND circuit 63 is connected to the D input terminal of the third D flip-flop 66. The clock terminal of the third D flip-flop 66 receives the digital signal UP, and the Q NOT output terminal receives the digital signal DN. The Q output of the third D flip-flop 66 is connected to the input of the latch 67, and the output of the latch 67 is connected to the control terminal of the switch 68. One end of the switch 68 is connected to the power supply, and the other end is connected to the loop filter 3. The power supply is a current source supply circuit.

[0036] The first D flip-flop 64, the second D flip-flop 65, the third D flip-flop 66, and the latch 67 all receive a reset signal RESET. The number and connection of the D flip-flops can be individually designed according to the application bandwidth.

[0037] from Figure 3 It can be analyzed that the time it takes for the entire phase-locked loop circuit to reach lock is determined by two parts: the large-signal bandwidth and the small-signal bandwidth. The traditional way to reduce the lock time of the phase-locked loop circuit is to increase the small-signal bandwidth. The small-signal bandwidth of the traditional phase-locked loop circuit is shown in Formula 1:

[0038]

[0039] Where KVCO represents the gain of the VCO; Icp represents the charge pump charge and discharge current; N represents the divider ratio; and R represents the resistor R1 of the loop filter.

[0040] For mobile device SOCs that require fast locking, the small signal bandwidth fc of the phase-locked loop can be increased to accelerate the small signal locking process, such as Figure 3However, simply increasing the small signal bandwidth will cause more voltage-controlled oscillator (VCO) phase noise to contribute to the phase noise of the output signal. At the same time, increasing the charge pump current will also increase system power consumption and deteriorate Spur performance.

[0041] Therefore, a fast charging circuit using digital assisted technology is used to improve the large signal bandwidth of the system, such as Figure 3 As shown, it can take into account both power consumption and output jitter performance. The large signal bandwidth is proportional to the charging current I charge , is inversely proportional to the size of the loop filter capacitor C1, as shown in Formula 2. Therefore, increasing the charging current during the large signal locking process and properly controlling the charging time can effectively reduce the locking time of the entire phase-locked loop circuit.

[0042] Large Signal Bandwidth:

[0043]

[0044] A fast-charging circuit employs digitally assisted technology to improve large-signal bandwidth. Specifically, it includes a digital counter and latch that can be set to detect the number of UP / DN pulses. The digital output signal controls the duration of the charging current. The UP / DN pulse counter circuit can set the count period based on the specific design bandwidth; in this example, a four-up counter is used. The charging current on-time can be adjusted based on the charging time. When the count period ends, latch 67 outputs the shutdown signal, shutting off the additional charging current. This puts the system into a small-signal lock state without affecting the overall system's loop transfer function, effectively ensuring the output signal's jitter and power consumption performance.

[0045] From the above derivation process, it can be seen that compared with traditional phase-locked loop technology, the digital auxiliary technology used in this application can effectively control the large signal process during the locking process, and does not introduce additional components to increase power consumption and area. Instead, it directly uses the output signal of the frequency detector and phase detector to control the length of time for the additional charging current of the loop filter to shorten the large signal locking process. Experiments have shown that under the same small signal bandwidth setting, the fast charging circuit mentioned in this application can effectively shorten the locking time by more than 50%.

[0046] The above embodiments are only used to illustrate the present invention, rather than to limit the present invention. Those skilled in the art may make various changes or modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention and should be defined by the claims.

Claims

1. A phase-locked loop circuit capable of fast locking, comprising: The phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider are connected in sequence to form a loop, characterized in that they also include: a fast charging circuit, The two output ends of the frequency and phase detector respectively output a digital signal UP and a digital signal DN to the fast charging circuit; The fast charging circuit outputs a current signal to the loop filter; The fast charging circuit includes: a first OR gate circuit, a second OR gate circuit, an AND gate circuit, a first D flip-flop, a second D flip-flop, a third D flip-flop, a latch and a switch, wherein: The clock end of the first D flip-flop receives the digital signal UP, the D input end is connected to the output end of the first OR gate circuit, and the Q non-output end is connected to the first input end of the first OR gate circuit; The second input terminal of the first OR gate circuit is connected to the Q output terminal of the second D flip-flop; A first input terminal of the second OR gate circuit is connected to a Q output terminal of the second D flip-flop, a second input terminal of the second OR gate circuit is connected to a Q output terminal of the first D flip-flop, and an output terminal of the second OR gate circuit is connected to a D input terminal of the second D flip-flop; The clock terminal of the second D flip-flop receives the digital signal UP, and the Q non-output terminal receives the digital signal DN; The first input end of the AND gate circuit is connected to the Q output end of the second D flip-flop, the second input end of the AND gate circuit is connected to the Q output end of the first D flip-flop, and the output end of the AND gate circuit is connected to the D input end of the third D flip-flop; The clock terminal of the third D flip-flop receives the digital signal UP, and the Q non-output terminal receives the digital signal DN; The Q output terminal of the third D flip-flop is connected to the input terminal of the latch, and the output terminal of the latch is connected to the control terminal of the switch; One end of the switch is connected to a power source, and the other end is connected to the loop filter.

2. The phase-locked loop circuit capable of fast locking according to claim 1, characterized in that: The two output ends of the frequency and phase detector are connected to the two input ends of the charge pump; The output end of the charge pump is connected to the input end of the loop filter and the input end of the voltage controlled oscillator; The output end of the voltage-controlled oscillator serves as a circuit signal output end and is connected to the input end of the frequency divider; The output end of the frequency divider outputs a feedback clock to an input end of the phase frequency detector, and the other input end of the phase frequency detector receives a reference clock.

3. The phase-locked loop circuit capable of fast locking according to claim 1, characterized in that: The loop filter includes a resistor, a first capacitor and a second capacitor which are connected in series in sequence to form a loop, wherein the connecting ends of the first capacitor and the second capacitor are grounded; and the connecting ends of the resistor and the first capacitor are connected to the output end of the fast charging circuit.

4. The phase-locked loop circuit capable of fast locking according to claim 1, characterized in that: The first D flip-flop, the second D flip-flop, the third D flip-flop and the latch all receive a reset signal.

Images