A motherboard and a server

Abstract

Embodiments of the present invention disclose a motherboard and a server, relating to the field of computer technology. It includes a printed circuit board, on which a processor socket, memory slots and a first-rate interface component are provided. The processor socket is used to install a processor, and the first-rate interface component includes multiple PCIE slots, OCP connectors, SATA connectors and M.2 connectors; the processor socket is electrically connected to multiple memory slots, PCIE slots, OCP connectors, SATA connectors and M.2 connectors respectively, and each memory slot supports the installation of any one of UDIMM, RDIMM and LRDIMM. Since the first-rate interface component adopted by the motherboard can support high-speed signal transmission, it is convenient to realize the transmission of high-speed signals. The present invention is applicable to the development, OEM and chip testing scenarios of electronic devices or equipment such as motherboards, computers, industrial control computers and servers.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a motherboard and a server. Background Art

[0002] The motherboard, also known as the mainboard, systemboard or motherboard, is an important component of a computer and determines the functions and performance characteristics of the computer system.

[0003] At present, the motherboards on the market are usually designed according to the requirements of specific application systems. The transmission rate of the IO (Input / Output) signals of some motherboards is limited by the types of IO (Input / Output) interfaces (mainly referring to the types of communication standards adopted), which is not conducive to the transmission of high-speed signals. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a motherboard and a server, which are convenient for realizing the transmission of high-speed signals.

[0005] To achieve the above invention purpose, the following technical solutions are adopted:

[0006] In a first aspect, the motherboard provided by the embodiments of the present invention includes a printed circuit board, on which a processor socket, a memory slot and a first-rate interface component are provided. The processor socket is used to install a processor, and the first-rate interface component includes a plurality of PCIE slots, an OCP connector, a SATA connector and an M.2 connector;

[0007] The processor socket is electrically connected to a plurality of memory slots, PCIE slots, OCP connectors, SATA connectors and M.2 connectors respectively, and each memory slot supports the installation of any one of UDIMM, RDIMM and LRDIMM.

[0008] Optionally, the processor socket is used to install a processor, supports 8-channel memory slots, and each channel of memory slots supports the installation of two memory modules.

[0009] Optionally, the PCIE slots include a first PCIE slot, a second PCIE slot, a third PCIE slot, a fourth PCIE slot, and a fifth PCIE slot. The first PCIE slot is connected to a first input / output interface corresponding to a first group of signal paths of the processor on the processor socket. The second PCIE slot is connected to a second input / output interface corresponding to a second group of signal paths of the processor on the processor socket. The third PCIE slot is connected to a third input / output interface corresponding to a third group of signal paths of the processor on the processor socket. The fourth PCIE slot is connected to a fourth input / output interface corresponding to a fourth group of signal paths of the processor on the processor socket. The fifth PCIE slot is connected to a fifth input / output interface corresponding to a fifth group of signal paths of the processor on the processor socket;

[0010] Among them, the first PCIE slot supports at least PCIE standard cards x8 / x4 / x2 / x1, and the second PCIE slot, the third PCIE slot, the fourth PCIE slot, and the fifth PCIE slot support PCIE standard cards x16 / x8 / x4 / x2 / x1 respectively.

[0011] Optionally, the seventh group of signal paths includes at least 6 paths, and the SATA connectors include:

[0012] MiniSAS HD connectors. There are 4 groups or 6 groups of MiniSAS HD connectors, and each group has 4 SATA interfaces. Among them, at least two groups of MiniSAS HD connectors are connected to the sixth input / output interface through the first signal switch;

[0013] 7-pin SATA interfaces; there are 2 groups of 7-pin SATA interfaces, which are respectively connected to the seventh input / output interface and used to connect to 2 paths in the seventh group of signal paths;

[0014] And an optical disc connector with SATA interfaces, and the optical disc connector with SATA interfaces supports connecting an optical disc drive or a solid-state drive.

[0015] Optionally, the processor socket has a seventh input / output interface corresponding to the seventh group of signal paths of the processor. The seventh group of signal paths includes at least 5 paths. Five of the signals transmitted by the seventh input / output interface are connected to the M.2 connector through a second signal switch. Among them, 4 paths are configured as PCIE signals and 1 path is configured as a SATA signal. The second signal switch is used to switch between one of the 4 paths of PCIE signals and the 1 path of SATA signal.

[0016] Optionally, a baseboard management controller and a second-rate interface component are further provided on the printed circuit board. The signal transmission rate of the second-rate interface component is less than that of the first-rate interface component. One end of the baseboard management controller is electrically connected to the processor socket through a printed circuit, and the other end is electrically connected to the second-rate interface component, which is used to enable the motherboard to support remote task management.

[0017] Optionally, the second-rate interface component includes a UART interface, a JTAG interface, an SPI interface, an LPC interface, an I2C interface, and an APML interface.

[0018] In a second aspect, an embodiment of the present invention provides a server, including the motherboard according to any one of the first aspects, and a processor is installed in the processor socket on the motherboard.

[0019] The motherboard and the server provided by the embodiments of the present invention are improved by improving their own structures. A processor socket, a memory slot, and a first-rate interface component are provided on the printed circuit board. The processor socket is used to install a processor. The first-rate interface component includes multiple PCIE slots, OCP connectors, SATA connectors, and M.2 connectors. The processor socket is electrically connected to multiple memory slots, PCIE slots, OCP connectors, SATA connectors, and M.2 connectors respectively. Each memory slot supports the installation of any one of UDIMM, RDIMM, and LRDIMM. Since the first-rate interface components adopted by the motherboard, such as PCIE slots and SATA connectors, have high bandwidth, they can support high-speed signal transmission. In addition, multiple (i.e., commonly known as multi-channel) memory slots adopted, for example, any one of UDIMM, RDIMM, and LRDIMM, can support memory modules with higher frequencies. In summary, the motherboard composed of the adopted hardware and its topology is convenient for realizing high-speed signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 It is a schematic block diagram of the structure of an embodiment of the motherboard of the present invention;

[0022] Figure 2 It is a schematic block diagram of the structure of another embodiment of the motherboard of the present invention;

[0023] Figure 3Schematic block diagram of the structure of a CPU supported by the motherboard of the present invention;

[0024] Figure 4 Schematic block diagram of the structure of another embodiment of the motherboard in the present invention;

[0025] Figure 5 Schematic block diagram of the structure of another embodiment of the motherboard in the present invention;

[0026] Figures 6 to 8 Schematic block diagram of the structure of an embodiment of the motherboard with a JTAG interface function circuit in the present invention;

[0027] Figure 9 Schematic block diagram of the structure of an embodiment of the motherboard with an SPI interface function circuit in the present invention;

[0028] Figure 10 Schematic block diagram of the structure of an embodiment of the motherboard with a BMC function circuit in the present invention;

[0029] Figure 11 Schematic diagram of the circuit for remotely turning on, off and restarting the motherboard through the BMC network port;

[0030] Figure 12 Schematic block diagram of the structure of an embodiment of the motherboard with a temperature control system interaction interface function circuit in the present invention. Detailed implementation manners

[0031] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] It should be clear that, in order to more clearly illustrate the present invention, numerous technical details are described in the following specific embodiments. Those skilled in the art should understand that the present invention can still be implemented without some of these details. Additionally, in order to highlight the inventive concept of the present invention, some methods, means, components and their applications well-known to those skilled in the art are not described in detail, but this does not affect the implementation of the present invention. The embodiments described herein are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0033] Figure 1 Schematic block diagram of the structure of an embodiment of the motherboard of the present invention; see Figure 1As shown, the mainboard provided by the embodiment of the present invention, commonly known as the motherboard, also called the system board or the motherboard; it is applicable to various electronic devices such as personal computers, industrial control computers, and servers. The mainboard includes a printed circuit board, commonly known as the PCB board; a processor socket is provided on the printed circuit board for installing a processor (CPU: Central Processing Unit / Processor), and the processor socket is also called a processor slot, which is mainly divided into two types: Socket and Slot.

[0034] In one embodiment, the central processing unit is a Haiguang 7100 or Haiguang 7200 series processor, which belongs to the X86 CPU. A SP3 4094 package Socket socket is designed on the printed circuit board of the mainboard for installing the Haiguang 7100 / 7200 CPU; the Haiguang 7100 / 7200 CPU chip is a high-performance chip with rich IO interfaces, and some of its pins are function-configurable interfaces.

[0035] Memory slots; among them, refer to Figure 3 As shown, the Haiguang 7100 / 7200 CPU supports a total of 8-channel memory slots (English: DDR Channel). As Figure 2 shown, its channels are respectively identified as: A, B, C, D, E, F, G, and H. Each channel memory slot supports 2 dual in-line memory modules (dual In-line memory module, abbreviated as DIMM), and a total of 16 DDR4-2667 rate UDIMM / RDIMM / LRDIMM are supported.

[0036] The first-rate interface component; it includes multiple PCIE (PCI-Express: peripheral component interconnect express, which is a high-speed serial computer expansion bus standard) slots, OCP connectors, SATA connectors, and M.2 connectors.

[0037] The processor socket is electrically connected to multiple memory slots, PCIE slots, OCP connectors, SATA connectors, and M.2 connectors respectively. Each memory slot supports the installation of any one of UDIMM, RDIMM, and LRDIMM.

[0038] The OCP connector supports the OCP mezzanine card, the SATA connector supports the standard SATA hard disk, and the M.2 connector supports the M.2 SSD. Among them, PCIE, OCP, SATA, and M.2 are terms in the field of communication technology and can be simply understood as the communication transmission standards of the interfaces.

[0039] The motherboard provided by the embodiment of the present invention is improved by itself in structure. Since the first-rate interface components adopted by the motherboard, such as PCIE slots, SATA connectors, etc., have a high bandwidth, they can support high-speed signal transmission. In addition, multiple (i.e., commonly known as multi-channel) memory slots are adopted, such as any one of UDIMM, RDIMM, and LRDIMM, which can support memory modules with a higher frequency. In summary, the motherboard composed of the adopted hardware and its topology is convenient for realizing the transmission of high-speed signals.

[0040] The PCIE slot is used to connect PCIE devices; in some embodiments, the PCIE slot includes a first PCIE slot, a second PCIE slot, a third PCIE slot, a fourth PCIE slot, and a fifth PCIE slot, which Figure 1 and Figure 2 correspond to 5 PCIE x16 Slot0 / 1 / 2 / 3 / 4 in sequence. The first PCIE slot is connected to the first input / output interface corresponding to the first group of signal paths (Lane) G3[15:8] of the processor on the processor socket, the second PCIE slot is connected to the second input / output interface corresponding to the second group of signal paths P2[15:0] of the processor on the processor socket, the third PCIE slot is connected to the third input / output interface corresponding to the third group of signal paths P3[15:0] of the processor on the processor socket, the fourth PCIE slot is connected to the fourth input / output interface corresponding to the fourth group of signal paths G0[15:0] of the processor on the processor socket, and the fifth PCIE slot is connected to the fifth input / output interface corresponding to the fifth group of signal paths G1[15:0] of the processor on the processor socket.

[0041] As Figure 2 shown, Slot0: is an x8 PCIE connector, connecting the G3[15:8] signal of the CPU. Of course, Slot0 can also be selected to support x16. Slot1-2: are both x16 PCIE connectors, respectively connecting the P2 / P3[15:0] signals of the CPU; Slot3: supports x16 PCIE signals and connects the G0[15:0] signal of the CPU; Slot4: supports x16 PCIE signals and connects the G1[15:0] signal of the CPU.

[0042] Among them, the first PCIE slot supports at least PCIE standard cards x8 / x4 / x2 / x1, and the second, third, fourth, and fifth PCIE slots support PCIE standard cards x16 / x8 / x4 / x2 / x1 respectively.

[0043] The x16, x8, x4, x2, and x1 respectively represent the number of transmission channels (i.e., the aforementioned paths, English is Lane). For example, x16 represents 16 channels.

[0044] In this embodiment, the PCIE slots are PCIE 3.0 slots, and there are five of them, among which 3 are vertical slots, 1 is a straddle slot, and the other 1 is a right angle slot.

[0045] According to actual application requirements, the PCIE Slot can be arranged at different positions on the PCB board to support built-in plug-in cards or rear I / O plug-in cards, and also support being designed as horizontal plug-in cards or vertical plug-in cards, etc. Slots 1-4 can support PCIE standard cards x16 / x8 / x4 / x2 / x1. By inserting different adapter boards, it can support 1 PCIE x16 or 2 x8 Slots or 1 x8 + 2 x4 PCIE Slots. Slot0 can support PCIE standard cards x8 / x4 / x2 / x1, and by inserting different adapter boards, it can support 2 x4 PCIE Slots.

[0046] In this embodiment, the motherboard reserves a central processing unit installation position when leaving the factory. At the specific installation position, there may be a processor socket, or there may be a processor soldering point at the installation position for OEMs, server manufacturers, or users to select and match by themselves.

[0047] Continue to refer to Figure 1As shown, in some embodiments, the OCP connector has a first interface, a second interface, and a third interface. An OCP connector generally having these three interfaces is commonly referred to as Connector A+B+C. Among them, the first interface corresponds to the A interface, the second interface corresponds to the B interface, and the third interface corresponds to the C interface. The processor socket has a sixth input / output interface corresponding to the sixth signal path group of the processor. The sixth signal path group includes 16 paths. One 8-path P1[15:8] transmitted by the sixth input / output interface is connected to the first interface. The first interface is configured to be a PCIE protocol. The other 8-path P1[7:0] transmitted is connected to a first signal switch (not shown in the figure). The output ends of the first signal switch are respectively connected to the second interface and an M.2 connector. The second interface is configured to be a SATA protocol or to be configured with the first interface into a 16-path PCIE protocol together.

[0048] The processor socket has a seventh input / output interface corresponding to the seventh signal path group of the processor. The seventh signal path group includes at least 4 paths. Among the 4 paths P0[7:4] transmitted by the seventh input / output interface, 4 paths are connected to the third interface. The third interface is configured to be a KR protocol.

[0049] Continue to refer to Figure 2 As shown, in another embodiment, the SATA connector includes: a MiniSAS HD connector. The MiniSAS HD connector is provided with 4 groups or 6 groups, and each group is provided with 4 SATA interfaces, providing a total of 16 groups or 24 groups of SATA interfaces. Among them, at least two groups of MiniSAS HD connectors are connected to the sixth input / output interface through the first signal switch. That is, the first signal switch switches the connector connected to P1[7:0] in the sixth signal path group of the CPU as needed, so that the SATA signal is selectively connected to two groups of MiniSAS HD 6-7 or the second interface of the OCP connector.

[0050] The Mini-SAS HD (High density) connector is a new generation of SAS interface, meeting the channel bandwidth requirements of 6Gb / s to 12Gb / s and 14Gb / s, and conforming to or exceeding the SAS 2.1 specification and the SAS 3.0 recommended implementation specification. The Mini-SAS HD product has a higher port density than the existing Mini-SAS 2.0 product.

[0051] When selecting and connecting between MiniSAS HD 6-7 and the OCP B connector, when P1[7:0] is connected to a SATA device, that is, 24 groups of SATA interfaces are supported. When P1[7:0] is connected to the second interface of the OCP connector, 16 groups of SATA signals are supported.

[0052] Specifically, the signal switching between the MiniSAS HD connector and the OCP connector can be intelligently switched through a signal switch, such as a multiplexer (MUX); or it can be manually selected by using P1[7:0] to share components (Co-layout) on the motherboard, which can save costs and the wiring space of the PCB board.

[0053] A 7-pin SATA interface; there are 2 groups of the 7-pin SATA interfaces, which are respectively connected to the seventh input / output interface. The seventh group of signal paths includes at least 6 paths. Among them, in addition to 4 paths P0[7:4] being connected to the third interface of the aforementioned OCP connector, the other 2 paths P0[3] and P0[2] are respectively connected to the 2 groups of 7-pin SATA interfaces in a one-to-one correspondence.

[0054] And an optical disc connector for the SATA interface, and the optical disc connector for the SATA interface supports connecting an optical disc drive (ODD) or a solid-state drive (DOM). Among them, the solid-state drive is a DOM with a SATA interface.

[0055] See Figure 4 As shown, in some embodiments, the processor socket has a seventh input / output interface corresponding to the seventh group of signal paths of the processor. The seventh group of signal paths includes at least 5 paths. 5 of the signals transmitted by the seventh input / output interface are connected to the M.2 connector through a second signal switch. Among them, 4 paths P0[11:8] are configured as PCIE signals and can support a PCIE M.2 disk; 1 path is configured as a SATA signal, and the second signal switch is used to switch between P0[8] of the 4 PCIE signals and 1 path of P0[1] SATA signal. Specifically: when the SEL pin is at a high level, the A pin and the C pin of the second signal switch are connected, and the signal is switched to LaneP0[8]; when the SEL pin is at a low level, the A pin and the B pin of the second signal switch are connected, and the signal is switched to Lane P0[1].

[0056] Continue to see Figure 4As shown, specifically, the second signal switch is an MUX chip. The 1-way P0[1] SATA signal is connected to the Lane0 port of the M.2 connector. A pull-up resistor is set on the SEL PIN (level signal pin) of the second signal switch. When a PCIE M.2 is inserted, since the 69th pin on the M.2 is NC (indicating that the terminal is suspended, which means in a digital logic circuit: the pin is not connected to any signal, neither to the high level nor to the low level), under the action of the pull-up resistor, SEL is at a high level, and the PCIE signal is connected to the M.2 connector through the MUX. When a SATA M.2 is inserted, since the 69th pin on the M.2 hard disk is grounded, SEL will be pulled low by the 69th pin on the M.2 hard disk, and the SATA signal is connected to the M.2 connector through the MUX, thus realizing the automatic identification and connection of PCIE and SATA M.2.

[0057] In addition to the occasions that require high-speed communication, the motherboard also needs to adapt to the occasions of low-speed communication. For example, in the debugging scenario, the motherboard needs to have some low-speed communication interfaces to facilitate debugging and remote monitoring and management. Therefore, referring to Figure 4 As shown, in some embodiments, a baseboard management controller and a second-rate interface component are further provided on the printed circuit board. The signal transmission rate of the second-rate interface component is less than the transmission rate of the first-rate interface component. One end of the baseboard management controller is electrically connected to the processor mount through a printed circuit, and the other end is electrically connected to the second-rate interface component, for enabling the motherboard to support remote task management.

[0058] Among them, remote task management includes: BIOS debugging, programming, updating, etc., as well as tasks such as power-on and power-off of the motherboard and CPU heat dissipation strategy adjustment.

[0059] The second-rate interface component includes a UART (Universal Asynchronous Receiver / Transmitter) interface, a JTAG (Joint Test Action Group) interface, an SPI (Serial Peripheral Interface) interface, an LPC (Low pin count) interface, an I2C ((Inter-Integrated Circuit) interface, and an APML (Advanced Platform Management Link) interface.

[0060] Among them, referring to Figure 5As shown, a circuit topology of the UART interface function is presented. After inserting the CPU into the processor socket, the CPU is connected to the Baseboard Management Controller (BMC) through the UART interface. On the motherboard, there are a first pin connector (Header) 1 and a second pin connector Header 2. The node between the CPU and the BMC is connected to the first pin connector Header 1 through a cable, and the second pin connector Header 2 is connected to the BMC through the RS232 interface. This interface function circuit can implement the local UART debugging method.

[0061] In some other embodiments, the BMC is provided with a network port. Through this network port, the BMC can implement the SOL (Serial over LAN) debugging function, that is, use the network port for remote connection and login to view the debugging information. Specifically, after the serial port information of the CPU is sent to the BMC, the SOL function is implemented through the BMC firmware. When logging in to the BMC web page and opening the SOL interface, the serial port information of the CPU can be seen, thus realizing the remote debugging function.

[0062] See Figures 6 to 8 As shown, a circuit topology of the JTAG interface function is presented, which can implement local JTAG debugging or remote JTAG debugging through the BMC. The JTAG interface generally has three types: 10-pin, 14-pin, and 20-pin.

[0063] In addition, the BMC can also burn the Complex Programmable Logic Device (CPLD) program. For ease of description, the CPLD program is collectively referred to below. Among them, HDT (Hygon Debug Tool) is the local JTAG debugger. See Figure 6As shown, the implementation principle is as follows: The TCK (Test Clock Input) / TMS (Test Mode Selection Input) signals of the BMC pass through a switching chip Switch with a selection switch and can be divided into two paths. One path is connected to the CPLD and the third pin connector Header3. Here, Header3 is the JTAG programming header of the CPLD. The JTAG programming header3 has VCC (power supply) / TDO (Test Data Output) / TDI (Test Data Input) / TMS (Test Mode Selection Input) / GND (power ground) / TCK signal). The other path is connected to the CPU after passing through a transmission gate with a control terminal OE (Output Enable, generally an output enable signal). The TCK / TMS of the HDT is connected to the CPU after passing through a transmission gate with a control terminal. Both the HDT and the BMC can be used as debuggers to debug the CPU. Therefore, the enable control terminals HDT_OE and BMC_OE of these two debuggers are reverse to ensure that only one is enabled at the same time, that is, either the HDT or the TCK / TMS of the BMC is connected to the CPU, and the OE is controlled by the BMC. See Figure 7 As shown, the TRST (Test Reset Input) / DBREQ signals of the HDT and the BMC are respectively interconnected with the CPU after passing through transmission gates with control terminals OE. An inverter is added between the control terminal signals HDT_OE and BMC_OE of the two transmission gates to ensure that the two transmission gates are not opened simultaneously, and the OE is controlled by the BMC. Among them, Figure 8 illustrates the switching control principle of the TDI and TDO of the HDT and the BMC. The principle is the same as the above TCK / TMS signal switching principle and can be referred to each other, so it will not be elaborated here.

[0064] See Figure 9As shown, a circuit topology of the SPI interface function is presented. The SPI0 (DI / DO / HOLD_L / WP_L / CS0) interfaces of the CPU and BMC are switched through a MUX chip. The MUX path is default set to connect to the CPU. After the mainboard powers on and starts up, the CPU reads firmware information from the BIOS ROM to initialize the mainboard. When the mainboard CPU does not need to start the BIOS, the BMC can control the MUX to switch the SPI path to connect to the BMC through GPIO (general-purpose input / output ports), so as to remotely burn the BIOS ROM. After the BMC finishes burning, it controls the GPIO to switch the connection of the BIOS ROM to the CPU. After the mainboard restarts, the CPU starts the mainboard from the BIOS ROM, thus realizing the function of the BMC remotely burning the BIOS. At the same time, the SPI1 (DI / DO / HOLD_L / WP_L / CS1) interface of the CPU is connected to the TCM / TPM module, enabling the mainboard to support the security module function.

[0065] See Figure 10 As shown, a circuit topology of the BMC function is presented. The mainboard uses the ASPEED AST2500 BMC chip as the management system to control the power on, power off, and restart of the mainboard system, perform firmware burning, and monitor system errors, alarms, temperature, voltage, etc. The BMC can receive external control commands through the network. The AST2500 is connected to the CPU, and other control circuits are also connected to the periphery of the AST2500. The other control circuits include fans, memory cards, buttons, UART interfaces, network card chips, etc., as Figure 10 shown.

[0066] Among them, as Figure 11 shown, the PWR BTN and RST BTN signals of the CPU are controlled through the BMC network to power on, power off, and reset the mainboard.

[0067] It can be understood that the CPU generates heat during operation. To monitor and control the CPU temperature, a temperature control system interaction interface is also provided on the mainboard. As Figure 12As shown in the figure, the specific working principle is as follows: The CPU transmits temperature-related signals of itself, such as the Thermaltrip of the CPU (Thermaltrip is a pin of the CPU. When the chip temperature reaches the set value, the chip will pull down this pin. After the external circuit detects this pin being pulled down, it cuts off the power supply on the motherboard to achieve protection), the Tdie (core temperature), and other temperature signals, as well as the Tmon (Tdie is a temperature-sensing diode inside the chip used to sense the internal temperature of the chip) temperature transmitted through the AMPL interface, to the fourth pin connector Header4, the fifth pin connector Header5, and the BMC respectively. The temperature control module or BMC of the test system senses them, thereby controlling the heat dissipation module of the CPU to adjust according to different strategies.

[0068] According to the above description, it can be known that for the motherboard provided by the embodiment of the present invention, a CPLD is used to control the power-on and power-off of the voltage regulator (VR). Through logical codes, the power-on and power-off timings of the voltage regulator VR (Voltage Regulator) and the signals input to the CPU can be flexibly adjusted, and it supports the remote BMC management system to remotely control, debug, and monitor the motherboard, which can improve the manageability of the overall system of the motherboard.

[0069] The present invention is applicable to the development, OEM, and chip testing scenarios of electronic devices or equipment such as motherboards, computers, industrial control computers, and servers.

[0070] In addition, the embodiment of the present invention further provides a server, including a chassis. Inside the chassis, there is a motherboard described in any of the foregoing embodiments. A processor is installed in the central processor socket on the motherboard, and the processor is electrically connected to the input end of the signal switcher.

[0071] Among them, the processor is a central processing unit. Specifically, the processor is a Haiguang processor, with models 7100 and 7200, and supports multi-channel memory.

[0072] For the server in this embodiment, since its motherboard facilitates the transmission of high-speed signals, its performance can be optimized to a certain extent.

[0073] It should be noted that in this text, terms indicating the orientation or positional relationship such as "upper" and "lower" are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present invention. Unless otherwise clearly specified and defined, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium. Relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element. Those of ordinary skill in the art can understand through specific circumstances.

[0074] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A motherboard, characterized in that, It includes a printed circuit board, on which a processor socket, a memory slot and a first-rate interface component are provided. The processor socket is used to install a processor. The first-rate interface component includes multiple PCIE slots, an OCP connector, a SATA connector and an M.2 connector; The processor socket is electrically connected to multiple memory slots, PCIE slots, an OCP connector, a SATA connector and an M.2 connector respectively. Each memory slot supports installing any one of UDIMM, RDIMM and LRDIMM; among them, at least a part of the interfaces are function-configurable interfaces; The processor socket has a seventh input / output interface corresponding to the seventh group of signal paths of the processor. The seventh group of signal paths includes at least 5 paths. Five of the paths transmitted by the seventh input / output interface are connected to the M.2 connector through a second signal switch. Four of them are configured as PCIE signals and one is configured as a SATA signal. The second signal switch is used to switch between one of the 4 PCIE signals and one SATA signal; When the SEL pin of the second signal switch is at a high level, the A pin and the C pin of the second signal switch are connected; when the SEL pin is at a low level, the A pin and the B pin of the second signal switch are connected.

2. The motherboard according to claim 1, wherein The processor socket is used to install a processor and supports 8-channel memory slots. Each channel's memory slot supports installing two memory modules.

3. The motherboard according to claim 1 or 2, characterized in that, The PCIE slots include a first PCIE slot, a second PCIE slot, a third PCIE slot, a fourth PCIE slot and a fifth PCIE slot. The first PCIE slot is connected to the first input / output interface corresponding to the first group of signal paths of the processor on the processor socket. The second PCIE slot is connected to the second input / output interface corresponding to the second group of signal paths of the processor on the processor socket. The third PCIE slot is connected to the third input / output interface corresponding to the third group of signal paths of the processor on the processor socket. The fourth PCIE slot is connected to the fourth input / output interface corresponding to the fourth group of signal paths of the processor on the processor socket. The fifth PCIE slot is connected to the fifth input / output interface corresponding to the fifth group of signal paths of the processor on the processor socket; Among them, the first PCIE slot supports at least PCIE standard cards x8 / x4 / x2 / x1, and the second PCIE slot, the third PCIE slot, the fourth PCIE slot and the fifth PCIE slot support PCIE standard cards x16 / x8 / x4 / x2 / x1 respectively.

4. The motherboard according to claim 1, characterized in that The OCP connector has a first interface, a second interface, and a third interface. The processor socket has a sixth input / output interface corresponding to the sixth group of signal paths of the processor. The sixth group of signal paths includes 16 paths. One of the 8 paths transmitted by the sixth input / output interface is connected to the first interface, and the first interface is configured to the PCIE protocol. The other 8 paths transmitted are connected to the first signal switch. The output ends of the first signal switch are respectively connected to the second interface and the M.2 connector. The second interface is configured to the SATA protocol or configured to the 16-path PCIE protocol together with the first interface. The processor socket has a seventh input / output interface corresponding to the seventh group of signal paths of the processor. The seventh group of signal paths includes at least 4 paths. 4 of the paths transmitted by the seventh input / output interface are connected to the third interface, and the third interface is configured to the KR protocol.

5. The motherboard according to claim 4, wherein The seventh group of signal paths includes at least 6 paths. The SATA connector includes: MiniSAS HD connectors. There are 4 or 6 groups of MiniSAS HD connectors, and each group has 4 SATA interfaces. Among them, at least two groups of MiniSAS HD connectors are connected to the sixth input / output interface through the first signal switch. 7-pin SATA interfaces. There are 2 groups of 7-pin SATA interfaces, which are respectively connected to the seventh input / output interface and used to connect to 2 paths in the seventh group of signal paths. And a CD-ROM connector with SATA interfaces. The CD-ROM connector with SATA interfaces supports connecting to an optical disc drive or a solid-state drive.

6. The motherboard according to claim 1, wherein The printed circuit board is also provided with a baseboard management controller and a second rate interface component. The signal transmission rate of the second rate interface component is less than the transmission rate of the first rate interface component. One end of the baseboard management controller is electrically connected to the processor mount through a printed circuit, and the other end is electrically connected to the second rate interface component, which is used to enable the motherboard to support remote task management.

7. The motherboard according to claim 6, characterized in that, The second rate interface component includes a UART interface, a JTAG interface, an SPI interface, an LPC interface, an I2C interface, and an APML interface.

8. A server, characterized in that, It includes a chassis. The main board according to any one of claims 1 to 7 is provided in the chassis, and a processor is installed in the processor socket on the main board.

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