RF chip and antenna module

Abstract

A radio frequency chip and an antenna module are disclosed. The antenna module includes a multilayer board, a radio frequency (RF) chip, and a first active device array. The multilayer board includes an antenna for transmitting and receiving electromagnetic waves. The RF chip is on the bottom surface of the multilayer board and includes a plurality of transmission circuits, each of the plurality of transmission circuits forming a part of each of a plurality of transmission paths for generating RF signals to be provided to the antenna. The first active device array is on the bottom surface of the multilayer board and includes a first group of active devices respectively including a part of a plurality of power amplifiers in the plurality of transmission paths of the plurality of transmission circuits, and a plurality of first input pins and a plurality of first output pins are respectively connected to electrodes of the first group of active devices.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0089796, filed with the Korean Intellectual Property Office on Jul. 24, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to wireless communication, and more particularly, to a transceiver for wireless communication and an antenna module including the transceiver. Background Art

[0003] To increase data throughput in wireless communication, an extended frequency band may be used, and thus a wireless communication device may need the ability to process high-frequency signals. For example, 5G millimeter wave (mmWave) frequency allocations assigned by the 3rd Generation Partnership Project (3GPP) may include high-frequency bands of 20 GHz or higher. To better process such high-frequency signals, a high-performance transceiver may be included in a wireless communication device.

[0004] In addition to high performance, a transceiver may also be required to have high availability (such as low cost, low power consumption, low operating temperature, high stability, etc.). In particular, due to limited space, temperature, and power, a transceiver included in a portable wireless communication device (such as a mobile phone) may be required to have higher availability. Summary of the Invention

[0005] On the one hand, a transceiver and an antenna module including the transceiver that can provide high performance and high availability are provided.

[0006] According to an aspect of an example embodiment, there is provided a radio frequency (RF) chip configured to process RF signals, the RF chip including: input / output pins for connecting to an antenna; a first output pin and a first input pin for connecting to electrodes of a first active device included in a first active device array, respectively; and a transmission circuit constituting a part of a transmission path for generating an RF signal to be provided to the antenna, wherein the transmission path sequentially passes through the first output pin, the first active device, and the first input pin.

[0007] According to another aspect of the exemplary embodiment, there is provided an antenna module including: a multilayer board including an antenna configured to transmit and receive electromagnetic waves through a top surface of the multilayer board; a radio frequency (RF) chip connected to the antenna and configured to process RF signals on a bottom surface of the multilayer board; and a first active device array including a plurality of active devices, a first input pin, and a first output pin, the first input pin and the first output pin being connected to electrodes of a first active device among the plurality of active devices, wherein the multilayer board includes: a first pattern for providing a first signal from the RF chip to the first input pin; and a second pattern for providing a second signal from the first output pin to the RF chip.

[0008] According to another aspect of the exemplary embodiment, there is provided an antenna module including a first active device array, the antenna module including: a multilayer board including at least one antenna configured to transmit and receive electromagnetic waves; a radio frequency (RF) chip on a bottom surface of the multilayer board, the RF chip including a plurality of transmission circuits, each of the plurality of transmission circuits forming a part of each of a plurality of transmission paths for generating a plurality of RF signals to be provided to the at least one antenna; and a first active device array on the bottom surface of the multilayer board, the first active device array including a first group of active devices including at least a part of a plurality of power amplifiers respectively included in the plurality of transmission paths of the plurality of transmission circuits, and a plurality of first input pins and a plurality of first output pins being connected to electrodes of the first group of active devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 shows a wireless communication system according to an exemplary embodiment;

[0011] Figure 2 shows an antenna module according to an exemplary embodiment;

[0012] Figure 3A and Figure 3B shows an example of an antenna module according to an exemplary embodiment;

[0013] Figure 4A and Figure 4B shows an example of an antenna module according to an exemplary embodiment;

[0014] Figure 5A and Figure 5B shows an example of an antenna module according to an exemplary embodiment;

[0015] Figure 6 shows a radio frequency (RF) chip according to an exemplary embodiment;

[0016] Figure 7 Shows an antenna module according to an exemplary embodiment;

[0017] Figure 8A and Figure 8B shows an example of an antenna module according to an exemplary embodiment;

[0018] Figure 9 shows an antenna module according to an exemplary embodiment, Figure 10 shows an enlarged view of region A according to an exemplary embodiment of Figure 9 ;

[0019] Figure 11 and Figure 12 shows an example of an RF chip according to an exemplary embodiment;

[0020] Figure 13A and Figure 13B shows an example of the layout of an active device array according to an exemplary embodiment;

[0021] Figure 14 shows a multilayer board according to an exemplary embodiment;

[0022] Figure 15 shows an antenna module according to an exemplary embodiment;

[0023] Figure 16 shows an antenna module according to an exemplary embodiment;

[0024] Figures 17A to 17C shows an example of an antenna module according to an exemplary embodiment; and

[0025] Figure 18 shows an antenna module according to an exemplary embodiment. Detailed Description

[0026] The drawings may not be to scale and, for purposes of illustration, components shown may be enlarged or reduced. In this specification, the phrase "at least one of A and B" includes within its scope "only A", "only B", and "both A and B".

[0027] Figure 1 Shows a wireless communication system 5 according to an exemplary embodiment. As a non-limiting example, the wireless communication system 5 may include a wireless communication system using a cellular network, such as, a fifth generation wireless (5G) system, a long term evolution (LTE) system, an LTE advanced system, a code division multiple access (CDMA) system, or a global system for mobile communications (GSM) system, a wireless personal area network (WPAN) system, or any other wireless communication system. Hereinafter, the wireless communication system 5 will be mainly described with reference to a wireless communication system using a cellular network. However, it will be understood that the exemplary embodiments are not limited thereto.

[0028] Base station BS 1 generally may represent a fixed station that communicates with a user equipment and / or another base station, and may switch data and control information by communicating with the user equipment and / or another base station. For example, base station 1 may be referred to as Node B, evolved Node B (eNB), next-generation Node B (gNB), sector, site, base transceiver system (BTS), access point (AP), relay node, remote radio head (RRH), radio unit (RU), small cell, etc. In the present specification, BS or cell may be fully understood as a partial area or function covered by a base station controller (BSC) in CDMA, Node B in WCDMA, eNB in LTE, gNB in 5G, sector (site), etc., and may cover various coverage areas (such as macro cell, macro cell, micro cell, pico cell, femto cell, relay node, RRH, RU, and small cell communication range, etc.).

[0029] User equipment UE 10 may be fixed or mobile, and may represent any device that can send and receive data and / or control information by communicating with a base station (e.g., base station 1). For example, user equipment 10 may be referred to as a terminal, terminal device, mobile station (MS), mobile terminal (MT), user terminal (UT), user station (SS), wireless device, or handheld device, etc. Hereinafter, example embodiments will be described with reference to user equipment 10 as a wireless communication device. However, it will be understood that the example embodiments are not limited thereto.

[0030] The wireless communication network between user equipment 10 and base station 1 may support multiple users to communicate with each other by sharing available network resources. For example, in a wireless communication network, information may be transmitted by various multiple access methods (such as code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), orthogonal frequency division multiple access (OFDMA), single carrier frequency division multiple access (SC-FDMA), orthogonal frequency division multiple access - frequency division multiple access (OFDM-FDMA), orthogonal frequency division multiple access - time division multiple access (OFDM-TDMA), and orthogonal frequency division multiple access - code division multiple access (OFDM-CDMA)). As Figure 1 shown, user equipment 10 may communicate with base station 1 through an uplink (UL) and a downlink (DL). In some embodiments, user equipment may communicate with each other through a sidelink (such as device-to-device (D2D)). As Figure 1As shown in the figure, the user equipment 10 may include a first antenna module 11, a second antenna module 12, a third antenna module 13, a fourth antenna module 14, a backend module 15, and a data processor 16. In some embodiments, the first antenna module 11 to the fourth antenna module 14 may be independently packaged and spaced apart from each other. In some embodiments, the backend module 15 and the data processor 16 may be independently packaged or may be packaged together.

[0031] Each of the first antenna module 11 to the fourth antenna module 14 may include at least one antenna, and may process signals received through the antenna and signals to be transmitted through the antenna. In some embodiments, the first antenna module 11 to the fourth antenna module 14 may generate or process first intermediate frequency (IF) signals to fourth intermediate frequency (IF) signals (S_IF1 to S_IF4). For example, the first antenna module 11 may generate the first IF signal S_IF1 from the RF signal received through the antenna, and process the first IF signal S_IF1 provided from the backend module 15 to output the generated RF signal through the antenna. Similarly, the second antenna module 12 may generate the second IF signal S_IF2 from the RF signal received through the antenna, and process the second IF signal S_IF2 provided from the backend module 15 to output the generated RF signal through the antenna, and so on. In some embodiments, each of the first antenna module 11 to the fourth antenna module 14 may be referred to as a front-end module or an RF module. The following will refer to Figure 2 show the structures of the first antenna module 11 to the fourth antenna module 14.

[0032] In a high-frequency band (such as millimeter wave (mmWave)), a signal with a short wavelength may have high straightness, so the communication quality may be affected by obstacles and / or the direction of the antenna. The user equipment 10 may include multiple antenna modules (for example, the first antenna module 11 to the fourth antenna module 14), such that: even though signal transmission and reception through some antenna modules may be blocked by obstacles (such as the user's body), communication with the base station 1 can still be carried out, and / or communication with the base station 1 can be carried out regardless of the direction of the user equipment 10. As Figure 1 shown in the figure, the first antenna module 11 to the fourth antenna module 14 included in the user equipment 10 may be separately arranged from each other, and in some embodiments, the first antenna module 11 to the fourth antenna module 14 may be spaced apart from each other at the edge of the user equipment 10. Figure 1 show four antenna modules. However, in some embodiments, the number of antenna modules in the user equipment 10 may be different, and may be greater than or less than Figure 1 the number of antenna modules shown in the figure.

[0033] As the required performance of the antenna module increases, the complexity of the antenna module may increase, and the requirements for implementing the antenna module (such as space, power, and cost) may increase. In addition, as described above, since the user equipment 10 may include multiple antenna modules, the increase in the requirements for implementing the antenna module may be a high burden for the user equipment 10. As described below with reference to the drawings, according to various example embodiments, each of the first antenna module 11 to the fourth antenna module 14 may include an active device array. Therefore, the transceiver may provide improved performance (such as high output current and high linearity) by using the active devices included in the active device array, and may also provide improved efficiency (such as small space and low cost) by using passive devices with high integration. In addition, each of the first antenna module 11 to the fourth antenna module 14 may provide high stability by separating the active devices that serve as important heat sources.

[0034] The backend module 15 may process or generate the baseband signal S_BB. For example, the backend module 15 may generate at least one of the first IF signal S_IF1 to the fourth IF signal S_IF4 by processing the baseband signal S_BB provided from the data processor 16, and may generate the baseband signal S_BB by processing at least one of the first IF signal S_IF1 to the fourth IF signal S_IF4. In some embodiments, different from that shown in Figure 1 the first antenna module 11 to the fourth antenna module 14 may respectively generate a baseband signal and provide the baseband signal to the data processor 16. In this case, the backend module 15 may be omitted.

[0035] The data processor 16 may extract the information transmitted by the base station 1 from the baseband signal S_BB received from the backend module 15, and may also generate a baseband signal S_BB including the information to be transmitted to the base station 1. The data processor 16 may include a hardware block designed by logic synthesis, or may include a processing block that includes a software module containing a series of commands and one or more processors (such as a microprocessor or a central processing unit (CPU)) that execute the software module. The hardware block and / or the processing block of the data processor 16 may be the same as or different from the hardware block and / or the processing block of the backend module 15. The data processor 16 may be referred to as a communication processor, a baseband processor, a modem, etc.

[0036] Figure 2 An antenna module 20 according to an example embodiment is shown. As Figure 2 shown, the antenna module 20 may include a first antenna 22_1 to an nth antenna 22_n and a transceiver 24 (n is an integer greater than 1). As described above with reference to Figure 1As described above, the antenna module 20 can output the first RF signal S_RF1 to the nth RF signal S_RFn to the first antenna 22_1 to the nth antenna 22_n, or can receive the first RF signal S_RF1 to the nth RF signal S_RFn from the first antenna 22_1 to the nth antenna 22_n, and can also generate or receive an IF signal S_IF. Figure 2 The antenna module 20 can be Figure 1 an example of each of the first antenna module 11 to the fourth antenna module 14, which will be described below with reference to Figure 1 for description. Figure 2 .

[0037] As a non-limiting example, the first antenna 22_1 to the nth antenna 22_n can be used in space diversity, polarization diversity, space multiplexer, beamforming, etc. Each of the first antenna 22_1 to the nth antenna 22_n can include any type of antenna (e.g., patch antenna, dipole antenna, etc.). As Figure 2 shown in, the transceiver 24 can include circuits corresponding to the first antenna 22_1 to the nth antenna 22_n respectively, and includes a combiner / splitter 24_2, a mixer 24_6, and a local oscillator generator 24_8.

[0038] In the transceiver 24, n transmission paths and n reception paths corresponding to the first antenna 22_1 to the nth antenna 22_n can be formed. For example, as Figure 2 shown in, the first transmission path TX1 and the first reception path RX1 corresponding to the first antenna 22_1 can be formed, and the nth transmission path TXn and the nth reception path RXn can be formed corresponding to the nth antenna 22_n. In addition, in some example embodiments, the transceiver 24 can include a first switch SW1 and a second switch SW2 corresponding to each of the first antenna 22_1 to the nth antenna 22_n, such that the first transmission path TX1 is selected in the transmission mode, and the first reception path RX1 is selected in the reception mode. Figure 2 The first switch SW1 and the second switch SW2 can indicate the state in which the first transmission path TX1 is selected in the transmission mode. In some embodiments, as described below with reference to Figure 8A etc., two or more transmission paths and two or more reception paths corresponding to one antenna can be formed in the transceiver 24, such that two or more RF signals with different polarizations are output from one antenna.

[0039] The combiner / distributor 24_2 can, in transmission mode, supply the signal upconverted from the IF signal S_IF by the local oscillation signal LO provided by the local oscillator generator 24_8 to the first transmission path TX1 to the nth transmission path TXn. On the other hand, in reception mode, the combiner / distributor 24_2 can supply at least some or a combination of the signals received from the first reception path RX1 to the nth reception path RXn to the mixer 24_6. The mixer 24_6 can perform upconversion or downconversion according to the local oscillation signal LO. The local oscillator generator 24_8 can generate the local oscillation signal LO based on the carrier frequency, etc., and in some embodiments, the local oscillator generator 24_8 can include a phase-locked loop (PLL).

[0040] The transmission path can include a transmission circuit. For example, as Figure 2 shown, the transmission circuit constituting the first transmission path TX1 can include a first phase shifter PS1, a first matching network (M / N) M1, a first amplifier circuit A1, and a second matching network (M / N) M2. In addition, the transmission circuit can include a power amplifier. For example, the power amplifier can include a first matching network (M / N) M1, a first amplifier circuit A1, and a second matching network (M / N) M2. Similarly, the reception path can include a reception circuit. For example, as shown in FIG. 2, the reception circuit constituting the first reception path RX1 can include a third matching network (M / N) M3, a second amplifier circuit A2, a fourth matching network (M / N) M4, and a second phase shifter PS2. In addition, the reception circuit can include a low-noise amplifier. For example, the low-noise amplifier can include a third matching network (M / N) M3, a second amplifier circuit A2, and a fourth matching network (M / N) M4. In some embodiments, Figure 2 some of the components constituting the transmission path and / or the reception path shown in Figure 2 can be omitted, or the components can be arranged differently from the components shown in

[0041] For example, the transmission circuit and the reception circuit can include active devices (such as transistors), and can also include passive devices (such as capacitors, inductors, etc.). For example, in the transmission circuit constituting the first transmission path TX1, the first amplifier circuit A1 can include at least one transistor as an active device, while the first matching network (M / N) M1 and the second matching network (M / N) M2 can each include at least one capacitor and / or at least one inductor. As referred to above in Figure 1 it is described, it may be necessary for the transmission circuit and the reception circuit to meet high performance and high availability.

[0042] Components included in transceiver 24 can be manufactured through semiconductor processes. In one example, when transceiver 24 is manufactured as a single chip through a complementary metal oxide semiconductor (CMOS) process, transceiver 24 can provide low cost and high integration, while transceiver 24 can provide relatively low output power capability, low linearity, and weak breakdown characteristics. In addition, a fully depleted silicon-on-insulator (FD-SOI) process can provide lower leakage power and heat generation compared to a bulk silicon process. In another example, when transceiver 24 is manufactured as a single chip through a BiCMOS process (such as a SiGe BiCMOS (bipolar-CMOS) process), transceiver 24 can provide higher output power capability compared to a transceiver manufactured through a CMOS process, while transceiver 24 can have a higher cost compared to a transceiver manufactured through a CMOS process. In another example, when transceiver 24 is manufactured as a single chip through a III-V compound semiconductor process (such as a GaAs compound semiconductor process), transceiver 24 can provide higher output power capability and linearity compared to a transceiver manufactured through the above-mentioned CMOS and / or BiCMOS processes, while due to low density, transceiver 24 can have a higher cost and occupy a larger area compared to a transceiver manufactured through the above-mentioned CMOS and / or BiCMOS processes.

[0043] In some example embodiments, transceiver 24 can include two or more chips manufactured through different semiconductor processes. For example, combiner / splitter 24_2, mixer 24_6, and local oscillator generator 24_8 can be included in a chip manufactured through a CMOS process that can provide high integration, while the remaining components of transceiver 24 including the transmit circuit and the receive circuit can be included in a chip manufactured through a semiconductor process (such as a BiCMOS or III-V compound semiconductor process) that can provide higher performance. However, even in this case, transceiver 24 may still have the above-mentioned advantages and disadvantages. In addition, when only the transmit circuit that requires higher performance than the receive circuit is included in a chip manufactured through a semiconductor process different from the CMOS process (such as a III-V compound semiconductor process), due to the limited number of layers and dielectric materials, it may not be easy to integrate passive devices therein, and thus the chip including the transmit circuit can be enlarged.

[0044] According to example embodiments, as described below with reference to Figure 3A and Figure 3BAs described above, the transceiver 24 may include: a chip including at least some of the active devices included in the transmission circuit and / or the reception circuit (which may be referred to herein as an active device array) and a chip including other components including passive devices (which may be referred to herein as an RF chip). The active device array may be manufactured by a semiconductor process (such as a III-V compound semiconductor process) that can provide higher performance than a comparable CMOS process (e.g., an FD-SOI process), while the RF chip may be manufactured by a CMOS process that can provide high integration and low cost. Thus, the transceiver 24 can provide high availability while providing high performance. In the following drawings, for ease of description, it is assumed that: the first amplifier circuit A1 constituting the first transmission path TX1 and the second amplifier circuit A2 constituting the first reception path RX1 may include only active devices (such as transistors).

[0045] Figure 3A and Figure 3B illustrates an example of an antenna module according to an exemplary embodiment. Specifically, Figure 3A and Figure 3B is a block diagram showing one antenna in the antenna module and a transmission circuit and a reception circuit corresponding to the one antenna. As referred to above with reference to Figure 2 described above, Figure 3A the RF chip 34a in Figure 3B and the RF chip 34b in Figure 3A may be manufactured by a CMOS process (e.g., an FD-SOI process), respectively, while the active device array 36a in Figure 3B and the active device arrays 36b and 38b in Figure 3A and Figure 3B may be manufactured by a semiconductor process (such as a GaAs compound semiconductor process) that can provide higher performance than a comparable CMOS process. Hereinafter, for brevity, the mutually repetitive descriptions of Figure 2 and the descriptions repetitive of the description of

[0046] Referring to Figure 3A, the antenna module 30a may include an antenna 32a, an RF chip 34a, and an active device array 36a. The RF chip 34a may include a first phase shifter PS1, a first matching network (M / N) M1, and a second matching network (M / N) M2 as a transmission circuit constituting a first transmission path TX1, and may include a third matching network (M / N) M3, a second amplifier circuit A2, a fourth matching network (M / N) M4, and a second phase shifter PS2 as a reception circuit constituting a first reception path RX1. In addition, the RF chip 34a may include a first switch SW1 and a second switch SW2 for selecting the first transmission path TX1 or the first reception path RX1 according to an operation mode. The RF chip 34a may include pins exposed to the outside of the RF chip 34a to be connected to other components. For example, as Figure 3A shown, the RF chip 34a may include a first input pin IN1 and a first output pin OUT1 for connecting to the active device array 36a, and may include an input / output pin (IO) for connecting to the antenna 32a. The RF chip 34a may be referred to as a radio frequency integrated circuit (RFIC)

[0047] The active device array 36a may include a plurality of active devices, and may include a plurality of pins connected to electrodes of the plurality of active devices. For example, as Figure 3A shown, the active device array 36a may include a first amplifier circuit A1 configured by active devices, and the first amplifier circuit A1 may be connected to both a second input pin IN2 and a second output pin OUT2. In some embodiments, the active devices included in the active device array 36a may include high electron mobility transistors (HEMTs) that may use a junction between materials having different bandgaps (e.g., GaAs) as a channel, whereby the active devices may drive a large current with a small control signal and operate well at high frequencies. The active devices included in the active device array 36a may be referred to as power units herein.

[0048] The active device array 36a may include a first amplifier circuit A1 as at least one of the active devices included in the transmission circuit. Thus, as Figure 3A shown, the first transmission path TX1 may sequentially pass through the first output pin OUT1, the second input pin IN2, the first amplifier circuit A1, the second output pin OUT2, and the first input pin IN1. Therefore, since the active device array 36a provides high performance, the first transmission path TX1 may output a good RF signal to the antenna 32a. At the same time, since the passive devices included in the RF chip 34a have a high degree of integration, an increase in the size of the antenna module 30a may be restricted.

[0049] Referring to Figure 3B, the antenna module 30b may include an antenna 32b, an RF chip 34b, a first active device array 36b, and a second active device array 38b. The RF chip 34b may include a first input pin IN1 and a first output pin OUT1 for connecting to the first active device array 36b, and may include a third input pin IN3 and a third output pin OUT3 for connecting to the second active device array 38b. The first active device array 36b may include a first amplifier circuit A1, and may include a second input pin IN2 and a second output pin OUT2 for connecting to the RF chip 34b. The second active device array 38b may include a second amplifier circuit A2, and may include a fourth input pin IN4 and a fourth output pin OUT4 for connecting to the RF chip 34b. In some embodiments, the first active device array 36b and the second active device array 38b may be configured as a single chip.

[0050] Similar to Figure 3A the active device array 36a of, the first active device array 36b may include a first amplifier circuit A1 as at least one of the active devices included in the transmission circuit. Thus, as shown in Figure 3B , the first transmission path TX1 may sequentially pass through the first output pin OUT1, the second input pin IN2, the first amplifier circuit A1, the second output pin OUT2, and the first input pin IN1. The second active device array 38b may include a second amplifier circuit A2 as at least one of the active devices included in the reception circuit. Thus, as shown in Figure 3B , the first reception path RX1 may sequentially pass through the third output pin OUT3, the fourth input pin IN4, the second amplifier circuit A2, the fourth output pin OUT4, and the third input pin IN3. Therefore, since the first active device array 36b and the second active device array 38b provide high performance, a good RF signal S_RF may be provided to the antenna 32b, and the RF signal received from the antenna 32b may be well processed. At the same time, since the passive devices included in the RF chip 34b have high integration, an increase in the size of the antenna module 30b may be limited. In some embodiments, different from those shown in Figure 3B , the first active device array 36b may be omitted, and the RF chip 34b may include the first amplifier circuit A1. Optionally, in some embodiments, different from those shown in Figure 3B , the second active device array 38b may be omitted, and the RF chip 34b may include the second amplifier circuit A2.

[0051] Figure 4A and Figure 4B show examples of antenna modules according to example embodiments. Specifically, Figure 4A and Figure 4Bis a block diagram showing an antenna in an antenna module and a part of a transmission circuit corresponding to the one antenna. In some embodiments, a power amplifier included in the transmission circuit may be a multi-stage amplifier, and an active device array may include active devices included in one of multiple stages of the multi-stage amplifier.

[0052] Referring to Figure 4A , the antenna module 40a may include an antenna 42a, an RF chip 44a, and an active device array 46a. In some embodiments, the active device array 46a may include active devices included in the last stage of a multi-stage amplifier. For example, as Figure 4A shown, the power amplifier may be a three-stage amplifier, and the RF chip 44a may include a first amplification circuit A41a and a second amplification circuit A42a corresponding to the first stage and the second stage, respectively, while the active device array 46a may include a third amplification circuit A43a corresponding to the third stage, which is the last stage of the multi-stage amplifier. As Figure 4A shown, the third amplification circuit A43a may include transistors, and the active device array 46a may include a second input pin IN42, a second output pin OUT42, and a ground pin G4 respectively connected to electrodes of the transistors (i.e., the gate, drain, and source, respectively). In some embodiments, the transistors of the active device array 46a may be HEMTs.

[0053] The RF chip 44a may include a first matching network (M / N) M41a and a second matching network (M / N) M42a, which are passive devices provided between multiple stages of the multi-stage amplifier, and may include a first output pin OUT41 and a first input pin IN41 for connecting to the active device array 46a. In addition, the RF chip 44a may include a switch SW41a for selecting a transmission path or a reception path, and may include an input / output pin IO4 for connecting to the antenna 42a.

[0054] Referring to Figure 4B , the antenna module 40b may include an antenna 42b, an RF chip 44b, and an active device array 46b. In some embodiments, the active device array 46b may include active devices included in two or more of multiple stages of a multi-stage amplifier, and the two or more stages include the last stage. For example, as Figure 4B shown, the power amplifier may be a three-stage amplifier, and the RF chip 44b may include a first amplification circuit A41b corresponding to the first stage, while the active device array 46b may include a second amplification circuit A42b and a third amplification circuit A43b corresponding to the second stage and the third stage, respectively. As Figure 4BAs shown, the second amplifier circuit A42b and the third amplifier circuit A43b may each include a transistor, and the active device array 46b may include a second input pin IN42 and a fourth input pin IN44, a second output pin OUT42 and a fourth output pin OUT44, and a first ground pin G41 and a second ground pin G42 that are respectively connected to the electrodes of the transistors. In some embodiments, the transistors of the active device array 46b may be HEMTs.

[0055] The RF chip 44b may include a first matching network (M / N) M41b and a second matching network (M / N) M42b that are passive devices disposed between multiple stages of the multi-stage amplifier, and may include a first input pin IN41 and a third input pin IN43 for connecting to the active device array 46b, and a first output pin OUT41 and a third output pin OUT43. In addition, the RF chip 44b may include a switch SW41b for selecting a transmission path or a reception path, and may include an input / output pin IO4 for connecting to the antenna 42b.

[0056] Figure 5A and Figure 5B shows an example of an antenna module according to an exemplary embodiment. Specifically, Figure 5A and Figure 5B are block diagrams showing one antenna in the antenna module and a part of the receiving circuit corresponding to the one antenna. In some embodiments, the low-noise amplifier included in the receiving circuit may be a multi-stage amplifier, and the active device array may include active devices included in one of the multiple stages of the multi-stage amplifier.

[0057] Referring to Figure 5A , the antenna module 50a may include an antenna 52a, an RF chip 54a, and an active device array 56a. In some embodiments, the active device array 56a may include active devices included in the initial stage of the multi-stage amplifier. For example, as Figure 5A shown, the low-noise amplifier may include a two-stage amplifier, and the active device array 56a may include a first amplifier circuit A51a corresponding to the first stage that is the initial stage of the multi-stage amplifier, while the RF chip 54a may include a second amplifier circuit A52a corresponding to the second stage. As Figure 5A shown, the first amplifier circuit A51a may include a transistor, and the active device array 56a may include a second input pin IN52, a second output pin OUT52, and a ground pin G5 that are respectively connected to the electrodes of the transistor (i.e., the gate, drain, and source respectively). In some embodiments, the transistors of the active device array 56a may be HEMTs.

[0058] The RF chip 54a may include a matching network (M / N) M5a as a passive device disposed between multiple stages of a multi-stage amplifier, and may include a first output pin OUT51 and a first input pin IN51 for connection to the active device array 56a. In addition, the RF chip 54a may include a switch SW51a for selecting a transmission path or a reception path, and may include an input / output pin IO5 for connection to the antenna 52a.

[0059] Referring to Figure 5B , the antenna module 50b may include an antenna 52b, an RF chip 54b, and an active device array 56b. In some embodiments, the active device array 56b may include active devices in two or more of the multiple stages of a multi-stage amplifier, the two or more stages including an initial stage. For example, as Figure 5B shown, a low-noise amplifier may be a two-stage amplifier including a first stage and a second stage, and the active device array 56b may include a first amplification circuit A51b and a second amplification circuit A52b corresponding to the first stage and the second stage, respectively. As Figure 5B shown, the first amplification circuit A51b and the second amplification circuit A52b may each include a transistor, and the active device array 56b may include a second input pin IN52 and a fourth input pin IN54, a second output pin OUT52 and a fourth output pin OUT54, and a first ground pin G51 and a second ground pin G52 that are respectively connected to electrodes of the transistors. In some embodiments, the transistors of the active device array 56b may be HEMTs.

[0060] The RF chip 54b may include a matching network (M / N) M5b as a passive device disposed between multiple stages of a multi-stage amplifier, and may include a first input pin IN51 and a third input pin IN53, and a first output pin OUT51 and a third output pin OUT53 for connection to the active device array 56b. In addition, the RF chip 54b may include a switch SW51b for selecting a transmission path or a reception path, and may include an input / output pin IO5 for connection to the antenna 52b.

[0061] Figure 6 An RF chip according to an example embodiment is shown. Specifically, Figure 6 is a block diagram showing an RF chip 64 including a tunable matching network. As Figure 6 shown, as compared with Figure 3BSimilar to the RF chip 34b, the RF chip 64 may include: a first phase shifter PS1, a first matching network (M / N) M1, and a second matching network (M / N) M2 included in the transmission circuit, and a third matching network (M / N) M3, a fourth matching network (M / N) M4, and a second phase shifter PS2 included in the reception circuit. The RF chip 64 may include a first switch SW1 and a second switch SW2 for selecting a transmission path or a reception path, and may include a first input pin IN1 and a second input pin IN2, a first output pin OUT1 and a second output OUT2 for connecting to an active device array, and an input / output pin IO for connecting to an antenna.

[0062] The RF chip 64 may further include an interface circuit 64_2 and a controller 64_4. The controller 64_4 may include a hardware block designed by logic synthesis, or may include a processing block, which includes a software module containing a series of commands and one or more processors (such as a microprocessor or a central processing unit (CPU)) for executing the software module. The interface circuit 64_2 may receive a control signal CTRL from outside the RF chip 64 and provide the control signal CTRL or a signal converted therefrom to the controller 64_4. The controller 64_4 may adjust at least one matching parameter of the first matching network (M / N) M1 to the fourth matching network (M / N) M4 based on the signal provided by the interface circuit 64_2 as Figure 6 shown by the dashed line in. For example, the matching parameters of the first matching network (M / N) M1 to the fourth matching network (M / N) M4 may be adjusted individually according to the characteristics of one or more active devices included in the active device array. Therefore, for each of the matching networks (M / N) M1 to M4, the matching parameters may be the same, or some or all of the matching parameters may be different from each other. The first matching network (M / N) M1 to the fourth matching network (M / N) M4 may include adjustable matching parameters and may include, for example, passive devices having values variable under the control of the controller 64_4. It should be noted that the term "matching parameter" refers to a parameter for tuning a matching network (such as impedance matching, etc.) for one or more active devices.

[0063] Due to the first matching network (M / N) M1 to the fourth matching network (M / N) M4 that can be adjusted from outside the RF chip 64, various active device arrays can be connected to the RF chip 64. Therefore, the RF chip 64 may have high availability, and thus, a reconfigurable antenna module can be used according to a wireless communication device (such as, Figure 1 10). In some embodiments, it can be from Figure 1The data processor 16 provides the control signal CTRL. In some embodiments, the controller may be omitted, and the control signal CTRL may be provided to the first matching network (M / N) M1 to the fourth matching network (M / N) M4 through the interface circuit 64_2.

[0064] Figure 7 An antenna module according to an exemplary embodiment is shown. Specifically, Figure 7 is a perspective view showing an antenna module 70 including two active device arrays. Hereinafter, the Z-axis direction may be referred to as the vertical direction, a component disposed in the +Z-axis direction with respect to other components may be referred to as above the other components, and a component disposed in the -Z-axis direction with respect to other components may be referred to as below the other components. In addition, among the multiple surfaces of a component, the surface exposed in the +Z-axis direction may be referred to as the upper surface of the component, the surface exposed in the -Z-axis direction may be referred to as the lower surface of the component, and the surface exposed in a direction perpendicular to the Z-axis may be referred to as the side surface of the component. As Figure 7 shown, the antenna module 70 may include a multilayer board 71 and a connector 72, an RF chip 73, a first active device array 74_1, a second active device array 74_2, discrete devices 75, and a power management integrated circuit (PMIC) 76 on the lower surface of the multilayer board 71.

[0065] As will be described hereinafter with reference to Figure 8A and Figure 8B the multilayer board 71 may include multiple layers, each of the multiple layers may include the same or different materials, and the multiple layers may include conductive layers. In some embodiments, the multilayer board 71 may be a printed circuit board (PCB). The multilayer board 71 may include an antenna including a pattern formed on at least one layer, and the antenna may be configured to transmit and receive electromagnetic waves through the upper surface (i.e., in the Z-axis direction) of the multilayer board 71. In addition, the multilayer board 71 may include a pattern for connecting the RF chip 73 to the antenna (e.g., for connecting Figure 3A the input / output pins IO of the RF chip 34a to the antenna), and may include a pattern for connecting the RF chip 73 to the first active device array 74_1 and the second active device array 74_2. Examples of the multilayer board 71 will be described with reference to Figure 8A and Figure 8B

[0066] The connector 72 may be connected to a cable and / or other connectors, and may provide an interface between the antenna module 70 and external components. For example, the connector 72 may receive a voltage and / or current for powering the antenna module 70 and send the voltage and / or current to the PMIC 76 of the antenna module 70. In addition, the connector 72 may send a signal received from outside the antenna module 70 (e.g., Figure 1 ​The first intermediate frequency signal S_IF1) in is sent to the RF chip 73, and the signal provided from the RF chip 73 (e.g., Figure 1 S_IF1) can be output to the outside of the antenna module 70.

[0067] Each of the first active device array 74_1 and the second active device array 74_2 can extend parallel to the X-axis and can be adjacent to the edge of the RF chip 73 that extends parallel to the X-axis. That is, as Figure 7 shown, the first active device array 74_1 and the second active device array 74_2 can be adjacent to the edges of the RF chip 73 that face each other in the Y-axis direction. Figure 7 The arrangement of the RF chip 73, the first active device array 74_1, and the second active device array 74_2 shown in may be only an example, and other examples will be described below with reference to Figures 17A to 17C In some embodiments, the first active device array 74_1 and the second active device array 74_2 can be the same, thereby improving the productivity of the antenna module 70.

[0068] The discrete device 75 can include at least one passive device having a relatively large value and / or a relatively high breakdown voltage. For example, the discrete device 75 can include a bypass (or decoupling) capacitor for stabilizing the power supply voltage. The PMIC 76 can supply power to the components of the antenna module 70 (such as the RF chip 73) from the power supplied through the connector 72. For example, the PMIC 76 can generate at least one power supply voltage and can supply at least one power supply voltage to the RF chip 73 through the pattern included in the multilayer board 71.

[0069] Figure 8A and Figure 8B show examples of an antenna module according to an exemplary embodiment. Specifically, Figure 8A and Figure 8B are cross-sectional views showing an example of a cross-section taken along the line Y1 - Y2 in a plane perpendicular to the X-axis in the antenna module 70 of Figure 7 Hereinafter, will be described with reference to Figure 7 and Figure 8A and Figure 8B For the sake of brevity, descriptions that are repeated with each other and references to the descriptions described in Figure 7 will be omitted.

[0070] Referring to Figure 8A, the antenna module 70a may include a multilayer board 71a, and may include an RF chip 73a, a first active device array 74_1a, and a second active device array 74_2a on the bottom surface of the multilayer board 71a. The multilayer board 71a may include a patch antenna 71_1a configured to transmit and receive electromagnetic waves through the top surface of the multilayer board 71a. The patch antenna 71_1a may include patterns and vias for connecting to the second pin P72 and the third pin P73 of the RF chip 73a. The second pin P72 and the third pin P73 of the RF chip 73a may be input / output pins. In addition, the multilayer board 71a may include a ground plane TG under the patch antenna 71_1a, and may include a first heat dissipation structure 71_2a and a second heat dissipation structure 71_3a. In some embodiments, as Figure 8A shown, the first heat dissipation structure 71_2a and the second heat dissipation structure 71_3a may be connected to the ground plane TG, so the first heat dissipation structure 71_2a and the second heat dissipation structure 71_3a may have a ground potential. In some embodiments, the first heat dissipation structure 71_2a and the second heat dissipation structure 71_3a may have shapes different from those Figure 8A shown, and may be arranged differently from those Figure 8A shown. In addition, in some embodiments, the multilayer board 71a may include three or more heat dissipation structures, and in some embodiments, the first heat dissipation structure 71_2a and the second heat dissipation structure 71_3a may be combined into one structure (e.g., a structure surrounding the patch antenna 71_1a).

[0071] The multilayer board 71a may include patterns for connecting the RF chip 73a to the first active device array 74_1a and the second active device array 74_2a. For example, as Figure 8A shown, the multilayer board 71a may include a first pattern T71a for connecting to the fourth pin P74 of the RF chip 73a and the fifth pin P75a of the first active device array 74_1a, and may include a second pattern T72a for connecting to the first pin P71 of the RF chip 73a and the sixth pin P76a of the second active device array 74_2a. In some embodiments, the first pin P71 and the fourth pin P74 of the RF chip 73a may be input pins, and the fifth pin P75a of the first active device array 74_1a and the sixth pin P76a of the second active device array 74_2a may be output pins. In some embodiments, the first pin P71 and the fourth pin P74 of the RF chip 73a may be output pins, and the fifth pin P75a of the first active device array 74_1a and the sixth pin P76a of the second active device array 74_2a may be input pins.

[0072] Referring to Figure 8B, the antenna module 70b may include a multilayer board 71b, and may include an RF chip 73b, a first active device array 74_1b, and a second active device array 74_2b on the bottom surface of the multilayer board 71b. The multilayer board 71b may include a patch antenna 71_1b, a ground plane TG, a first heat dissipation structure 71_2b, and a second heat dissipation structure 71_3b.

[0073] In some embodiments, the active device array may be directly connected to the heat dissipation structure of the multilayer board. For example, as Figure 8B shown, the multilayer board 71b may include a first pattern T71b extending from the first heat dissipation structure 71_2b, and a fifth pin P75b of the first active device array 74_1b may be connected to the first pattern T71b. Similarly, the multilayer board 71b may include a second pattern T72b extending from the second heat dissipation structure 71_3b, and a sixth pin P76b of the second active device array 74_2b may be connected to the second pattern T72b. Compared with the prior art configuration in which the active devices included in the first active device array and the second active device array are included in the RF chip, since the first active device array 74_1b and the second active device array 74_2b separated from the RF chip 73b can be directly connected to the first heat dissipation structure 71_2b and the second heat dissipation structure 71_3b, the temperature rise of the components included in the RF chip 73b caused by the heat generation of the first active device array 74_1b and the second active device array 74_2b can be limited, and the temperature rise of the active devices included in the first active device array 74_1b and the second active device array 74_2b can also be limited. Specifically, the power consumption and heat generation in the transmission mode may mainly occur in the power amplifier, so that when the first active device array 74_1b and the second active device array 74_2b include the active devices included in the transmission circuit, the temperature characteristics of the antenna module 70b can be significantly improved. In some embodiments, as Figure 8B shown, the first heat dissipation structure 71_2b and the second heat dissipation structure 71_3b may be connected to the ground plane TG, and the fifth pin P75b of the first active device array 74_1b and the sixth pin P76b of the second active device array 74_2b may be ground pins (e.g., Figure 4A the ground pin G4 in the embodiment of

[0074] Figure 9 shows an antenna module according to an exemplary embodiment, Figure 10 shows according to an exemplary embodiment Figure 9 an enlarged view of region A of Figure 9 and Figure 10 are views showing from Figure 7A top view of an example of an RF chip 73, a first active device array 74_1, and a second active device array 74_2 as viewed along the -Z axis direction of the bottom surface of the multilayer board 71. Hereinafter, reference will be made to Figure 7 Description Figure 9 And Figure 10 .

[0075] Referring to Figure 9 , the antenna module 90 may include an RF chip 93, a first active device array 94_1, and a second active device array 94_2. The RF chip 93 may include a first set of pins PG01 and a second set of pins PG02. The first set of pins PG01 includes pins for connecting to the first active device array 94_1, and the second set of pins PG02 includes pins for connecting to the second active device array 94_2. In addition, the first active device array 94_1 may include a plurality of pins PG10 including pins for connecting to the RF chip 93, and the second active device array 94_2 may include a plurality of pins PG20 including pins for connecting to the RF chip 93.

[0076] As Figure 9 shown, the first active device array 94_1 may be adjacent to the first edge E1 of the RF chip 93, and the first set of pins PG01 of the RF chip 93 may be arranged parallel to the first edge E1. The first active device array 94_1 may extend parallel to the first edge E1, and the plurality of pins PG10 of the first active device array 94_1 may also be arranged parallel to the first edge E1. In addition, the second active device array 94_2 may be adjacent to the second edge E2 of the RF chip 93, and the second set of pins PG02 of the RF chip 93 may be arranged parallel to the second edge E2. The second active device array 94_2 may extend parallel to the second edge E2, and the plurality of pins PG20 of the second active device array 94_2 may also be arranged parallel to the second edge E2.

[0077] Referring to Figure 10 , the pins of the RF chip 93 and the pins of the second active device array 94_2 may be spaced apart from each other by the same pitch X0. As described above with reference to Figure 4A etc., when the second active device array 94_2 includes transistors and includes pins connected to the electrodes of the transistors, input pins, ground pins, and output pins may be repeated. For example, as Figure 10As shown in the figure, the first pin P1, the second pin P2, and the third pin P3 of the RF chip 93 can respectively correspond to an input pin, a ground pin, and an output pin, and the fourth pin P4, the fifth pin P5, and the sixth pin P6 of the second active device array 94_2 can respectively correspond to an output pin, a ground pin, and an input pin. Optionally, the first pin P1 to the third pin P3 of the RF chip 93 can respectively correspond to an output pin, a ground pin, and an input pin, and the fourth pin P4 to the sixth pin P6 of the second active device array 94_2 can respectively correspond to an input pin, a ground pin, and an output pin. As will be described hereinafter with reference to Figure 14 As described, a multilayer board (e.g., Figure 7 71 in the embodiment of

[0078] Figure 11 and Figure 12 may include patterns for interconnecting the input pins and output pins of the RF chip 93 and the second active device array 94_2. Figure 11 shows a block diagram of an RF chip 110 including 16 transmit circuits and 16 receive circuits, Figure 12 shows Figure 11 an example of the layout of the RF chip 110. In some embodiments, similar to those shown in Figure 7 the RF chip 110 can be connected to two active device arrays.

[0079] Referring to Figure 11 , the RF chip 110 can include eight first transmit and receive circuits 111, eight second transmit and receive circuits 112, and a processing circuit 113. The first transmit and receive circuits 111 can be respectively connected to eight pins P11 to P18 for connecting to an antenna, and the second transmit and receive circuits 112 can also be respectively connected to eight pins P21 to P28 for connecting to an antenna. The processing circuit 113 can be connected to the first transmit and receive circuits 111 and the second transmit and receive circuits 112, and can include switches, combiners / dividers, mixers, local oscillator generators, etc. As shown by the dashed lines in Figure 11 some of the active devices in the transmit circuits included in the RF chip 110 can be omitted, and the RF chip 110 can be connected to an active device array including the omitted active devices.

[0080] Referring to Figure 12, in the RF chip 110', the first transmit and receive circuit 111' and the second transmit and receive circuit 112' can be adjacent to the first edge E1 and the second edge E2 of the RF chip 110' respectively, and the processing circuit 113' can be between the first transmit and receive circuit 111' and the second transmit and receive circuit 112'. The first transmit and receive circuit 111' can include eight pairs of "transmit circuit and receive circuit" 111_1 and a phase shifter 111_2. As Figure 12 shown, the eight pairs of "transmit circuit and receive circuit" 111_1 can be adjacent to the first edge E1 and arranged parallel to the first edge E1. In addition, the second transmit and receive circuit 112' can include eight pairs of "transmit circuit and receive circuit" 112_1 and a phase shifter 112_2. As Figure 12 shown, the eight pairs of "transmit circuit and receive circuit" 112_1 can be adjacent to the second edge E2 and arranged parallel to the second edge E2.

[0081] Figure 13A And Figure 13B show an example of the layout of the active device array according to an exemplary embodiment. In some embodiments, Figure 13A the active device array 130a and Figure 13B the active device array 130b can be adjacent to the first edge E1 or the second edge E2 of the Figure 12 RF chip 110' respectively, and can be connected to the RF chip 110'. Hereinafter, reference will be made to Figure 12 to describe Figure 13A and Figure 13B .

[0082] Referring to Figure 13A , the active device array 130a can include the first active device A01a to the eighth active device A08a. The first active device A01a to the eighth active device A08a can be respectively connected to Figure 12 the eight pairs of "transmit circuit and receive circuit" 111_1 (or 112_1) of the first transmit and receive circuit 111' (or 112') of

[0083] Referring to Figure 13B , the active device array 130b can pre-include additional active devices. For example, as Figure 13B shown, the active device array 130b can include the first active device A01b to the eleventh active device A11b. Eight of the first active device A01b to the eleventh active device A11b can be respectively connected to Figure 12Eight pairs of "transmission circuits and reception circuits" 111_1 (or 112_1) of the first transmission and reception circuit 111' (or 112') are provided, and the remaining three active devices may not participate in the transmission and reception operations and may be referred to as dummy active devices. For example, the RF chip 110' may include switches (or multiplexers) between the first transmission and reception circuit 111' and the pins, and some of the 11 active devices A01b to A11b included in the active device array 130b (i.e., eight active devices in this example) may be selected through the switches.

[0084] Figure 14 Shows a multilayer board according to an exemplary embodiment. In some embodiments, Figure 10 The RF chip 93 and the second active device array 94_2 may be disposed on Figure 14 The bottom surface of the multilayer board 140, and Figure 14 Shows Figure 10 An example of the patterns of the first pin P1 to the sixth pin P6 in. Hereinafter, reference will be made to Figure 10 To describe Figure 14 .

[0085] As Figure 14 Shown in, the multilayer board 140 may include first patterns T141 to fourth patterns T144. The first pattern T141 may interconnect Figure 10 The first pin P1 and the fourth pin P4 of, and the third pattern T143 may interconnect Figure 10 The third pin P3 and the sixth pin P6 of. In addition, the second pattern T142 may be connected to Figure 10 The second pin P2 of, and the fourth pattern T144 may be connected to Figure 10 The fifth pin P5 of. As described above with reference to Figure 10 , the first pin P1 to the third pin P3 of the RF chip 93 and the fourth pin P4 to the sixth pin P6 of the second active device array 94_2 may be spaced apart from each other by the same pitch in the X-axis direction. Therefore, as Figure 14 Shown in, the first pattern T141 and the third pattern T143 may extend parallel to the Y-axis and may be arranged along the X-axis. In addition, for connection to the pins, the patterns may include regions exposed to the outside of the multilayer board 140. For example, as Figure 14 Shown in, the first patterns T141 to the fourth patterns T144 in the first region R1 to the sixth region R6 may be exposed to the outside of the multilayer board 140, and the exposed regions may be referred to as pads.

[0086] Figure 15 Shows an antenna module according to an exemplary embodiment. Specifically, Figure 15is a block diagram showing one antenna in the antenna module 150 and a part of the transmission circuit constituting a transmission path corresponding to the one antenna. Compared with the antenna module 40a of Figure 4A in the antenna module 150 of Figure 15 the second matching network (M / N) M152 can be included in the multilayer board 152 instead of being included in the RF chip 154. Hereinafter, for simplicity, descriptions that are repetitive with the description of Figure 4A will be omitted.

[0087] The RF chip 154 may include a first amplifier circuit A151, a second amplifier circuit A152, a first matching network (M / N) M151, and a first switch SW151, and may further include a first input pin IN151, a first output pin OUT151, and an input / output pin IO15 connected to the multilayer board 152. The active device array 156 may include a third amplifier circuit A153, and includes a second input pin IN152, a second output pin OUT152, and a ground pin G15 connected to the multilayer board 152. The multilayer board 152 may include a second matching network (M / N) M152 and an antenna 152_1. Due to the size of the multilayer board 152 being larger than that of the RF chip 154, compared with the matching network (M / N) included in the RF chip 154, the second matching network (M / N) M152 included in the multilayer board 152 may have good characteristics and / or the second matching network (M / N) M152 included in the multilayer board 152 may be easier to design. Therefore, the performance and usability of the transmission circuit can be further improved. In some embodiments, different from those shown in Figure 15 the RF chip 154 may include an additional matching network between the second amplifier circuit A152 and the second matching network (M / N) M152, and the additional matching network and the second matching network (M / N) M152 may provide matching between the second amplifier circuit A152 and the third amplifier circuit A153.

[0088] Figure 16 shows an antenna module according to an exemplary embodiment. Specifically, as described above with reference to Figure 15 Figure 16 shows a cross-sectional view of the antenna module 160 including a multilayer board 161 including a matching network (M / N) 161_4 cut along a plane perpendicular to the X axis. As shown in Figure 16 the antenna module 160 may include a multilayer board 161, an RF chip 162, a first active device array 164_1, and a second active device array 164_2.

[0089] ​The multilayer board 161 may include a matching network (M / N) 161_4 below the ground plane TG, and the RF chip 162 may include a first pin P1 connected to the matching network (M / N) 161_4. The second active device array 164_2 may also include a second pin P2 connected to the matching network (M / N) 161_4. When the first pin P1 is an input pin, the second pin P2 may be an output pin, and when the first pin P1 is an output pin, the second pin P2 may be an input pin.

[0090] Figures 17A to 17C An example of an antenna module according to an exemplary embodiment is shown. Specifically, Figures 17A to 17C is a perspective view showing antenna modules 170a, 170b, and 170c corresponding to various combinations of an RF chip and active device arrays, respectively. Hereinafter, for simplicity of description, the description of Figures 17A to 17C omits the description that duplicates the description of Figure 7

[0091] Referring to Figure 17A , the antenna module 170a may include a multilayer board 171a, a connector 172a, an RF chip 173a, first to fourth active device arrays 174_1a to 174_4a, a discrete device 175a, and a PMIC 176a. As shown in Figure 17A , the first active device array 174_1a and the second active device array 174_2a may extend parallel to the X-axis and may be equidistantly spaced from an edge of the RF chip 173a in the Y-axis direction. Similarly, the third active device array 174_3a and the fourth active device array 174_4a may extend parallel to the X-axis and may be equidistantly spaced from an edge of the RF chip 173a in the Y-axis direction. In some embodiments, the first to fourth active device arrays 174_1a to 174_4a may be the same.

[0092] Referring to Figure 17B , the antenna module 170b may include a multilayer board 171b, a connector 172b, an RF chip 173b, first to fourth active device arrays 174_1b to 174_4b, a discrete device 175b, and a PMIC 176b. As shown in Figure 17B , the first to fourth active device arrays 174_1b to 174_4b may be adjacent to the edges of the RF chip 173b, respectively. In some embodiments, the first to fourth active device arrays 174_1b to 174_4b may be the same.

[0093] Referring to Figure 17C, the antenna module 170c may include a multilayer board 171c, a connector 172c, a first RF chip 173_1c, a second RF chip 173_2c, an active device array 174c, discrete devices 175c, and a PMIC 176c. In some embodiments, the antenna module 170c may include multiple RF chips, and the multiple RF chips may share at least one active device array. For example, as Figure 17C shown, the active device array 174c may be between the first RF chip 173_1c and the second RF chip 173_2c, and may be connected to the first RF chip 173_1c and the second RF chip 173_2c respectively. Therefore, some of the active devices included in the active device array 174c may be connected to the first RF chip 173_1c, while other active devices may be connected to the second RF chip 173_2c.

[0094] Figure 18 shows an antenna module according to an exemplary embodiment. Specifically, Figure 18 is a perspective view showing an antenna module including a dipole antenna. As Figure 18 shown, the antenna module 180 may include a multilayer board 181, a connector 182, an RF chip 183, a first active device array 184_1, a second active device array 184_2, discrete devices 185, and a PMIC 186. Hereinafter, for simplicity, descriptions that are repetitive of Figure 7 will be omitted.

[0095] The multilayer board 181 may include first to fourth dipole antennas 187_1 to 187_4. As Figure 18 shown, the multilayer board 181 may include a first region 181_1 and a second region 181_2. The first region 181_1 includes a patch antenna that can transmit and receive electromagnetic waves through the upper surface of the multilayer board 181 (i.e., the surface exposed in the +Z-axis direction), and the second region 181_2 includes dipole antennas. The connector 182, the RF chip 183, the first active device array 184_1, the second active device array 184_2, the discrete devices 185, and the PMIC 186 may be disposed on the bottom surface of the first region 181_1. The first to fourth dipole antennas 187_1 to 187_4 may be connected to the RF chip 183, and may transmit and receive electromagnetic waves through the side surface of the multilayer board 181 (e.g., the surface perpendicular to the Y-axis). It will be understood that the exemplary embodiment is not limited to Figure 18 the shapes and numbers of the first to fourth dipole antennas 187_1 to 187_4 shown.

[0096] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A radio frequency chip, the radio frequency chip being configured to process radio frequency signals, the radio frequency chip comprising: Input / output pins for connecting to an antenna; A first output pin and a first input pin for connecting to electrodes of a first active device included in a first active device array separated from the radio frequency chip, respectively; And A transmitting circuit forming part of a transmission path for generating a radio frequency signal to be provided to the antenna, wherein the transmission path sequentially passes through the first output pin, the first active device, and the first input pin, wherein the transmitting circuit includes passive devices and active devices implemented by a first process, and wherein the first process is different from a second process for implementing the first active device array.

2. The radio frequency chip according to claim 1, wherein the first active device is a transistor included in a power amplifier forming part of the transmission path.

3. The radio frequency chip according to claim 2, wherein the power amplifier is a multi-stage amplifier, and the transistor is included in the last stage of the multi-stage amplifier.

4. The radio frequency chip according to claim 1, further comprising: A second output pin and a second input pin for connecting to electrodes of a second active device included in the first active device array, respectively, wherein the transmission path sequentially passes through the second output pin, the second active device, the second input pin, and the first output pin.

5. The radio frequency chip according to claim 1, wherein The transmitting circuit includes: A first matching network connected to the first output pin and including at least one passive device; and A second matching network connected to the first input pin and including at least one passive device.

6. The radio frequency chip according to claim 5, further comprising: An interface circuit configured to receive a control signal from outside the radio frequency chip, wherein at least one of the first matching network and the second matching network is tunable according to the control signal.

7. The radio frequency chip according to claim 1, wherein the first active device is one of a plurality of active devices included in the first active device array, the radio frequency chip includes a first set of pins for connecting to electrodes of the plurality of active devices, respectively, and the first set of pins is arranged parallel and adjacent to a first edge of the radio frequency chip.

8. The radio frequency chip according to claim 7, further comprising: A second set of pins for connecting to electrodes of a plurality of active devices included in a second active device array, wherein the second set of pins is arranged parallel and adjacent to a second edge of the radio frequency chip opposite to the first edge.

9. The radio frequency chip according to claim 8, further comprising: A plurality of transmitting circuits, each transmitting circuit forming part of each of a plurality of transmission paths, wherein a first part of the plurality of transmitting circuits is arranged parallel and adjacent to the first edge, and a second part of the plurality of transmitting circuits is arranged parallel and adjacent to the second edge.

10. The radio frequency chip according to claim 1, further comprising: A third output pin and a third input pin for connecting to electrodes of a third active device included in the first active device array or included in a third active device array, and A receiving circuit, forming part of a receiving path for processing radio frequency signals received from an antenna, wherein the receiving path sequentially passes through a third output pin, a third active device, and a third input pin.

11. The radio frequency chip according to claim 10, wherein, the third active device is a transistor included in a low noise amplifier forming part of the receiving path.

12. The radio frequency chip according to claim 11, wherein, the low noise amplifier is a multi-stage amplifier, and the transistor is included in the initial stage of the multi-stage amplifier.

13. The radio frequency chip according to claim 12, further comprising: a fourth output pin and a fourth input pin for respectively connecting to electrodes of a fourth active device included in a first active device array or included in a third active device array, and wherein the receiving path sequentially passes through the third input pin, the fourth output pin, the fourth active device, and the fourth input pin.

14. The radio frequency chip according to claim 10, wherein, The receiving circuit comprises: a third matching network connected to the third output pin and including at least one passive device; and a fourth matching network connected to the third input pin and including at least one passive device.

15. The radio frequency chip according to claim 1, wherein, the first process is a complementary metal oxide semiconductor process.

16. An antenna module, comprising: a multilayer board including an antenna configured to transmit and receive electromagnetic waves through a top surface of the multilayer board; a radio frequency chip on a bottom surface of the multilayer board, the radio frequency chip being connected to the antenna and configured to process radio frequency signals; and a first active device array on the bottom surface of the multilayer board and separated from the radio frequency chip, the first active device array including a plurality of active devices, a first input pin, and a first output pin, the first input pin and the first output pin being respectively connected to electrodes of a first active device among the plurality of active devices, wherein the multilayer board comprises: a first pattern for providing a first signal from the radio frequency chip to the first input pin; and a second pattern for providing a second signal from the first output pin to the radio frequency chip, wherein the radio frequency chip includes a transmitting circuit, the transmitting circuit forming part of a transmitting path for generating radio frequency signals to be provided to the antenna, and the transmitting path sequentially passes through the first input pin, the first active device, and the first output pin.

17. The antenna module according to claim 16, wherein, the first active device is a high electron mobility transistor, and the radio frequency chip includes passive devices and active devices implemented by a complementary metal oxide semiconductor process.

18. The antenna module according to claim 16, wherein, the transmitting path sequentially passes through the first pattern, the first input pin, the first active device, the first output pin, and the second pattern.

19. The antenna module according to claim 16, wherein, the first active device array further includes a first ground pin connected to an electrode of the first active device configured to receive a ground potential, and the multilayer board further includes a heat dissipation structure connected to the first ground pin.

20. The antenna module according to claim 16, wherein, The multilayer board comprises: at least one of a first matching network connected to the first pattern and a second matching network connected to the second pattern, Wherein, the first signal passes through a first matching network, and wherein, the second signal passes through a second matching network.

21. An antenna module, comprising: a multilayer board including at least one antenna configured to transmit and receive electromagnetic waves; a radio frequency chip on a bottom surface of the multilayer board, the radio frequency chip including a plurality of transmitting circuits, each of the plurality of transmitting circuits forming a part of each of a plurality of transmitting paths for generating a plurality of radio frequency signals to be provided to the at least one antenna; and a first active device array on the bottom surface of the multilayer board and separated from the radio frequency chip, the first active device array including a first group of active devices, a plurality of first input pins, and a plurality of first output pins, the first group of active devices respectively including at least a part of a plurality of power amplifiers in the plurality of transmitting paths of the plurality of transmitting circuits, the plurality of first input pins and the plurality of first output pins respectively connected to electrodes of the first group of active devices, wherein, the plurality of transmitting paths sequentially pass through the plurality of first input pins, the first group of active devices, and the plurality of first output pins, the plurality of transmitting circuits include passive devices and active devices implemented by a first process, and wherein, the first process is different from a second process for implementing the first active device array.

22. The antenna module according to claim 21, wherein, each active device in the first group of active devices is a high electron mobility transistor, and the first process is a complementary metal oxide semiconductor process.

23. The antenna module according to claim 21, wherein, the first active device array extends parallel to and adjacent to a first edge of the radio frequency chip, and the plurality of first input pins and the plurality of first output pins are arranged parallel to the first edge.

24. The antenna module according to claim 23, further comprising: a second active device array on the bottom surface of the multilayer board, the second active device array including a second group of active devices respectively including at least a part of a plurality of power amplifiers, and a plurality of second input pins and a plurality of second output pins respectively connected to electrodes of the second group of active devices, wherein, the second active device array extends parallel to and adjacent to a second edge of the radio frequency chip opposite to the first edge.

25. The antenna module according to claim 23, wherein, The multilayer board includes: a first group of patterns for providing signals from the radio frequency chip to the plurality of first input pins; and a second group of patterns for providing signals from the plurality of first output pins to the radio frequency chip, wherein, the first group of patterns and the second group of patterns extend in a direction perpendicular to the first edge.

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