Display devices

Abstract

A display apparatus includes a display panel including scan lines, data lines, light emission control lines, and pixels connected to the scan lines, the data lines, and the light emission control lines; a scan driver configured to sequentially provide scan signals to the scan lines; a data driver configured to provide data signals to the data lines; a light emission driver configured to provide light emission control signals to the light emission control lines based on a light emission clock signal having pulses; and a timing controller configured to provide the light emission clock signal to the light emission driver, output a pulse of the light emission clock signal during a frame in a first mode, mask at least one of the pulses during a first period of the frame in a second mode, and output at least another of the pulses during a second period after the first period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0091893, filed on July 29, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] An embodiment of the present disclosure relates to a display device. Background Art

[0004] A display device includes a display panel and a driver. The display panel includes scan lines, data lines, light-emission control lines, and pixels. The driver includes a scan driver that sequentially supplies scan signals to the scan lines, a light-emission driver that sequentially supplies light-emission control signals to the light-emission control lines, and a data driver that supplies data signals to the data lines. Each pixel can emit light having a brightness corresponding to a data signal supplied via a corresponding data line, in response to a scan signal supplied via the corresponding scan line, for a time corresponding to the light-emission control signal.

[0005] Recently, foldable display devices have been developed. To reduce power consumption, a driving condition for displaying an image only in some areas of the foldable display panel in a folded state or driving the display panel at different frequencies can be implemented by dividing the display panel into multiple areas. Summary of the Invention

[0006] When a complete display panel is divided into a plurality of regions and driven under different conditions, display quality is degraded in boundary regions affected by the different conditions.

[0007] Embodiments of the present disclosure provide a display device capable of driving regions of a display panel under mutual driving conditions (eg, different frequencies) or driving only some regions of a display panel without degradation of display quality.

[0008] To achieve one aspect of the present disclosure, a display device according to an embodiment of the present disclosure includes: a display including scan lines, data lines, light-emitting control lines, and pixels connected to the scan lines, data lines, and light-emitting control lines; a scan driver configured to sequentially provide scan signals to the scan lines; a data driver configured to provide data signals to the data lines; a light-emitting driver configured to provide light-emitting control signals to the light-emitting control lines based on a light-emitting clock signal having pulses; and a timing controller configured to provide the light-emitting clock signal to the light-emitting driver, output pulses of the light-emitting clock signal during a frame in a first mode, shield at least one of the pulses during a first period of the frame in a second mode, and output at least another pulse of the pulses during a second period after the first period.

[0009] The light emitting driver may be configured to sequentially provide light emitting control signals to the light emitting control lines in a first mode, and not provide any of the light emitting control signals to the light emitting control line corresponding to the at least one pulse among the light emitting control lines in a second mode.

[0010] The first period may be less than or equal to a pulse width of each of the light emitting control signals.

[0011] The second period may be greater than or equal to a period of the light emitting clock signal.

[0012] The light-emitting clock signal may include a first light-emitting clock signal and a second light-emitting clock signal obtained by delaying the phase of the first light-emitting clock signal by half a period, and the timing controller may be configured to partially shield one of the first light-emitting clock signal and the second light-emitting clock signal in the second mode.

[0013] In the second period, the first light emitting clock signal may have at least one pulse, and the second light emitting clock signal may have at least one pulse.

[0014] The timing controller may be configured to partially shield the other of the first light emitting clock signal and the second light emitting clock signal.

[0015] The frame may further include a third period after the second period, the timing controller may be configured to shield the first and second light emitting clock signals during the third period in the second mode, and the third period may be greater than a pulse width of each of the light emitting control signals.

[0016] The scan driver may be configured to generate the scan signal based on the scan clock signal, and the timing controller may be configured to provide the scan clock signal to the scan driver and mask one pulse of the scan clock signal in the second mode.

[0017] The data driver may be configured to output a data voltage corresponding to a black grayscale at a first time point when one pulse of the scan clock signal is shielded.

[0018] A second time point at which the timing controller shields at least one pulse of the light-emitting clock signal may be later than a first time point at which the timing controller shields one pulse of the scan clock signal.

[0019] A difference between the first time point and the second time point may be less than or equal to a pulse width of each of the light emitting control signals.

[0020] A difference between the first time point and the second time point may be greater than a pulse width of each of the light emitting control signals.

[0021] The timing controller may include: an area determiner for determining a first area in the display where a static image is displayed or no image is displayed by comparing a current frame with a previous frame; a shielding time point determiner for generating a shielding signal based on the first area; and a clock generator for generating a light-emitting clock signal, and for shielding at least one pulse of the light-emitting clock signal based on the shielding signal.

[0022] The timing controller may further include a data compensator for generating image data by compensating input image data, the data driver may be configured to generate a data signal based on the image data, the shielding time point determiner may be configured to determine a compensation period in which a pulse width of at least one of the light emitting control signals is changed based on the shielding signal, and the data compensator may be configured to compensate for a portion of the image data corresponding to the compensation period based on the pulse width.

[0023] The timing controller may periodically switch between the first mode and the second mode.

[0024] Each of the pixels may include: a light-emitting element; a first transistor including a first electrode connected to a first power supply, a second electrode connected to a first node, a gate electrode connected to a second node, and a body to which a common control voltage is applied; a second transistor configured to transmit a corresponding data signal among the data signals to the second node in response to a scan signal among the scan signals; and a third transistor connecting the first node and the light-emitting element.

[0025] A common control voltage having a first voltage level is applied to the pixels in a first mode, and a common control voltage having a second voltage level different from the first voltage level may be applied to a portion of the pixels in a second mode.

[0026] The display may include a first pixel area and a second pixel area separated from each other, each of the first pixels provided in the first pixel area can be connected to a first common control line to receive a common control voltage, and each of the second pixels provided in the second pixel area can be connected to a second common control line to receive a common control voltage.

[0027] The data driver may include a digital-to-analog converter configured to generate a data signal based on the gamma voltages, a common buffer configured to output one of the gamma voltages as a reference voltage, and an output buffer configured to alternately output the data signal and the reference voltage in the second mode.

[0028] Beneficial effects

[0029] A display device according to an embodiment of the present disclosure can shield a portion of the pulses included in the light-emission clock signal during a portion of a frame period, thereby shielding the output of the stage corresponding to the shielded light-emission clock signal, in other words, shielding the light-emission control signal. Therefore, the display device can drive only a portion of the display panel during a frame period.

[0030] In addition, by setting the time point when the light-emitting clock signal is shielded (or the time point when the scanning clock signal is shielded) to be slower than the time point when the black image is displayed, or by predicting the impact caused by shielding the light-emitting clock signal to compensate for the data, the degradation of display quality can be reduced or prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0032] Figure 2 It is an icon Figure 1 FIG. 1 is a diagram showing an example of a driving mode of a display device.

[0033] Figure 3 The diagram is included in Figure 1 A circuit diagram of an example of a pixel in a display device.

[0034] Figure 4 The diagram is included in Figure 1 A circuit diagram of another example of a pixel in a display device.

[0035] Figure 5 The diagram is included in Figure 4 A cross-sectional view of an example of a first transistor in a pixel.

[0036] Figure 6 The diagram is included in Figure 1 FIG. 1 is a diagram of an example of a display in a display device.

[0037] Figure 7 It is an icon Figure 6 The waveform diagram of the display operation.

[0038] Figure 8 The diagram is included in Figure 1 A block diagram of an example of a light emitting driver in a display device.

[0039] Figure 9 The diagram is included in Figure 8 1 is a circuit diagram of an example of a stage in a light-emitting driver.

[0040] Figure 10 The diagram is shown in the first mode of operation. Figure 9 A waveform diagram of an example of a signal measured in the stage.

[0041] Figure 11 The diagram is shown in the second mode of operation. Figure 9 A waveform diagram of an example of a signal measured in the stage.

[0042] Figure 12 The diagram is shown in the second mode of operation. Figure 9 A waveform diagram of another example of a signal measured in the stage .

[0043] Figure 13 The diagram is shown in the second mode of operation. Figure 9 A waveform diagram of yet another example of a signal measured in the stage.

[0044] Figure 14 It is shown in the figure Figure 8 FIG. 1 is a waveform diagram of an example of a signal measured in a light emitting driver.

[0045] Figure 15 It is shown in the figure Figure 8 FIG. 1 is a waveform diagram of another example of a signal measured in a light emitting driver.

[0046] Figure 16 The diagram shows the operation in the second mode. Figure 1 A diagram of an example of a display device.

[0047] Figure 17 It is shown in the figure Figure 16 A waveform diagram showing an example of a signal measured in a display device.

[0048] Figure 18 The diagram is included in Figure 1 A block diagram of an example of a timing controller in a display device.

[0049] Figure 19 The diagram is included in Figure 1 A block diagram of another example of a timing controller in a display device.

[0050] Figure 20 It is an icon Figure 1 A waveform diagram showing the operation of the device.

[0051] Figure 21 The diagram is included in Figure 1 A block diagram of an example of a data driver in a display device.

[0052] Figure 22 The diagram is included in Figure 21 A circuit diagram of an example of an output buffer in a data driver. DETAILED DESCRIPTION

[0053] By referring to the specific implementation methods and drawings of the embodiments, the features of the present invention and the methods for implementing the same can be more easily understood. Hereinafter, the embodiments will be described in more detail with reference to the drawings. However, the described embodiments can be embodied in various different forms and should not be understood as being limited to the illustrative embodiments herein. On the contrary, these embodiments are provided as examples to make this disclosure comprehensive and complete and to fully convey the inventions and features of the present invention to those skilled in the art. Therefore, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present invention may not be described.

[0054] Unless otherwise noted, the same reference numerals denote the same elements throughout the drawings and written description, and therefore, their descriptions will not be repeated. In addition, components not relevant to the description of the embodiments may not be shown to make the description clear. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity.

[0055] Various embodiments are described herein with reference to cross-sectional illustrations, which are schematic illustrations of embodiments and / or intermediate structures. As such, variations between the illustrated shapes are to be expected as a result, for example, of manufacturing techniques and / or tolerances. Furthermore, specific structural or functional descriptions disclosed herein are merely for purposes of describing embodiments according to the concepts of the present disclosure. Accordingly, the embodiments disclosed herein should not be construed as limited to the shapes of the specific illustrated regions, but are to include deviations in shapes resulting, for example, from manufacturing.

[0056] For example, an implanted region illustrated as a rectangle will typically have rounded or curved features and / or a gradient of implant concentration at its edges, rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions illustrated in the figures are schematic in nature, their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to be limiting. Furthermore, as will be appreciated by those skilled in the art, the described embodiments may be modified in a variety of different ways, all without departing from the spirit or scope of the present disclosure.

[0057] In the detailed description, for purposes of illustration, numerous specific details are set forth to provide a thorough understanding of the various embodiments. However, it will be apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0058] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion described below may be referred to as a second element, component, region, layer, or portion without departing from the spirit and scope of the present disclosure.

[0059] For ease of description, spatial relative terms such as "below", "beneath", "below", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the drawings. It should be understood that spatial relative terms are intended to include different orientations of the device in use or operation other than the orientation depicted in the drawings. For example, if the device in the drawings is turned over, the elements described as being "below" or "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the example terms "below" and "below" may include both above and below. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first component is described as being disposed "on" a second component, this indicates that the first component is disposed on the upper or lower side of the second component, and is not limited to the upper side of the second component based on the direction of gravity.

[0060] It will be understood that when an element, layer, region or component is referred to as being "on," "connected to" or "coupled to" another element, layer, region or component, the element, layer, region or component can be directly on, directly connected to or coupled to the other element, layer, region or component, or one or more intermediate elements, layers, regions or components can be present. However, "direct connection / direct coupling" refers to a component being directly connected or coupled to another component without intermediate components. At the same time, other expressions describing the relationship between components, such as "between," "immediately adjacent to," or "adjacent to," and "directly adjacent to," can be similarly interpreted. In addition, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers can also be present.

[0061] For purposes of this disclosure, expressions such as "at least one of..." when following a list of elements modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. Throughout, like numbers refer to like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0062] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular form "a" is intended to also include the plural form, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "having," and "comprising" and their variations when used in this specification indicate the presence of stated features, wholes, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or combinations thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0063] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art will recognize. Taking into account the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the stated value and mean within an acceptable range of deviations from the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Further, when describing embodiments of the present disclosure, the use of "can" relates to "one or more embodiments of the present disclosure."

[0064] When a certain embodiment can be implemented differently, a specific process sequence can be performed in a different order than described. For example, two processes described in succession can be performed substantially simultaneously, or in a reverse order to the described order.

[0065] The electronic or electrical devices and / or any other related devices or components according to the embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0066] In addition, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in a memory (e.g., random access memory (RAM)) that can be implemented in a computing device using standard storage devices. The computer program instructions can also be stored in other non-transitory computer-readable media such as, for example, a CD-ROM, a flash drive, etc. In addition, those skilled in the art will recognize that the functions of various computing devices can be combined or integrated into a single computing device, or that the functions of a particular computing device can be distributed across one or more other computing devices without departing from the spirit and scope of the embodiments of the present disclosure.

[0067] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0068] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 It is an icon Figure 1 FIG. 1 is a diagram showing an example of a driving mode of a display device.

[0069] First, refer to Figure 1 , the display device 100 may include a display unit / display / display panel 110, a scan driver 120 (or gate driver), a data driver 130 (or source driver), a timing controller 140 and a light emitting driver 150 (or emission driver or EM driver).

[0070] The display 110 may include scan lines / gate lines SL1 to SLn (n is a positive integer), data lines DL1 to DLm (m is a positive integer), emission control lines EL1 to ELn, and pixels PXL. The pixels PXL may be located in a region (e.g., a pixel region) partitioned by the scan lines SL1 to SLn, the data lines DL1 to DLm, and the emission control lines EL1 to ELn.

[0071] The pixel PXL can be connected to at least one of the scan lines SL1 to SLn, one of the data lines DL1 to DLm, and at least one of the emission control lines EL1 to ELn. For example, the pixel PXL can be connected to the scan line SLi, the previous scan line SLi-1 adjacent to the scan line SLi, the data line DLj, and the emission control line ELi (each of i and j is a positive integer).

[0072] The pixel PXL can be initialized in response to a scan signal provided by the previous scan line SLi-1 (or in response to a scan signal provided at a previous time point, or in response to a previous gate signal). The pixel PXL can store or record a data signal provided by the data line DLj in response to a scan signal provided by the scan line SLi (or in response to a scan signal provided at a current time point, or in response to a current gate signal). The pixel PXL can also emit light at a brightness corresponding to the stored data signal in response to a light emission control signal provided by the light emission control line ELi.

[0073] The display 110 may be supplied with a first power voltage VDD and a second power voltage VSS. The power voltages VDD and VSS are voltages suitable for the operation of the pixel PXL, and the first power voltage VDD may have a higher voltage level than the second power voltage VSS.

[0074] The scan driver 120 may generate a scan signal based on the scan control signal SCS and may sequentially provide the scan signal to the scan lines SL1 to SLn. Here, the scan control signal SCS may include a scan start signal, a scan clock signal, etc., and may be provided from the timing controller 140. For example, the scan driver 120 may include a shift register (or stage) that sequentially generates and outputs a pulse-type scan signal corresponding to the pulse-type scan start signal using the scan clock signal.

[0075] The light emitting driver 150 may generate a light emitting control signal based on the light emitting drive control signal ECS and may sequentially provide the light emitting control signal to the light emitting control lines EL1 to ELn. Here, the light emitting drive control signal ECS may include a light emitting start signal, a light emitting clock signal, etc., and may be provided from the timing controller 140. For example, the light emitting driver 150 may include a shift register that sequentially generates and outputs a pulse-type light emitting control signal corresponding to the pulse-type light emitting start signal using the light emitting clock signal.

[0076] Will refer to it later Figure 8 A detailed configuration of the light emitting driver 150 is described.

[0077] The data driver 130 may generate a data signal based on the image data DATA2 and the data control signal DCS provided from the timing controller 140, and may provide the data signal to the display 110 (or to the pixel PXL). Here, the data control signal DCS is a signal for controlling the operation of the data driver 130 and may include a load signal (or a data enable signal) for instructing the output of a valid data signal.

[0078] The timing controller 140 may receive input image data DATA1 and a control signal CS from an external device (e.g., a graphics processor), may generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and may generate image data DATA2 by converting the input image data DATA1. For example, the timing controller 140 may convert the input image data DATA1 in RGB format into image data DATA2 in RGBG format to conform to the pixel arrangement in the display 110.

[0079] In some of the embodiments, the timing controller 140 may operate in a first mode and a second mode.Here, the first mode and the second mode may be operation modes of the timing controller 140 (or the display device 100).

[0080] refer to Figure 2 , for example, the first mode MODE1 is a normal mode, and in the first mode MODE1 , the display device 100 may display a first image IMAGE1 corresponding to the entire display 110 .

[0081] For example, the second mode MODE2 is a partial driving mode, and in the second mode MODE2, the display device 100 can display a second image IMAGE2 (for example, a video) in the first display area DA1 of the display 110, and can also display a third image IMAGE3 (for example, a static image or a low-frequency image) in the second display area DA2 of the display 110, or conversely can display no image.

[0082] Therefore, in order to display the first image IMAGE1 on the entire display 110 in the first mode MODE1 , the timing controller 140 may control so that each of the scan driver 120 , the data driver 130 , and the light emitting driver 150 operates normally.

[0083] In contrast, to display the second image IMAGE2 only in the first display area DA1 of the display 110, the timing controller 140 may control the scan driver 120, the data driver 130, and the light emitting driver 150 to partially operate. For example, under the control of the timing controller 140, the scan signal SCAN may be provided only to the first through k-1th scan lines SL1 (k is a positive integer) corresponding to the first display area DA1, and the scan signal SCAN may not be provided to the k-th through n-th scan lines SLk (SCAN OFF). Similarly, the light emitting control signal EM may be provided only to the first through k-1th light emitting control lines EL1 (EL1) corresponding to the first display area DA1, and the light emitting control signal EM may not be provided to the k-th through n-th light emitting control lines ELk (EM OFF). In addition, the normal data signal DATA may be provided to the first display area DA1, and the black data signal DATA BLACK (i.e., a data signal corresponding to a black grayscale value) may be provided to the second display area DA2.

[0084] Meanwhile, the first display area DA1 and the second display area DA2 may be fixed, but are not limited thereto. For example, when the display device 100 is configured as a foldable display device, the first display area DA1 and the second display area DA2 may be divided by a folding axis that can be pre-set as the center of the display device 100.

[0085] As another example, when the display device 100 is configured as a general display device, and when the display device 100 displays an image corresponding to a document being edited (in the first display area DA1) and a virtual keyboard (in the second display area DA2), the sizes of the first display area DA1 and the second display area DA2 (or the boundary between the first display area DA1 and the second display area DA2 and the value of k) can be changed.

[0086] In one embodiment, the timing controller 140 may mask at least one of the pulses included in the scan clock signal during a portion of one frame period. Here, one frame period may be a period during which one frame of image is displayed. A portion of the frame period may be a time point when the scan signal SCAN is supplied to the k-th scan line SLk, or may be a period including this time point.

[0087] For example, the scan clock signal may have a first voltage level (e.g., a cut-off voltage level for turning off a switching element or transistor), but may also have a pulse waveform that periodically transitions to a second voltage level (e.g., a turn-on voltage level for turning on a switching element or transistor). The timing controller 140 may skip transitions of the scan clock signal to the second voltage level during a specific period. In other words, the scan clock signal may have periodic pulses at the turn-on voltage level, and the timing controller 140 may mask, remove, or skip at least one pulse of the scan clock signal during a specific period. Therefore, the scan clock signal may have the first voltage level instead of the second voltage level during a specific period.

[0088] In this case, the scan driver 120 may sequentially output a pulse-type scan signal having a second voltage level before a specific period of one frame period, and then may output a scan signal having only a first voltage level during a specific period of the one frame period (also after the specific period). Thus, only pixels in a partial area of ​​the display 110 (i.e., an area corresponding to a period before the partial period of the one frame period) may be selected to update the data signal.

[0089] In one embodiment, the timing controller 140 may shield at least one of the pulses included in the light emitting clock signal during a partial period of one frame period. Here, the partial period may be a time point when the light emitting control signal EM is supplied to the k-th light emitting control line ELk, or may be a period including this time point, and may be the same as or different from a period during which the scan clock signal is shielded. Figure 16 Describe this.

[0090] For example, the light-emitting clock signal may have a second voltage level (e.g., a turn-on voltage level), but may have a pulse waveform that periodically transitions to a first voltage level (e.g., a turn-off voltage level), and the timing controller 140 may skip transitions of the light-emitting clock signal to the first voltage level during a specific period. That is, the light-emitting clock signal may have pulses that periodically have a turn-off voltage level, and the timing controller 140 may mask or remove at least one pulse of the light-emitting clock signal during a specific period. Thus, the light-emitting clock signal may have the second voltage level instead of the first voltage level during a specific period.

[0091] In this case, the light emitting driver 150 may sequentially output a pulse-type light emitting control signal having a first voltage level to a portion of the light emitting control lines EL1 to ELn in a period before a partial period of one frame period, and then may output a light emitting control signal having only a second voltage level in the partial period of one frame period (also after the partial period, for example, to the i-th light emitting control line ELi to the n-th light emitting control line ELn). As will be described later with reference to Figure 3 As described above, when the light emitting control signal having the first voltage level is supplied to the pixel PXL, the pixel PXL may update the data signal stored therein in response to the scan signal. Therefore, only the pixels in a partial area of ​​the display 110 (i.e., the area corresponding to the period before the partial period of the one frame period) may emit light using the updated data signal.

[0092] The timing controller 140 partially shields the scan clock signal so that the scan signal (i.e., the pulse-type scan signal having the second voltage level) is applied to only a portion of the scan lines SL1 to SLn. Similarly, the timing controller 140 partially shields the light-emission clock signal so that the light-emission control signal (i.e., the pulse-type light-emission control signal having the first voltage level) is applied to only a portion of the light-emission control lines EL1 to ELn.

[0093] Therefore, the display device 100 can provide the scan signal to only a part of the scan lines SL1 to SLn without adding a separate circuit configuration or modifying the scan driver 120 and the light-emitting driver 150, can provide the light-emitting control signal to only a part of the light-emitting control lines EL1 to ELn, and can partially drive the display 110, and thereby can reduce power consumption.

[0094] Meanwhile, at least one of the scan driver 120, the data driver 130, the timing controller 140, and the light emitting driver 150 may be formed in the display 110, or configured as an IC, and may be connected to the display 110 through a flexible circuit board. In addition, at least two of the scan driver 120, the data driver 130, the timing controller 140, and the light emitting driver 150 may be configured as one IC.

[0095] Figure 3 The diagram is included in Figure 1 A circuit diagram of an example of a pixel in a display device.

[0096] refer to Figure 3 , the pixel PXL may include first to seventh transistors T1 to T7 , a storage capacitor Cst, and a light emitting element LD.

[0097] Each of the first to seventh transistors T1 to T7 may be configured by a P-type transistor, but is not limited thereto. For example, some or all of the first to seventh transistors T1 to T7 may be configured by an N-type transistor.

[0098] A first electrode of the first transistor T1 (driving transistor) can be connected to a second node N2 and can be connected to a first power line (e.g., a power line transmitting a first power supply voltage VDD) via a fifth transistor T5. A second electrode of the first transistor T1 can be connected to a first node N1 and can be connected to an anode of the light-emitting element LD via a sixth transistor T6. A gate electrode of the first transistor T1 can be connected to a third node N3. The first transistor T1 can control the amount of current flowing from the first power line through the light-emitting element LD to the second power line (i.e., a power line transmitting a second power supply voltage VSS) in response to a voltage at the third node N3.

[0099] The second transistor T2 may be connected between the data line DLj and the second node N2. A gate electrode of the second transistor T2 may be connected to the scan line SLi. The second transistor T2 may be turned on when a scan signal is supplied to the scan line SLi to electrically connect the first electrode of the first transistor T1 to the data line DLj.

[0100] The third transistor T3 may be connected between the first node N1 and the third node N3. A gate electrode of the third transistor T3 may be connected to the scan line SLi. The third transistor T3 may be turned on when a scan signal is supplied to the scan line SLi to electrically connect the first node N1 to the third node N3. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0101] The storage capacitor Cst may be connected between the first power line and the third node N3. The storage capacitor Cst may store a voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0102] The fourth transistor T4 may be connected between the third node N3 and an initialization power line (i.e., a power line that transmits the initialization power voltage Vint). The gate electrode of the fourth transistor T4 may be connected to the previous scan line SLi-1. When the scan signal is supplied to the previous scan line SLi-1, the fourth transistor T4 may be turned on to supply the initialization power voltage Vint to the third node N3. Here, the initialization power voltage Vint may be set to have a voltage level lower than the voltage level of the data signal.

[0103] The fifth transistor T5 may be connected between the first power line and the second node N2. A gate electrode of the fifth transistor T5 may be connected to the light emission control line ELi. The fifth transistor T5 may be turned off when the light emission control signal is supplied to the light emission control line ELi, and may be turned on in other cases.

[0104] The sixth transistor T6 may be connected between the first node N1 and the anode of the light emitting element LD. A gate electrode of the sixth transistor T6 may be connected to the light emission control line ELi. The sixth transistor T6 may be turned off when the light emission control signal is supplied to the light emission control line ELi, and may be turned on in other cases.

[0105] The seventh transistor T7 may be connected between the initialization power supply line and the anode of the light-emitting element LD. The gate electrode of the seventh transistor T7 may be connected to the scan line SLi. The seventh transistor T7 may be turned on when a scan signal is supplied to the scan line SLi to supply the initialization power supply voltage Vint to the anode of the light-emitting element LD.

[0106] The anode of the light-emitting element LD can be connected to the first transistor T1 through the sixth transistor T6, and the cathode of the light-emitting element LD can be connected to the second power supply line. The light-emitting element LD can generate light (e.g., light of a predetermined brightness) in response to the current supplied from the first transistor T1. The first power supply voltage VDD can be set to have a voltage level higher than the second power supply voltage VSS so that current flows through the light-emitting element LD.

[0107] Figure 4 The diagram is included in Figure 1 A circuit diagram of another example of a pixel in a display device.

[0108] refer to Figure 3 and Figure 4 , Figure 4 The pixel PXL_1 is Figure 3 The difference of the PXL pixel is that Figure 4 The pixel PXL_1 includes a first transistor T1' instead of the first transistor T1. In addition to the first transistor T1', Figure 4 The pixel PXL_1 is Figure 3 The pixels PXL are substantially the same or similar, and therefore a redundant description thereof will not be repeated.

[0109] The first electrode of the first transistor T1' can be connected to the second node N2 and can be connected to the first power line through the fifth transistor T5. The second electrode of the first transistor T1' can be connected to the first node N1 and can be connected to the anode of the light emitting element LD through the sixth transistor T6. The gate electrode of the first transistor T1' can be connected to the third node N3. The body (or body electrode) of the first transistor T1' can be connected to the common control line BL. Here, as will be referred to later Figure 6 As described above, the common control line BL may be connected to the data driver 130 (or the timing controller 140), and the first power supply voltage VDD (or alternatively, a voltage corresponding thereto) or the gate-off voltage may be selectively applied to the common control line BL. For example, the gate-off voltage may be a voltage having a voltage level higher than that of the first power supply voltage VDD.

[0110] For example, when the first power supply voltage VDD is applied to the body of the first transistor T1', the first transistor T1' can Figure 3 As another example, when a gate-off voltage is applied to the body of the first transistor T1′, an electric field is formed in the body of the first transistor T1′, thereby reducing the channel of the first transistor T1′, and the first transistor T1′ may be turned off even if a voltage is applied to the gate electrode.

[0111] For reference, refer to Figure 1 and Figure 2The described display 110 may be integrally configured with a first display area DA1 and a second display area DA2, and therefore, the second display area DA2 alone may not be powered off. A reference voltage corresponding to a black grayscale value may be applied to the second display area DA2 of the display 110 (or the pixel PXL_1 located in the second display area DA2) so that the second display area DA2 appears to be turned off. However, when the reference voltage is applied to the second display area DA2, power consumption may occur in the data driver 130. Therefore, the display device 100 according to an embodiment of the present disclosure applies a gate-off voltage to the body of the first transistor T1' located in the second display area DA2, and thus the power consumption of the data driver 130 may be reduced while the image is not displayed in the second display area DA2.

[0112] You can refer to Figure 5 A more specific configuration of the first transistor T1 ′ will be described.

[0113] Figure 5 The diagram is included in Figure 4 A cross-sectional view of an example of a first transistor in a pixel.

[0114] refer to Figure 4 and Figure 5 , the first transistor T1 ′ (or the pixel PXL_1 or the display 110 ) may include a substrate SUB, a buffer layer BUF, insulating layers INS1 , INS2 , INS3 , INS4 , and INS5 , a semiconductor pattern SC, and conductive patterns GAT, BML, BRP1 , and BRP2 .

[0115] The substrate SUB may configure a base member of the pixel PXL_1 (or the display 110). The substrate SUB may be a rigid substrate or a flexible substrate, and its material and physical properties are not particularly limited.

[0116] The buffer layer BUF may be located on the substrate SUB and may reduce or prevent impurities from diffusing into the circuit elements. The buffer layer BUF may be configured as a single layer, but may also be configured as multiple layers (e.g., at least two layers). Depending on the embodiment, the buffer layer BUF may be omitted.

[0117] The insulating layers INS1, INS2, INS3, INS4 and INS5 may be sequentially arranged on the substrate SUB (or the buffer layer BUF), and may include a first insulating layer INS1 (or a first gate insulating film), a second insulating layer INS2 (or a first interlayer insulating film), a third insulating layer INS3 (or a second gate insulating film), a fourth insulating layer INS4 (or a second interlayer insulating film) and a fifth insulating layer INS5 (or a passivation film).

[0118] Each of the insulating layers INS1, INS2, INS3, INS4, and INS5 may be configured as a single layer or multiple layers and may include at least one inorganic insulating material and / or organic insulating material. For example, each of the insulating layers INS1, INS2, INS3, INS4, and INS5 may include a currently known SiN x Various types of organic / inorganic insulating materials. In addition, the configuration material of each of the insulating layers INS1, INS2, INS3, INS4 and INS5 is not specifically limited. In addition, the insulating layers INS1, INS2, INS3, INS4 and INS5 may include insulating materials different from each other, or at least some of the insulating layers INS1, INS2, INS3, INS4 and INS5 may include the same insulating material as each other.

[0119] The conductive patterns GAT, BML, BRP1 and BRP2 may include a gate electrode GAT (or gate electrode pattern), a body electrode BML (or body electrode pattern), a first bridge pattern BRP1 and a second bridge pattern BRP2, and in addition, may further include a common control line BL and a data line DLj.

[0120] Each of the gate electrode GAT, the body electrode BML, the first bridge pattern BRP1, the second bridge pattern BRP2, the common control line BL and the data line DLj may include at least one conductive material, for example, at least one material of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti and / or alloys thereof, and is not limited thereto.

[0121] The body electrode BML may be located on the first insulating layer INS1 .

[0122] The semiconductor pattern SC may be located on the second insulating layer INS2. For example, the semiconductor pattern SC may be located between the second insulating layer INS2 and the third insulating layer INS3. The semiconductor pattern SC may include a first region in contact with the first transistor electrode ET1, a second region in contact with the second transistor electrode ET2, and a channel region between the first and second regions. One of the first and second regions may be a source region, and the other may be a drain region.

[0123] The semiconductor pattern SC may be formed of polysilicon, amorphous silicon, LTPS, etc. The channel region of the semiconductor pattern SC may be an intrinsic semiconductor as a semiconductor pattern not doped with impurities, and the first and second regions of the semiconductor pattern SC may be doped (eg, doped with predetermined impurities), respectively.

[0124] The semiconductor pattern SC may overlap with the body electrode BML, and the body electrode BML may overlap with at least one region of the semiconductor pattern SC.

[0125] The gate electrode GAT may be located on the third insulating layer INS3. For example, the gate electrode GAT may be located between the third insulating layer INS3 and the fourth insulating layer INS4. The gate electrode GAT may overlap at least one region of the semiconductor pattern SC.

[0126] The gate electrode GAT, the semiconductor pattern SC, the body electrode BML, and the first and second transistor electrodes ET1 and ET2 may configure a first transistor T1 ′.

[0127] In addition, the common control line BL may be located on the third insulating layer INS3 and may be connected to the main electrode BML through a contact hole penetrating the second insulating layer INS2 and the third insulating layer INS3. The arrangement position of the common control line BL is not limited thereto, and for example, the common control line BL may be located on the fourth insulating layer INS4.

[0128] The first and second bridge patterns BRP1 and BRP2 and the data line DLj may be located on the fourth insulating layer INS4.

[0129] The first bridge pattern BRP1 may contact one region of the semiconductor pattern SC through a contact hole penetrating the third insulating layer INS3 and the fourth insulating layer INS4, and may configure the second transistor electrode ET2 of the first transistor T1'. The first bridge pattern BRP1 may be connected to the light emitting element LD formed on the fifth insulating layer INS5 (see FIG. Figure 3 ), and can configure reference Figure 3 Described is the first node N1.

[0130] The second bridge pattern BRP2 may make contact with one region of the semiconductor pattern SC through a contact hole penetrating the third and fourth insulating layers INS3 and INS4 and may configure the first transistor electrode ET1 of the first transistor T1 ′.

[0131] As reference Figure 3 As described, the second bridge pattern BRP2 may connect the first electrode of the first transistor T1 to the second electrode of the fifth transistor T5, and may connect the first electrode of the first transistor T1 to the data line DLj through the second transistor T2, and may configure the second node N2.

[0132] However, reference Figure 5 The described structure of the first transistor T1 ′ is an example, and if the first transistor T1 ′ has a structure including the body electrode BML, the structure of the first transistor T1 ′ may be modified in various forms.

[0133] Figure 6 The diagram is included in Figure 1 FIG. 1 is a diagram of an example of a display in a display device.

[0134] refer to Figure 1 and Figure 6 , Figure 6 The display 110_1 shown in FIG. Figure 1 The display 110 shown in FIG. 1 is different in that Figure 6 The display 110_1 further includes a first common control line BL1 and a second common control line BL2. In addition to the first common control line BL1 and the second common control line BL2, the display 110_1 and Figure 1 The illustrated displays 110 are substantially the same or similar, and thus a redundant description thereof will not be repeated.

[0135] The display 110_1 may include a first active area AA1 and a second active area AA2. The first active area AA1 and the second active area AA2 are areas where pixels PXL1 and PXL2 are provided, respectively, and may correspond to reference pixels. Figure 2 The first display area DA1 and the second display area DA2 are described. The first pixel PXL1 may be provided in the first active area AA1, and the second pixel PXL2 may be provided in the second active area PXL2.

[0136] The first active area AA1 and the second active area AA2 may be distinguished from each other with the reference line L_REF as the center and may have substantially the same area as each other. For example, when the display 110_1 is configured as a foldable display panel, the first active area AA1 and the second active area AA2 may be distinguished from each other with the folding axis as the center.

[0137] A first common control line BL1 may be located in the first active area AA1 and connected to the first pixel PXL1. All pixels located in the first active area AA1 may be commonly connected to the first common control line BL1. As described above, a first power supply voltage VDD or a gate-off voltage may be selectively applied to the first common control line BL1 from the data driver 130.

[0138] Similarly, the second common control line BL2 may be located in the second active area AA2 and connected to the second pixel PXL2. All pixels located in the second active area AA2 may be commonly connected to the second common control line BL2.

[0139] Figure 7 It may be used as a reference to describe the control of the display 110_1 through the common control lines BL1 and BL2.

[0140] Figure 7 It is an icon Figure 6 The waveform diagram of the display operation.

[0141] Figure 7 The diagram illustrates a vertical synchronization signal VSYNC, a scan signal applied to the first scan line SL1 to the nth scan line SLn (or a light-emitting control signal applied to the first light-emitting control line EL1 to the nth light-emitting control line ELn), a data signal DATA, and a common control voltage applied to the first common control line BL1 and the second common control line BL2.

[0142] The vertical synchronization signal VSYNC may be included in the control signal CS (see Figure 1 ) and the start of the frame period can be limited.

[0143] When the display device 100 operates in the first mode MODE1, a scan signal of a low-level pulse may be sequentially applied to the first to n-th scan lines SL1 to SLn, and a data signal DATA having a valid value (e.g., a voltage level corresponding to each grayscale value other than a black grayscale value) may be applied to the data lines. When the display 110_1 (or the first and second active areas AA1 and AA2) normally displays the first image IMAGE1, a common control voltage of the first power supply voltage level V1 (e.g., the first power supply voltage VDD) may be applied to the first and second common control lines BL1 and BL2.

[0144] When the display device 100 operates in the second mode MODE2, a scan signal of a low-level pulse may be sequentially applied to the first to k-1th scan lines SL1 to SLk-1 (i.e., applied only to the first active area AA1), a data signal DATA having a valid value may be applied to the data lines corresponding to the first to k-1th scan lines SLk-1, and a data signal DATA having a reference voltage (i.e., a voltage level corresponding to a black grayscale value) may be applied to the data lines corresponding to the k-th to n-th scan lines SLk to SLn. Since only the first active area AA1 displays the second image IMAGE2 and the second active area AA2 displays the third image IMAGE3 (e.g., a black image), a common control voltage of a first power supply voltage level V1 may be applied to the first common control line BL1, and a common control voltage of a second voltage level V2 (e.g., a gate-off voltage) may be applied to the second common control line BL2.

[0145] The display 110_1 may be configured as a foldable display panel, and when the display 110_1 is folded (e.g., in the second mode MODE2), an image may be displayed in a fixed manner only in one area of ​​the display 110_1 (e.g., in the first active area AA1). In this case, Figure 6 The display 110_1 may be applied to the display device 100 and may reduce power consumption of the display device 100 (or the data driver 130 ).

[0146] at the same time, Figure 6 The display 110_1 is shown to include two active areas AA1 and AA2 and two common control lines BL1 and BL2, but the present disclosure is not limited thereto. For example, the display 110_1 may include three or more active areas and three or more common control lines corresponding thereto, respectively.

[0147] Figure 8 The diagram is included in Figure 1 A block diagram of an example of a light emitting driver in a display device.

[0148] refer to Figure 8 The light emitting driver 150 may include stages ST1 to ST4 (or light emitting stages). The stages ST1 to ST4 may be connected to corresponding light emitting control lines EL1 to EL4, respectively, and may be commonly connected to a light emitting clock signal line (i.e., a signal line transmitting light emitting clock signals EM_CLK1 and EM_CLK2). The stages ST1 to ST4 may have substantially the same circuit structure.

[0149] Each of the stages ST1 to ST4 may include a first input terminal IN1 , a second input terminal IN2 , a third input terminal IN3 , and an output terminal OUT.

[0150] The first input terminal IN1 can receive a carry signal. Here, the carry signal can include the light-emitting start signal EM_FLM (or light-emitting start pulse) or the output signal (i.e., light-emitting control signal) of the previous stage (or the previous stage). For example, the first input terminal IN1 of the first stage ST1 can receive the light-emitting start signal EM_FLM, and the first input terminal IN1 of each of the remaining stages ST2 to ST4 can receive the output signal / light-emitting control signal of the previous stage. That is, the light-emitting control signal of the previous stage (e.g., the stage immediately preceding the previous stage) of the corresponding stage can be provided to the corresponding stage as a carry signal.

[0151] The second input terminal IN2 of the first stage ST1 may be connected to the first emission clock signal line to receive the first emission clock signal EM_CLK1 , and the third input terminal IN3 of the first stage ST1 may be connected to the second emission clock signal line to receive the second emission clock signal EM_CLK2 .

[0152] The second input terminal IN2 of the second stage ST2 may be connected to the second emission clock signal line to receive the second emission clock signal EM_CLK2 , and the third input terminal IN3 of the second stage ST2 may be connected to the first emission clock signal line to receive the first emission clock signal EM_CLK1 .

[0153] Similar to the first stage ST1, the second input terminal IN2 of the third stage ST3 may be connected to the first emission clock signal line to receive the first emission clock signal EM_CLK1, and the third input terminal IN3 of the third stage ST3 may be connected to the second emission clock signal line to receive the second emission clock signal EM_CLK2.

[0154] Similar to the second stage ST2 , the second input terminal IN2 of the fourth stage ST4 may be connected to the second emission clock signal line to receive the second emission clock signal EM_CLK2 , and the third input terminal IN3 of the fourth stage ST4 may be connected to the first emission clock signal line to receive the first emission clock signal EM_CLK1 .

[0155] That is, the first and second light-emitting clock signal lines can be alternately connected to the second and third input terminals IN2 and IN3 of each stage, or the first and second light-emitting clock signals EM_CLK1 and EM_CLK2 can be alternately provided to the second and third input terminals IN2 and IN3 of each stage, respectively.

[0156] As will be described later, pulses of the first emission clock signal EM_CLK1 provided through the first emission clock signal line and pulses of the second emission clock signal EM_CLK2 provided through the second emission clock signal line may not overlap with each other in time. At this time, each of the pulses may have a turn-on voltage level.

[0157] Stages ST1 to ST4 may receive a first voltage VGH (or a high voltage level) and a second voltage VGL (or a low voltage level). The first voltage VGH may be set to a turn-off voltage level, and the second voltage VGL may be set to a turn-on voltage level.

[0158] Figure 9 The diagram is included in Figure 8 The circuit diagram of an example of a stage in a light emitting driver. Figure 8 The stages ST1 to ST4 shown in FIG. 1 are substantially identical to one another except for a configuration for receiving the emission clock signals EM_CLK1 and EM_CLK2 , and thus hereinafter, a k-th stage STk (eg, the first stage ST1 ) will be described as representing the stages ST1 to ST4 .

[0159] refer to Figure 8 and Figure 9 , the kth stage STk may include first to tenth switching elements M1 to M10 (or transistors) and first to third capacitors C1 to C3.

[0160] The first switching element M1 may include a first electrode (eg, a first electrode connected to the first power input terminal IN_V1 to which the first voltage VGH is applied), a second electrode connected to the output terminal OUT, and a gate electrode connected to the second control node QB (or QB node).

[0161] The second switching element M2 may include a first electrode connected to the output terminal OUT, a second electrode connected to the second power input terminal IN_V2 to which the second voltage VGL is applied, and a gate electrode connected to the first control node Q (or Q-node).

[0162] The first switching element M1 and the second switching element M2 can configure an output stage and can output the first voltage VGH or the second voltage VGL as the kth light emitting control signal EMk (for example, as the first light emitting control signal EM1) in response to the node voltage of the first control node Q and the node voltage of the second control node QB.

[0163] The third switching element M3 may include a first electrode connected to the first input terminal IN1 , a second electrode connected to the first control node Q, and a gate electrode connected to the second input terminal IN2 .

[0164] The fourth switching element M4 may include a first electrode connected to the third control node SR_QB (or SR_QB node), a second electrode connected to the second input terminal IN2, and a gate electrode connected to the first control node Q. As will be described later, the third control node SR_QB may be connected to the second control node QB via the second capacitor C2 and the ninth switching element M9.

[0165] The fifth switching element M5 may include a first electrode connected to the third control node SR_QB, a second electrode connected to the second power input terminal IN_V2 , and a gate electrode connected to the second input terminal IN2 .

[0166] The third to fifth switching elements M3 to M5 configure an input stage and can control the node voltage of the first control node Q and the node voltage of the third control node SR_QB in response to the k-1th light emitting control signal EMk-1 (for example, in response to the light emitting start signal EM_FLM) applied to the first input terminal IN1 and in response to the first light emitting clock signal EM_CLK1 applied to the second input terminal IN2.

[0167] The sixth switching element M6 and the seventh switching element M7 may be connected in series between the first power input terminal IN_V1 and the first control node Q.

[0168] The sixth switching element M6 may include a first electrode connected to the second electrode of the seventh switching element M7 , a second electrode connected to the first control node Q, and a gate electrode connected to the third input terminal IN3 .

[0169] The seventh switching element M7 may include a first electrode connected to the first power input terminal IN_V1 , a second electrode connected to the first electrode of the sixth switching element M6 , and a gate electrode connected to the third control node SR_QB.

[0170] The first capacitor C1 may be connected between the first control node Q and the third input terminal IN3 .

[0171] The sixth and seventh switching elements M6 and M7 and the first capacitor C1 may maintain the node voltage of the first control node Q based on the second light emitting clock signal EM_CLK2 applied to the third input terminal IN3 and based on the third control node SR_QB.

[0172] The second capacitor C2 may be connected between the second control node QB and the third control node SR_QB.

[0173] The eighth switching element M8 may include a first electrode connected to the first electrode of the ninth switching element M9 , a second electrode connected to the third input terminal IN3 , and a gate electrode connected to the third control node SR_QB.

[0174] The ninth switching element M9 may include a first electrode connected to the second capacitor C2 and to the first electrode of the eighth switching element M8 , a second electrode connected to the second control node QB, and a gate electrode connected to the third input terminal IN3 .

[0175] The third capacitor C3 may be connected between the first power input terminal IN_V1 and the second control node QB.

[0176] The tenth switching element M10 may include a first electrode connected to the first power input terminal IN_V1 , a second electrode connected to the second control node QB, and a gate electrode connected to the first control node Q.

[0177] The eighth to tenth switching elements M8 to M10 and the third capacitor C3 may control the node voltage of the second control node QB based on the node voltage of the third control node SR_QB, the second emission clock signal EM_CLK2 applied to the third input terminal IN3 and the node voltage of the first control node Q.

[0178] at the same time, Figure 9 The first to tenth switching elements M1 to M10 are shown as being configured by P-type transistors, but this embodiment is an example and is not limited thereto. For example, the first to tenth switching elements M1 to M10 may be configured by N-type transistors.

[0179] Figure 10 The diagram is shown in the first mode of operation. Figure 9 The waveform diagram of an example of a signal measured at the level of . Figure 10 In the embodiment, the width of each of the first to tenth periods P1 to P10 may be one horizontal period 1H.

[0180] Figure 9 and Figure 10 The diagram illustrates a light-emission start signal EM_FLM, a first light-emission clock signal EM_CLK1, and a second light-emission clock signal EM_CLK2, node voltages of the first to third control nodes Q, QB, and SR_QB of the first stage ST1, and first to third light-emission control signals EM1 to EM3. Hereinafter, for ease of description, a cut-off voltage level equal to the voltage level of the first voltage VGH is referred to as a high level, and a cut-on voltage level equal to the voltage level of the second voltage VGL is referred to as a low level.

[0181] In the first period P1 , the light emitting start signal EM_FLM may have a low level, and the first light emitting clock signal EM_CLK1 may have a low level pulse.

[0182] In this case, in the first stage ST1, the third switching element M3 may be turned on, the light emitting control signal EM_FLM may be applied to the first control node Q, and the node voltage of the first control node Q may have a low level. Therefore, the second switching element M2 may be turned on and the first light emitting control signal EM1 may have a low level.

[0183] At the same time, the fourth switching element M4 and the fifth switching element M5 may be turned on, the second voltage VGL may be applied to the third control node SR_QB, and the third control node SR_QB may have a low level. The tenth switching element M10 may be turned on in response to the node voltage of the first control node Q, and the second control node QB may have a high level.

[0184] During the second period P2, the second light-emitting clock signal EM_CLK2 may have a low-level pulse. In this case, due to the first capacitor C1, the node voltage of the first control node Q may have a voltage level lower than the low level. According to the node voltage of the first control node Q, the second switching element M2 may maintain a conductive state, and the first light-emitting control signal EM1 (e.g., the output signal EMk) may have a low level.

[0185] In the third period P3 , the light emitting start signal EM_FLM may be transitioned to a high level, and the first light emitting clock signal EM_CLK1 may have a low level pulse.

[0186] In this case, the third switching element M3 may be turned on, the light emission start signal EM_FLM of a high level may be applied to the first control node Q, and the node voltage of the first control node Q may have a high level.

[0187] At the same time, the fifth switching element M5 may be turned on, the second voltage VGL may be applied to the third control node SR_QB, and the third control node SR_QB may have a low level. The eighth switching element M8 may be turned on in response to the node voltage of the third control node SR_QB, and a voltage difference between the high level and the low level may be stored in the second capacitor C2.

[0188] Meanwhile, since the ninth switching element M9 is in the off state, the node voltage of the second control node QB may have a high level and the first switching element M1 may maintain the off state. Therefore, the first light emitting control signal EM1 may have a low level as in the second period P2.

[0189] In the fourth period P4, the second light-emitting clock signal EM_CLK2 may have a low-level pulse. In this case, the ninth switching element M9 may be turned on, and the second light-emitting clock signal EM_CLK2 may be applied to the second control node QB through the eighth switching element M8 and the ninth switching element M9, and the second control node QB may have a low level. At the same time, the node voltage of the third control node SR_QB may be boosted to a voltage level lower than the low level by the second capacitor C2.

[0190] The first switching element M1 may be turned on in response to the node voltage of the second control node QB, and the first light emitting control signal EM1 may have a high level.

[0191] In the fifth period P5 , the first light emitting clock signal EM_CLK1 may have a low-level pulse. However, since the light emitting start signal EM_FLM has a high level, the node voltage of the first control node Q may be maintained at a high level.

[0192] The node voltage of the second control node QB may be maintained at a low level by the third capacitor C3 , and the voltage level of the first light emitting control signal EM1 may be maintained at a high level by the turned-on first switching element M1 .

[0193] The operation of the first stage ST1 in the sixth period P6 is substantially the same as the operation of the first stage ST1 in the fourth period P4 , and thus, the voltage level of the first light emitting control signal EM1 may be maintained at a high level.

[0194] In the seventh period P7 , the light emitting start signal EM_FLM may be transitioned to a low level, and the first light emitting clock signal EM_CLK1 may have a low-level pulse.

[0195] In this case, the third switching element M3 may be turned on, the low-level light emission start signal EM_FLM may be applied to the first control node Q, and the node voltage of the first control node Q may be at a low level. Therefore, the second switching element M2 may be turned on, and the voltage level of the first light emission control signal EM1 may be shifted to a low level.

[0196] The second control node QB may be turned to a high level by the turned-on tenth switching element M10. The first light emitting clock signal EM_CLK1 may be applied to the third control node SR_QB through the turned-on fourth switching element M4, and the third control node SR_QB may have a low level in response to a pulse of the first light emitting clock signal EM_CLK1 and then may be turned to a high level.

[0197] In the eighth period P8, the second light emitting clock signal EM_CLK2 may have a low level pulse. In this case, the node voltage of the first control node Q may be boosted to a voltage level lower than the low level by the first capacitor C1, and the first light emitting control signal EM1 may have a low level.

[0198] The operation of the first stage ST1 in the ninth period P9 may be substantially the same as that in the first period P1, and the operation of the first stage ST1 in the tenth period P10 may be substantially the same as that in the second period P2. Therefore, redundant descriptions thereof will not be repeated.

[0199] As reference Figure 10 As described, the first stage ST1 may shift the light emitting start signal EM_FLM by one horizontal period 1H based on the first and second light emitting clock signals EM_CLK1 and EM_CLK2 and may output the first light emitting control signal EM1 .

[0200] At the same time, similar to the first stage ST1, the second stage ST2 (see Figure 8 ) can shift the first light emitting control signal EM1 and can output the second light emitting control signal EM2 of high level in the fifth period P5 to the eighth period P8. The third stage ST3 (see Figure 8) can shift the second light emitting control signal EM2 and can output a high-level third light emitting control signal EM3 in the sixth to ninth periods P6 to P9.

[0201] Figure 11 The diagram is shown in the second mode of operation. Figure 9 1 is a waveform diagram of an example of a signal measured at the level 1. Figure 11 is with Figure 10 The waveform diagram of the signal corresponding to the signal.

[0202] refer to Figures 9 to 11 , at least one of the pulses included in the second light emitting clock signal EM_CLK2 may be masked in the second mode.

[0203] The operation of the first stage ST1 in the first to third periods P1 to P3 may be compared with the reference Figure 10 The operations of the described first stage ST1 in the first to third periods P1 to P3 are substantially the same, and therefore, redundant descriptions thereof will not be repeated.

[0204] In the fourth period P4, the low-level pulse of the second light-emitting clock signal EM_CLK2 is masked, and thus, the second light-emitting clock signal EM_CLK2 may have a high level. In addition, the first light-emitting clock signal EM_CLK1 may have a high level.

[0205] Therefore, the first stage ST1 may maintain the same state as that in the third period P3 , the node voltage of the second control node QB may have a high level, and the first light emitting control signal EM1 may be maintained at a low level.

[0206] In the fifth period P5 , the first light emitting clock signal EM_CLK1 may have a low-level pulse. However, the light emitting start signal EM_FLM has a high level, and thus, the node voltage of the first control node Q may be maintained at a high level.

[0207] The node voltage of the second control node QB may be maintained at a high level by the third capacitor C3, and the first switching element M1 may maintain a turn-off state. Therefore, the first light emitting control signal EM1 may have a low level as in the fourth period P4.

[0208] The operation of the first stage ST1 in the sixth period P6 is substantially the same as the operation of the first stage ST1 in the fourth period P4 , and thus, the voltage level of the first light emitting control signal EM1 may be maintained at a low level.

[0209] In the seventh period P7 , the light emitting start signal EM_FLM may be transitioned to a low level, and the first light emitting clock signal EM_CLK1 may have a low-level pulse.

[0210] In this case, the third switching element M3 may be turned on, the low-level light emission start signal EM_FLM may be applied to the first control node Q, and the node voltage of the first control node Q may have a low level. Therefore, the second switching element M2 may be turned on, and the voltage level of the first light emission control signal EM1 may be maintained at a low level.

[0211] The second control node QB can be maintained at a high level by the turned-on tenth switching element M10. The first emission clock signal EM_CLK1 can be applied to the third control node SR_QB through the turned-on fourth switching element M4. The third control node SR_QB can have a low level in response to the pulse of the first emission clock signal EM_CLK1 and then can be transitioned to a high level.

[0212] That is, in the seventh period P7, the node voltage of the first control node Q can be initialized or reset to a low level by the pulse of the first light-emitting clock signal EM_CLK1 (i.e., by the pulse of the first light-emitting clock signal EM_CLK1 applied immediately after the second light-emitting clock signal EM_CLK2 is shielded), and the node voltage of the third control node SR_QB can be initialized or reset to a high level.

[0213] The operation of the first stage ST1 in the eighth period P8 to the tenth period P10 is similar to the reference Figure 10 The operations of the described first stage ST1 in the eighth to tenth periods P8 to P10 are substantially the same, and therefore, redundant descriptions thereof will not be repeated.

[0214] As reference Figure 11 As described, in the second mode, the pulses of the second light-emitting clock signal EM_CLK2 are shielded during the periods corresponding to the pulses of the light-emitting start signal EM_FLM (e.g., the fourth period P4 to the sixth period P6), and therefore, the first stage ST1 can only output the low-level first light-emitting control signal EM1.

[0215] When the first light emitting control signal EM1 is shifted to be output, the second stage ST2 (see Figure 8 ) can output only the second light emitting control signal EM2 of low level, and similarly, the third stage ST3 (see Figure 8 ) can only output the third light emitting control signal EM3 of a low level.

[0216] at the same time, Figure 11 It is illustrated that only the second light emitting clock signal EM_CLK2 is shielded in the fourth to sixth periods P4 to P6 , but the present disclosure is not limited thereto.

[0217] Figure 12The diagram is shown in the second mode of operation. Figure 9 A waveform diagram of another example of a signal measured in the stage . Figure 12 is with Figure 11 The waveform diagram of the signal corresponding to the signal.

[0218] refer to Figure 11 and Figure 12 , while at least one of the pulses included in the second light emitting clock signal EM_CLK2 is masked in the second mode, at least one of the pulses included in the first light emitting clock signal EM_CLK1 may also be masked.

[0219] The operation of the first stage ST1 in the first period P1 to the fourth period P4 and the sixth period P6 to the tenth period P10 is similar to the reference period Figure 11 The operations of the described first stage ST1 in the first to fourth periods P1 to P4 and the sixth to tenth periods P6 to P10 are substantially the same, and therefore, redundant descriptions thereof will not be repeated.

[0220] In the fifth period P5 , the low level pulse of the first light emitting clock signal EM_CLK1 is masked, and thus, the first light emitting clock signal EM_CLK1 may have a high level.

[0221] Therefore, the first stage ST1 maintains the same state as the fourth period P4 , the node voltage of the second control node QB may have a high level, and the first light emitting control signal EM1 may be maintained at a low level.

[0222] That is, when all of the first light-emitting clock signal EM_CLK1 and the second light-emitting clock signal EM_CLK2 are shielded in the fourth period P4 to the sixth period P6, the first light-emitting control signal EM1 corresponding to the fourth period P4 and subsequent light-emitting control signals (for example, the second light-emitting control signal EM2, the third light-emitting control signal EM3, etc.) may have only a low level.

[0223] Figure 13 The diagram is shown in the second mode of operation. Figure 9 A waveform diagram of yet another example of a signal measured in the stage. Figure 13 is with Figure 11 The waveform diagram of the signal corresponding to the signal.

[0224] refer to Figure 11 and Figure 13 , after at least one of the pulses included in the second light emitting clock signal EM_CLK2 is masked in the second mode, the first light emitting clock signal EM_CLK1 and the second light emitting clock signal EM_CLK2 may all be masked.

[0225] The operation of the first stage ST1 in the first period P1 to the eighth period P8 is similar to the reference Figure 11 The operations of the described first stage ST1 in the first to eighth periods P1 to P8 are substantially the same, and therefore, redundant descriptions thereof will not be repeated.

[0226] As reference Figure 11 As described, in the seventh period P7, the node voltage of the first control node Q can be initialized or reset to a low level by a pulse of the first light-emitting clock signal EM_CLK1 (i.e., by a pulse of the first light-emitting clock signal EM_CLK1 applied immediately after the second light-emitting clock signal EM_CLK2 is shielded), and the node voltage of the third control node SR_QB can be initialized or reset to a high level.

[0227] In addition, in the eighth period P8, the second light emitting clock signal EM_CLK2 may have a low level pulse, and the node voltage of the first control node Q may be boosted to a level lower than the low level by the first capacitor C1, and the first light emitting control signal EM1 may be completely converted to or maintained at a low level.

[0228] After the first control node Q and the third control node SR_QB are fully initialized (or stabilized), the first light-emitting clock signal EM_CLK1 and the second light-emitting clock signal EM_CLK2 can be shielded until the end of the corresponding frame period or until the end of the second mode MODE2 (or until the start of the first mode MODE1).

[0229] like Figure 13 As shown in FIG, in the ninth period P9, the pulse of the first light-emitting clock signal EM_CLK1 may be shielded, and the first light-emitting clock signal EM_CLK1 may have a high level. In addition, the second light-emitting clock signal EM_CLK2 may have a high level. Therefore, the first stage ST1 may maintain the same state as the eighth period P8, the node voltage of the first control node Q may be maintained at a high level, and the first light-emitting control signal EM1 may be maintained at a low level.

[0230] Similarly, in the tenth period P10, the pulse of the second light-emitting clock signal EM_CLK2 may be shielded, and the first light-emitting clock signal EM_CLK1 and the second light-emitting clock signal EM_CLK2 may have a high level. Therefore, the first stage ST1 may maintain the same state as the ninth period P9, the node voltage of the first control node Q may be maintained at a high level, and the first light-emitting control signal EM1 may be maintained at a low level.

[0231] That is, after the tenth period P10 , when the first and second emission clock signals EM_CLK1 and EM_CLK2 are shielded, the first stage ST1 may continuously maintain the same state as in the eighth period P8 , and the first emission control signal EM1 may be maintained at a low level.

[0232] Meanwhile, the first stage ST1 may not perform a switching operation in response to the light emitting clock signals EM_CLK1 and EM_CLK2 maintained at a high level, i.e., the transistors M1 to M10 in the first stage ST1 may not repeat the on and off states. Therefore, the power consumption of the light emitting driver 150 can be reduced.

[0233] Figure 14 It is shown in the figure Figure 8 FIG. 1 is a waveform diagram of an example of a signal measured in a light emitting driver. Figure 15 It is shown in the figure Figure 8 FIG. 1 is a waveform diagram of another example of a signal measured in a light emitting driver. Figure 14 and Figure 15 The diagram shows signals measured in the light emitting driver 150 operating in the second mode.

[0234] First, refer to Figure 8 、 Figure 10 and Figure 14 , Figure 14 The light-emitting start signal EM_FLM, the first light-emitting clock signal EM_CLK1, the second light-emitting clock signal EM_CLK2, and the first to third light-emitting control signals EM1, EM2, and EM3 are respectively Figure 10 The light emitting start signal EM_FLM, the first and second light emitting clock signals EM_CLK1 and EM_CLK2, and the first to third light emitting control signals EM1, EM2, and EM3 in FIG. 1 are substantially the same or similar, and thus, redundant descriptions thereof will not be repeated.

[0235] In order to block the output of the seventh light emitting control signal EM7 (and subsequent light emitting control signals), the second light emitting clock signal EM_CLK2 may be masked in a first masking period P_EM_MASK1 between the first time point TP1 and the second time point TP2 .

[0236] In this case, the light emitting control signal subsequent to the seventh light emitting control signal EM7 may be changed by the shielded second light emitting clock signal EM_CLK2 .

[0237] The fourth stage ST4 included in the light emitting driver 150 may output the fourth light emitting control signal EM4 by shifting the third light emitting control signal EM3 by one horizontal period 1H.

[0238] At the first time point TP1, with reference Figure 10 The operation of the first stage ST1 in the seventh period P7 is similar to that described above. The node voltage of the first control node Q in the fourth stage ST4 should be transitioned to a low level based on the pulse of the second emission clock signal EM_CLK2. However, the first control node Q in the fourth stage ST4 may not be initialized during the first masking period P_EM_MASK1, and the high-level fourth emission control signal EM4 may be output during the first masking period P_EM_MASK1. After the second time point TP2 when the first masking period P_EM_MASK1 ends, the node voltage of the first control node Q in the fourth stage ST4 may be transitioned to a low level based on the pulse of the second emission clock signal EM_CLK2, and the low-level fourth emission control signal EM4 may be output.

[0239] The first to third light emitting control signals EM1, EM2, and EM3 may respectively have pulse widths PW1, PW2, and PW3 (e.g., four horizontal periods each) corresponding to the reference pulse width PW0 of the light emitting start signal EM_FLM (e.g., four horizontal periods). However, the fourth light emitting control signal EM4 may have a fourth pulse width PW4 (e.g., eight horizontal periods) greater than the reference pulse width PW0 of the light emitting start signal EM_FLM.

[0240] The fifth stage included in the light emitting driver 150 may output the fifth light emitting control signal EM5 by shifting the fourth light emitting control signal EM4 by one horizontal period 1H.

[0241] The node voltage of the first control node Q in the fifth stage may be transitioned to a low level based on the pulse of the first emission clock signal EM_CLK1 in the first masking period P_EM_MASK1. Subsequently, the node voltage of the first control node Q in the fifth stage may be boosted to a voltage level lower than the low level by the second emission clock signal EM_CLK2 after the second time point TP2, and the fifth emission control signal EM5 may be completely transitioned to a low level.

[0242] The fifth pulse width PW5 of the fifth light emitting control signal EM5 may be substantially the same as the third pulse width PW3 of the third light emitting control signal EM3.

[0243] However, if Figure 15As shown in FIG, when the pulse of the first emission clock signal EM_CLK1 is masked in the first masking period P_EM_MASK1, the node voltage of the first control node Q in the fifth stage may not be transitioned to a low level. After the second time point TP2, the node voltage of the first control node Q in the fifth stage may be transitioned to a low level based on the pulse of the second emission clock signal EM_CLK2. In this case, the fifth pulse width PW5' of the fifth emission control signal EM5 may be greater than the third pulse width PW3 of the third emission control signal EM3 and may be approximately six horizontal periods.

[0244] Return Reference Figure 14 , the sixth stage included in the light emitting driver 150 may output the sixth light emitting control signal EM6 by shifting the fifth light emitting control signal EM5 by one horizontal period 1H.

[0245] Similar to the fourth stage ST4, the first control node Q in the sixth stage may not be initialized during the first masking period P_EM_MASK1, and the high-level sixth light-emitting control signal EM6 may be output during the first masking period P_EM_MASK1. After the second time point TP2 when the first masking period P_EM_MASK1 ends, the node voltage of the first control node Q in the sixth stage may be transitioned to a low level based on the pulse of the second light-emitting clock signal EM_CLK2, and the low-level sixth light-emitting control signal EM6 may be output.

[0246] The sixth pulse width PW6 of the sixth light emitting control signal EM6 may be greater than the third pulse width PW3 of the third light emitting control signal EM3 and may be approximately six horizontal periods.

[0247] The seventh light emitting control signal EM7 and subsequent light emitting control signals EM8, EM9 and EM10 may have the same value as the reference signal. Figure 11 The first to third light emitting control signals EM1, EM2, and EM3 are similarly described as being at a low level.

[0248] As reference Figure 14 As described, when the second light-emitting clock signal EM_CLK2 is shielded to skip the light-emitting control signal of a suitable light-emitting control line (for example, the seventh light-emitting control signal EM7), the pulse widths of the light-emitting control signals of one or more previous light-emitting control lines (for example, the fourth pulse width PW4 of the fourth light-emitting control signal EM4 to the sixth pulse width PW6 of the sixth light-emitting control signal EM6) may be changed.

[0249] Therefore, the display device according to this embodiment can adjust the shielding time point of the emission clock signals EM_CLK1 and EM_CLK2 relative to the data signal (and / or the scan signal), or can compensate the data signal (or grayscale value) in response to the emission control signal having a varying pulse width. Therefore, it is possible to reduce or prevent degradation in the display quality of the image displayed on the display 110.

[0250] at the same time, Figure 14 and Figure 15 It is illustrated that the first light emitting clock signal EM_CLK1 and the second light emitting clock signal EM_CLK2 are not masked after the first masking period P_EM_MASK1, but the present disclosure is not limited thereto. Figure 13 Similar to the ninth and tenth periods P9 described above, the first and second emission clock signals EM_CLK1 and EM_CLK2 may be masked during a second masking period P_EM_MASK2 after the third time point TP3. The first masking period P_EM_MASK1 may be less than or equal to the reference pulse width PW0. The period from the second time point TP2 to the third time point TP3 may be greater than or equal to the period of the first and second emission clock signals EM_CLK1 and EM_CLK2. The second masking period P_EM_MASK2 may be greater than the reference pulse width PW0.

[0251] Figure 16 The diagram shows the operation in the second mode. Figure 1 A diagram of an example of a display device. Figure 17 It is shown in the figure Figure 16 A waveform diagram showing an example of a signal measured in a display device.

[0252] First, refer to Figure 2 and Figure 16 , Figure 16 The display device 100 shown in FIG. Figure 2 The display device 100 in FIG. 1 is substantially the same except for the masking time point SCAN MASKING of the scan clock signal and the masking time point EMMASKING of the emission clock signal. Therefore, a redundant description thereof will not be repeated.

[0253] refer to Figure 14 and Figure 17 , Figure 17 The light-emitting start signal EM_FLM, the first light-emitting clock signal EM_CLK1, the second light-emitting clock signal EM_CLK2, and the k-2th light-emitting control signal EMk-2 to the k+4th light-emitting control signal EMk+4 are Figure 14The light emitting start signal EM_FLM, the first and second light emitting clock signals EM_CLK1 and EM_CLK2, and the first to eighth light emitting control signals EM1 to EM8 are substantially the same or similar, and therefore, redundant descriptions thereof will not be repeated.

[0254] With reference Figures 8 to 11 Similar to the light emitting driver 150 described above, the scan driver 120 can be operated by using Figure 17 The scan start signal FLM is shifted (eg, by one horizontal period) by the first scan clock signal SCAN_CLK1 and the second scan clock signal SCAN_CLK2 shown in FIG. 1 , and the scan signals are sequentially supplied to the first to n-th scan lines SL1 to SLn.

[0255] The scan start signal FLM may have a pulse width smaller than the period of the first scan clock signal SCAN_CLK1 and the second scan clock signal SCAN_CLK2 (e.g., a pulse width of one horizontal period), and the scan signal may not overlap with the previous scan signal or the subsequent scan signal. Therefore, even if the first scan clock signal SCAN_CLK1 and the second scan clock signal SCAN_CLK2 are shielded, the pulse width of the scan signal may not be changed.

[0256] like Figure 17 As shown in , the data signal DATA may have a valid value before the reference time point TP0 , and the data signal DATA may have a reference voltage (ie, a voltage level corresponding to a black gray value) after the reference time point TP0 .

[0257] In this case, the timing controller 140 may determine to cut off the supply of the scan signal SCAN in a period after the reference time point TP0 , that is, may determine to cut off the supply of the scan signal SCAN to the kth to nth scan lines SLk to SLn.

[0258] Therefore, the second scan clock signal SCAN_CLK2 may be masked in the scan masking period P_SCAN_MASK including the reference time point TP0. Meanwhile, this is an example, and instead of the second scan clock signal SCAN_CLK2, the first scan clock signal SCAN_CLK1 may be masked after the reference time point TP0.

[0259] At the same time, the emission clock signals EM_CLK1 and / or EM_CLK2 may be masked from a first time point TP1 during a first masking period P_EM_MASK1, where the first time point TP1 is a time point reached after a suitable time has elapsed from the scan masking period P_SCAN_MASK. For example, the pulse of the second emission clock signal EM_CLK2 may be masked from a first time point TP1 during a first masking period P_EM_MASK1 (e.g., three horizontal time periods), where the first time point TP1 is a time point reached after a reference pulse width PW0 of the emission start signal EM_FLM has elapsed from a reference time point TP0 (e.g., four horizontal time periods). The period from the reference time point TP0 to the first time point TP1 may be less than or greater than the reference pulse width PW0.

[0260] In this case, the k+4th light-emitting control signal EMk+4 may have only a low level, the pulse widths PW4 of the k+1th light-emitting control signal EMk+1 to PW6 of the k+3th light-emitting control signal EMk+3 may be changed, and the third pulse width PW3 of the kth light-emitting control signal EMk and the pulse widths of the previous light-emitting control signals EMk-1, EMk-2, etc. may correspond to the reference pulse width PW0.

[0261] However, the k+1th to k+3th light emitting control lines to which the k+1th to k+3th light emitting control signals EMk+1 to EMk+3 are applied may be included in Figure 16 For example, when a black image is displayed in the second display area DA2, brightness variation or degradation of display quality caused by the k+1th to k+3th emission control signals EMk+1 to EMk+3 may not be visually recognized by the user.

[0262] Taking into account the margin, the display device 100 (or the timing controller 140) may shield at least one pulse of the emission clock signals EM_CLK1 and EM_CLK2 at a time point corresponding to the k+x-th emission control line ELk+x, which is x lines later than the k-th emission control line ELk (e.g., x lines after the k-th emission control line ELk). Here, x may be greater than or equal to PW0 / 1H, and, for example, may be similar to the reference pulse width PW0 of the emission start signal EM_FLM.

[0263] Will refer to Figure 18 A masking time point EM MASKING of the emission clock signal that may increase or maximize power consumption reduction of the display device 100 without deteriorating display quality is described in detail.

[0264] Figure 18 The diagram is included in Figure 1 A block diagram of an example of a timing controller in a display device.

[0265] refer to Figure 1 、 Figure 16 and Figure 18 , the timing controller 140 may include an area determination unit / area determiner 1810, a masking time point determination unit / masking time point determiner 1820, and a clock generator 1830. Each of the area determiner 1810, the masking time point determiner 1820, and the clock generator 1830 may be configured as a logic circuit.

[0266] The area determiner 1810 can determine the second display area DA2 in which a static image or a black image is displayed by comparing the current frame data and the previous frame data included in the input image data DATA1. For example, the area determiner 1810 can calculate the difference between the current frame data and the previous frame data, and can determine the area with a difference calculation result less than or equal to a reference value as the second display area DA2. The area determiner 1810 can generate information S_DA2 about the second display area DA2, or generate information L_START (e.g., SLk) about the starting line of the second display area DA2.

[0267] The masking time point determiner 1820 may generate a masking signal MASK_START (or a masking start signal) based on the information S_DA2 (or based on the information about the start line L_START) for the second display area DA2 and may generate a reference pulse width PW0 of the emission start signal EM_FLM.

[0268] The number of emission control lines affected by the masking operation of the emission clock signals EM_CLK1 and EM_CLK2 may be equal to the reference pulse width PW0 of the emission start signal EM_FLM divided by one horizontal period 1H minus 1 (e.g., (PW0 / 1H)−1). For example, when the reference pulse width PW0 is 4, the number of emission control lines affected by the masking operation may be 3. In this case, the masking time point determiner 1820 may generate a masking signal MASK_START so that the emission clock signals EM_CLK1 and EM_CLK2 may be masked at a time point corresponding to "start line + 3 + tolerance of the second display area DA2."

[0269] In one embodiment, the pulse width (or the changed pulse width) of the light emitting control signal applied to each of the light emitting control lines affected by the shielding operation may be calculated.

[0270] refer to Figure 14For example, when only the second light-emitting clock signal EM_CLK2 is shielded, the pulse width of the light-emitting control signal of the first light-emitting control line affected by the shielding operation (e.g., the fourth light-emitting control signal EM4) may be "PW0×2". The pulse width of the light-emitting control signal of the second light-emitting control line affected by the shielding operation (e.g., the fifth light-emitting control signal EM5) may be "PW0". The pulse width of the light-emitting control signal of the third light-emitting control line affected by the shielding operation (e.g., the sixth light-emitting control signal EM6) may be equal to "PW0×3 / 2". In addition, when there are four or more light-emitting control lines affected by the shielding operation, the pulse width of each of the fourth and subsequent light-emitting control lines may be "PW0×3 / 2" in the same manner as the pulse width of the third light-emitting control line.

[0271] At the same time, reference Figure 15 For example, when both the first emission clock signal EM_CLK1 and the second emission clock signal EM_CLK2 are shielded, the pulse width of the emission control signal of the first emission control line affected by the shielding operation (e.g., the fourth emission control signal EM4) may be "PW0×2". The pulse width of the emission control signal of the second emission control line affected by the shielding operation (e.g., the fifth emission control signal EM5) may be "PW0×3 / 2". In addition, the pulse widths of the emission control signals of the second emission control line and subsequent emission control lines affected by the shielding operation (e.g., the sixth emission control signal EM6) may be equal to "PW0×3 / 2".

[0272] The changed pulse width of the light emitting control signal of the light emitting control line affected by the shielding operation may be pre-stored and used for data compensation, which will be referred to later. Figure 19 Provide a description.

[0273] Return Reference Figure 18 , the clock generator 1830 may generate the emission clock signals EM_CLK1 and EM_CLK2 and may mask at least one pulse of the emission clock signals EM_CLK1 and EM_CLK2 based on the masking signal MASK_START. Figure 17 For example, the clock generator 1830 may mask the second light emitting clock signal EM_CLK2 in the first masking period P_EM_MASK1. In addition, the clock generator 1830 may mask the first light emitting clock signal EM_CLK1 and the second light emitting clock signal EM_CLK2 in the second masking period P_EM_MASK2 separated from the first masking period P_EM_MASK1.

[0274] As reference Figure 18As described, by determining the optimal or appropriate shielding time point of the emission clock signals EM_CLK1 and EM_CLK2 based on the reference pulse width PW0 of the emission start signal EM_FLM, the power consumption reduction of the display device 100 can be maximized while reducing or preventing the degradation of display quality.

[0275] Figure 19 The diagram is included in Figure 1 A block diagram of another example of a timing controller in a display device.

[0276] refer to Figure 18 and Figure 19 , Figure 19 The timing controller 140_1 can be used with reference Figure 18 The described timing controller 140 is substantially the same or similar except for the addition of the data compensator 1940. Therefore, a redundant description thereof will not be repeated.

[0277] The masking time point determiner 1820 may also determine the masking time point of the scan clock signal and the masking time point of the light emitting clock signal in the same manner.

[0278] In addition, the masking time point determiner 1820 may determine a compensation period LINE_C in which the pulse width of the light emitting clock signal changes based on the masking signal MASK_START. Here, the compensation period LINE_C may be a period (or time) in which the light emitting control signal of the light emitting control line affected by the masking operation is output.

[0279] The data compensator 1940 can compensate for a portion of the input image data DATA1 (or image data DATA2) corresponding to the compensation period LINE_C based on the changed pulse width PWS of the light-emitting control signal of the light-emitting control line affected by the shielding operation, thereby generating compensated data DATA2_C. For example, the data compensator 1940 can increase the grayscale value in proportion to the changed pulse width PWS. As another example, the brightness reduction rate can be calculated based on the pulse width PWS, and the grayscale value can be compensated based on the brightness reduction rate.

[0280] The compensated data DATA2_C may be provided to the data driver 130 , and the data driver 130 may generate a data signal based on the compensated data DATA2_C.

[0281] As reference Figure 19 As described, the pulse widths of some of the light-emitting clock signals adjacent to the time point when the light-emitting clock signal is shielded can be changed, but by partially compensating for the image data corresponding to the changed pulse widths, the reduction in power consumption can be improved or maximized while preventing quality degradation.

[0282] In some embodiments, the timing controller 140 may periodically switch between the first mode and the second mode to display images on the display 110 at multiple frequencies simultaneously.

[0283] Figure 20 It is an icon Figure 1 A waveform diagram showing the operation of the device.

[0284] refer to Figure 1 and Figure 20 , the data signal DATA may have a valid value throughout the entire first frame FRAME1 (or the first frame period).

[0285] In this case, in the first frame FRAME1, the timing controller 140 can operate in the first mode MODE1 and can generate a light emitting clock signal and a scan clock signal without a shielding operation. Therefore, the light emitting control signal having a high level pulse can be sequentially applied to the first light emitting control line EL1 to the nth light emitting control line ELn.

[0286] The data signal DATA may have a valid value in some periods of the second frame FRAME2 (or the second frame period), and the data signal DATA may have an invalid value in the remaining periods of the second frame FRAME2.

[0287] In this case, in the second frame FRAME2, the timing controller 140 operates in the second mode MODE2, and as shown in FIG. Figure 18 As described, the timing controller 140 can determine the shielding time point of the light-emitting clock signal (and the shielding time point of the scan clock signal), and can partially shield the light-emitting clock signal (and the scan clock signal) at an appropriate time point (or within an appropriate period) of the second frame FRAME2. Therefore, the light-emitting control signal having a high-level pulse can be sequentially applied to the first light-emitting control line EL1 to the k-1th light-emitting control line ELk-1, and only the light-emitting control signal having a low level (i.e., in the form of a direct current) can be applied to the k-th light-emitting control line ELk to the n-th light-emitting control line ELn.

[0288] When the first frame FRAME1 and the second frame FRAME2 are alternately repeated, in the second display area DA2 (see FIG. 1 ) corresponding to the kth to nth light emitting control lines ELk to ELn, Figure 2 ), an image having a driving frequency (e.g., 60 Hz) that is half the driving frequency (e.g., 120 Hz) of the first display area DA1 corresponding to the first to k-1th light-emitting control lines EL1 to ELk-1 can be displayed.

[0289] During the second frame FRAME2 to the p-th frame FRAMEp, when the timing controller 140 operates in the second mode MODE2, images may be displayed in the second display area DA2 at a lower frequency (see Figure 2 For example, when p is 120, an image with a frequency of 1 Hz can be displayed in the second display area DA2 (see Figure 2 )middle.

[0290] At the same time, in order to further reduce power consumption, the display device 100 can generate and output the second display area DA2 (see FIG. Figure 2 ) data signal DATA.

[0291] Figure 21 The diagram is included in Figure 1 A block diagram of an example of a data driver in a display device.

[0292] refer to Figure 21 , the data driver 130 may include a shift register 2110 , a latch 2120 , a decoder 2130 (or a digital-to-analog converter DAC), an output buffer 2140 , a gamma voltage generator 2150 , and a common buffer (or a local buffer) 2160 .

[0293] The shift register 2110 may provide the image data DATA2 received from the timing controller 140 in parallel to the latch 2120. The shift register 2110 may generate a latch clock signal to provide the latch 2120, and the latch clock signal may be used to control the timing when the parallel data is output.

[0294] The latch 2120 may latch or temporarily store data sequentially received from the shift register 2110 and transfer the data to the decoder 2130 .

[0295] The decoder 2130 may convert digital data (ie, grayscale values ​​of parallel data) into analog data signals (or data voltages) using the gamma voltages V_GAMMA.

[0296] The output buffer 2140 may receive a data signal and output the data signal to the data line DLs (ie, reference line DLs). Figure 1 The output buffer 2140 may include a source buffer connected to the data lines DL1 to DLm of the display 110 as described above.

[0297] The output buffer 2140 may alternately or selectively output the data signal and the common voltage provided from the common buffer 2160 in the second mode.

[0298] The gamma voltage generator 2150 may generate gamma voltages V_GAMMA of various voltage levels.

[0299] The gamma voltage generator 2150 may include a gamma buffer that transmits a representative gamma voltage to the resistor string and the tap of the resistor string. The gamma voltage generator 2150 may be a digital gamma voltage generator. In this case, the gamma voltage output from the gamma voltage generator 2150 may be linear.

[0300] The common buffer 2160 may output one gamma voltage provided from the gamma voltage generator 2150 as a common voltage (eg, a data voltage BLACK DATA corresponding to a black grayscale).

[0301] Figure 22 It can be used as a reference for describing the configuration of the output buffer 2140.

[0302] Figure 22 The diagram is included in Figure 21 A circuit diagram of an example of an output buffer in a data driver.

[0303] refer to Figure 22 , the output buffer 2140 may include source buffers AMP1, AMP2, AMP3, and AMP4 and switches SW1 to SW8. The power amplifier AMP_P may represent Figure 21 An example of a common buffer 2160 is shown in .

[0304] The first source buffer AMP1 may be connected to the first output terminal OT1 through the first switch SW1, and for example, the first output terminal OT1 may be connected to the first data line DL1 (see Figure 1 ).

[0305] The second switch SW2 may be connected between the output terminal of the power amplifier AMP_P and the first output terminal OT1 .

[0306] Similarly, the second source buffer AMP2 may be connected to the second output terminal OT2 through the third switch SW3, and for example, the second output terminal OT2 may be connected to the second data line DL2 (see FIG. 2 ). Figure 1 ).

[0307] The fourth switch SW4 may be connected between the output terminal of the power amplifier AMP_P and the second output terminal OT2 .

[0308] The third source buffer AMP3 may be connected to the third output terminal OT3 through the fifth switch SW5 , and the sixth switch SW6 may be connected between the output terminal of the power amplifier AMP_P and the third output terminal OT3 .

[0309] The fourth source buffer AMP4 may be connected to the fourth output terminal OT4 through the seventh switch SW7 , and the eighth switch SW8 may be connected between the output terminal of the power amplifier AMP_P and the fourth output terminal OT4 .

[0310] When the data driver 130 operates in the first mode, the first to seventh switches SW1 , SW3 , SW5 , and SW7 may be turned on, and data signals may be output from the output terminals OT1 to OT4 to the data lines through the source buffers AMP1 to AMP4 .

[0311] When the data driver 130 operates in the second mode, the first switch SW1, the third switch SW3, the fifth switch SW5, and the seventh switch SW7 can be turned on during some periods of the frame, and the data signals can be output from the output terminals OT1 to OT4 to the data lines through the source buffers AMP1 to AMP4. During the remaining periods of the frame, the second switch SW2, the fourth switch SW4, the sixth switch SW6, and the eighth switch SW8 can be turned on, and the common voltage can be output through the power amplifier AMP_P. In this case, the bias current supplied to the source buffers AMP1 to AMP4 can be cut off, and the power consumption caused by the operation of the source buffers AMP1 to AMP4 can be reduced.

[0312] Although the technical concept of the present disclosure has been described in detail according to the above embodiments, it should be noted that the embodiments are for descriptive purposes rather than for limiting purposes. In addition, those skilled in the art of the present disclosure will understand that various modified examples can be made within the scope of the technical concept of the present disclosure.

[0313] The scope of the present disclosure is not limited to the contents described in the detailed description, but should be defined by the claims. In addition, it should be interpreted that all changes or modification examples derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present disclosure.

Claims

1. A display device, comprising: A display comprising scan lines, data lines, light-emitting control lines, and pixels connected to the scan lines, the data lines, and the light-emitting control lines; a scan driver configured to sequentially provide scan signals to the scan lines; a data driver configured to provide a data signal to the data line; a light emitting driver configured to provide a light emitting control signal to the light emitting control line based on a light emitting clock signal having pulses; as well as a timing controller configured to provide the light-emitting clock signal to the light-emitting driver, output the pulses of the light-emitting clock signal during a first frame in a first mode and during a first period of a second frame in a second mode, and mask at least one of the pulses during a second period of the second frame in the second mode that is subsequent to the first period, In which, the timing controller periodically performs mode switching between the first mode and the second mode, so that the first image displayed on the first area of ​​the display corresponding to the first time period of the second frame and the second image displayed on the second area of ​​the display corresponding to the second time period of the second frame have different refresh rates.

2. The display device according to claim 1, wherein The light emitting driver is configured to sequentially provide the light emitting control signals to the light emitting control lines in the first mode, and is configured not to provide any of the light emitting control signals to the light emitting control line corresponding to the at least one pulse among the light emitting control lines in the second mode.

3. The display device according to claim 2, wherein The first period is less than or equal to a pulse width of each of the light emitting control signals.

4. The display device according to claim 3, wherein The second period is greater than or equal to a period of the light-emitting clock signal.

5. The display device according to claim 1, wherein The light-emitting clock signal includes a first light-emitting clock signal and a second light-emitting clock signal obtained by delaying the phase of the first light-emitting clock signal by half a cycle, and The timing controller is configured to partially shield one of the first light-emitting clock signal and the second light-emitting clock signal in the second mode. The display device according to claim 5 , wherein: In the second period, the first light emitting clock signal has at least one pulse, and the second light emitting clock signal has at least one pulse.

7. The display device according to claim 5, wherein The timing controller is configured to partially shield the other of the first light emitting clock signal and the second light emitting clock signal.

8. The display device according to claim 5, wherein The frame further includes a third time period after the second time period, wherein the timing controller is configured to shield the first light emitting clock signal and the second light emitting clock signal during the third period in the second mode, and The third period is greater than a pulse width of each of the light emitting control signals.

9. The display device according to claim 1, wherein The scan driver is configured to generate the scan signal based on a scan clock signal, and The timing controller is configured to provide the scan clock signal to the scan driver and mask one pulse of the scan clock signal in the second mode.

10. The display device according to claim 9, wherein The data driver is configured to output a data voltage corresponding to a black grayscale at a first time point when the one pulse of the scan clock signal is shielded.

11. The display device according to claim 9, wherein A second time point at which the timing controller shields the at least one pulse of the light-emitting clock signal is later than a first time point at which the timing controller shields the one pulse of the scan clock signal.

12. The display device according to claim 11, wherein A difference between the first time point and the second time point is less than or equal to a pulse width of each of the light emitting control signals.

13. The display device according to claim 11, wherein A difference between the first time point and the second time point is greater than a pulse width of each of the light emitting control signals.

14. The display device according to claim 1, wherein The timing controller includes: a region determiner for determining the first region of the display by comparing a current frame with a previous frame; a masking time point determiner, configured to generate a masking signal based on the first area; and A clock generator is configured to generate the light emitting clock signal and to mask the at least one pulse of the light emitting clock signal based on the masking signal.

15. The display device according to claim 14, wherein The timing controller further includes a data compensator for generating image data by compensating the input image data, wherein the data driver is configured to generate the data signal based on the image data, wherein the masking time point determiner is configured to determine a compensation period during which a pulse width of at least one of the light emitting control signals is changed based on the masking signal, and The data compensator is configured to compensate a portion of the image data corresponding to the compensation period based on the pulse width.

16. The display device according to claim 1, wherein Each of the pixels comprises: Light-emitting element; a first transistor including a first electrode connected to a first power source, a second electrode connected to a first node, a gate electrode connected to a second node, and a body to which a common control voltage is applied; a second transistor configured to transmit a corresponding data signal among the data signals to the second node in response to a scan signal among the scan signals; and A third transistor is connected to the first node and the light emitting element.

17. The display device according to claim 16, wherein The common control voltage having a first voltage level is applied to the pixel in the first mode, and The common control voltage having a second voltage level different from the first voltage level is applied to a portion of the pixels in the second mode.

18. The display device according to claim 16, wherein The display includes a first pixel region and a second pixel region separated from each other, wherein each of the first pixels provided in the first pixel area among the pixels is connected to a first common control line to receive the common control voltage, and Each of the second pixels provided in the second pixel area among the pixels is connected to a second common control line to receive the common control voltage.

19. The display device according to claim 1, wherein The data driver includes: a digital-to-analog converter configured to generate the data signal based on the gamma voltage; a common buffer configured to output one of the gamma voltages as a reference voltage; and The output buffer is configured to alternately output the data signal and the reference voltage in the second mode.

Images