Display device

Abstract

A display device is provided. The display device includes a plurality of pixels arranged in a display area having a non-quadrilateral shape and a plurality of driving circuits arranged in a peripheral area outside the display area and connected to the plurality of pixels, wherein a plurality of sub-driving circuits included in each of the plurality of driving circuits are distributed in lines in the peripheral area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0092035, filed on July 29, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device. Background Art

[0004] With the rapid development of the display field for visually expressing different electrical signal information, various display devices with excellent characteristics such as light weight, thinness and low power consumption have been promoted. The display device may include a plurality of pixels arranged in a display area and a driving circuit arranged around the display area to drive the pixels. Summary of the invention

[0005] One or more embodiments include a display device that can reduce a dead zone and increase an area of ​​a display region.

[0006] However, aspects and features of the embodiments of the present disclosure are not limited to the above aspects and features, and other aspects and features not mentioned herein will be clearly understood by those of ordinary skill in the art from the description of the present disclosure.

[0007] Additional aspects and features of the embodiments will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed embodiments.

[0008] According to one or more embodiments, a display device may include a plurality of pixels, a first driving circuit, a second driving circuit, and a third driving circuit, wherein the plurality of pixels are arranged in a display area having a non-quadrilateral shape, the first driving circuit includes a plurality of first sub-driving circuits, each of the plurality of first sub-driving circuits outputs a first signal to the plurality of pixels, the second driving circuit includes a plurality of second sub-driving circuits, each of the plurality of second sub-driving circuits outputs a second signal to the plurality of pixels, and the third driving circuit includes a plurality of third sub-driving circuits, each of the plurality of third sub-driving circuits outputs a third signal to the plurality of pixels. A peripheral area outside the display area may include a first peripheral area and a second peripheral area, the first peripheral area and the second peripheral area are symmetrical to each other with respect to the display area, and the display area is between the first peripheral area and the second peripheral area. The plurality of first sub-driving circuits and the plurality of second sub-driving circuits may be alternately arranged in lines in the first peripheral area. The plurality of third sub-driving circuits may be arranged in lines in the second peripheral area. The sum of the size of the area where one of the plurality of first sub-driving circuits is arranged and the size of the area where one of the plurality of second sub-driving circuits is arranged may be equal to the size of the area where one of the plurality of third sub-driving circuits is arranged.

[0009] Each of the plurality of pixels may include a first thin film transistor, a second thin film transistor, and a third thin film transistor, each of the first thin film transistor and the second thin film transistor includes a silicon semiconductor, and the third thin film transistor includes an oxide semiconductor.

[0010] A plurality of first sub-driving circuits may be connected to a first signal line connected to a gate electrode of a first thin film transistor and extending in a first direction. A plurality of second sub-driving circuits may be connected to a second signal line connected to a gate electrode of a second thin film transistor and extending in the first direction. A plurality of third sub-driving circuits may be connected to a third signal line connected to a gate electrode of a third thin film transistor and extending in the first direction.

[0011] Each of the plurality of pixels may be connected to a fourth signal line extending in a second direction intersecting the first direction. The display device may further include a fourth drive circuit and a fifth drive circuit, wherein the fourth drive circuit includes a plurality of fourth sub-drive circuits outputting a fourth signal to one end of the fourth signal line, and the fifth drive circuit includes a plurality of fifth sub-drive circuits outputting a fifth signal to the other end of the fourth signal line. The plurality of fourth sub-drive circuits and the plurality of fifth sub-drive circuits may be distributed in the first peripheral region and the second peripheral region.

[0012] The plurality of fourth sub driving circuits and the plurality of fifth sub driving circuits may be distributed between the plurality of first sub driving circuits, the plurality of second sub driving circuits, and the plurality of third sub driving circuits.

[0013] A plurality of fourth sub driving circuits and a plurality of fifth sub driving circuits may be arranged between the plurality of pairs of the first sub driving circuits and the second sub driving circuits.

[0014] The display device may further include a plurality of output lines, wherein the plurality of output lines are arranged in the peripheral area and connect the first to fourth signal lines to the plurality of first to fifth sub driving circuits.

[0015] Each of the plurality of output lines may include a portion extending in a direction toward a center of the display area.

[0016] The peripheral area may have a shape corresponding to a shape of an edge of the display area.

[0017] The peripheral area may include an area having a shape corresponding to the shape of the edge of the display area and an area having a shape different from the shape of the edge of the display area.

[0018] A width of a region of the peripheral region having a shape different from a shape of the edge of the display region may be smaller than a width of a region of the peripheral region having a shape corresponding to a shape of the edge of the display region.

[0019] According to one or more embodiments, the display device may include a plurality of signal lines, wherein the plurality of signal lines extend in a first direction and are arranged in a display area having a non-quadrilateral shape. A plurality of drive circuits may be arranged in a peripheral area outside the display area and output signals to the plurality of signal lines. A plurality of output lines may be arranged in the peripheral area and connect the plurality of drive circuits to the plurality of signal lines. A plurality of sub-drive circuits included in each of the plurality of drive circuits may be arranged in lines in the peripheral area. Each of the plurality of output lines may include a portion extending in a direction toward the center of the display area.

[0020] The plurality of signal lines may include a plurality of first signal lines, a plurality of second signal lines, and a plurality of third signal lines. The plurality of sub-drive circuits may include a plurality of first sub-drive circuits that output first signals to the plurality of first signal lines, a plurality of second sub-drive circuits that output second signals to the plurality of second signal lines, and a plurality of third sub-drive circuits that output third signals to the plurality of third signal lines. The peripheral area may include a first peripheral area and a second peripheral area, the first peripheral area and the second peripheral area being symmetrical to each other relative to the display area, the display area being between the first peripheral area and the second peripheral area. The plurality of first sub-drive circuits and the plurality of second sub-drive circuits may be arranged alternately in lines in the first peripheral area. The plurality of third sub-drive circuits may be arranged in lines in the second peripheral area. The sum of the size of the area where one of the plurality of first sub-drive circuits is arranged and the size of the area where one of the plurality of second sub-drive circuits is arranged may be equal to the size of the area where one of the plurality of third sub-drive circuits is arranged.

[0021] The plurality of signal lines may further include a plurality of fourth signal lines extending in a second direction intersecting the first direction and arranged in the display area. The plurality of sub-driving circuits may further include a plurality of fourth sub-driving circuits outputting a fourth signal to an end of the fourth signal line and a plurality of fifth sub-driving circuits outputting a fifth signal to the other end of the fourth signal line. The plurality of fourth sub-driving circuits and the plurality of fifth sub-driving circuits may be distributed in the first peripheral area and the second peripheral area.

[0022] The plurality of fourth sub driving circuits and the plurality of fifth sub driving circuits may be distributed between the plurality of first sub driving circuits, the plurality of second sub driving circuits, and the plurality of third sub driving circuits.

[0023] A plurality of fourth sub driving circuits and a plurality of fifth sub driving circuits may be arranged between the plurality of pairs of the first sub driving circuits and the second sub driving circuits.

[0024] The peripheral area may have a shape corresponding to a shape of an edge of the display area.

[0025] The peripheral area may include an area having a shape corresponding to the shape of the edge of the display area and an area having a shape different from the shape of the edge of the display area.

[0026] A width of a region of the peripheral region having a shape different from a shape of the edge of the display region may be smaller than a width of a region of the peripheral region having a shape corresponding to a shape of the edge of the display region.

[0027] A plurality of pixels connected to a plurality of signal lines may be arranged in the display area. Each of the plurality of pixels may include a first thin film transistor, a second thin film transistor, and a third thin film transistor, each of the first and second thin film transistors includes a silicon semiconductor, and the third thin film transistor includes an oxide semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, together with the specification, illustrate embodiments of the subject matter of the present disclosure, and together with the description serve to explain the principles of the embodiments of the subject matter of the present disclosure, wherein

[0029] Figure 1 is a configuration diagram of a display device according to an embodiment;

[0030] Figure 2 yes Figure 1 A view of a display panel of a display device shown in ;

[0031] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment;

[0032] Figure 4A and Figure 4B is a cross-sectional view of a portion of a display device according to an embodiment;

[0033] Figure 5 is a view of a first scan driving circuit and an emission control circuit according to an embodiment;

[0034] Figure 6 is a view of a second scan driving circuit according to an embodiment;

[0035] Figure 7 yes Figure 2 A plan view of an example of area A1;

[0036] Figure 8 yes Figure 2 A plan view of an example of area A2;

[0037] Fig. 9 is a view showing the size of a driving circuit according to an embodiment;

[0038] Fig.10 is a configuration diagram of a display device according to another embodiment;

[0039] Fig.11 yes Fig.10 A view of a display panel of a display device shown in ;

[0040] Fig. 12A and Fig. 12B is a diagram of a data distribution circuit according to an embodiment;

[0041] Fig.13 is a diagram of a test circuit according to an embodiment;

[0042] Figures 14 to 17 They are Fig.11 A plan view of an example of areas B1 to B4;

[0043] Fig.18 is a view of an arrangement of output lines according to an embodiment;

[0044] Fig.19 is an exemplary view of an arrangement of output lines according to an embodiment; and

[0045] Figure 20 to Figure 22 is a view of a display panel of a display device according to another embodiment. DETAILED DESCRIPTION

[0046] Now will refer to embodiment in more detail, and the example of embodiment is shown in the accompanying drawings, wherein similar reference numerals always indicate similar elements. In this regard, the present embodiment may have different forms, and should not be construed as being limited to the description set forth herein. Accordingly, the embodiments are described below only by reference to the accompanying drawings to explain the various aspects of this description. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout the disclosure, the statement "at least one of a, b and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or its variants.

[0047] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another component.

[0048] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0049] It will be further understood that the terms “comprises,” “comprising,” “includes,” and “including” as used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0050] It will be understood that when a layer, region or component is referred to as being “on” another layer, region or component, it can be directly or indirectly on the other layer, region or component. For example, intervening layers, regions or components may be present.

[0051] As used herein, the term "use" may be considered synonymous with the term "utilize."

[0052] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0053] In the present specification, "A and / or B" means A or B, or A and B. In the present specification, "at least one of A and B" means A or B, or A and B.

[0054] As used herein, a wiring “extending in the first direction or the second direction” is intended to mean that the wiring may extend not only in a straight line but also in a zigzag or curved line in the first direction or the second direction.

[0055] As used herein, the term "in a plan view" means "observing an object from above", and the term "in a cross-sectional view" means "observing a vertical cross-section of an object from the side". As used herein, "overlap" includes "overlap in a plan view" and "overlap in a cross-sectional view".

[0056] Hereinafter, embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. In the accompanying drawings, like reference numerals are assigned to like or corresponding elements.

[0057] Figure 1 1 is a diagram showing the configuration of the display device 10 according to the embodiment. Figure 2 yes Figure 1 FIG. 1 is a view of a display panel 110 of a display device 10 shown in FIG.

[0058] Reference Figure 1 and Figure 2 According to an embodiment, the display device 10 may include a display panel 110, and the display panel 110 may include a substrate 100. The substrate 100 may include a display area DA and a peripheral area PA as a non-display area outside the display area DA.

[0059] The substrate 100 may have a non-quadrilateral shape. The non-quadrilateral shape may be, for example, a circle, an ellipse, a polygon whose part is a circle, or a polygon other than a quadrilateral.

[0060] The display area DA may have a shape corresponding to the shape of the substrate 100 . Figure 2An example in which the substrate 100 has a circular shape and the display area DA has a circular shape corresponding to the shape of the substrate 100 is shown, but the present disclosure is not limited thereto. The display area DA may be divided into four areas surrounding the center O of the display area DA. The display area DA may include a first display area DA1 at the upper left, a second display area DA2 at the lower left, a third display area DA3 at the upper right, and a fourth display area DA4 at the lower right. The peripheral area PA may surround the display area DA and have a shape corresponding to the shape of the edge of the display area DA. The peripheral area PA may include a first peripheral area PA1, a second peripheral area PA2, a third peripheral area PA3, and a fourth peripheral area PA4, wherein the first peripheral area PA1 is the periphery of the edge of the first display area DA1, the second peripheral area PA2 is the periphery of the edge of the second display area DA2, the third peripheral area is the periphery of the edge of the third display area DA3, and the fourth peripheral area PA4 is the periphery of the edge of the fourth display area DA4. With the display area DA interposed therebetween, the first peripheral area PA1 and the second peripheral area PA2 may be symmetrical with the third peripheral area PA3 and the fourth peripheral area PA4, respectively. The first and third peripheral areas PA1 and PA3 may minimize or reduce the dead zone, and the second and fourth peripheral areas PA2 and PA4 may minimize or reduce the dead zone.

[0061] A plurality of pixels PX and signal lines may be located in the display area DA, and the signal lines may apply electrical signals to the plurality of pixels PX. The plurality of pixels PX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3, the first pixel PX1 emitting light of a first color, the second pixel PX2 emitting light of a second color, and the third pixel PX3 emitting light of a third color. Figure 2 As shown in FIG. 1 , the unit pixels UP including the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be repeatedly arranged in the first direction D1 and the second direction D2 in the display area DA. The plurality of unit pixels UP may be arranged in a shape corresponding to the display area DA. For example, the row arrangement and column arrangement of the plurality of unit pixels UP arranged along the edge of the display area DA may generate a step difference.

[0062] The plurality of signal lines may include a plurality of data lines DL, a plurality of first scan lines SL1, a plurality of second scan lines SL2, a plurality of third scan lines SL3, a plurality of fourth scan lines SL4, and a plurality of emission control lines EL, and the plurality of signal lines may apply an electrical signal to each of the plurality of pixels PX. The plurality of data lines DL may each extend in the first direction D1. The plurality of first to fourth scan lines SL1 to SL4 and the plurality of emission control lines EL may each extend in the second direction D2.

[0063] Each of the multiple pixels PX can be connected to a corresponding first scan line SL1 among a plurality of first scan lines SL1, a corresponding second scan line SL2 among a plurality of second scan lines SL2, a corresponding third scan line SL3 among a plurality of third scan lines SL3, a corresponding fourth scan line SL4 among a plurality of fourth scan lines SL4, a corresponding emission control line EL among a plurality of emission control lines EL, and a corresponding data line DL among a plurality of data lines DL.

[0064] The peripheral area PA may be an area where pixels PX are not arranged and a driving circuit may be located, and the driving circuit supplies a signal for driving the pixels PX. The driving circuit may include a first scan driving circuit 120, a second scan driving circuit 130, an emission control circuit 140, and a data driving circuit 150. The first scan driving circuit 120 may be connected to the first scan line SL1 and the second scan line SL2, and may transmit a first scan signal GP1 (see Figure 3 ) is output to the first scan line SL1 and the second scan signal GP2 (see Figure 3 ) is output to the second scan line SL2. The second scan driving circuit 130 may be connected to the third scan line SL3 and the fourth scan line SL4, and may output the third scan signal GN1 (see Figure 3 ) is output to the third scan line SL3 and the fourth scan signal GN2 (see Figure 3 ) is output to the fourth scan line SL4. The emission control circuit 140 may be connected to the emission control line EL and may output the emission control signal EM (see Figure 3 ) is output to the emission control line EL. The data driving circuit 150 may be connected to the data line DL and may output the data signal DATA (see Figure 3 ) is output to the data line DL.

[0065] The first scan driving circuit 120, the second scan driving circuit 130 and the emission control circuit 140 may be arranged in the peripheral area PA along the edge of the display area DA (e.g., the periphery of the display area DA). For example, the first scan driving circuit 120 and the emission control circuit 140 may be arranged in the first peripheral area PA1 and the second peripheral area PA2. The plurality of sub-driving circuits SC included in the first scan driving circuit 120 and the plurality of sub-driving circuits SC included in the emission control circuit 140 may be arranged in line in the first peripheral area PA1 and the second peripheral area PA2. The second scan driving circuit 130 may be arranged in the third peripheral area PA3 and the fourth peripheral area PA4. The plurality of sub-driving circuits SC included in the second scan driving circuit 130 may be arranged in line in the third peripheral area PA3 and the fourth peripheral area PA4. Because the plurality of sub-driving circuits SC are arranged in line in the first peripheral area PA1 to the fourth peripheral area PA4, the dead zone may be reduced. Figure 2In the embodiment, with the display area DA interposed therebetween, the portions of the peripheral area PA facing each other may be symmetrical to each other. In another embodiment, with the display area DA interposed therebetween, the portions of the peripheral area PA facing each other may not be symmetrical to each other. For example, a peripheral area where an input sensing driver (such as a touch driver) is arranged may not be symmetrical to another peripheral area facing the peripheral area. The shape of a portion of the peripheral area may be different from the shape of another portion of the peripheral area depending on the position where the input sensing driver is arranged.

[0066] The data driving circuit 150 may be arranged on the film 103 in a chip on film (COF) method, and the film 103 is electrically connected to pads arranged in the peripheral area PA of the substrate 100. Figure 2 The film 103 connected to the circular substrate 100 is shown, but the embodiments of the present disclosure are not limited thereto. For example, in another embodiment, the protrusion may extend and protrude from one side of the substrate 100, and the data driving circuit 150 may be arranged on the film 103 electrically connected to the pad arranged on the protrusion. In one embodiment, the protrusion may be included in the peripheral area PA and may include a bending area. In another embodiment, the data driving circuit 150 may be directly arranged on a portion of the substrate 100 in a chip on glass (COG) or chip on plastic (COP) method, and the portion of the substrate 100 extends and protrudes from the substrate 100.

[0067] Figure 3 is an equivalent circuit diagram of a pixel PX according to an embodiment.

[0068] Reference Figure 3 In one embodiment, the pixel PX may include a plurality of first transistors T1, second transistors T2, third transistors T3, fourth transistors T4, fifth transistors T5, sixth transistors T6, and seventh transistors T7, a first capacitor Cst, a second capacitor Cbt, an organic light emitting diode OLED as a display element, and a plurality of signal lines SL1, SL2, SL3, SL4, EL, and DL, an initialization voltage line VIL, and a power supply voltage line PL connected thereto. In another embodiment, at least one of the plurality of signal lines SL1, SL2, SL3, SL4, EL, and DL, the initialization voltage line VIL, and / or the power supply voltage line PL may be shared by pixels adjacent to (e.g., adjacent to) each other. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be implemented as thin film transistors. Figure 3It is shown that the third transistor T3 and the fourth transistor T4 among the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be n-channel metal oxide semiconductor (NMOS) field effect transistors, and the remaining transistors may be p-channel metal oxide semiconductor (PMOS) field effect transistors.

[0069] The plurality of signal lines SL1, SL2, SL3, SL4, EL, and DL may include a plurality of data lines DL, a plurality of first scan lines SL1, a plurality of second scan lines SL2, a plurality of third scan lines SL3, a plurality of fourth scan lines SL4, and a plurality of emission control lines EL. The second scan line SL2 may be connected to the first scan line SL1 and may transmit a first scan signal GP1 and a second scan signal GP2.

[0070] The power voltage line PL may transmit the first power voltage ELVDD to the first transistor T1 , and the initialization voltage line VIL may transmit the initialization voltage Vint to the pixel PX, the initialization voltage Vint initializing the first transistor T1 and the organic light emitting diode OLED.

[0071] The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the emission control line EL, and the initialization voltage line VIL may extend in the second direction D2 and be spaced apart from each other on each row. The data line DL and the power supply voltage line PL may extend in the first direction D1 and be spaced apart from each other on each column.

[0072] The first transistor T1 may be connected to the power supply voltage line PL through the fifth transistor T5, and may be electrically connected to the organic light emitting diode OLED through the sixth transistor T6. The first transistor T1 may function as a driving transistor, receive the data signal DATA, and drive the driving current I according to the switching operation of the second transistor T2. OLED Supplied to the organic light emitting diode OLED.

[0073] The second transistor T2 may be connected to the first scan line SL1 and the data line DL, and may be connected to the power supply voltage line PL through the fifth transistor T5. The second transistor T2 may be turned on in response to the first scan signal GP1 transmitted through the first scan line SL1, and may perform a switching operation of transmitting the data signal DATA, which is transmitted to the node N1 through the data line DL.

[0074] The third transistor T3 may be connected to the fourth scan line SL4 and may be connected to the organic light emitting diode OLED through the sixth transistor T6. The third transistor T3 may be turned on in response to the fourth scan signal GN2 transmitted through the fourth scan line SL4 and may diode-connect the first transistor T1.

[0075] The fourth transistor T4 can be connected to the third scan line SL3 and the initialization voltage line VIL, can be turned on in response to the third scan signal GN1 transmitted through the third scan line SL3, and can transmit the initialization voltage Vint from the initialization voltage line VIL to the gate electrode of the first transistor T1, thereby initializing the voltage of the gate electrode of the first transistor T1.

[0076] The fifth transistor T5 and the sixth transistor T6 may be connected to the emission control line EL, may be turned on simultaneously (eg, synchronously) in response to the emission control signal EM transmitted through the emission control line EL, and may constitute a current path so that the driving current I OLED The power supply voltage flows from the power supply line PL through the organic light emitting diode OLED.

[0077] The seventh transistor T7 may be connected to the second scan line SL2 and the initialization voltage line VIL, may be turned on in response to the second scan signal GP2 transmitted through the second scan line SL2, and may transmit the initialization voltage Vint from the initialization voltage line VIL to the organic light emitting diode OLED, thereby initializing the organic light emitting diode OLED. In some embodiments, the seventh transistor T7 may be omitted.

[0078] The first capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 may be connected to the gate electrode of the first transistor T1, and the second electrode CE2 may be connected to the power supply voltage line PL. The first capacitor Cst may store and maintain a voltage corresponding to a difference between the power supply voltage line PL and two opposite ends of the gate electrode of the first transistor T1, thereby maintaining a voltage applied to the gate electrode of the first transistor T1.

[0079] The second capacitor Cbt may include a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 may be connected to the first scan line SL1 and the gate electrode of the second transistor T2. The fourth electrode CE4 may be connected to the gate electrode of the first transistor T1 and the first electrode CE1 of the first capacitor Cst. The second capacitor Cbt may be a boost capacitor. When the first scan signal GP1 of the first scan line SL1 is a voltage that turns off the second transistor T2, the second capacitor Cbt may increase the voltage of the node N2 and reduce the voltage (black voltage) for displaying black.

[0080] The organic light emitting diode OLED may include a pixel electrode and an opposite electrode. The opposite electrode may receive a second power supply voltage ELVSS. The organic light emitting diode OLED may receive a driving current I from the first transistor T1. OLED And emits light to display images.

[0081] The operation of each pixel PX according to the embodiment is described below.

[0082] During the initialization period, when the third scan signal GN1 is supplied through the third scan line SL3 , the fourth transistor T4 may be turned on in response to the third scan signal GN1 , and the first transistor T1 may be initialized by the initialization voltage Vint supplied from the initialization voltage line VIL.

[0083] During the data programming period, when the first scan signal GP1, the second scan signal GP2 and the fourth scan signal GN2 are supplied through the first scan line SL1, the second scan line SL2 and the fourth scan line SL4, respectively, the second transistor T2, the seventh transistor T7 and the third transistor T3 may be turned on in response to the first scan signal GP1, the second scan signal GP2 and the fourth scan signal GN2. In this case, the first transistor T1 may be diode-connected and forward-biased through the turned-on third transistor T3. Then, a voltage may be applied to the gate electrode of the first transistor T1, and the voltage may be compensated by the threshold voltage Vth of the first transistor T1 through the data signal DATA supplied from the data line DL. The organic light emitting diode OLED may be initialized by the initialization voltage Vint supplied from the initialization voltage line VIL through the turned-on seventh transistor T7. The first power supply voltage ELVDD and the compensation voltage may be applied to the two opposite ends of the first capacitor Cst, and the amount of charge corresponding to the voltage difference between the two opposite ends may be stored in the first capacitor Cst.

[0084] During the emission period, the fifth transistor T5 and the sixth transistor T6 may be turned on in response to the emission control signal EM supplied from the emission control line EL. OLED can be generated and supplied to the organic light emitting diode OLED through the sixth transistor T6. OLED Corresponding to a voltage difference between a voltage of the gate electrode of the first transistor T1 and the first power supply voltage ELVDD.

[0085] In the present embodiment, at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 may include a semiconductor layer including oxide, and the remaining transistors may include a semiconductor layer including silicon. For example, the first transistor T1 directly affecting the brightness of the display device 10 may include a semiconductor layer including polysilicon having high reliability, and a high-resolution display device 10 may be implemented by such a configuration.

[0086] Since the oxide semiconductor has high carrier mobility and low leakage current, the voltage drop is not large even if the driving time is long. Since the color change of the image corresponding to the voltage drop is not large even during low-frequency driving, the display device can be driven at a low frequency. Since the oxide semiconductor may have a low leakage current, at least one of the third transistor T3 and the fourth transistor T4 that may be connected to the gate electrode of the first transistor T1 may include an oxide semiconductor. Therefore, the leakage current that may flow to the gate electrode of the first transistor T1 may be reduced, and the power consumption may be reduced (for example, both the leakage current and the power consumption may be reduced at the same time).

[0087] Figure 4A is a cross-sectional view of a portion of the display device 10 according to the embodiment.

[0088] Reference Figure 4A The display device 10 according to the embodiment may include a substrate 100, a first thin film transistor TFT1 including a silicon semiconductor, a second thin film transistor TFT2 including an oxide semiconductor, a first capacitor Cst, and a second capacitor Cbt. The first thin film transistor TFT1 may be Figure 3 The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 or the seventh transistor T7. The second thin film transistor TFT2 can be Figure 3 The third transistor T3 or the fourth transistor T4.

[0089] The substrate 100 may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. In the case where the substrate 100 includes a flexible or bendable material, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC) and cellulose acetate propionate (CAP). The substrate 100 may have a single-layer structure or a multi-layer structure. In the case where the substrate 100 has a multi-layer structure, the substrate 100 may also include an inorganic layer. In an embodiment, the substrate 100 may have a structure of an organic material / inorganic material / organic material (for example, the substrate 100 may include an inorganic material layer between two organic material layers).

[0090] The buffer layer 101 may improve the flatness of the top surface of the substrate 100, and may include silicon oxide (SiO x ) oxide layer and / or silicon nitride (SiN x ) or a nitride layer of silicon oxynitride (SiON).

[0091] There may also be a barrier layer between the substrate 100 and the buffer layer 101. The barrier layer may prevent, minimize or reduce impurities from penetrating from the substrate 100 or the like into the silicon semiconductor layer. The barrier layer may include an inorganic material and / or an organic material, the inorganic material including an oxide and a nitride. The barrier layer may have a single-layer structure or a multi-layer structure of an inorganic material and an organic material (for example, a multi-layer structure may include an inorganic material and an organic material).

[0092] The first semiconductor layer AS of the first thin film transistor TFT1 including a silicon semiconductor may be located on the buffer layer 101. The first semiconductor layer AS may include a source region S1, a drain region D1, and a channel region C1, the source region S1 and the drain region D1 are doped with impurities and have conductivity, and the channel region C1 is located between the source region S1 and the drain region D1. The source region S1 and the drain region D1 may correspond to the source and drain of the first thin film transistor TFT1, respectively. The positions of the source region S1 and the drain region D1 may be interchangeable.

[0093] The gate electrode GE1 of the first thin film transistor TFT1 may be located above the first semiconductor layer AS. The first insulating layer 111 may be located between the first semiconductor layer AS and the gate electrode GE1.

[0094] The first insulating layer 111 may include an inorganic material including oxide and nitride. For example, the first insulating layer 111 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO 2 ).

[0095] The gate electrode GE1 of the first thin film transistor TFT1 may overlap the channel region C1 of the first semiconductor layer AS, and may include a single layer or a multilayer including at least one of Mo, Cu, and Ti.

[0096] The first electrode CE1 of the first capacitor Cst and the third electrode CE3 of the second capacitor Cbt may be located on the same layer on which the gate electrode GE1 of the first thin film transistor TFT1 is located. The first electrode CE1 of the first capacitor Cst and the third electrode CE3 of the second capacitor Cbt may include a material substantially the same as that of the gate electrode GE1 of the first thin film transistor TFT1. For example, the first electrode CE1 of the first capacitor Cst and the third electrode CE3 of the second capacitor Cbt may include a single layer or a multilayer including at least one of Mo, Cu, and Ti.

[0097] The second insulating layer 112 may be located on the gate electrode GE1 of the first thin film transistor TFT1, the first electrode CE1 of the first capacitor Cst, and the third electrode CE3 of the second capacitor Cbt.

[0098] The second insulating layer 112 may include an inorganic material including oxide and nitride. For example, the second insulating layer 112 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO 2 ).

[0099] The second electrode CE2 of the first capacitor Cst may be positioned on the second insulating layer 112 to overlap the first electrode CE1 of the first capacitor Cst. The second electrode CE2 may include a single layer or a multilayer including at least one of Mo, Cu, and Ti.

[0100] The third insulating layer 113 may be located on the second electrode CE2 of the first capacitor Cst. The third insulating layer 113 may include an inorganic material including oxide and nitride. For example, the third insulating layer 113 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO 2 ).

[0101] Despite Figure 4A , the first capacitor Cst is shown to be spaced apart from the first thin film transistor TFT1, but in some embodiments, such as Figure 4B As shown in FIG. 1 , for example, the first capacitor Cst may overlap with the first thin film transistor TFT1. For example, the second electrode CE2 may be located above the gate electrode GE1 of the first thin film transistor TFT1 so that the second electrode CE2 overlaps with the gate electrode GE1. In this case, the gate electrode GE1 of the first thin film transistor TFT1 may perform the function of the gate electrode and may also perform the function of the first electrode CE1 of the first capacitor Cst.

[0102] The second semiconductor layer AO of the second thin film transistor TFT2 may be located on the third insulating layer 113, and the second semiconductor layer AO includes an oxide semiconductor. The second semiconductor layer AO may include a source region S2, a drain region D2, and a channel region C2. The source region S2 and the drain region D2 may have conductivity and be spaced apart from each other, and the channel region C2 may be located between the source region S2 and the drain region D2. The oxide semiconductor may include Zn oxide, In-Zn oxide, and Ga-In-Zn oxide as a Zn oxide-based material. For example, the second semiconductor layer AO may include an IGZO (In-Ga-Zn-O) semiconductor, an ITZO (In-Sn-Zn-O) semiconductor, or an IGTZO (In-Ga-Sn-Zn-O) semiconductor containing ZnO, which contains metals such as In, Ga, and Sn (for example, the second semiconductor layer AO may include ZnO containing any one or more of In, Ga, and Sn). The source region S2 and the drain region D2 of the second semiconductor layer AO may be formed by adjusting the carrier concentration of the oxide semiconductor and making the oxide semiconductor conductive. For example, the source region S2 and the drain region D2 may be formed by performing a plasma process using a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof on an oxide semiconductor to increase carrier concentration.

[0103] The first gate electrode GEa may be located below the second semiconductor layer AO of the second thin film transistor TFT2, and the second gate electrode GEb may be located above the second semiconductor layer AO of the second thin film transistor TFT2. For example, the gate electrode GE2 of the second thin film transistor TFT2 may have a double gate structure. The third insulating layer 113 may be located between the first gate electrode GEa and the second semiconductor layer AO. The first gate electrode GEa of the second thin film transistor TFT2 may be located on the same layer as the second electrode CE2 of the first capacitor Cst, and may include a material substantially the same as that of the second electrode CE2. The channel region C2 of the second semiconductor layer AO may overlap with the first gate electrode GEa of the second thin film transistor TFT2.

[0104] The fourth insulating layer 114 may be located between the second semiconductor layer AO of the second thin film transistor TFT2 and the second gate electrode GEb. The second gate electrode GEb may overlap the channel region C2 of the second semiconductor layer AO. The fourth insulating layer 114 may be formed during the same mask process as the mask process of the second gate electrode GEb. In this case, the fourth insulating layer 114 may be substantially the same shape as the second gate electrode GEb.

[0105] The fourth insulating layer 114 may include an inorganic material including oxide and nitride. For example, the fourth insulating layer 114 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO 2 ). The second gate electrode GEb may include a single layer or a multilayer including at least one of Mo, Cu, and Ti.

[0106] The fourth electrode CE4 of the second capacitor Cbt may be located on the third insulating layer 113 so as to overlap the third electrode CE3. The fourth electrode CE4 of the second capacitor Cbt may include an oxide semiconductor. In an embodiment, the fourth electrode CE4 of the second capacitor Cbt may be a portion extending from the second semiconductor layer AO of the second thin film transistor TFT2 and overlapping the third electrode CE3. The second insulating layer 112 and the third insulating layer 113 may be located between the third electrode CE3 and the fourth electrode CE4.

[0107] The fifth insulating layer 115 may cover the second thin film transistor TFT2 . The fifth insulating layer 115 may be located on the second gate electrode GEb . The power supply voltage line PL and the first connection electrode 167 may be located on the fifth insulating layer 115 .

[0108] The fifth insulating layer 115 may include an inorganic material including oxide and nitride. For example, the fifth insulating layer 115 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO 2 ).

[0109] The power supply voltage line PL and the first connection electrode 167 may include a material having high conductivity, such as, for example, a metal and a conductive oxide. For example, the power supply voltage line PL and the first connection electrode 167 may include a single layer or multiple layers including at least one of Al, Cu, and Ti. In an embodiment, the power supply voltage line PL and the first connection electrode 167 may include a triple layer of Ti / Al / Ti in which titanium, aluminum, and titanium are sequentially arranged.

[0110] The first connection electrode 167 may be connected to the first semiconductor layer AS through the contact hole H1. The contact hole H1 may pass through the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fifth insulating layer 115, and expose a portion of the first semiconductor layer AS. A portion of the first connection electrode 167 may be inserted into the contact hole H1 and electrically connected to the first semiconductor layer AS.

[0111] The sixth insulating layer 116 as a planarization layer may be located on the power supply voltage line PL and the first connection electrode 167. The sixth insulating layer 116 may include an organic material such as acrylic acid, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). In some embodiments, the sixth insulating layer 116 may include an inorganic material. The sixth insulating layer 116 may function as a protective layer covering the first thin film transistor TFT1 and the second thin film transistor TFT2, and the top surface of the sixth insulating layer 116 may be flat. The sixth insulating layer 116 may include a single layer or multiple layers.

[0112] The data line DL and the second connection electrode 177 may be located on the sixth insulating layer 116. The data line DL may partially overlap with the power supply voltage line PL. The second connection electrode 177 may be connected to the first connection electrode 167 through a contact hole H2 defined in the sixth insulating layer 116. The data line DL and the second connection electrode 177 may include a conductive material such as a metal and a conductive oxide. For example, the data line DL and the second connection electrode 177 may include a single layer or multiple layers including at least one of Al, Cu, and Ti. The seventh insulating layer 117 may be located on the data line DL and the second connection electrode 177.

[0113] The organic light emitting diode OLED may be located on the seventh insulating layer 117. The organic light emitting diode OLED may include a pixel electrode 310, an opposite electrode 330, and an intermediate layer 320 located between the pixel electrode 310 and the opposite electrode 330 and including an emission layer.

[0114] The pixel electrode 310 may be connected to the second connection electrode 177 through a contact hole H3 defined in the seventh insulating layer 117 , and may be connected to the first thin film transistor TFT1 through the second connection electrode 177 and the first connection electrode 167 .

[0115] The eighth insulating layer 118 may be a pixel defining layer and may be located on the seventh insulating layer 117. The eighth insulating layer 118 may be defined by including an opening OP, and the opening OP is opposite to each pixel. For example, the opening OP may expose a portion of the pixel electrode 310. In addition, the eighth insulating layer 118 may reduce (e.g., prevent) arcing, etc., at the edge of the pixel electrode 310 by increasing the distance between the pixel electrode 310 and the edge of the opposing electrode 330 above the pixel electrode 310. The eighth insulating layer 118 may include an organic material including, for example, polyimide and HMDSO.

[0116] The pixel electrode 310 may be located on the seventh insulating layer 117 and may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In another embodiment, the pixel electrode 310 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. In another embodiment, the pixel electrode 310 may also include a conductive oxide including ITO, IZO, ZnO, or In on or under the reflective layer. 2 O 3 layer.

[0117] The intermediate layer 320 of the organic light emitting diode OLED may include an emission layer. The emission layer may include a polymer organic material or a low molecular weight organic material that emits light of a predetermined or set color. The emission layer may be a red emission layer, a green emission layer, or a blue emission layer. In some embodiments, the emission layer may have a multilayer structure in which a red emission layer, a green emission layer, and a blue emission layer are stacked to emit white light. In some embodiments, the emission layer may have a single-layer structure including a red emission material, a green emission material, or a blue emission material. In an embodiment, the intermediate layer 320 may include a first functional layer below the emission layer and / or a second functional layer on the emission layer. The first functional layer and / or the second functional layer may include a layer that is integrated above the plurality of pixel electrodes 310, or may include a patterned layer so as to correspond to each of the plurality of pixel electrodes 310.

[0118] The first functional layer may include a single layer or multiple layers. For example, when the first functional layer includes a polymer material, the first functional layer may be a hole transport layer (HTL) having a single layer structure. The first functional layer may include poly (3,4) -ethylene - dioxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer includes a low molecular weight material, the first functional layer may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0119] In some embodiments, the second functional layer may be omitted. For example, in the case where the first functional layer and the emission layer include a polymer material, the second functional layer may enable the organic light emitting diode OLED to have excellent characteristics. The second functional layer may include a single layer or multiple layers. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0120] The opposing electrode 330 may face the pixel electrode 310 with the intermediate layer 320 interposed therebetween. The opposing electrode 330 may include a conductive material having a low work function. For example, the opposing electrode 330 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. In some embodiments, the opposing electrode 330 may also include a (semi) transparent layer including ITO, IZO, ZnO, or In on or under the (semi) transparent layer including the above materials. 2 O 3 The opposing electrode 330 may be located on the intermediate layer 320 and the eighth insulating layer 118. The opposing electrode 330 may be integrated over the plurality of organic light emitting diodes OLED in the display area DA, and may be a common electrode facing the plurality of pixel electrodes 310.

[0121] The thin film encapsulation layer or encapsulation substrate may be arranged on the organic light emitting diode OLED to cover and protect the organic light emitting diode OLED. The thin film encapsulation layer may cover the display area DA and extend to the outside of the display area DA. The thin film encapsulation layer may include an inorganic encapsulation layer including at least one inorganic material and an organic encapsulation layer including at least one organic material. In an embodiment, the thin film encapsulation layer may have a structure in which a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer are stacked. The encapsulation substrate may face the substrate 100 and may be bonded to the substrate 100 by a sealing member such as a sealant and / or a frit, for example.

[0122] In addition, a spacer may be located on the eighth insulating layer 118, which reduces (e.g., prevents) mask chopping. Various functional layers may be located on the thin film encapsulation layer. The various functional layers may include a polarizing layer, a black matrix, a color filter for reducing external light reflection, and / or a touch screen including a touch electrode, etc.

[0123] Figure 5 is a view of a first scan driving circuit 120 and an emission control circuit 140 according to an embodiment, and Figure 6 is a view of the second scan driving circuit 130 according to an embodiment.

[0124] Reference Figure 5 and Figure 6, the first scan driving circuit 120, the second scan driving circuit 130, and the emission control circuit 140 may each include a shift register including a plurality of stages.

[0125] The first scan driving circuit 120 may include a plurality of stages SST11 to SST1n connected in a slave manner. The plurality of stages SST11 to SST1n may output a plurality of first scan signals GP11 to GP1n to the first scan lines SL1 corresponding thereto, and output a plurality of second scan signals GP21 to GP2n to the second scan lines SL2 corresponding thereto. The first stage SST11 among the plurality of stages SST11 to SST1n may output the first scan signal GP11 and the second scan signal GP21 in response to the start signal FLM, and the remaining stages SST12 to SST1n except the first stage SST11 may receive a carry signal as a start signal from the previous stage SST11 to SST1n-1. The carry signal may be the first scan signal or the second scan signal output from the previous stage. Each of the plurality of stages SST11 to SST1n may output the first scan signal and the second scan signal according to the driving timing. In an embodiment, the first scan signal and the second scan signal may be output from different output terminals of each stage, respectively, and output to the first scan line SL1 and the second scan line SL2. In another embodiment, the first scan signal and the second scan signal may be output from one output terminal of each stage as one scan signal, and may be divided and output to the first scan line SL1 and the second scan line SL2. The plurality of stages SST11 to SST1n may be respectively connected to the plurality of input lines 211 outside the plurality of stages SST11 to SST1n. The plurality of input lines 211 may include a plurality of voltage lines and a plurality of clock lines. Although for convenience of illustration, Figure 5 Only one input line 211 is shown, but embodiments of the present disclosure are not limited thereto.

[0126] The second scan driving circuit 130 may include a plurality of stages SST21 to SST2n connected in a slave manner. The plurality of stages SST21 to SST2n may output a plurality of third scan signals GN11 to GN1n to the third scan lines SL3 corresponding thereto, and output a plurality of fourth scan signals GN21 to GN2n to the fourth scan lines SL4 corresponding thereto. The first stage SST21 of the plurality of stages SST21 to SST2n may output the third scan signal GN11 and the fourth scan signal GN21 in response to the start signal FLM, and the remaining stages SST22 to SST2n except the first stage SST21 may receive a carry signal as a start signal from the previous stage SST21 to SST2n-1. The carry signal may be the third scan signal or the fourth scan signal outputted from the previous stage. Each of the plurality of stages SST21 to SST2n may output the third scan signal and the fourth scan signal according to the driving timing. In an embodiment, the third scan signal and the fourth scan signal may be output from different output terminals of each stage at different timings and output to the third scan line SL3 and the fourth scan line SL4. The plurality of stages SST21 to SST2n may be connected to a plurality of input lines 213 outside the plurality of stages SST21 to SST2n, respectively. The plurality of input lines 213 may include a plurality of voltage lines and a plurality of clock lines. Although for the convenience of illustration, Figure 6 Only one input line 213 is shown, but embodiments of the present disclosure are not limited thereto.

[0127] The emission control circuit 140 may include a plurality of stages EST1 to ESTn connected in a slave manner. The plurality of stages EST1 to ESTn may output an emission control signal EM to an emission control line EL corresponding thereto. The first stage EST1 of the plurality of stages EST1 to ESTn may output an emission control signal EM in response to a start signal FLM, and the remaining stages EST2 to ESTn except the first stage EST1 may receive a carry signal as a start signal from the previous stage EST1 to ESTn-1. The carry signal may be the emission control signal EM output from the previous stage. Each of the plurality of stages EST1 to ESTn may be connected to a plurality of input lines 215 outside the plurality of stages EST1 to ESTn. The plurality of input lines 215 may include a plurality of voltage lines and a plurality of clock lines. Although for the convenience of illustration, Figure 5 Only one input line 215 is shown, but embodiments of the present disclosure are not limited thereto.

[0128] Figure 7 yes Figure 2 A plan view of an example of area A1, and Figure 8 yes Figure 2 A plan view of an example of area A2. Fig. 9 is a view showing the size of a driving circuit according to an embodiment.

[0129] Reference Figure 7 , the first scan driving circuit 120 and the emission control circuit 140 may be arranged mixedly in the first peripheral area PA1 and the second peripheral area PA2. For example, different driving circuits may be arranged in lines in the peripheral area PA. The stages SST1 of the first scan driving circuit 120 and the stages EST of the emission control circuit 140 may be arranged alternately in the first peripheral area PA1 and the second peripheral area PA2. A pair of the stages SST1 of the first scan driving circuit 120 and the stages EST of the emission control circuit 140 (referred to as a stage group SG) may be arranged in lines to correspond to one row. For example, as Fig. 9 As shown in , a pair of the i-th stage SST1i of the first scan driving circuit 120 corresponding to the i-th row and the i-th stage ESTi of the emission control circuit 140 may be arranged in a line adjacent to each other along the edge of the display area DA (e.g., along the periphery). A pair of the (i+1)-th stage SST1i+1 of the first scan driving circuit 120 corresponding to the (i+1)-th row and the (i+1)-th stage ESTi+1 of the emission control circuit 140 may be arranged in a line adjacent to each other along the edge of the display area DA (e.g., along the periphery). Because the driving circuits performing different functions are distributed in lines, the width of the peripheral area PA can be reduced.

[0130] Each of the plurality of stages SST11 to SST1n of the first scan driving circuit 120 may be connected to the first output line OLs11 and the second output line OLs12. The first output line OLs11 and the second output line OLs12 may be connected to the first scan line SL1 and the second scan line SL2 of the pixel PX in the corresponding row, respectively. The first scan signal GP1 and the second scan signal GP2 outputted from each of the plurality of stages SST11 to SST1n of the first scan driving circuit 120 may be applied to the pixel PX in the corresponding row through the first output line OLs11 and the second output line OLs12. Each of the plurality of stages EST1 to ESTn of the emission control circuit 140 may be connected to the output line OLe, and the output line OLe may be connected to the emission control line EL of the pixel PX in the corresponding row. The emission control signal EM outputted from each of the plurality of stages EST1 to ESTn of the emission control circuit 140 may be applied to the pixel PX in the corresponding row through the corresponding output line OLe.

[0131] Reference Figure 8 , the second scan driving circuit 130 may be arranged in the third peripheral area PA3 and the fourth peripheral area PA4. Each of the plurality of stages SST21 to SST2n of the second scan driving circuit 130 may be arranged to correspond to one row. Fig. 9As shown in , the i-th stage SST2i of the second scan driving circuit 130 corresponding to the i-th row and the (i+1)-th stage SST2i+1 of the second scan driving circuit 130 corresponding to the (i+1)-th row may be arranged in a line adjacent to each other along an edge (e.g., along the periphery) of the display area DA. Each of the plurality of stages SST21 to SST2n of the second scan driving circuit 130 may be connected to the first output line OLs21 and the second output line OLs22, and the first output line OLs21 and the second output line OLs22 may be connected to the third scan line SL3 and the fourth scan line SL4 of the pixels PX in the corresponding row. The third scan signal GN1 and the fourth scan signal GN2 outputted from each of the plurality of stages SST21 to SST2n of the second scan driving circuit 130 may be applied to the pixels PX in the corresponding row through the first output line OLs21 and the second output line OLs22.

[0132] The areas occupied by the stages of different driving circuits may be different from each other. The area of ​​one stage SST1 of the first scan driving circuit 120, the area of ​​one stage SST2 of the second scan driving circuit 130, and the area of ​​one stage EST of the emission control circuit 140 may be different from each other. For example, Fig. 9 As shown in , an area in which one stage SST1 of the first scan driving circuit 120, one stage SST2 of the second scan driving circuit 130, and one stage EST of the emission control circuit 140 may be arranged in the peripheral area PA may have a substantially quadrilateral shape. Hereinafter, the size of the area in which each stage is arranged is defined as the size of each stage.

[0133] The length W1 of the long side of one stage SST1 of the first scan driving circuit 120, the length W2 of the long side of one stage EST of the emission control circuit 140, and the length W3 of the long side of one stage SST2 of the second scan driving circuit 130 may be the same (e.g., substantially the same) or different from each other. The length H1 of the short side of one stage SST1 of the first scan driving circuit 120, the length H2 of the short side of one stage EST of the emission control circuit 140, and the length H3 of the short side of one stage SST2 of the second scan driving circuit 130 may be the same (e.g., substantially the same) or different from each other. For example, in one embodiment, the length H1 of the short side of one stage SST1 of the first scan driving circuit 120 may be substantially the same as the length H2 of the short side of one stage EST of the emission control circuit 140. The length H3 of the short side of one stage SST2 of the second scan driving circuit 130 may be substantially the same as the sum of the length H1 of the short side of one stage SST1 of the first scan driving circuit 120 and the length H2 of the short side of one stage EST of the emission control circuit 140. In this specification, "substantially the same" means that the difference in length is within a preset error range, which is within about 5%.

[0134] In an embodiment in which the number of driving circuits arranged at the left and right sides of the display area DA is different from each other, the sizes of the stages of the respective driving circuits may be substantially horizontally symmetrical with each other. For example, in an embodiment in which two different driving circuits (such as, for example, the first scan driving circuit 120 and the emission control circuit 140) are arranged at the left side of the display area DA, and one driving circuit (such as, for example, the second scan driving circuit 130) is arranged at the right side of the display area DA, the sum of the size of the stage SST1 of the first scan driving circuit 120 and the size of the stage EST of the emission control circuit 140 may be substantially the same as the size of the stage SST2 of the second scan driving circuit 130. Therefore, in some embodiments, the designed circuit may reduce the dead zone without making one of the left and right sides of the peripheral area larger than the other. In some embodiments, the left and right positions of the first scan driving circuit 120 and the second scan driving circuit 130 may be changed. For example, the second scan driving circuit 130 and the emission control circuit 140 may be distributed in the left peripheral area of ​​the display area DA, and the first scan driving circuit 120 may be arranged in the right peripheral area of ​​the display area DA.

[0135] In a plan view, each stage of the driving circuit may be inclined at a predetermined angle or a set angle along the shape of the display area DA. Fig. 9 As shown in , the stage SST1 of the first scan driving circuit 120 may be tilted at a first angle α1 relative to the reference line Lref. The stage EST of the emission control circuit 140 may be tilted at a second angle α2 relative to the reference line Lref. The stage SST2 of the second scan driving circuit 130 may be tilted at a third angle α3 relative to the reference line Lref. The reference line Lref may be a virtual line parallel to the second direction D2. The first angle α1, the second angle α2, and the third angle α3 may be based on the position of the stage. Each of the first angle α1, the second angle α2, and the third angle α3 may be within a range greater than 0° and less than 90°.

[0136] Fig.10 is a configuration diagram of a display device 10 ′ according to another embodiment. Fig.11 yes Fig.10 FIG. 1 is a view of a display panel 110 ′ of a display device 10 ′ shown in FIG. Fig. 12A and Fig. 12B is a diagram of a data distribution circuit 160 according to an embodiment, and Fig.13 is a diagram of a test circuit 170 according to an embodiment.

[0137] Reference Fig.10 and Fig.11, a display device 10' according to an embodiment may include a display panel 110', and the display panel 110' may include a substrate 100. The substrate 100 may include a display area DA and a peripheral area PA as a non-display area outside the display area DA. The peripheral area PA may surround the display area DA and have a shape corresponding to the shape of the edge of the display area DA.

[0138] and Figure 1 Compared with the display device 10 shown in FIG. Fig.10 The display device 10' shown in FIG. 1 may further include a data distribution circuit 160 and a test circuit 170. Figure 1 The description of similar features in the embodiment of the present invention will be omitted, and the features added thereto will be mainly described.

[0139] The plurality of stages SST11 to SST1n of the first scan driving circuit 120 may be distributed in the first peripheral area PA1 and the second peripheral area PA2. The plurality of stages SST21 to SST2n of the second scan driving circuit 130 may be distributed in the third peripheral area PA3 and the fourth peripheral area PA4. The plurality of stages EST1 to ESTn of the emission control circuit 140 may be distributed in the first peripheral area PA1 and the second peripheral area PA2.

[0140] The data distribution circuit 160 may be arranged between the data driving circuit 150 and the display area DA, may be connected to the data lines DL, and may transmit the data signal DATA from the data driving circuit 150 to the data lines DL. The data distribution circuit 160 may time-divide the data signal DATA, which is applied through one output line FL of the data driving circuit 150, and distribute the divided data signal DATA to the plurality of data lines DL.

[0141] like Fig. 12A As shown in , the data distribution circuit 160 may include a plurality of demultiplexers DMUX. The number of demultiplexers DMUX may be the same as the number of output lines FL of the data driving circuit 150. Each demultiplexer DMUX may include a plurality of first switches SW1. The first switch SW1 may be a thin film transistor.

[0142] Each demultiplexer DMUX may divide a data signal DATA and supply the divided data signal DATA to six data lines DL1 to DL6, the data signal DATA being applied from one output line FL among a plurality of output lines FL of the data driving circuit 150. A plurality of first switches SW1 may be respectively turned on in response to corresponding control signals CLA to CLF, and may apply the data signal DATA to the data lines DL1 to DL6 corresponding thereto. In some embodiments, the number of output lines FL of the data driving circuit 150 may be reduced to 1 / 6 of the number of data lines DL by using the demultiplexer DMUX. In some embodiments, the number of data lines DL connected to one demultiplexer DMUX may be changed. For example, as Fig. 12B As shown in , each demultiplexer DMUX may divide a data signal DATA and supply the divided data signal DATA to nine data lines DL1 to DL9, the data signal DATA being applied from one output line FL among a plurality of output lines FL of the data driving circuit 150. The first switches SW1 may be turned on respectively in response to corresponding control signals CLA to CLI, and may apply the data signal DATA to the data lines DL1 to DL9 corresponding thereto. Each demultiplexer DMUX may be divided into a plurality of sub-demultiplexers SDMUX. As shown in Fig. 12A and Fig. 12B As shown in , each demultiplexer DMUX may be divided into a plurality of sub-demultiplexers SDMUX on a three-data-line basis. The sub-demultiplexers SDMUX of the demultiplexer DMUX may be distributed in the second peripheral area PA2 and the fourth peripheral area PA4.

[0143] The test circuit 170 may be connected to the data line DL and may apply a test signal to the data line DL. Fig.13 As shown in FIG. 1 , the test circuit 170 may include a plurality of sub-test circuits STU. Each sub-test circuit STU may include as many second switches SW2 as the number of pixels PX constituting the unit pixel UP. Fig.13 An example in which the sub-test circuit STU includes three second switches SW2 is shown. The plurality of second switches SW2 may be connected to three data lines DL respectively connected to the three pixels PX. The second switch SW2 may be a thin film transistor. Each of the plurality of second switches SW2 may be turned on in response to the control signal DC_GATE, and may output a test signal DC_R, DC_G or DC_B applied from a corresponding input line among the plurality of input lines 221, 223 and 225 to the data line DL corresponding thereto. The display device 10' may identify whether the pixel PX and the signal line are defective by using the test circuit 170. The sub-test circuit STU of the test circuit 170 may be distributed in the first peripheral area PA1 and the third peripheral area PA3.

[0144] The data distribution circuit 160 may be connected to one end portion (eg, terminal) of the plurality of data lines DL, and the test circuit 170 may be connected to the other end portion (eg, terminal) of the plurality of data lines DL.

[0145] Figures 14 to 17 yes Fig.11 1 to 4. Figures 7 to 9 Description of similar features in the embodiments of the present invention.

[0146] Reference Fig.14 , the test circuit 170, the first scan driving circuit 120, and the emission control circuit 140 may be mixedly arranged in the first peripheral area PA1. For example, driving circuits different from each other may be arranged in lines in the first peripheral area PA1. Each stage group SG may be arranged in lines in the first peripheral area PA1 to correspond to one row. The sub-test circuits STU connected to the data lines DL arranged in the first display area DA1 and the second display area DA2 among the plurality of sub-test circuits STU of the test circuit 170 may be distributed between the stage groups SG in the first peripheral area PA1.

[0147] Depending on the arrangement of pixels, at least one sub-test circuit STU may be arranged between the stage groups SG, or at least one stage group SG may be arranged between two sub-test circuits STU. For example, one or two or more sub-test circuits STU may be arranged continuously in a line between two stage groups SG in one area of ​​the first peripheral area PA1. In some embodiments, one or two or more stage groups SG may be arranged continuously in a line between two sub-test circuits STU in another area of ​​the first peripheral area PA1.

[0148] Each of the plurality of sub-test circuits STU may be connected to as many output lines as the number of pixels constituting the unit pixel UP. For example, each of the plurality of sub-test circuits STU may be connected to three output lines including a first output line OLt1, a second output line OLt2, and a third output line OLt3. Each of the first output line OLt1, the second output line OLt2, and the third output line OLt3 may be connected to a data line DL of a corresponding column. Each of the three test signals DC_R, DC_G, and DC_B outputted from the sub-test circuit STU may be applied to the pixel PX in the corresponding column through a corresponding output line among the first output line OLt1, the second output line OLt2, and the third output line OLt3.

[0149] Reference Fig.15, the data distribution circuit 160, the first scan driving circuit 120, and the emission control circuit 140 may be mixedly arranged in the second peripheral area PA2. For example, driving circuits different from each other may be arranged in lines in the second peripheral area PA2. Each of the plurality of stage groups SG may be arranged in lines in the second peripheral area PA2 to correspond to one row. The sub-demultiplexers SDMUX connected to the data lines DL arranged in the first display area DA1 and the second display area DA2 among the plurality of sub-demultiplexers SDMUX of the data distribution circuit 160 may be distributed between the stage groups SG in the second peripheral area PA2.

[0150] Depending on the arrangement of pixels, at least one sub-demultiplexer SDMUX may be arranged between the stage groups SG, or at least one stage group SG may be arranged between two sub-demultiplexers SDMUX. For example, one or two or more sub-demultiplexers SDMUX may be arranged continuously in a line between the stage groups SG in one area of ​​the second peripheral area PA2. In some embodiments, one or two or more stage groups SG may be arranged continuously in a line between two sub-demultiplexers SDMUX in another area of ​​the second peripheral area PA2.

[0151] Each of the plurality of sub-demultiplexers SDMUX may be connected to as many output lines as the number of pixels constituting the unit pixel UP. For example, each of the plurality of sub-demultiplexers SDMUX may be connected to three output lines including a first output line OLd1, a second output line OLd2, and a third output line OLd3. Each of the first output line OLd1, the second output line OLd2, and the third output line OLd3 may be connected to a data line DL of a corresponding column. The data signal DATA output from the sub-demultiplexer SDMUX may be applied to the pixel PX in the corresponding column through a corresponding output line among the first output line OLd1, the second output line OLd2, and the third output line OLd3.

[0152] Reference Fig.16 , the test circuit 170 and the second scan driving circuit 130 may be arranged mixedly in the third peripheral area PA3. For example, driving circuits different from each other may be arranged in lines in the third peripheral area PA3. Each of the plurality of stages SST2 of the second scan driving circuit 130 may be arranged in lines in the third peripheral area PA3 to correspond to one row. The sub-test circuits STU connected to the data lines DL arranged in the third display area DA3 and the fourth display area DA4 among the plurality of sub-test circuits STU of the test circuit 170 may be distributed between the stages SST2 of the third peripheral area PA3.

[0153] Depending on the arrangement of pixels, at least one sub-test circuit STU may be arranged between the stages SST2, or at least one stage SST2 may be arranged between two sub-test circuits STU. For example, one or two or more sub-test circuits STU may be arranged continuously in a line between two stages SST2 in one area of ​​the third peripheral area PA3. In addition, for example, one or two or more stages SST2 may be arranged continuously in a line between two sub-test circuits STU in another area of ​​the third peripheral area PA3.

[0154] Reference Fig.17 , the data distribution circuit 160 and the second scan driving circuit 130 may be arranged mixedly in the fourth peripheral area PA4. For example, driving circuits different from each other may be arranged in lines in the fourth peripheral area PA4. Each of the plurality of stages SST2 of the second scan driving circuit 130 may be arranged in lines in the fourth peripheral area PA4 to correspond to one row. The sub-demultiplexers SDMUX connected to the data lines DL arranged in the third display area DA3 and the fourth display area DA4 among the plurality of sub-demultiplexers SDMUX of the data distribution circuit 160 may be distributed between the stages SST2 of the fourth peripheral area PA4.

[0155] Depending on the arrangement of pixels, at least one sub-demultiplexer SDMUX may be arranged between the stages SST2, or at least one stage SST2 may be arranged between two sub-demultiplexers SDMUX. For example, one or two or more sub-demultiplexers SDMUX may be continuously arranged in a row between the stages SST2 in one area of ​​the fourth peripheral area PA4. In some embodiments, one or two or more stages SST2 may be continuously arranged in a row between two sub-demultiplexers SDMUX in another area of ​​the fourth peripheral area PA4.

[0156] exist Figures 14 to 17 In the embodiment, output lines arranged on the same layer may extend in a predetermined or set direction so that the output lines do not intersect each other.

[0157] The areas occupied by the stages of different driving circuits may be different from each other. The area in which one of the plurality of sub-test circuits STU of the test circuit 170 and one of the plurality of sub-demultiplexers SDMUX of the data distribution circuit 160 are each arranged in the peripheral area PA may have a substantially quadrilateral shape. The area of ​​one of the plurality of sub-test circuits STU of the test circuit 170, the area of ​​one of the plurality of sub-demultiplexers SDMUX of the data distribution circuit 160, the area of ​​one of the stages SST1 of the first scan driving circuit 120, the area of ​​one of the stages SST2 of the second scan driving circuit 130, and the area of ​​one of the stages EST of the emission control circuit 140 may be the same (e.g., substantially the same) or different from each other.

[0158] exist Fig.11In the implementation mode, if Fig. 9 As shown in , the length W1 of the long side of one stage SST1 of the first scan driving circuit 120, the length W2 of the long side of one stage EST of the emission control circuit 140, and the length W3 of the long side of one stage SST2 of the second scan driving circuit 130 may be substantially the same or different from each other. The length H1 of the short side of one stage SST1 of the first scan driving circuit 120, the length H2 of the short side of one stage EST of the emission control circuit 140, and the length H3 of the short side of one stage SST2 of the second scan driving circuit 130 may be the same (e.g., substantially the same) or different from each other. For example, in one embodiment, the length H1 of the short side of one stage SST1 of the first scan driving circuit 120 may be substantially the same as the length H2 of the short side of one stage EST of the emission control circuit 140. The length H3 of the short side of one stage SST2 of the second scan driving circuit 130 may be substantially the same as the sum of the length H1 of the short side of one stage SST1 of the first scan driving circuit 120 and the length H2 of the short side of one stage EST of the emission control circuit 140.

[0159] Fig.18 is a view of an arrangement of output lines according to an embodiment. Fig.19 is an exemplary view of an arrangement of output lines according to an embodiment.

[0160] Reference Fig.18 , the peripheral area PA of the substrate 100 may include a driving circuit area DCA where driving circuits are arranged along the edge of the display area DA. Figure 2 and Fig.11 As described, the sub-driving circuits SC of the plurality of different driving circuits may be mixedly distributed in lines in the driving circuit area DCA. The sub-driving circuits SC may include a stage SST1 of the first scan driving circuit 120, a stage SST2 of the second scan driving circuit 130, a stage EST of the emission control circuit 140, a sub-demultiplexer SDMUX of the data distribution circuit 160, and a sub-test circuit STU of the test circuit 170.

[0161] The peripheral area PA of the substrate 100 may further include an input line area ILA located between the driving circuit area DCA and the edge of the substrate 100. A plurality of input lines for applying signals and / or voltages to the driving circuits may be arranged in the input line area ILA. The input lines may include input lines 211 of the first scan driving circuit 120 (see Figure 5 ), the input line 213 of the second scan drive circuit 130 (see Figure 6 ), the input line 215 of the emission control circuit 140 (see Figure 5 ), transmitting the data signal DATA to the output line FL of the data distribution circuit 160, applying the control signal CLA to CLI (see Fig. 12Aand Fig. 12B ) signal line, a signal line for applying a control signal DC_GATE to the test circuit 170, and a plurality of input lines 221, 223, and 225 for applying a plurality of test signals DC_R, DC_G, and DC_B (see Fig.13 ).

[0162] The peripheral area PA of the substrate 100 may further include an output line area OLA located between the display area DA and the drive circuit area DCA. The output lines OL connecting the sub-drive circuit SC to the pixel PX may be arranged in the output line area OLA. The output lines OL may include the first output lines OLs11 and the second output lines OLs12 of the first scan drive circuit 120, the first output lines OLs21 and the second output lines OLs22 of the second scan drive circuit 130, the output lines OLe of the emission control circuit 140, the first output lines OLd1, the second output lines OLd2 and the third output lines OLd3 of the data distribution circuit 160, and the first output lines OLt1, the second output lines OLt2 and the third output lines OLt3 of the test circuit 170. Each of the first output lines OLs11 and the second output lines OLs12 of the first scan drive circuit 120 may be electrically connected to the first scan lines SL1 and the second scan lines SL2 in the corresponding row. Each of the first output lines OLs21 and the second output lines OLs22 of the second scan drive circuit 130 may be electrically connected to the third scan lines SL3 and the fourth scan lines SL4 in the corresponding row. Each of the plurality of output lines OLe of the emission control circuit 140 may be electrically connected to the emission control line EL in the corresponding row. Each of the first output line OLd1, the second output line OLd2, and the third output line OLd3 of the data distribution circuit 160 may be electrically connected to the data line DL in the corresponding column. Each of the first output line OLt1, the second output line OLt2, and the third output line OLt3 of the test circuit 170 may be electrically connected to the data line DL in the corresponding column.

[0163] The output line area OLA may include a first output line area OLA1 and a second output line area OLA2, the first output line area OLA1 is adjacent to (e.g., adjacent to) the driving circuit area DCA, and the second output line area OLA2 is adjacent to (e.g., adjacent to) the display area DA. Each of the plurality of output lines OL may include a first portion OLa and a second portion OLb, the first portion OLa being arranged in the first output line area OLA1, and the second portion OLb being arranged in the second output line area OLA2. The first portion OLa of each output line OL may extend in a predetermined direction or a set direction in the first output line area OLA1, and the second portion OLb bent from the first portion OLa may extend toward the center O of the display area DA in the second output line area OLA2. For example, the plurality of extension lines of the plurality of second portions OLb of the plurality of output lines OL may converge to the center O of the display area DA, respectively. The second portion OLb of the output line OL may be inclined at a fourth angle β relative to the reference line Lref. The fourth angle β may be based on the position of the output line OL.

[0164] In one embodiment, since the output line of the sub-driving circuit SC connected to the driving circuit is bent at the boundary between the first output line area OLA1 and the second output line area OLA2 and has directionality in the second output line area OLA2, a non-connected area where the sub-driving circuit SC is not connected to the pixel PX may not be generated.

[0165] As an example, Fig.19 The sub test circuit STU of the test circuit 170, the stage SST1 of the first scan driving circuit 120, and the stage EST of the emission control circuit 140 are shown as three sub driving circuits SC arranged in a line in the driving circuit area DCA.

[0166] A plurality of input lines may be arranged in the input line area ILA. In some embodiments, one input line may be connected to each sub-driving circuit SC. In other embodiments, a plurality of input lines may be connected to each sub-driving circuit SC. For example, Fig.19 As shown in , the first input line IL1, the second input line IL2, and the third input line IL3 may be spaced apart (e.g., separated) from each other by a predetermined interval or a set spacing in the input line area ILA. In addition, the first input line IL1 may be connected to the stage SST1 of the first scan driving circuit 120, the second input line IL2 may be connected to the stage EST of the emission control circuit 140, and the third input line IL3 may be connected to the sub-test circuit STU of the test circuit 170. The first input line IL1 and the second input line IL2 may include a plurality of voltage lines and a plurality of clock lines. The third input line IL3 may include a plurality of signal lines that apply the control signal DC_GATE and the plurality of test signals DC_R, DC_G, and DC_B to the sub-test circuit STU.

[0167] The output lines OL may be spaced apart from each other in the output line area OLA, and the plurality of output lines OL connect the plurality of sub-drive circuits SC to the first pixel PX1, the second pixel PX2, and the third pixel PX3. The output lines OL may be connected to the sub-drive circuit SC through the wiring 231 and the connection pad 235 of the sub-drive circuit SC. The plurality of first portions OLa of the plurality of output lines OL may be spaced apart from each other (e.g., separated) so that they do not intersect each other, and may extend in a predetermined direction or a set direction according to the layout of the sub-drive circuit SC. The second portion OLb of the output line OL may be bent at a boundary between the first output line area OLA1 and the second output line area OLA2, and may extend toward the center O (also referred to as the origin O) in the second output line area OLA2.

[0168] Fig.19 An embodiment is shown in which a scan signal output from the wiring 231 of the stage SST1 of the first scan driving circuit 120 is divided and transmitted to two output lines, and the two output lines are electrically connected to the first scan line SL1 and the second scan line SL2, respectively.

[0169] The common initialization voltage line CVIL may be further arranged in the driving circuit area DCA along the edge of the display area DA. The common initialization voltage line CVIL may apply the initialization voltage Vint to the initialization voltage line VIL of the pixel PX. In the driving circuit area DCA, the wiring 237 connected to the common initialization voltage line CVIL may be connected to the output line OL' through the connection pad 235, and the output line OL' may be electrically connected to the initialization voltage line VIL of the pixel PX. Like other output lines OL, the output line OL' connected to the common initialization voltage line CVIL may include a first portion OLa and a second portion OLb, and an extension line of the second portion OLb of each output line OL' may pass through the origin O of the display area DA (e.g., extend toward the origin O of the display area DA).

[0170] Figure 20 to Figure 22 is a view of a display panel of a display device according to another embodiment.

[0171] Reference Fig. 20 , the substrate 100' of the display panel according to the embodiment may have a non-quadrilateral shape including a circular portion. The substrate 100' may include a circular first edge E1 and a linear second edge E2. The display area DA may be circular as a whole. The peripheral area PA surrounding the display area DA may include an area having a shape corresponding to the shape of the display area DA and an area having a shape different from the shape of the display area DA.

[0172] The drive circuit area DCA may include a circular first drive circuit area DCAa and a second drive circuit area DCAb having a linear shape. The first drive circuit area DCAa may be included in the peripheral area PA having a shape corresponding to that of the display area DA, and the second drive circuit area DCAb may be included in the peripheral area PA having a shape different from that of the display area DA. For example, the display area DA is circular, but the drive circuit area DCA may include an area having a shape corresponding to that of the display area DA and an area having a shape different from that of the display area DA.

[0173] The sub-driving circuits SC arranged in the first driving circuit area DCAa may be inclined at a predetermined or set angle α relative to the reference line Lref. The sub-driving circuits SC arranged in the second driving circuit area DCAb may be inclined at 90° relative to the reference line Lref. ° The width W5 of the peripheral area PA where the second driving circuit area DCAb is located may be smaller than the width W4 of the peripheral area PA where the first driving circuit area DCAa is located. Therefore, the peripheral area PA of the display area DA, which may be a dead zone, may be reduced.

[0174] like Fig.21 As shown in , one or more portions of the peripheral area PA having a shape different from that of the display area DA may be located between portions of the peripheral area PA having a shape corresponding to the shape of the display area DA. Similarly, two or more second drive circuit areas DCAb having shapes different from those of the display area DA may be located between the first drive circuit areas DCAa. The plurality of second drive circuit areas DCAb may include at least one second drive circuit area DCAb1 and at least one second drive circuit area DCAb2, the sub drive circuits SC in the second drive circuit area DCAb1 being arranged at 90° relative to the reference line Lref, and the sub drive circuits SC in the second drive circuit area DCAb2 being arranged at 0° relative to the reference line Lref. Fig.21 In the figure, the substrate 100" may include a circular first edge E1, a third edge E3 and a fifth edge E5. The substrate 100" may also have a second edge E2, a fourth edge E4 and a sixth edge E6 with a straight line shape. Although the display area DA is circular as a whole, depending on the shape of the substrate 100", the driving circuit area DCA may include some areas having a shape different from that of the display area DA.

[0175] Fig. 22 is a view of a display panel of a display device according to another embodiment.

[0176] Reference Fig. 22, the substrate 100a of the display panel according to the embodiment may have a non-quadrilateral shape of which a portion is circular. The substrate 100a may be circular as a whole. The substrate 100a may include a display area DA and a peripheral area PA surrounding the display area DA. The display area DA may have a circular shape as a whole, but a portion of the display area DA may have a straight line shape.

[0177] exist Fig. 22 In one embodiment, a portion of the left edge of the display area DA has a straight line shape, and thus the shape and size of the peripheral area PA at the left edge may be different from the size and shape of the peripheral area PA at the right edge. In another embodiment, a portion of one of the left edge, right edge, upper edge, and lower edge of the display area DA may have a straight line shape.

[0178] A width Wb of the peripheral area PA surrounding the edge of the display area DA having a straight line shape may be greater than a width Wa of the peripheral area PA surrounding the edge of the display area DA having a circular shape. A pad electrically connected to a flexible printed circuit board (FPCB) may be arranged in the peripheral area PA surrounding the edge of the display area DA having a straight line shape. The FPCB may include a driver for driving an input sensing member (e.g., a touch panel). The area where the pad may be arranged may be a predetermined area or a set area between sub-driving circuits SC distributed in the peripheral area PA.

[0179] According to an embodiment, since a pixel circuit driving a display element includes a first thin film transistor TFT1 including a silicon semiconductor and a second thin film transistor TFT2 including an oxide semiconductor, a high-resolution display device with low power consumption may be provided.

[0180] According to an embodiment, the display device can reduce the area of ​​the peripheral area PA, and symmetrically arrange the driving circuits in the left peripheral area and the right peripheral area by arranging the driving circuits in lines in the peripheral area PA. The driving circuits can output different signals for driving the pixels PX, and the pixels PX have a mixture of thin film transistors including different semiconductors. The embodiments of the present disclosure are also applicable to the arrangement of driving circuits that output different signals for driving pixels, and the pixels include thin film transistors including a single semiconductor.

[0181] According to an embodiment, the display device may improve the arrangement of the driving circuit by allowing the output line to have directionality. The output line may connect the driving circuit to the signal line, and the signal line may be connected to the pixel PX.

[0182] According to an embodiment, by providing a portion of the peripheral area PA having a shape different from that of the display area DA, a display device having a reduced area in the peripheral area PA can be provided. The drive circuit may be arranged in the portion of the peripheral area PA (which is a peripheral area surrounding the display area DA). The portions of the peripheral area PA facing the display area DA may be symmetrical to each other in an embodiment, or may not be symmetrical to each other in another embodiment. In either case, the drive circuit and the integrated circuit chip may be arranged in the peripheral area PA so as to minimize or reduce the size (width) of the peripheral area PA.

[0183] According to an embodiment, since different driving circuits arranged around the display area DA may be mixedly distributed, a dead zone of the display device may be reduced. However, the scope of the present disclosure is not limited by such effects.

[0184] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes may be made in form and detail without departing from the scope and spirit as defined in the appended claims and their equivalents.

Claims

1. A display device, comprising: a plurality of pixels arranged in a display area having a non-quadrilateral shape; a first driving circuit, the first driving circuit comprising a plurality of first sub-driving circuits, each of the plurality of first sub-driving circuits outputting a first signal to the plurality of pixels; a second driving circuit, the second driving circuit comprising a plurality of second sub-driving circuits, each of the plurality of second sub-driving circuits outputting a second signal to the plurality of pixels; as well as a third driving circuit, the third driving circuit comprising a plurality of third sub-driving circuits, each of the plurality of third sub-driving circuits outputting a third signal to the plurality of pixels; The peripheral area outside the display area includes a first peripheral area and a second peripheral area, the first peripheral area and the second peripheral area are symmetrical to each other relative to the display area, and the display area is between the first peripheral area and the second peripheral area. The plurality of first sub-driving circuits and the plurality of second sub-driving circuits are alternately arranged in lines in the first peripheral area, The plurality of third sub-driving circuits are arranged in a line in the second peripheral area, and A sum of a size of a region where one of the plurality of first sub driving circuits is arranged and a size of a region where one of the plurality of second sub driving circuits is arranged is equal to a size of a region where one of the plurality of third sub driving circuits is arranged.

2. The display device according to claim 1, wherein: Each of the plurality of pixels includes a first thin film transistor, a second thin film transistor, and a third thin film transistor, each of the first thin film transistor and the second thin film transistor includes a silicon semiconductor, and the third thin film transistor includes an oxide semiconductor.

3. The display device according to claim 2, wherein: The plurality of first sub-driving circuits are connected to a first signal line, the first signal line is connected to a gate electrode of the first thin film transistor and extends in a first direction, The plurality of second sub-driving circuits are connected to a second signal line connected to a gate electrode of the second thin film transistor and extending in the first direction, and The plurality of third sub-driving circuits are connected to a third signal line connected to a gate electrode of the third thin film transistor and extending in the first direction.

4. The display device according to claim 3, wherein: Each of the plurality of pixels is connected to a fourth signal line extending in a second direction intersecting the first direction, The display device further includes: a fourth driving circuit including a plurality of fourth sub-driving circuits that output a fourth signal to one end of the fourth signal line; and a fifth driving circuit including a plurality of fifth sub-driving circuits that output a fifth signal to the other end of the fourth signal line, and The plurality of fourth sub driving circuits and the plurality of fifth sub driving circuits are distributed in the first peripheral area and the second peripheral area.

5. The display device according to claim 4, wherein: The plurality of fourth sub driving circuits and the plurality of fifth sub driving circuits are distributed among the plurality of first sub driving circuits, the plurality of second sub driving circuits, and the plurality of third sub driving circuits.

6. The display device according to claim 4, wherein: The plurality of fourth sub driving circuits and the plurality of fifth sub driving circuits are arranged between a plurality of pairs of the first sub driving circuits and the second sub driving circuits.

7. The display device according to claim 4, further comprising: A plurality of output lines are arranged in the peripheral region and connect the first to fourth signal lines to the plurality of first to fifth sub-driving circuits.

8. The display device according to claim 7, wherein: Each of the plurality of output lines includes a portion extending in a direction toward the center of the display area.

9. The display device according to claim 1, wherein: The peripheral area has a shape corresponding to a shape of an edge of the display area.

10. The display device according to claim 1, wherein: The peripheral area includes an area having a shape corresponding to a shape of an edge of the display area and an area having a shape different from the shape of the edge of the display area.

11. The display device according to claim 10, wherein: The width of the area of ​​the peripheral area having a shape different from the shape of the edge of the display area is smaller than the width of the area of ​​the peripheral area having a shape corresponding to the shape of the edge of the display area.

12. A display device, comprising: a plurality of signal lines extending in a first direction and arranged in a display area having a non-quadrilateral shape; a plurality of driving circuits arranged in a peripheral area outside the display area and outputting signals to the plurality of signal lines; as well as a plurality of output lines arranged in the peripheral region and connecting the plurality of drive circuits to the plurality of signal lines, wherein a plurality of sub-driving circuits included in each of the plurality of driving circuits are arranged in a line in the peripheral region, and Each of the plurality of output lines includes a portion extending in a direction toward a center of the display area, and Wherein, a virtual extension line of the portion of each of the plurality of output lines passes through the center of the display area.

13. The display device according to claim 12, wherein: The plurality of signal lines include a plurality of first signal lines, a plurality of second signal lines, and a plurality of third signal lines, The plurality of sub-driving circuits include a plurality of first sub-driving circuits outputting first signals to the plurality of first signal lines, a plurality of second sub-driving circuits outputting second signals to the plurality of second signal lines, and a plurality of third sub-driving circuits outputting third signals to the plurality of third signal lines. The peripheral area includes a first peripheral area and a second peripheral area, the first peripheral area and the second peripheral area are symmetrical to each other with respect to the display area, and the display area is between the first peripheral area and the second peripheral area, The plurality of first sub-driving circuits and the plurality of second sub-driving circuits are alternately arranged in lines in the first peripheral area, The plurality of third sub-driving circuits are arranged in a line in the second peripheral area, and A sum of a size of a region where one of the plurality of first sub driving circuits is arranged and a size of a region where one of the plurality of second sub driving circuits is arranged is equal to a size of a region where one of the plurality of third sub driving circuits is arranged.

14. The display device according to claim 13, wherein: The plurality of signal lines further include a plurality of fourth signal lines extending in a second direction intersecting the first direction and arranged in the display area, The plurality of sub-driving circuits further include a plurality of fourth sub-driving circuits that output a fourth signal to an end of the fourth signal line and a plurality of fifth sub-driving circuits that output a fifth signal to the other end of the fourth signal line, and The plurality of fourth sub driving circuits and the plurality of fifth sub driving circuits are distributed in the first peripheral area and the second peripheral area.

15. The display device according to claim 14, wherein: The plurality of fourth sub driving circuits and the plurality of fifth sub driving circuits are distributed among the plurality of first sub driving circuits, the plurality of second sub driving circuits, and the plurality of third sub driving circuits.

16. The display device according to claim 14, wherein: The plurality of fourth sub driving circuits and the plurality of fifth sub driving circuits are arranged between a plurality of pairs of the first sub driving circuits and the second sub driving circuits.

17. The display device according to claim 12, wherein: The peripheral area has a shape corresponding to a shape of an edge of the display area.

18. The display device according to claim 12, wherein: The peripheral area includes an area having a shape corresponding to a shape of an edge of the display area and an area having a shape different from the shape of the edge of the display area.

19. The display device according to claim 18, wherein: The width of the area of ​​the peripheral area having a shape different from the shape of the edge of the display area is smaller than the width of the area of ​​the peripheral area having a shape corresponding to the shape of the edge of the display area.

20. The display device according to claim 12, wherein: A plurality of pixels connected to the plurality of signal lines are arranged in the display area, and Each of the plurality of pixels includes a first thin film transistor, a second thin film transistor, and a third thin film transistor, each of the first thin film transistor and the second thin film transistor includes a silicon semiconductor, and the third thin film transistor includes an oxide semiconductor.

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