Storage device and operation method thereof

Abstract

A memory device includes: a board including a plurality of word lines, a plurality of bit lines, and memory cells connected to a first word line among the plurality of word lines and a first bit line among the plurality of bit lines; a row decoder configured to bias at least one word line among the word lines that is adjacent to the first word line and to float the remaining non-adjacent word lines among the plurality of word lines that are not adjacent to the first word line in an access operation associated with the memory cells; and a column decoder configured to bias at least one bit line among the bit lines that is adjacent to the first bit line and to float the remaining non-adjacent bit lines among the plurality of bit lines that are not adjacent to the first bit line in an access operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0091004 filed on July 26, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concepts described herein relate to a memory device, and more particularly, to a nonvolatile memory device for controlling unselected memory cells according to proximity to a selected memory cell, and a method for operating the nonvolatile memory device. Background Art

[0004] Semiconductor memories may include nonvolatile memories such as phase change memories, ferroelectric memories, magnetic memories, resistive memories, and flash memories, etc. Specifically, among nonvolatile memories, phase change memories perform a write operation by changing the resistance value of a memory cell by applying an electric current, and perform a read operation by applying another electric current.

[0005] When a read operation or a write operation is performed on a selected memory cell, an off current may flow into an unselected memory cell adjacent to the selected memory cell due to leakage of a programming current. However, the leakage of the programming current reduces a sensing margin of the selected memory cell. Summary of the invention

[0006] At least one embodiment of the inventive concept provides a nonvolatile memory device for controlling unselected memory cells according to proximity to a selected memory cell, and a method for operating the nonvolatile memory device.

[0007] According to an exemplary embodiment of the present invention, a memory device includes: a bay including a plurality of word lines, a plurality of bit lines, and memory cells connected to a first word line of the plurality of word lines and a first bit line of the plurality of bit lines; a row decoder configured to bias at least one of the word lines adjacent to the first word line to a level of a first non-selected row voltage and float the remaining non-adjacent word lines of the plurality of word lines that are not adjacent to the first word line to a level of a second non-selected row voltage in an access operation associated with the memory cells; and a column decoder configured to bias at least one of the bit lines adjacent to the first bit line to a level of a first non-selected column voltage and float the remaining non-adjacent bit lines of the plurality of bit lines that are not adjacent to the first bit line to a level of a second non-selected column voltage in the access operation.

[0008] According to an exemplary embodiment of the present invention, a memory device includes: a memory cell array including first to third word lines, first to third bit lines, and memory cells connected to the first word lines and the first bit lines, wherein the second word line is inserted between the first word line and the third word line, and the second bit line is inserted between the first bit line and the third bit line; a row driver configured to output a first selection row voltage, a first non-selection row voltage, and a second non-selection row voltage; a column driver configured to output a first selection column voltage, a first non-selection column voltage, and a second non-selection column voltage; voltage; a row decoder configured to apply the first selection row voltage to the first word line, bias the second word line to the level of the first non-selection row voltage, and float the third word line to the level of the second non-selection row voltage in a write operation; a column decoder configured to apply the first selection column voltage to the first bit line, bias the second bit line to the level of the first non-selection column voltage, and float the third bit line to the level of the second non-selection column voltage in a read operation; and a sense amplifier configured to sense the level of the read voltage of the first word line in the read operation.

[0009] According to an exemplary embodiment conceived in the present invention, a method for performing a read operation on a memory cell connected to a first word line and a first bit line in a memory device includes: precharging the first word line to the level of a first selection row voltage; floating the first word line; precharging the first bit line to the level of a first selection column voltage; biasing the second bit line to the level of a first non-selection column voltage, and floating the third bit line to the level of a second non-selection column voltage; floating the first bit line; and sensing the level of a read voltage of the first word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The inventive concept will become apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept.

[0012] Figure 2 It is shown Figure 1 A circuit diagram of a memory cell of a memory cell array.

[0013] Figure 3 It is shown that the Figure 1 A block diagram of an example of a memory cell array in a memory device.

[0014] Figure 4 is shown in detail for describing a read operation of a memory device according to an exemplary embodiment of the inventive concept. Figure 1Circuit diagram of a memory device.

[0015] Figure 5A and Figure 5B is shown applied to Figure 4 A graph of the voltages of the word lines, bit lines, and transistors in a circuit diagram of FIG.

[0016] Figure 6 is shown in detail for describing a write operation of a memory device according to an exemplary embodiment of the inventive concept. Figure 1 Circuit diagram of a memory device.

[0017] Fig. 7A and Figure 7B is shown applied to Figure 6 A graph of the voltages of the word lines, bit lines, and transistors in a circuit diagram of FIG.

[0018] Figure 8 is shown in detail for describing a read operation of a memory device according to an exemplary embodiment of the inventive concept. Figure 1 Circuit diagram of a memory device.

[0019] Fig. 9 Shown for description Figure 8 A graph showing voltages of word lines and bit lines and currents flowing into memory cells connected to the word lines and bit lines in a circuit diagram of FIG.

[0020] Fig.10 is a flowchart illustrating a method of a read operation of a memory device according to an exemplary embodiment of the inventive concept.

[0021] Fig.11 It is shown that the Figure 1 A block diagram of another example of a memory cell array in a memory device.

[0022] Fig.12 An example of a structure of a memory cell array according to an exemplary embodiment of the inventive concept is shown.

[0023] Fig.13 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept.

[0024] Fig.14 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept.

[0025] Fig.15 is a block diagram illustrating an electronic device to which a memory device according to an exemplary embodiment of the inventive concept is applied.

[0026] Fig.16 is a block diagram illustrating a computing system according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0027] Exemplary embodiments of the inventive concept will be described below in detail and clearly to the extent that a person having ordinary skill in the art can implement the inventive concept.

[0028] Figure 1 1 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept. The memory device 100 includes a memory cell array 110, a row decoder 120 (e.g., a decoder circuit), a row driver 130 (e.g., a driver circuit), a sense amplifier 140, a column decoder 150 (e.g., a decoder circuit), a column driver 160 (e.g., a driver circuit), and a read / write control circuit 170.

[0029] The memory cell array 110 may include first to third word lines WL1 to WL3 and first to third bit lines BL1 to BL3. The second word line WL2 is inserted between the first word line WL1 and the third word line WL3, and the second bit line BL2 is inserted between the first bit line BL1 and the third bit line BL3. For example, the memory cell array 110 may be a cross-point memory cell array. The memory cell array 110 may include a memory cell MC connected between the first word line WL1 and the first bit line BL1. The memory cell MC may be a dynamic random access memory (DRAM) cell, a static RAM (SRAM) cell, a phase change RAM (PRAM) cell, a resistance RAM (ReRAM) cell, a ferroelectric RAM (FeRAM) cell, a thyristor RAM (TRAM) cell, or a magnetic RAM (MRAM) cell, but the inventive concept is not limited thereto. The number of word lines WL1 to WL3 and the number of bit lines BL1 to BL3 are merely examples. For example, there may be more or less than three word lines and more or less than three bit lines.

[0030] The row decoder 120 may apply a word line voltage to the first to third word lines WL1 to WL3 in a read operation or a write operation of the memory device 100. The row decoder 120 may precharge the first to third word lines WL1 to WL3 using the applied word line voltage. The voltage to be applied to the first to third word lines WL1 to WL3 may be output from the row driver 130, and the row decoder 120 may selectively apply the voltage to the first to third word lines WL1 to WL3. The row decoder 120 may bias or float the first to third word lines WL1 to WL3 in a read operation or a write operation of the memory device 100. The row driver 130 may drive the first to third word lines WL1 to WL3. The row driver 130 may output a voltage to be applied to the first to third word lines WL1 to WL3. The row decoder 120 may bias the first to third word lines WL1 to WL3 to set them to the level of the voltage output from the row driver 130 . The row decoder 120 may float the first to third word lines WL1 to WL3 at the level of the voltage output from the row driver 130 .

[0031] In a read operation, the sense amplifier 140 senses the level of a read voltage (or the level of a read current) of another one of the first to third word lines WL1 to WL3. The sensing result of the sense amplifier 140 may indicate data stored in the memory cell array 110. For example, the sense amplifier 140 may compare the read voltage with a reference voltage to determine the state of a memory cell in the memory cell array, and the state may indicate the value of the data. The sense amplifier 140 may be selectively connected to the first to third word lines WL1 to WL3 through the row decoder 120 and the row driver 130. The selective connection between the sense amplifier 140 and the first to third word lines WL1 to WL3 is combined with the sense amplifier 140 to generate a sense signal. Figure 8 Detailed components of the row driver 130 shown in FIG. 1 are fully described together.

[0032] The column decoder 150 may apply a bit line voltage to the first bit line BL1 to the third bit line BL3 in a read operation or a write operation of the memory device 100. The column decoder 150 may precharge the first bit line BL1 to the third bit line BL3 using the applied bit line voltage. The voltage to be applied to the first bit line BL1 to the third bit line BL3 may be output from the column driver 160, and the column decoder 150 may selectively apply the voltage to the first bit line BL1 to the third bit line BL3. The column decoder 150 may bias or float the first bit line BL1 to the third bit line BL3 in a read operation or a write operation of the memory device 100. The column driver 160 may drive the first bit line BL1 to the third bit line BL3. The column driver 160 may output a voltage to be applied to the first bit line BL1 to the third bit line BL3. The column decoder 150 may bias the first bit line BL1 to the third bit line BL3 to the level of the voltage output from the column driver 160. The column decoder 150 may float the first to third bit lines BL1 to BL3 to the level of a voltage output from the column driver 160 .

[0033] The read / write control circuit 170 controls the row decoder 120, the row driver 130, the sense amplifier 140, the column decoder 150, and the column driver 160. The read / write control circuit 170 may control the bias or floating of the first to third word lines WL1 to WL3 through the row decoder 120, and may control the bias or floating of the first to third bit lines BL1 to BL3 through the column decoder 150. For example, when the memory cell MC connected to the first word line WL1 and the first bit line BL1 is a selected memory cell (or a read object cell or a write object cell), the read / write control circuit 170 can allow the row decoder 120 to bias the second word line WL2 (or adjacent word line) adjacent to the first word line WL1, can allow the row decoder 120 to float the third word line WL3 (or non-adjacent word line) not adjacent to the first word line WL1, can allow the column decoder 150 to bias the second bit line BL2 (or adjacent bit line) adjacent to the first bit line BL1, and can allow the column decoder 150 to float the third bit line BL3 (or non-adjacent bit line) not adjacent to the first bit line BL1.

[0034] The read / write control circuit 170 may allow the row decoder 120 to selectively bias or float the first to third word lines WL1 to WL3, and may allow the column decoder 150 to selectively bias or float the first to third bit lines BL1 to BL3. The read / write control circuit 170 may control the voltage output by the row driver 130 or the column driver 160. The read / write control circuit 170 may allow the row decoder 120 to selectively apply the word line voltage to the first to third word lines WL1 to WL3, and may allow the column decoder 150 to selectively apply the bit line voltage to the first to third bit lines BL1 to BL3. In a read operation or a write operation, the read / write control circuit 170 may control the level of the voltage applied to the first to third word lines WL1 to WL3 and the first to third bit lines BL1 to BL3, the time of applying the voltage, and the order of applying the voltage.

[0035] In a read operation of the memory device 100, when a memory cell MC (or a selected memory cell) connected to a first word line WL1 (or a selected word line) and a first bit line BL1 (or a selected bit line) is a read target cell, the read / write control circuit 170 may allow the column decoder 150 to apply a selection voltage (or a selection column voltage) output from the column driver 160 to the first bit line BL1 connected to the memory cell MC. The selection voltage may have a level of a voltage for precharging the first bit line BL1, and the following will refer to Figure 5A and Figure 5B To describe the precharge in the read operation. The column driver 160 may output a non-selected column voltage (or bias voltage or floating voltage) for biasing or floating the unselected bit lines BL2 and BL3. In the read operation, the column decoder 150 may bias or float the second bit line BL2 and the third bit line BL3 at the level of the non-selected column voltage. The sense amplifier 140 may sense the level of the read voltage of the first word line WL1, which is determined according to the current of the memory cell MC responding to the selection voltage. The read / write control circuit 170 may read the data stored in the selected memory cell MC based on the sensing result of the sense amplifier 140. For example, the sensing result may be compared with a reference voltage to determine the value of the data read.

[0036] In a write operation of the memory device 100, when a memory cell MC (or a selected memory cell) connected to a first word line WL1 (or a selected word line) and a first bit line BL1 (or a selected bit line) is a write target cell, the read / write control circuit 170 may allow the row decoder 120 to apply a selection voltage (or a selection row voltage) output from the row driver 130 to the first word line WL1 connected to the memory cell MC. The selection voltage may have a level of a voltage for precharging the first word line WL1, and will be referred to below. Fig. 7A and Figure 7B Describe the precharge in the write operation. The row driver 130 may output a non-selected row voltage (or bias voltage or floating voltage) for biasing or floating the unselected word lines WL2 and WL3. In the write operation, the row decoder 120 may bias or float the second word line WL2 and the third word line WL3 at the level of the non-selected row voltage. The selected memory cell MC may store data in response to the selection voltage.

[0037] Figure 2 It is shown Figure 1 A circuit diagram of a memory cell array of a memory cell. Figure 2 , the memory cell MC may include a resistance element “R” and a selection element “S” connected to the word line WL1 and the bit line BL1 .

[0038] In an exemplary embodiment, the resistance element "R" includes a phase change material whose state changes according to the amount of current applied thereto. Depending on an electrical signal, Joule heat, or a temperature applied to the memory cell MC1, the phase change material may have a high resistance state corresponding to an amorphous state, or a low resistance state corresponding to a crystalline state. For example, the resistance element "R" may include a chalcogenide material (e.g., Ge2Sb2Te5 (GST)).

[0039] The selection element "S" can control the current supplied to the resistance element "R" based on the voltage applied to the bit line BL1 and the word line WL1. The selection element "S" can be connected between the resistance element "R" and the bit line BL1, and the resistance element "R" can be connected between the word line WL1 and the selection element "S". The position of the selection element "S" and the position of the resistance element "R" can be interchanged. For example, the selection element "S" can be a diode element or a bidirectional threshold switch (OTS) element having bidirectional characteristics, and the selection element "S" can include a chalcogenide material. The OTS element can be determined by a threshold voltage (hereinafter referred to as Fig. 9 Vth) and the switching voltage (shown below Fig. 9 That is, the threshold voltage and the switching voltage may be unique parameters of the OTS element. In the case where the selection element "S" is an OTS element, the performance of the memory device 100 may be reduced due to the leakage current flowing at the memory cell MC.

[0040] Figure 3 It is shown that the Figure 1 A block diagram of an example of a memory cell array in a memory device of FIG. Figure 1 describe Figure 3The memory cell array 110a includes first to s-th word lines WL1 to WLs (s is an integer of 6 or greater), first to t-th bit lines BL1 to BLt (t is an integer of 10 or greater), and memory cells MC11 to MCst (e.g., MC11 to MC1t, MC21 to MC2t, MC31 to MC3t, MC41 to MC4t, MC51 to MC5t, MCs1 to MCst). Figure 3 Reference for describing division of a plurality of memory cells MC11 to MCst in a read operation or a write operation. However, the inventive concept is not limited thereto, as the number of memory cells MC11 to MCst, the number of word lines WL1 to WLs, and the number of bit lines BL1 to BLt shown are only examples.

[0041] In a read operation or a write operation of the memory device 100, the bit line BL5 and the word line WL3 are respectively the selected bit line and the selected word line. The bit line BL4 is adjacent to the selected bit line BL5 in the direction D1. The bit line BL6 is adjacent to the selected bit line BL5 in the direction D2. The word line WL2 is adjacent to the selected word line WL3 in the direction D3. The word line WL4 is adjacent to the selected word line WL3 in the direction D4.

[0042] In a read operation or a write operation of the memory device 100, the row decoder 120 may bias the word lines WL2 and WL4 to be set to the level of the voltage output from the row driver 130, and may float the word lines WL1 and WL5 to WLs at the level of the voltage output from the row driver 130. In a read operation or a write operation of the memory device 100, the column decoder 150 may bias the bit lines BL4 and BL6 to be set to the level of the voltage output from the column driver 160, and may float the bit lines BL1 to BL3 and the bit lines BL7 to BLt at the level of the voltage output from the column driver 160. That is, the number of word lines WL2 and WL4 biased from the unselected word lines WL1, WL2, and WL4 to WLs may be 2, and the number of bit lines BL4 and BL6 biased from the unselected bit lines BL1 to BL4 and BL6 to BLt may be 2. However, the inventive concept is not limited to the above numerical values.

[0043] exist Figure 3, a plurality of memory cells MC11 to MCst include an A memory cell MC35; B memory cells MC15, MC25, MC31 to MC34, MC36 to MC3t, and MC45 to MCs5; C1 memory cells MC24, MC26, MC44, and MC46; and C2 memory cells MC11 to MC14, MC16 to MC1t, MC21 to MC23, MC27 to MC2t, MC41 to MC43, MC47 to MC4t, MC51 to MC54, MC56 to MC5t, MCs1 to MCs4, and MCs6 to MCst. The A memory cell MC35 is a selected memory cell. The A memory cell MC35 is connected to a selected word line WL3 and a selected bit line BL5. The memory device 100 is configured to read data from the A memory cell MC35 or write data to the A memory cell MC35.

[0044] B memory cells MC15, MC25, MC31 to MC34, MC36 to MC3t and MC45 to MCs5 are connected to unselected word lines WL1, WL2 and WL4 to WLs and a selected bit line BL5, or to a selected word line WL3 and unselected bit lines BL1 to BL4 and BL6 to BLt. B memory cells MC15, MC25, MC31 to MC34, MC36 to MC3t and MC45 to MCs5 include: memory cells MC34 and MC36 connected to the selected word line WL3 and the biased bit line BL4 and bit line BL6; memory cells MC31 to MC33 and MC37 to MC3t connected to the selected word line WL3 and the floating bit lines BL1 to BL3 and BL7 to BLt; memory cells MC25 and MC45 connected to the selected bit line BL5 and the biased word lines WL2 and WL4; and memory cells MC15 and MC55 to MCs5 connected to the selected bit line BL5 and the floating word line WL1 and word lines WL5 to WLs.

[0045] C1 memory cells MC24, MC26, MC44 and MC46 and C2 memory cells MC11 to MC14, MC16 to MC1t, MC21 to MC23, MC27 to MC2t ... MCs1 to MCs4 and MCs6 to MCst are connected to unselected word lines WL1, WL2, WL4 to WLs and unselected bit lines BL1 to BL4 and BL6 to BLt. C1 memory cells MC24, MC26, MC44 and MC46 are connected to biased word lines WL2 and WL4 and biased bit lines BL4 and BL6. C2 memory cells MC11 to MC14, MC16 to MC1t, MC21 to MC23, MC27 to MC2t, MCs1 to MCs4, and MCs6 to MCst include: memory cells MC21 to MC23, MC27 to MC2t, MC41 to MC43, and MC47 to MC4t connected to biased word lines WL2 and WL4 and floating bit lines BL1 to BL3 and BL7 to BLt; memory cells MC11 to MC14, MC16 to MC1t, MC21 to MC23, MC27 to MC2t, MC41 to MC43, and MC47 to MC4t connected to floating word lines WL1 and Memory cells MC14, MC16, MC54, MC56...MCs and MCs6 of WL5 to WLs and biased bit lines BL4 and BL6; and memory cells MC11 to MC13, MC17 to MC1t, MC51 to MC53, MC57 to MC5t...MCs1 to MCs3 and MCs7 to MCst connected to floating word lines WL1 and WL5 to WLs and floating bit lines BL1 to BL3 and BL7 to BLt.

[0046] Due to leakage of current flowing at the selected memory cell MC35 in a read operation or a write operation, an off current (or leakage current) may flow through unselected memory cells (the remaining memory cells except the memory cell MC35) in the memory cell array 110. Figure 3 As shown, the leakage current flowing through the unselected memory cells can be significantly reduced by biasing the unselected word lines WL2 and WL4 adjacent to (or closest to, adjacent to, or closest to) the selected word line WL3 and the unselected bit lines BL4 and BL6 adjacent to (or closest to, adjacent to, or closest to) the selected bit line BL5, and by floating the remaining unselected word lines WL1 and WL5 to WLs (or the remaining non-adjacent word lines) and the remaining unselected bit lines BL1 to BL3 and BL7 to BLt (or the remaining non-adjacent bit lines). In addition, the power consumption of the memory device 100 for biasing can be reduced by minimizing the number of biased word lines and the number of biased bit lines.

[0047] Figure 4 is shown in detail for describing a read operation of a memory device according to an exemplary embodiment of the inventive concept. Figure 1 The circuit diagram of the memory device will be referenced Figure 1 The memory device 100 and Figure 3 The memory cell array 110a is described as follows Figure 4 A memory device 100a is provided. The memory cell array 110 includes a selected word line WL3, a selected bit line BL5, unselected bit lines BL6 and BL7, a selected memory cell MC35, and unselected memory cells MC36 and MC37. The row decoder 120 includes transistors Tpw3 and Tnw3. The column decoder 150 includes transistors Tpb5 to Tpb7 and Tnb5 to Tnb7. The transistors Tpb5 to Tpb7, Tnb5 to Tnb7, Tpw3, and Tnw3 can be used to precharge, bias, or float the word line WL3 or the bit lines BL5 to BL7. For example, the transistors Tnb5 to Tnb7, Tnw3 can be NMOS transistors, and the transistors Tpb5 to Tpb7 and Tpw3 can be PMOS transistors.

[0048] In the row decoder 120, first terminals (e.g., source terminals) of transistors Tpw3 and Tnw3 are connected to the row driver 130. Second terminals (e.g., drain terminals) of transistors Tpw3 and Tnw3 are connected to the word line WL3. Third terminals (e.g., gate terminals) of transistors Tpw3 and Tnw3 are connected to the read / write control circuit 170.

[0049] In the column decoder 150, first terminals (e.g., source terminals) of transistors Tpb5 to Tpb7 and Tnb5 to Tnb7 are connected to the column driver 160. Second terminals (e.g., drain terminals) of transistors Tpb5 and Tnb5 are connected to the bit line BL5. Second terminals (e.g., drain terminals) of transistors Tpb6 and Tnb6 are connected to the bit line BL6. Second terminals (e.g., drain terminals) of transistors Tpb7 and Tnb7 are connected to the bit line BL7. Third terminals (e.g., gate terminals) of transistors Tpb5 to Tpb7 and Tnb5 to Tnb7 are connected to the read / write control circuit 170.

[0050] The row driver 130 outputs a voltage Vpw3 to be applied to a first terminal (e.g., source terminal) of the transistor Tpw3. The column driver 160 outputs voltages Vpb5 to Vpb7 and Vn5 to Vn7 to be applied to first terminals (e.g., source terminals) of the transistors Tpb5 to Tpb7 and Tnb5 to Tnb7. In an exemplary embodiment, the voltages Vpw3, Vpb5 to Vpb7, and Vn5 to Vn7 are power supply voltages. The power supply voltages Vpw3, Vpb5 to Vpb7, and Vn5 to Vn7 may be generated by the row driver 130, or may be generated by any other component (e.g., by referring to Fig.14In order to control the precharge, bias, or floating of the word line WL3, the read / write control circuit 170 may output the voltages Gpw3 and Gnw3 to be applied to the third terminals (e.g., gate terminals) of the transistors Tpw3 and Tnw3 in the row decoder 120. In order to control the precharge, bias, or floating of the bit lines BL5 to BL7, the read / write control circuit 170 may output the voltages Gpb5 to Gpb7 and Gnb5 to Gnb7 to be applied to the third terminals (e.g., gate terminals) of the transistors Tpb5 to Tpb7 and Tnb5 to Tnb7 in the column decoder 150. Figure 5A and Figure 5B The gate voltages Gpb5 to Gpb7 , Gnb5 to Gnb7 , Gpw3 , and Gnw3 of the transistors Tpb5 to Tpb7 , Tnb5 to Tnb7 , Tpw3 , and Tnw3 will be described more fully.

[0051] Figure 5A and Figure 5B is shown applied to Figure 4 The circuit diagram of FIG. 1 is a graph of the voltages of the word line, the bit line, and the transistor in FIG. The circuit diagram of FIG. 1 is described based on the time period t00 to t01 (standby phase), the time period t01 to t02 (selected word line precharge phase), the time period t02 to t04 (selected bit line precharge phase), and the time period t04 to t05 (sensing phase). Figure 5A and Figure 5B The curve graph of Figure 5A and Figure 5B , the horizontal axis represents time and the vertical axis represents voltage.

[0052] In the time period t00 to t01 (standby phase), the memory device 100a stands by for access operation (e.g., read operation). In the standby phase, the memory device 100a may wait for a read command from an external device (e.g., a host). In the standby phase, the voltages Gpb5 to Gpb7 and Gpw3 applied to the gates of the transistors Tpb5 to Tpb7 and Tpw3 have a logic high (or logic "1") level, and the voltages Gnb5 to Gnb7 and Gnw3 applied to the gates of the transistors Tnb5 to Tnb7 and Tnw3 have a logic low (or logic "0") level. The voltage VWL3 of the selected word line WL3 is a voltage level Vwr1. The voltages VBL5 to VBL7 of the bit lines BL5 to BL7 are voltage levels Vbr1. For example, the voltage levels Vbr1 and Vwr1 may be 0V. In an exemplary embodiment, the transistors Tpw3 and Tnw3 are turned off during the standby phase.

[0053] In the time period t01 to t02 (selected word line precharge phase), in order to precharge the selected word line WL3, the voltages Gpw3 and Gnw3 applied to the gates of the transistors Tpw3 and Tnw3 connected to the selected word line WL3 are logic high (or logic "1") levels. The voltage VWL3 of the selected word line WL3 may change from the voltage level Vwr1 to the voltage level Vwr2 (e.g., it may be reduced when Vwr1>Vwr2). Therefore, the selected word line WL3 may be precharged to the voltage level Vwr2 at time t02. For example, before the end of the precharge phase, the selected word line WL3 may reach the voltage level Vwr2. In an exemplary embodiment, during the precharge of the selected word line WL3, the voltage VBL5 of the selected bit line BL5 and the voltages Gpb5 and Gnb5 to be applied to the gates of the transistors Tpb5 and Tnb5 connected to the selected bit line BL5 are the same as those in the standby phase. In an exemplary embodiment, during a selected word line precharge phase, the transistor Tpw3 is turned off and the transistor Tnw3 is turned on, so the selected word line WL3 may receive a precharge voltage from the row driver 130 .

[0054] In the time period t01 to t02 (the selected word line precharge phase), the voltages Gpb6 and Gnb6 to be applied to the gates of the transistors Tpb6 and Tpn6 connected to the unselected bit line BL6 adjacent to the selected bit line BL5 are respectively at the levels of logic low (or logic "0") and logic high (or logic "1"), and the voltage VBL6 of the unselected bit line BL6 is the voltage level Vbr4. Here, the voltage level Vbr4 may be referred to as the "level of the bias voltage". For example, the voltage level Vbr4 may be 0V. In this case, the voltage level Vbr4 may be referred to as the "zero bias voltage level". In an exemplary embodiment, the unselected bit line BL6 is biased to the voltage level Vbr4 starting from time t01. However, the time t01 at which the biasing of the unselected bit line BL6 starts is merely an example. Figure 5B Differently, the unselected bit line BL6 can maintain the standby stage in the period t01 to t02 (the selected word line precharge stage).

[0055] In the time period t01 to t02 (selected word line precharge phase), the voltages Gpb7 and Gnb7 to be applied to the gates of transistors Tpb7 and Tpn7 connected to the unselected bit line BL7 which is not adjacent to the selected bit line BL5 are at a logic high (or logic "1") level, and the voltage VBL7 of the unselected bit line BL7 can change from the voltage level Vbr1 to the voltage level Vbr3 (for example, can be reduced when Vbr1>Vbr3).

[0056] In the time period t02 to t04 (selected bit line precharge phase), in order to precharge the selected bit line BL5, the voltage to be applied to the gates of the transistors Tpb5 and Tnb5 connected to the selected bit line BL5 is a logic low (or logic "0") level. The voltage VBL5 of the selected bit line BL5 can change from the voltage level Vbr1 to the voltage level Vbr2 (for example, it can be increased when Vbr2>Vbr1). Therefore, the selected bit line BL5 can be precharged to the voltage level Vbr2 at time t04. During the selected bit line precharge phase before time t04, the selected bit line BL5 can reach the voltage Vbr2. The voltage level Vbr2 can be referred to as "the level of the selected column voltage to be applied to the selected bit line BL5 to read the data stored in the selected memory cell MC35". During at least a portion of the time period t03 to t04 during which the selected bit line BL5 is precharged, the voltage Gpw3 to be applied to the gate of the transistor Tpw3 is a logic high (or logic "1") level, and the voltage Gnw3 to be applied to the gate of the transistor Tnw3 is a logic low (or logic "0") level. Therefore, during at least a portion of the time period t03 to t04 during which the selected bit line BL5 is precharged, the selected word line WL3 at the voltage level Vwr2 is floated. For example, in the case where time t03 is the same as time t02, the selected word line WL3 at the voltage level Vwr2 may be floated during the time period t02 to t04 during which the selected bit line BL5 is precharged. The voltage VWL3 of the selected word line WL3 during the time period t03 to t04 may be the same as the voltage VWL2 of the selected word line WL3. Fig. 9 The voltage VWLon and VWLoff.ideal (which will be described later) of the word line WL3 in the period t22 to t26 are the same.

[0057] In the period t02 to t04 (selected bit line precharge phase), the unselected bit line BL6 is biased to the voltage level Vbr4. Figure 5A and Figure 5B Unlike the example shown in FIG. 1 , the biasing of the unselected bit line BL6 may be started at any time between time t02 and time t04. For example, the biasing of the unselected bit line BL6 may be started at time t03 between time t02 and time t04.

[0058] During the time period t02 to t04 (the selected bit line precharge phase), the voltage Gpb7 to be applied to the gate of the transistor Tpb7 is a logic high (or logic "1") level, and the voltage Gnb7 to be applied to the gate of the transistor Tnb7 is a logic low (or logic "0") level. Therefore, during the time period t02 to t04 when the selected bit line BL5 is precharged, the selected bit line BL7, which is at the voltage level Vbr3 and is not adjacent to the selected bit line BL5, is floated. Here, the voltage level Vbr3 may be referred to as the "floating voltage level". In an exemplary embodiment, during the selected bit line precharge phase, the transistors Tpb7 and Tnb7 are turned off to float the selected bit line BL5. However, the time t02 at which the floating of the unselected bit line BL7 starts is merely an example. Figure 5A and Figure 5B Unlike the example shown in FIG. 1 , the floating of the unselected bit line BL7 may start at any time between time t02 and time t04. For example, the floating of the unselected bit line BL7 may start at time t03 between time t02 and time t04.

[0059] In the time period t04 to t05 (sensing phase), the sense amplifier 140 senses the read voltage level of the selected word line WL3. The voltages Gpw3 and Gnw3 to be applied to the gates of the transistors Tpw3 and Tnw3 are at a logic high (or logic "1") level. Since the voltage Gnw3 is applied to the gate of the transistor Tnw3 at a logic high, the transistor Tnw3 is turned on, and the sense amplifier 140 is connected to the selected word line WL3 through the turned-on transistor Tnw3, which will refer to Figure 8 In addition, in the sensing phase, the selected word line WL3 floating at the voltage level Vwr2 may maintain a floating state. The voltage VWL3 of the selected word line WL3 in the time period t04 to t05 may be the same as Fig. 9 The voltage VWLon and VWLoff.ideal (which will be described later) of the word line WL3 in the time period t26 to t27 are the same. In an exemplary embodiment, during the sensing phase, the transistor Tpw3 is turned off and the transistor Tnw3 is turned on.

[0060] During the time period t04 to t05 (sensing phase), the voltage Gpb5 to be applied to the gate of the transistor Tpb5 is a logic high (or logic "1") level, and the voltage Gnb5 to be applied to the gate of the transistor Tnb5 is a logic low (or logic "0") level. In the time period t04 to t05 (sensing phase), the selected bit line BL5 is floated. In an exemplary embodiment, the transistor Tpb5 and the transistor Tnb5 are turned off during the sensing phase to float the selected bit line BL5. When the selected bit line BL5 floats, the voltage VBL5 of the selected bit line BL5 can change from the voltage level Vbr2 to the voltage level Vbr1 (for example, when Vbr2>Vbr1, it can be reduced). In the time period t04 to t05 (sensing phase), the unselected bit line BL6 adjacent to the selected bit line BL5 can be maintained in a biased state, wherein the unselected bit line BL6 is set to the voltage level Vbr4. The unselected bit line BL7 not adjacent to the selected bit line BL5 may be maintained in a floating state, wherein the unselected bit line BL7 at the voltage level Vbr3 is floated. The time when the biasing of the bit line BL6 and the floating of the bit line BL7 are completed and the time when the sensing phase is completed may be time t05. That is, the time when the biasing of the bit line BL6 and the floating of the bit line BL7 are completed may be the same as the time when the sensing phase is completed.

[0061] Figure 6 is shown in detail for describing a write operation of a memory device according to an exemplary embodiment of the inventive concept. Figure 1 The circuit diagram of the memory device will be referenced Figure 1 The memory device 100 and Figure 3 The memory cell array 110a is described as follows Figure 6 The memory device 100b of the present invention is a memory device 100b. The memory cell array 110 includes a selected bit line BL5, a selected word line WL3, unselected word lines WL4 and WL5, a selected memory cell MC35, and unselected memory cells MC45 and MC55. The row decoder 120 includes transistors Tpw3 to Tpw5 and Tnw3 to Tnw5. The column decoder 150 includes transistors Tpb5 and Tnb5. The transistors Tpw3 to Tpw5, Tnw3 to Tnw5, Tpb5, and Tnb5 can be used to precharge, bias, or float the bit line BL5 or the word lines WL3 to WL5. For example, the transistors Tnw3 to Tnw5, Tnb5 can be NMOS transistors, and the transistors Tpw3 to Tpw5 and Tpb5 can be PMOS transistors.

[0062] In the row decoder 120, first terminals (e.g., source terminals) of transistors Tpw3 to Tpw5 and Tnw3 to Tnw5 are connected to the row driver 130. Second terminals (e.g., drain terminals) of transistors Tpw3 and Tnw3 are connected to the word line WL3. Second terminals (e.g., drain terminals) of transistors Tpw4 and Tnw4 are connected to the word line WL4. Second terminals (e.g., drain terminals) of transistors Tpw5 and Tnw5 are connected to the word line WL5. Third terminals (e.g., gate terminals) of transistors Tpw3 to Tpw5 and Tnw3 to Tnw5 are connected to the read / write control circuit 170.

[0063] In the column decoder 150, first terminals (e.g., source terminals) of transistors Tpb5 and Tnb5 are connected to the column driver 160. Second terminals (e.g., drain terminals) of transistors Tpb5 and Tnb5 are connected to the bit line BL5. Third terminals (e.g., gate terminals) of transistors Tpb5 and Tnb5 are connected to the read / write control circuit 170.

[0064] The row driver 130 outputs voltages Vpw3 to Vpw5 to be applied to first terminals (e.g., source terminals) of transistors Tpw3 to Tpw5. The column driver 160 outputs voltages Vpb5 and Vn5 to be applied to first terminals (e.g., source terminals) of transistors Tpb5 to Tnb5. In an exemplary embodiment, the voltages Vpb5, Vn5, and Vpw3 to Vpw5 are power supply voltages. The power supply voltages Vpb5, Vn5, and Vpw3 to Vpw5 may be generated by the row driver 130, or may be generated by another component (e.g., by converting a reference Fig.14 The voltage generator 338 described above is generated. In order to control the precharging, biasing, or floating of the bit line BL5, the read / write control circuit 170 can output the voltages Gpb5 and Gnb5 to be applied to the third terminals (e.g., gate terminals) of the transistors Tpb5 and Tnb5 in the column decoder 150. In order to control the precharging, biasing, or floating of the word lines WL3 to WL5, the read / write control circuit 170 can output the voltages Gpw3 to Gpw5 and Gnw3 to Gnw5 to be applied to the third terminals (e.g., gate terminals) of the transistors Tpw3 to Tpw5 and Tnw3 to Tnw5 in the row decoder 120. Fig. 7A and Figure 7B The gate voltages Gpw3 to Gpw5, Gnw3 to Gnw5, Gpb5 and Gnb5 of the transistors Tpw3 to Tpw5, Tnw3 to Tnw5, Tpb5 and Tnb5 are described more fully. For example, the word line WL4 adjacent to the selected word line WL3 may be biased to the non-selected row voltage Vpw4 by the row decoder 130.

[0065] Fig. 7A and Figure 7B is shown applied to Figure 6 Graphs of exemplary voltages of word lines, bit lines, and transistors in a circuit diagram of FIG. The description will be based on a time period t10 to t11 (standby phase), a time period t11 to t12 (precharge phase), and a time period t12 to t13 (write phase). Fig. 7A and Figure 7B The curve graph of Fig. 7A and Figure 7B , the horizontal axis represents time and the vertical axis represents voltage.

[0066] In the time period t10 to t11 (standby phase), the memory device 100b stands by for access operations (e.g., write operations). In the standby phase, the memory device 100b may wait for a write command from an external device (e.g., a host). In the standby phase, the voltages Gpw3 to Gpw5 and Gpb5 applied to the gates of the transistors Tpw3 to Tpw5 and Tpb5 are logic high (or logic "1") levels, and the voltages Gnw3 to Gnw5 and Gnb5 applied to the gates of the transistors Tnw3 to Tnw5 and Tnb5 are logic low (or logic "0") levels. The voltage VBL5 of the selected bit line BL5 is the voltage level Vbw1. The voltages VWL3 to VWL5 of the word lines WL3 to WL5 are the voltage level Vww1. For example, the voltage levels Vbw1 and Vww1 may be 0V. In an exemplary embodiment, transistors Tpw3 to Tpw5 are turned off during the standby phase.

[0067] In the time period t11 to t12 (precharge phase), in order to precharge the selected bit line BL5, the voltage Gpb5 to be applied to the gate of the transistor Tpb5 connected to the selected bit line BL5 is a logic low (or logic "0") level, and the voltage Gnb5 to be applied to the gate of the transistor Tnb5 connected to the selected bit line BL5 is a logic high (or logic "1") level. In order to precharge the selected word line WL3, the voltages Gpw3 and Gnw3 to be applied to the gates of the transistors Tpw3 and Tnw3 connected to the selected word line WL3 are a logic high (or logic "1") level. The voltage VBL5 of the selected bit line BL5 may change from the voltage level Vbw1 to the voltage level Vbw2 (for example, it may increase when Vbw2>Vbw1). Therefore, the selected bit line BL5 is precharged to the voltage level Vbw2 at time t12. For example, before the end of the precharge phase, the selected bit line BL5 may reach the voltage Vbw2. The voltage VWL3 of the selected word line WL3 may change from the voltage level Vww1 to the voltage level Vww3 (e.g., may be decreased when Vww1>Vww3). Therefore, the selected word line WL3 may be precharged to the voltage level Vww3 at time t12. The voltage level Vww3 may be referred to as a “select voltage applied to the selected word line WL3 to write data into the selected memory cell MC35”. Figure 7B In an exemplary embodiment, during a write operation, precharging of the selected bit line BL5 and precharging of the selected word line WL3 are performed at the same time or during the same period of time.

[0068] In the time period t11 to t12 (precharge phase), the voltages Gpw4 and Gnw4 to be applied to the gates of the transistors Tpw4 and Tnw4 connected to the unselected word line WL4 adjacent to the selected word line WL3 are respectively at the levels of logic low (or logic "0") and logic high (or logic "1"), and the voltage VWL4 of the unselected word line WL4 is the voltage level Vww4. Here, the voltage level Vww4 may be referred to as the "level of the bias voltage". The level Vww4 of the bias voltage of the unselected word line WL4 may be the same as Figure 5B The bias voltage level Vbr4 of the unselected bit line BL6 is different from that of the unselected bit line BL6. For example, the voltage level Vww4 may be 0V. In this case, the voltage level Vww4 may be referred to as a "zero bias voltage level". When the selected bit line BL5 and the selected word line WL3 are precharged, the unselected word line WL4 may be biased to the voltage level Vww4 starting from time t11. However, the time t11 at which the bias of the unselected word line WL4 starts is only an example. Figure 7B Differently, the unselected word line WL4 may maintain a standby phase in a period t11 to t12 (precharge phase).

[0069] In the time period t11 to t12 (precharge phase), the voltages Gpw5 and Gnw5 to be applied to the gates of transistors Tpw5 and Tnw5 connected to the unselected word line WL5 which is not adjacent to the selected word line WL3 are at a logic low (or logic "0") level, and the voltage VWL5 of the unselected word line WL5 can change from the voltage level Vww1 to the voltage level Vww2 (for example, can increase when Vww2>Vww1).

[0070] In the time period t12 to t13 (write phase), data is written into the selected memory cell MC35. For the write operation, the selected word line WL3 may maintain the voltage level Vww3, and the selected bit line BL5 may maintain the voltage level Vbw2. In the time period t12 to t13 (write phase), the unselected word line WL4 adjacent to the selected word line WL3 may maintain a bias state in which the unselected word line WL4 is set to the voltage level Vww4. Fig. 7A and Figure 7B Unlike what is shown in , biasing of the unselected word line WL4 may be started at any time between time t12 and time t13.

[0071] During the time period t12 to t13 (the writing phase), the voltage Gpw5 to be applied to the gate of the transistor Tpw5 is a logic high (or logic "1") level, while the voltage Tnw5 to be applied to the gate of the transistor Tnw5 is a logic low (or logic "0") level. Therefore, during the writing phase, the unselected word line WL5 that is not adjacent to the selected word line WL3 is floated to the voltage level Vww2. In an exemplary embodiment, the transistors Tpw5 and Tnw5 are turned off during the writing phase to float the unselected word line WL5. For example, the voltage level Vww2 may be referred to as a non-selected row voltage. Here, the voltage level Vww2 may be referred to as a "floating voltage level". However, the time t12 at which the floating of the unselected word line WL5 begins is merely an example. Fig. 7A and Figure 7B Unlike that shown in , the floating of the unselected word line WL5 can start at any time between time t12 and time t13. The time when the biasing of the word line WL4 and the floating of the word line WL5 are completed and the time when the write phase is completed can be time t13. That is, the time when the biasing of the word line WL4 and the floating of the word line WL5 are completed can be the same as the time when the write phase is completed.

[0072] Figure 8 is shown in detail for describing a read operation of a memory device according to an exemplary embodiment of the inventive concept. Figure 11 is a circuit diagram of a memory device of the present invention. The memory cell array 110 further includes a word line capacitor Cw and a bit line capacitor Cb. The row driver 130 includes a transistor Tsdl. A node providing a power supply voltage Vpw3 is connected to a first terminal (e.g., a source terminal) of the transistor Tpw3. The row driver 130 outputs the power supply voltages Vpw3 and Vsdl. The power supply voltages Vpw3 and Vsdl may be generated by the row driver 130, or may be generated by another component (e.g., a reference Fig.14 The voltage generator 338 described above generates.

[0073] The sense amplifier 140 includes a sense amplifier SA connected to the word line WL3 . Figure 8 It is used to describe the operation of sensing the voltages of the selected word line WL3 and the selected bit line BL5 to read the data stored in the selected memory cell MC35, and for the convenience of description, the unselected bit lines BL6 and BL7 and the transistors Tpb6, Tnb6, Tpb7 and Tnb7 are omitted. Figure 8 Has and includes Figure 1 The memory device 100 and Figure 4 The components of the memory device 100a have the same reference numerals / labels as those of Figure 1 and Figure 4 The components of the memory devices 100 and 100a are the same.

[0074] A first terminal of word line capacitor Cw is connected to word line WL3 (i.e., a word line node “WL-node” on word line WL3), and a second terminal of word line capacitor Cw may be connected to GNDw, which may be connected to a GNDw through any other word line (e.g., Figure 6 A first terminal of the bit line capacitor Cb is connected to the bit line BL5, and a second terminal of the bit line capacitor Cb is connected to GNDb, which may be a ground terminal connected to the ground via any other bit line (e.g., Figure 4 The word line capacitor Cw and the bit line capacitor Cb may be capacitors parasitic on the word line and the bit line in the memory cell array 110. For example, the capacitance value of the bit line capacitor Cb (e.g., the capacitance value of the bit line BL5) may be greater than the capacitance value of the word line capacitor Cw (e.g., the capacitance value of the word line WL3), but the inventive concept is not limited thereto.

[0075] A first terminal (e.g., an input terminal) of the sense amplifier SA is connected to transistor Tnw3. The first terminal of the sense amplifier SA is connected to transistor Tnw3 through a sense data line SDL. The first terminal of the sense amplifier SA is connected to word line WL3 through transistor Tnw3, which is turned on and off under the control of the read / write control circuit 170. For example, the read / write control circuit 170 can turn on transistor Tnw3 by applying a voltage Gnw3 of a logic high (or logic "1") level to the gate of transistor Tnw3. When transistor Tnw3 is turned on, word line WL3 is connected to the first terminal of the sense amplifier SA. When word line WL3 is connected to the first terminal of the sense amplifier SA, the sense amplifier SA senses a read voltage level VSDL of word line WL3. The voltage level VSDL can be related to Figure 5A The voltage level VWL3 is the same.

[0076] The second terminal of the sense amplifier SA is connected to the read / write control circuit 170. The read / write control circuit 170 provides the reference voltage level VREF to the second terminal of the sense amplifier SA. For example, the read / write control circuit 170 may be connected to the second terminal of the sense amplifier SA by another component (e.g., Fig.14 A reference voltage level VREF generated by a voltage generator 338 of the sense amplifier SA is provided to a second terminal of the sense amplifier SA. The reference voltage level VREF may be a reference for identifying a state of the memory cell MC35 (e.g., a state indicating a digital logic value of "1" (e.g., a set state) or a state indicating a digital logic value of "0" (e.g., a reset state). For example, in the case where the memory cell MC35 has a state indicating a digital logic value of "1", the memory cell MC35 may be referred to as a "turn-on cell"; in the case where the memory cell MC35 has a state indicating a digital logic value of "0", the memory cell MC35 may be referred to as a "turn-off cell". The sense amplifier SA may output a sensing result VSA by comparing the voltage level VSDL and the reference voltage level VREF. For example, a voltage level VSDL lower than the reference voltage level VREF may indicate one of the two states, and a voltage level VSDL higher than the reference voltage level VREF may indicate the other of the two states.

[0077] A first terminal (e.g., drain terminal) of the transistor Tsd1 is connected to a node providing a power supply voltage Vsd1. A second terminal (e.g., gate terminal) of the transistor Tsd1 is connected to a read / write control circuit 170. A third terminal (e.g., source terminal) of the transistor Tsd1 is connected to a node "SDL node" on a sensing data line SDL.

[0078] Fig. 9 Shown for description Figure 8A graph showing voltages of word lines and bit lines and currents flowing through memory cells connected to the word lines and bit lines in a circuit diagram of FIG. Fig. 9 The voltage VWLoff.ideal of the selected word line WL3 when the off current does not flow (I2=0) and the voltage VWLoff.real of the selected word line WL3 when the off current flows (I2≠0) are shown in the case where the selected memory cell MC35 is an off cell. The voltage VBL of the selected bit line BL5 when the selected memory cell MC35 is an on cell, the voltage VWLon of the selected word line WL3, the voltage VWLoff.real or VWLoff.ideal of the selected word line WL3 when the selected memory cell MC35 is an off cell, and the cell current flowing through the selected memory cell MC35 will be described with respect to the time period t20 to t27. Figure 5A and Figure 5B To describe Fig. 9 .

[0079] The time period t20 to t21 may correspond to Figure 5A and Figure 5B The voltage VBL of the selected bit line BL5 and the voltage VWLon, VWLoff.real or VWLoff.ideal of the selected word line WL3 correspond to the voltage level V2. For example, the voltage level V2 may be 0V.

[0080] The time period t21 to t22 may correspond to Figure 5A and Figure 5B The selected word line precharge phase. The voltage VWLon, VWLoff.real or VWLoff.ideal of the selected word line WL3 may change from the voltage level V2 to the voltage level V1 (for example, when V2>V1, it may be reduced). Therefore, the selected word line WL3 may be precharged to the voltage level V1 at time t22. When the selected word line WL3 is precharged, the voltage VBL of the selected bit line BL5 may be equal to its voltage in the standby phase. For example, the voltage VBL of the selected bit line BL5 may be Vbr1.

[0081] The time period t22 to t26 corresponds to Figure 5A and Figure 5BThe selected bit line precharge phase. The voltage VBL of the selected bit line BL5 may change from the voltage level V2 to the voltage level V5 (for example, when V5>V2, it may increase). When the difference between the voltage VBL of the bit line BL5 and the voltage VWLon, VWLoff.real or VWLoff.ideal of the precharged word line WL3 at time t23 reaches the threshold voltage Vth of the memory cell MC35, the memory cell MC35 is turned on, and the cell current flowing through the memory cell MC35 may change sharply from the current level I2 to the current level I1 (for example, when I1>I2, it may increase). In the time period t23 to t24, due to the sharp current change of the memory cell MC35, the voltage VBL of the bit line BL5 may change from the voltage level V4 to the voltage level V3 (for example, when V4>V3, it may decrease), and then, the cell current flowing through the memory cell MC35 may change again from the current level I1 to the current level I2 (for example, when I1>I2, it may decrease). When the voltage VBL of the bit line BL5 is at the voltage level V3, the difference between the voltage of the bit line BL5 and the voltage VWLon of the word line WL3 may be the switching voltage Vs of the memory cell MC35. Thereafter, the voltage VBL of the bit line BL5 may change from the voltage level V3 to the voltage level V5 (e.g., may increase when V5>V3). Thereafter, the selected bit line BL5 may be precharged to the voltage level V5 at time t26.

[0082] In the time period t22 to t26 (selected bit line precharge phase), the selected word line WL3 is floated. For example, the selected word line WL3 may be floated in at least a portion of the time period t22 to t26. In the case where the memory cell MC35 is an on-cell, the voltage VWLon of the selected word line WL3 may change from the voltage level V1 to the voltage level V2 (for example, when V2>V1, it may increase). The voltage VWLon of the selected word line WL3 may be the voltage level V2.

[0083] In the time period t22 to t26 (the selected word line precharge phase), when the memory cell MC35 is a turn-off cell and no turn-off current occurs (I2=0), the voltage VWLoff.ideal of the selected word line WL3 maintains the voltage level V1. When the memory cell MC35 is a turn-off cell and a turn-off current occurs (I2≠0), the voltage VWLoff.real of the selected word line WL3 may change from the voltage level V1 to the voltage level V1′ (e.g., may increase when V1′>V1).

[0084] The time period t26 to t27 may correspond to Figure 5A and Figure 5BSensing phase. In the time period t26 to t27 (sensing phase), the read / write control circuit 170 turns on the transistor Tnw3, and since the transistor Tnw3 is turned on, the word line WL3 is connected to the first terminal of the sense amplifier SA. When the word line WL3 is connected to the first terminal of the sense amplifier SA, the sense amplifier SA senses the read voltage level VSDL of the word line WL3. In the sensing phase, the selected word line WL3 can maintain a floating state at the voltage level Vwr2. In the time period t26 to t27 (sensing phase), the selected bit line BL5 is floated. The voltage VBL of the selected bit line BL5 can be reduced during the floating period. For example, the floating of the bit line BL5 can start at time t26.

[0085] In the time period t26 to t27 (sensing phase), the sensing margin when the shutdown current does not occur (I2=0) is greater than the sensing margin when the shutdown current occurs (I2≠0). As the sensing margin increases, the reliability required to read the data stored in the memory cell MC35 can be increased. In the read operation, according to an exemplary embodiment of the present inventive concept, the unselected bit line (e.g., Figure 3 BL4 and BL6) and biases the unselected bit lines (e.g., Figure 3 BL3 and BL7) are floated to increase (or improve) the sensing margin.

[0086] Fig.10 1 is a flowchart illustrating a method of a read operation of a memory device according to an exemplary embodiment of the inventive concept. Figure 8 The memory device 100c and Fig. 9 The curve diagram describes Fig.10 .

[0087] In operation S110, the selected word line WL3 is precharged to a voltage level V1. In operation S120, the row decoder 120 floats the selected word line WL3. In order to float the selected word line WL3, the read / write control circuit 170 may control the gate voltages of the transistors Tpw3 and Tnw3 connected to the selected word line WL3 (refer to Figure 5A For example, the selected word line WL3 may be floated by turning off transistors Tpw3 and Tnw3.

[0088] In operation S130, the selected bit line BL5 is precharged to a voltage level V5 by the column decoder 150. When the selected bit line BL5 is precharged, the word line capacitor Cw connected to the selected word line WL3 may be charged. In operation S130, the column decoder 150 precharges the bit line adjacent to the selected bit line BL5 (e.g., Figure 4BL6) is biased to set it to a first voltage level (e.g., Figure 5B Vbr4), and the bit lines not adjacent to the selected bit line BL5 (e.g., Figure 4 BL7) floats to a second voltage level (eg, Figure 5B To bias the bit lines adjacent to the selected bit line BL5 (e.g., Figure 4 BL6) and floating bit lines not adjacent to the selected bit line BL5 (e.g., Figure 4 BL7), the read / write control circuit 170 may control a bit line adjacent to the selected bit line BL5 (eg, Figure 4 The gate voltages of transistors (eg, Tpb6 and Tnb6) connected to the selected bit line BL6 and the gate voltages of bit lines (eg, Figure 4 The gate voltage of the transistors (e.g., Tpb7 and Tnb7) connected to the selected bit line BL5 is set to Figure 4 BL6) is biased to a first voltage level (e.g., Figure 5B Vbr4) and the bit lines that are not adjacent to the selected bit line BL5 (e.g., Figure 4 BL7) floats to a second voltage level (eg, Figure 5B The start time of precharging the selected bit line BL5 to the voltage level Vbr3) can be equal to the start time of precharging the selected bit line BL5 to the voltage level V5.

[0089] In operation S140, the column decoder 150 floats the selected bit line BL5. In order to float the selected bit line BL5, the read / write control circuit 170 may control the gate voltages of the transistors Tpb5 and Tnb5 connected to the selected bit line BL5 (refer to Figure 5B For example, the read / write control circuit 170 may apply a gate voltage to turn off the transistors Tpb5 and Tnb5, thereby floating the selected bit line BL5.

[0090] In operation S150, the sense amplifier SA senses the voltage level VSDL of the selected word line WL3. At the same time, the column decoder 150 floats the selected bit line BL5, or after the selected bit line BL5 is floated, the sense amplifier SA can sense the voltage generated by the charge transferred from the word line node "WL node" on the word line WL3 to the node "SDL node" on the sense data line SDL through charge sharing, and is charged at the word line capacitor Cw. The bit lines adjacent to the selected bit line (e.g., Figure 4 BL6) and the bit lines not adjacent to the selected bit line BL5 (e.g., Figure 4 The floating of BL7) can be completed at the time when operation S150 is completed.

[0091] Fig.11 It is shown that the Figure 1 A block diagram of another example of a memory cell array in a memory device of FIG. Figure 1 and Figure 3 To describe Fig.11 In addition to the difference between the memory cell array 110b and the memory cell array 110a in the number of biased word lines and the number of biased bit lines, the memory cell array 110b can be the same as Figure 3 The memory cell array 110a is substantially the same as that of the memory device 100. That is, in a read operation or a write operation of the memory device 100, compared with the memory device 100a, the row decoder 120 further biases the word lines WL5 to WLp (p is an integer greater than 5) to set them to the voltage level output from the row driver 130. In a read operation or a write operation of the memory device 100, compared with the memory device 100a, the column decoder 150 further biases the bit lines BL7 to BLk (k is an integer greater than 7) to set them to the voltage level output from the column driver 160. Therefore, referring to Figure 3 and Fig.11 In a read operation or a write operation of the memory device 100, the row decoder 120 may bias at least two word lines WL4 to WLp, and the column decoder 150 may bias at least two bit lines BL6 to BLk. At least two word lines WL4 to WLp may be biased sequentially at different times, and at least two bit lines BL6 to BLk may be biased sequentially at different times. Fig.11 , the row decoder 120 may float the word lines WL1 and WLq to WLs (q=p+1) at the levels of different voltages output from the row driver 130, and the column decoder 150 may float the bit lines BL1 to BL3 and BLm to BLt (m=k+1) at the levels of different voltages output from the column driver 160. The word lines WL1 and WLq to WLs may be sequentially floated at different times, and the bit lines BL1 to BL3 and BLm to BLt may be sequentially floated at different times. The row decoder 120 may apply voltages of different levels to the biased word lines WL2 and WL4 to WLp and the floating word lines WL1 and WLq to WLs. The column decoder 150 may apply voltages of different levels to the biased bit lines BL5 and BL6 to BLk and the floating bit lines BL1 to BL3 and BLm to BLt.

[0092] exist Fig.11 In, with Figure 3 The word lines WL5 to WLp additionally biased compared to the memory cell array 110a of the embodiment of the present invention may be adjacent to the selected word line WL3 in the direction D4 and may be adjacent to the selected word line WL3 in the direction D4. Figure 3The additionally biased bit lines BL7 to BLk may be adjacent to the selected bit line BL5 in the direction D2 compared to the memory cell array 110a. However, the additionally biased word lines and the additionally biased bit lines are not limited to Fig.11 For example, the additionally biased word line may be adjacent to the selected word line WL3 in the direction D3, and the additionally biased bit line may be adjacent to the selected bit line BL5 in the direction D1.

[0093] Fig.12 An example of a structure of a memory cell array according to an exemplary embodiment of the inventive concept is shown. Fig.12 , the memory device 110c includes a plurality of memory cells MC. Each of the memory cells MC may include a reference Figure 2 The selection element "S" and the resistance element "R" described. The memory cell MC may be inserted between a word line extending in a first direction and a bit line extending in a second direction perpendicular to the first direction. In this case, the selection element "S" and the resistance element "R" may be arranged in a third direction. For example, the resistance element "R" may be connected between the first word line WL1 and the selection element "S", and the selection element "S" may be connected between the resistance element "R" and the first bit line BL1.

[0094] A plurality of memory cells MC may be arranged in the first layer or may be arranged in the second layer. In this case, the memory cells MC of the second layer may be stacked in a third direction relative to the memory cells MC of the first layer. Fig.12 As shown, the memory cells MC of the first layer may be connected between the first word lines WL1 to WL4 and the first bit lines BL1 to BL4, and the memory cells MC of the second layer may be connected between the fifth word lines WL5 to WL8 and the first bit lines BL1 to BL4. In this case, the first bit lines BL1 to BL4 may be connected to both the memory cells MC of the first layer and the memory cells MC of the second layer. However, the inventive concept is not limited thereto. For example, a bit line may be provided for each layer, respectively.

[0095] According to the stack structure, at least one parasitic capacitor may exist in a space between the first to fourth word lines WL1 to WL4 and the first to fourth bit lines BL1 to BL4 or in a space between the first to fourth bit lines BL1 to BL4 and the fifth to eighth word lines WL5 to WL8 (e.g., Figure 8 When a voltage (eg, a selection voltage, a precharge voltage, a floating voltage, or a bias voltage) is applied to the word lines WL1 to WL8 or the bit lines BL1 to BL4, capacitors parasitic between the stack lines may be charged.

[0096] As reference Figures 1 to 11 As described, the memory device 100c may bias or float unselected word lines or unselected bit lines. Fig.12 An example of a structure of a memory device 110 c is shown in which word lines and bit lines are arranged to cross each other, and the number of word lines, the number of bit lines, and the number of layers may be variously changed or modified.

[0097] Fig.13 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept. Figure 1 To describe Fig.13 The memory device 200 may include a board 210, a row decoder 220, a row driver 230, a sense amplifier 240, a column decoder 250, a column driver 260, and a read / write control circuit 270. The row decoder 220, the row driver 230, the sense amplifier 240, the column decoder 250, the column driver 260, and the read / write control circuit 270 may be respectively connected to Figure 1 Components 120 to 170 are substantially the same.

[0098] The board 210 may include at least two or more tiles 211 to 21n (e.g., 211, 212, and 213). The at least two or more tiles 211 to 21n include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected between the plurality of word lines and the plurality of bit lines. For example, the number of word lines connected to the memory cells in each of the at least two or more tiles 211 to 21n may be greater than or equal to the number of bit lines connected to the memory cells in each of the at least two or more tiles 211 to 21n. Specifically, in each of the one or more tiles 211 to 21n, the number of word lines connected to the memory cells may be 4K (=2 12 ) or more (or may exceed 4K), and the number of bit lines connected to the memory cells may be 2K (=2 11 ) or more (or may exceed 2K). However, the inventive concept is not limited to the above values. The board 210 may be implemented as Figure 1 That is, in terms of the principle of implementing the memory cell, Figure 1 There may be a difference between the memory cell array 110 and the board 210 .

[0099] The row decoder 220, the row driver 230, and the sense amplifier 240 may be connected to at least two or more blocks 211 to 21n. Each of the row decoder 220, the row driver 230, and the sense amplifier 240 may include a component corresponding to each of the at least two or more blocks 211 to 21n. The components of the row decoder 220 corresponding to each of the at least two or more blocks 211 to 21n may independently perform floating and biasing of word lines. The components of the row driver 230 corresponding to each of the at least two or more blocks 211 to 21n may independently output precharge voltage, selection voltage, floating voltage, and bias voltage to the word line. The components of the sense amplifier 240 corresponding to each of the at least two or more blocks 211 to 21n may independently sense the read voltage level of the word line. The components of the column decoder 250 corresponding to each of the at least two or more blocks 211 to 21n may independently perform floating and biasing of the bit line. The components of the column driver 260 corresponding to each of the at least two or more blocks 211 to 21 n may independently output a precharge voltage, a selection voltage, a floating voltage, and a bias voltage to a bit line.

[0100] The read / write control circuit 270 may allow the row decoder 220 to bias or float the word lines in the first block 211, and may allow the column decoder 250 to bias or float the bit lines in the first block 211. In at least two or more blocks 211 to 21n, the number of floating word lines, the number of biased word lines, the number of floating bit lines, and the number of biased bit lines may be differently set by the read / write control circuit 270. In addition, in at least two or more blocks 211 to 21n, floating voltages and bias voltages of word lines and bit lines may be differently set by the read / write control circuit 270.

[0101] Fig.14 1 is a block diagram of a memory device according to an exemplary embodiment of the inventive concept. The memory device 300 includes a layer L1 and a layer L2 positioned, disposed, or stacked on the layer L1. The vertical relationship between the layer L1 and the layer L2 may be interchanged. Figures 1 to 13 The described memory cells MC may be arranged in the layer L2. The memory cells MC arranged in the layer L2 may constitute a bank 310. The bank 310 may include a plurality of plates 311. The plate 311 may include memory cells MC connected to the word lines WL and the bit lines BL. The number of memory cells MC, the number of plates 311, and the number of banks 310 are merely examples.

[0102] The board control circuit 320 may be provided in the layer L1. The board control circuit 320 may control the boards 311 provided in the layer L2, respectively. For example, in a top view, the board control circuit 320 and the boards 311 controlled by the board control circuit 320 may overlap each other. The board control circuit 320 may include a row decoder 321, a row driver 322, a sense amplifier 323, a column decoder 324, a column driver 325, and a read / write control circuit 326. The components 321 to 326 of the board control circuit 320 may be connected to the board 311. Fig.13 The components 220 to 270 of the memory device 200 are substantially the same.

[0103] The memory device 300 may include a command decoder 331 (e.g., a decoder circuit), an address buffer 332, a data processing circuit 333, an error correction circuit (ECC) 334, an on-cell counter (OCC) 335, a randomizer 336 (e.g., a randomization circuit), a register 337, and a voltage generator 338. The components 331 to 338 may be included in a peripheral circuit of the memory device 300, and the peripheral circuit may be provided in the layer L1. A structure in which the memory cell MC is provided in the layer L2 and the circuits 320 and 331 to 338 for controlling the memory cell MC are provided in the layer L1 may be referred to as a "cell on the periphery (COP)".

[0104] The command decoder 331 may receive a command CMD from the outside of the storage device 300 (e.g., a host or a storage controller). The command decoder 331 may decode the command CMD, and may control the remaining components 311, 320, and 332 to 338 of the storage device 300 based on the decoding result. For example, the command CMD may include a read command for the storage cell MC. The board control circuit 320 may perform operations S110 to S150 under the control of the command decoder 331, which once decodes the read command.

[0105] The address buffer 332 may receive an address ADD from a source located outside the memory device 300. The address ADD may indicate at least one or more memory cells to be selected from the memory cells of the memory device 300. The address buffer 332 may provide a column address to a column decoder 324 of a board control circuit 320 that controls a board 311 including a memory cell MC indicated by the address ADD, and may provide a row address to a row decoder 321 of a board control circuit 320 that controls a board 311 including a memory cell MC indicated by the address ADD. The command decoder 331 may select the board control circuit 320 that controls the board 311 including the memory cell MC indicated by the address ADD. For example, the command decoder 331 that receives one of a read command and a write command may select one or more board control circuits 320 at the same time.

[0106] The data processing circuit 333 may receive data "DATA" including write data from a source located outside the memory device 300. The data processing circuit 333 may provide the write data to the selected board control circuit 320. In each of the selected board control circuits 320, the read / write control circuit 326 may control the remaining components 321 to 326 to write the write data into the selected memory cell MC. The data processing circuit 333 may receive read data from the selected board control circuit 320. The data processing circuit 333 may output data "DATA" including the read data. In each of the selected board control circuits 320, the read / write control circuit 326 may control the remaining components 321 to 326 to read the read data from the selected memory cell MC. The read / write control circuit 326 may be implemented by the read / write control circuit 170.

[0107] The error correction circuit 334 may perform an encoding operation on the write data to be written into the selected memory cell MC based on the error correction code. The error correction circuit 334 may perform a decoding operation on the read data read from the selected memory cell MC based on the error correction code. The error correction circuit 334 may detect an error in the read data, may calculate an error count of the read data (e.g., the number of error (or failed) bits), may determine whether the error in the read data is correctable, or may correct the error in the read data. The error correction circuit 334 may provide the error count of the read data to the data processing circuit 333. For example, the data processing circuit 333 may provide the write data encoded by the error correction circuit 334 to the selected board control circuit 320. The data processing circuit 333 may output data "DATA" including the read data decoded by the error correction circuit 334.

[0108] The on-cell counter 335 may calculate the number of on-cells of the selected memory cell MC based on the read data output from the selected memory cell MC. The on-cell counter 335 may provide the number of on-cells to the data processing circuit 333. The on-cell counter 335 may not be included in the memory device 300. The randomizer 336 may perform a randomization operation on the write data to be written into the selected memory cell MC. The randomizer 336 may perform a de-randomization operation on the read data read from the selected memory cell MC. For example, when each of the memory cells MC stores one of the digital logic values ​​"0" and "1", the randomizer 336 may adjust the ratio of 1 to 0 of the write data to be written into the selected memory cell MC. The randomizer 336 may calculate the ratio of 1 to 0 of the read data. For example, the randomizer 336 may identify whether the ratio of 1 to 0 of the write data and the ratio of 1 to 0 of the read data are different. The randomizer 336 may provide information about the above ratio to the data processing circuit 333. The randomizer 336 may not be included in the memory device 300.

[0109] The register 337 may store various information about the memory device 300. For example, the register 337 may store the following information: a result of an operation performed by the error correction circuit 334, an error count calculated by the error correction circuit 334, the number of on-cells calculated by the on-cell counter 335, information about a ratio calculated by the randomizer 336, the number of bit lines to be biased among unselected bit lines, the number of bit lines to be floated among unselected bit lines, the number of word lines to be biased among unselected word lines, and the number of word lines to be floated among unselected word lines.

[0110] The voltage generator 338 may generate various voltages to be used in the memory device 300 by using the power supply voltage supplied to the memory device 300, and may supply the generated voltages to the components 310, 320, and 331 to 338 of the memory device 300. The power supply voltage supplied to the memory device 300 may include VDD, VPP, GND, etc. The various voltages used in the memory device 300 may include a non-selected bit line voltage to be applied to an unselected bit line, a non-selected word line voltage to be applied to an unselected word line, a level of a selection voltage (or precharge voltage) in a read operation or a write operation, a level of a floating voltage, a level of a bias voltage, a reference voltage level VREF used by the sense amplifier 323, etc.

[0111] Fig.151 is a block diagram showing an electronic device to which a memory device according to an embodiment of the present invention is applied. The electronic device 1000 may be referred to as a "computing system", "storage system", "electronic system" or "communication system". For example, each of the electronic devices 1000 may be a desktop computer, a laptop computer, a tablet computer, a mobile device, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a wearable device, a video game console, a workstation, a server, a data processing device capable of using or supporting an interface protocol proposed by the Mobile Industry Processor Interface (MIPI) Alliance, a home appliance, a black box, a drone, etc.

[0112] refer to Fig.15 , the electronic device 1000 may include a host 1100 and a storage module 1200. The host 1100 may exchange data with the storage module 1200. For example, the host 1100 may include one or more cores. The host 1100 may include a storage controller that controls the storage module 1200. The storage controller may send at least one of a command CMD, an address ADD, and data "DATA" to the storage module 1200 through a channel CH, or may receive data "DATA" from the storage module 1200 through the channel CH.

[0113] The storage module 1200 may include a storage device 1300. In the electronic device 1000, the number of the storage modules 1200 and the number of the storage devices 1300 attached to one storage module 1200 are not limited to Fig.15 The memory module 1200 may be a single in-line module (SIMM) or a dual in-line memory module (DIMM). The memory device 1300 may include at least one of the following: Figure 1 , Fig.13 and Fig.14 The described memory devices 100 to 300, static random access memory (SRAM) devices, dynamic RAM (DRAM) devices, thyristor RAM (TRAM) devices, NAND flash memory devices, NOR flash memory devices, resistive RAM (RRAM), and ferroelectric RAM (FRAM), and the number of types of the memory device 1300 may be one or more. For example, the memory module 1200 may be a SIMM, a DIMM, a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), a small outline DIMM (SO-DIMM), a non-volatile DIMM (NVDIMM), etc.

[0114] The storage module 1200 may be connected to the host 1100 via a DDR interface. In an embodiment, the DDR interface may comply with the memory standard specification of the Joint Electronic Device Engineering Council (JEDEC). At the same time, the storage module 1200 may be connected to the host 1100 based on the DDR interface. However, the inventive concept is not limited thereto. The storage module 1200 may be connected to the host 1100 via various types of communication interfaces other than the DDR interface. For example, the communication interface may include a non-volatile memory express (NVMe) interface, a peripheral component interconnect express (PCIe) interface, a serial connection (SATA) interface, a small computer system interface (SCSI), a serial attached SCSI (SAS), a SCSI (UAS) connected to a universal storage bus (USB), an Internet small computer system interface (iSCSI), a Fibre Channel interface, and Fibre Channel over Ethernet (FCoE).

[0115] Fig.16 is a block diagram illustrating a computing system according to an exemplary embodiment of the inventive concept. Fig.16 , the electronic device 2000 includes a host 2100 and a storage device 2200. The host 2100 can exchange data with the storage device 2200. The storage device 2200 may include a controller 2210, and the controller 2210 includes an on-chip memory 2215, a storage device 2220, and a buffer memory 2216. The controller 2210 may process a request of the host 2100, may execute a program loaded on the on-chip memory 2215, and may control the storage device 2220. The on-chip memory 2215, the buffer memory 2216, and the storage device 2220 may include at least one of the following: Figure 1 and Fig.14 The memory devices 100 and 200 described herein include SRAM devices, DRAM devices, TRAM devices, NAND flash memory devices, NOR flash memory devices, RRAM devices, FRAM devices, and MRAM devices.

[0116] In an embodiment, the memory device 2220 is a NAND flash memory device and the buffer memory 2216 is a reference Figure 1 , Fig.13 and Fig.14 In the case of one of the described storage devices 100, 200, and 300, the buffer memory 2216 may store metadata of the storage device 2220. For example, the storage device 2200 may be a solid state drive (SSD) device, a memory card that can be attached to or detached from the electronic device 2000, a secure digital (SD) card, an embedded multimedia card (eMMC), a universal flash memory (UFS) card, etc.

[0117] A memory device according to at least one exemplary embodiment of the inventive concept may reduce leakage current flowing at unselected memory cells in a read or write operation associated with a selected memory cell, and thus may improve reliability or endurance of the memory cells.

[0118] A memory module according to at least one example embodiment of the inventive concepts may reduce power consumption by biasing memory cells adjacent to a selected memory cell.

[0119] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept.

Claims

1. A storage device, comprising: a board including a plurality of word lines, a plurality of bit lines, and a memory cell connected to a first word line of the plurality of word lines and a first bit line of the plurality of bit lines; a row decoder configured to bias at least one word line of the plurality of word lines adjacent to the first word line to a level of a first non-selected row voltage and float the remaining non-adjacent word lines of the plurality of word lines that are not adjacent to the first word line to a level of a second non-selected row voltage in an access operation associated with the memory cell; as well as A column decoder is configured to apply an initial voltage to the plurality of bit lines during a standby phase, bias at least one bit line adjacent to the first bit line among the plurality of bit lines to a level of a first non-selected column voltage greater than the initial voltage during an access operation after the standby phase, and float the remaining non-adjacent bit lines among the plurality of bit lines that are not adjacent to the first bit line to a level of a second non-selected column voltage lower than the initial voltage during the access operation.

2. The memory device according to claim 1, further comprising: a first transistor and a second transistor connected to a first non-adjacent word line among the remaining non-adjacent word lines; as well as The read / write control circuit is configured to apply a voltage to the gate of the first transistor and the gate of the second transistor in the access operation including the write operation.

3. The memory device according to claim 2, wherein: In the write operation, when the read / write control circuit applies a logic high level voltage to the gate of the first transistor and a logic low level voltage to the gate of the second transistor, the first non-adjacent word line is floated to the level of the second non-selected row voltage.

4. The memory device according to claim 2, further comprising: a sense amplifier configured to sense a level of a read voltage of the first word line in the access operation including a read operation; a third transistor connected between the sense amplifier and the first word line, The read / write control circuit turns on the third transistor in the read operation, and the first word line is connected to the sense amplifier by turning on the third transistor.

5. The memory device according to claim 1, wherein: The number of the plurality of word lines is greater than or equal to the number of the plurality of bit lines.

6. The memory device according to claim 1, wherein: The capacitance value of the first bit line is greater than the capacitance value of the first word line.

7. The memory device according to claim 1, wherein: The memory cell is a phase change random access memory (PRAM) cell.

8. The memory device according to claim 1, wherein: The at least one bit line adjacent to the first bit line is not floated during a time period from after being biased to when a sensing phase is completed.

9. A storage device comprising: A memory cell array comprising first to third word lines, a first to third bit lines, and memory cells connected to the first word lines and the first bit lines, wherein a second word line is inserted between the first word line and the third word line, and a second bit line is inserted between the first bit line and the third bit line; a row driver configured to output a first selected row voltage, and a first non-selected row voltage and a second non-selected row voltage; a column driver configured to output a first selected column voltage, and a first non-selected column voltage and a second non-selected column voltage; a row decoder configured to, in a write operation, apply the first selection row voltage to the first word line, bias the second word line to a level of the first non-selection row voltage, and float the third word line to a level of the second non-selection row voltage; a column decoder configured to, in a read operation, apply the first selected column voltage to the first bit line, bias the second bit line to a level of the first non-selected column voltage, and float the third bit line to a level of the second non-selected column voltage; and a sense amplifier configured to sense a level of a read voltage of the first word line in the read operation, The time when biasing the second bit line to the level of the first non-selected column voltage and floating the third bit line to the level of the second non-selected column voltage is completed is the same as the time when sensing of the read voltage of the first word line is completed.

10. The memory device according to claim 9, wherein: In the write operation, the row decoder starts floating the third word line at the time when the second word line starts to be biased, and Wherein, in the read operation, the column decoder starts to float the third bit line at the time when the second bit line starts to be biased.

11. The memory device according to claim 9, wherein: In the read operation, the row decoder floats the first word line to a level of the first selection row voltage in at least a portion of a period in which the first selection column voltage output from the column driver is applied to the first bit line.

12. The memory device according to claim 9, wherein: In the read operation, the column decoder biases the second bit line to a level of the first non-selected column voltage while the sense amplifier senses a level of a read voltage of the first word line.

13. The memory device according to claim 9, wherein: A level of the first non-selected row voltage is different from a level of the first non-selected column voltage.

14. The memory device according to claim 9, wherein: The memory cell array further includes a fourth word line adjacent to the third word line and a fourth bit line adjacent to the third bit line, wherein, in the write operation, the row decoder further floats the fourth word line to a level of a third non-selected row voltage different from a level of the second non-selected row voltage; and In the read operation, the column decoder further floats the fourth bit line to a level of a third non-selected column voltage different from a level of the second non-selected column voltage.

15. The memory device according to claim 14, wherein: In the write operation, the row decoder floats the fourth word line after floating the third word line, and Wherein, in the read operation, the column decoder floats the fourth bit line after floating the third bit line.

16. A method for performing a read operation on a memory cell connected to a first word line and a first bit line in a memory device, the method comprising: precharging the first word line to a level of a first selected row voltage; floating the first word line; precharging the first bit line to a level of a first selected column voltage; biasing a second bit line adjacent to the first bit line to a level of a first non-selected column voltage, and floating a third bit line not adjacent to the first bit line to a level of a second non-selected column voltage; floating the first bit line; as well as sensing a level of a read voltage of the first word line, The time when biasing the second bit line to the level of the first non-selected column voltage and floating the third bit line to the level of the second non-selected column voltage is completed is the same as the time when sensing of the read voltage of the first word line is completed.

17. The method according to claim 16, wherein: Biasing the second bit line to the level of the first non-selected column voltage and floating the third bit line to the level of the second non-selected column voltage begins at the same time as precharging the first bit line to the level of the first selected column voltage.

18. The method according to claim 16, wherein: Biasing the second bit line to the level of the first non-selected column voltage and floating the third bit line to the level of the second non-selected column voltage comprises: controlling a gate voltage of a first transistor connected to the second bit line; and A gate voltage of a second transistor connected to the third bit line is controlled.

19. The method according to claim 16, wherein: Precharging the first bit line to the level of the first selected column voltage includes charging a capacitor of the first word line with an electric charge.

20. The method according to claim 19, wherein: Sensing a level of a read voltage of the first word line includes: The voltage of the capacitor is sensed at the same time as when the first bit line is floated or after the first bit line is floated.

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