Wafer processing apparatus and wafer processing method using the same

Abstract

A wafer processing apparatus is provided. The apparatus includes: a heating plate through which a vacuum port is formed; a plurality of temperature sensors; a heating device configured to heat the heating plate; a first power supply and a second power supply; a temperature controller for generating a first feedback temperature control signal and a second feedback temperature control signal based on measured values generated by the temperature sensors to control the power output of the power supplies; an electronic pressure regulator configured to provide a vacuum pressure for fixing a wafer to a plurality of vacuum ports; and a wafer clamping controller configured to control the electronic pressure regulator and generate a feedback pressure control signal for controlling the electronic pressure regulator based on the first feedback temperature control signal and the second feedback temperature control signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0089220, filed with the Korean Intellectual Property Office on July 23, 2019, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] A method and apparatus according to an embodiment of the present application relate to a wafer processing apparatus and a wafer processing method using the wafer processing apparatus. Background art

[0004] Various processes such as oxidation, lithography, etching, thin - film deposition, metallization, electronic die sorting (EDS), packaging, etc. are performed on wafers to manufacture semiconductor devices. As semiconductor devices are miniaturized, there is an increasing need for high - precision control of semiconductor process conditions. In particular, in order to improve the yield of semiconductor manufacturing processes, it is necessary to identify the warpage of wafers in each process, determine the degree of warpage, and achieve consistent processing conditions to minimize the warpage of wafers. Summary of the invention

[0005] One or more embodiments provide a wafer processing apparatus and a wafer processing method using the wafer processing apparatus for uniformly controlling the temperature of an entire wafer.

[0006] The embodiments are not limited to the above - mentioned purposes, and other purposes not mentioned can be clearly understood by those of ordinary skill in the art from the following description.

[0007] According to an aspect of an embodiment, there is provided a wafer processing apparatus including: a hot plate, in which a plurality of vacuum ports are formed and a central region and an edge region surrounding the central region are defined; a plurality of temperature sensors assembled in the hot plate; a heating device configured to heat the hot plate; a first power supply and a second power supply configured to provide operating power to different parts of the heating device; a first temperature controller configured to generate a first feedback temperature control signal for controlling the power output of the first power supply based on a first measurement value generated by the plurality of temperature sensors; a second temperature controller configured to generate a second feedback temperature control signal for controlling the power output of the second power supply based on a second measurement value generated by the plurality of temperature sensors; an electronic pressure regulator configured to provide a vacuum pressure for fixing a wafer disposed on the hot plate to the plurality of vacuum ports and regulate the pressure of the plurality of vacuum ports; and a wafer clamping controller configured to control the electronic pressure regulator and generate a feedback pressure control signal for controlling the pressure of the electronic pressure regulator based on the first feedback temperature control signal and the second feedback temperature control signal.

[0008] According to one aspect of the embodiment, a wafer processing apparatus is provided, including: a heating plate, through which a plurality of vacuum ports are formed and a central region, an edge region surrounding the central region, and an intermediate region between the central region and the edge region are defined; a plurality of temperature sensors configured to measure the temperature of the heating plate; a heating device configured to heat the heating plate; a first power supply, a second power supply, and a third power supply configured to supply operating power to the heating device; a first temperature controller configured to generate a first feedback temperature control signal for controlling a first power output of the first power supply based on a first measurement value of the plurality of temperature sensors; a second temperature controller configured to generate a second feedback temperature control signal for controlling a second power output of the second power supply based on a second measurement value of the plurality of temperature sensors; a third temperature controller configured to generate a third feedback temperature control signal for controlling a third power output of the third power supply based on a third measurement value of the plurality of temperature sensors; an electronic pressure regulator configured to regulate the pressure of the plurality of vacuum ports; and a wafer clamping controller configured to control the electronic pressure regulator. The plurality of vacuum ports include: a plurality of first vacuum ports arranged symmetrically with respect to a central circle of the heating plate; and a plurality of second vacuum ports arranged symmetrically with respect to the central circle of the heating plate and farther from the central region of the heating plate than the plurality of first vacuum ports. The electronic pressure regulator includes: a first electronic pressure regulator configured to regulate the pressure of the plurality of first vacuum ports; and a second electronic pressure regulator configured to regulate the pressure of the plurality of second vacuum ports. The wafer clamping controller is further configured to: generate a first feedback pressure control signal and a second feedback pressure control signal based on the first feedback temperature control signal, the second feedback temperature control signal, and the third feedback temperature control signal, the first feedback pressure control signal and the second feedback pressure control signal being configured to control the pressures of the first electronic pressure regulator and the second electronic pressure regulator, respectively.

[0009] According to one aspect of an embodiment, a wafer processing apparatus is provided, including: a heating plate through which a plurality of vacuum ports are formed and which defines a central region and an edge region surrounding the central region; a plurality of temperature sensors configured to measure the temperature of the heating plate; a heating device configured to heat the heating plate; a first power supply and a second power supply configured to supply operating power to the heating device; a first measuring device and a second measuring device configured to measure a first power output of the first power supply and a second power output of the second power supply, respectively; a first temperature controller and a second temperature controller configured to: generate a first feedback temperature control signal and a second feedback temperature control signal based on measurement values of the plurality of temperature sensors, the first feedback temperature control signal and the second feedback temperature control signal being configured to control the first power output and the second power output; an electronic pressure regulator configured to regulate the pressure of the plurality of vacuum ports; and a wafer clamping controller configured to control the pressure of the electronic pressure regulator and generate a feedback pressure control signal for controlling the pressure of the electronic pressure regulator based on the first power output and the second power output.

[0010] According to one aspect of an embodiment, a wafer processing method is provided, including: heating a heating plate through which a plurality of vacuum ports are formed and applying a vacuum pressure to the plurality of vacuum ports; loading a wafer onto the heating plate; controlling a heating device to heat the heating plate to a preset temperature and substantially maintain the heating plate at the preset temperature corresponding to a temperature change of the heating plate caused by loading the wafer onto the heating plate; identifying warping of the wafer based on a power output of the heating device; and adjusting a vacuum pressure in the plurality of vacuum ports based on the warping of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1A 、 Figure 1B and Figure 1C are schematic diagrams for describing a wafer processing apparatus according to an embodiment;

[0013] Figure 2A 、 Figure 2B and Figure 2C are plan views for describing a heating plate according to an embodiment;

[0014] Figure 3 is a flowchart of a wafer processing method according to an embodiment;

[0015] Figure 4 is a graph showing results of an experimental example for describing a wafer processing method according to an embodiment;

[0016] Figure 5 is a schematic diagram for describing a wafer processing apparatus according to other embodiments;

[0017] Figure 6 is a top view schematically showing a hot plate included in a wafer processing apparatus according to an exemplary embodiment;

[0018] Figure 7 is a flowchart of a wafer processing method according to an embodiment;

[0019] Figure 8A and Figure 8B is a plan view showing the top surface of a hot plate for clamping a wafer according to an embodiment;

[0020] Figure 9 is a schematic diagram for describing a wafer processing apparatus according to an embodiment;

[0021] Figure 10 is a flowchart of a wafer processing method according to an embodiment;

[0022] Figure 11 is a schematic perspective view for describing a baking apparatus according to an embodiment; and

[0023] Figure 12 is a block diagram of a system including a baking apparatus according to an embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments will be described in detail with reference to the drawings. In the drawings, like reference numerals will be used for like reference components, and repeated descriptions will not be given. In the following drawings, for ease of description and clarity, the thickness or size of each layer is exaggerated, so the actual shape and proportion of the components may be slightly different from the drawings. Expressions such as "at least one of..." modify the entire element list when preceding the element list, rather than modifying individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0025] Figure 1A is a schematic diagram for describing a wafer processing apparatus 100a according to an embodiment.

[0026] Reference Figure 1A, the wafer processing apparatus 100a may include: a hot plate 110, a first temperature controller 121 and a second temperature controller 123, a first power supply 131 and a second power supply 133, a wafer clamping controller 140, and an electronic pressure regulator 150. For example, the electronic pressure regulator 150 may include an electronic air flow regulator.

[0027] The wafer W may be disposed on the hot plate 110. According to one or more embodiments, the hot plate 110 may heat the wafer W to a preset temperature. According to one or more embodiments, the hot plate 110 may support and fix the wafer W and maintain the temperature of the wafer W at the preset temperature while performing various semiconductor device manufacturing processes on the wafer W.

[0028] The processes to be performed on the wafer W when the wafer W is loaded in the wafer processing apparatus 100a and supported by the hot plate 110 may include: i) a thermal oxidation process for forming an oxide layer, ii) a lithography process including spin coating, exposure, and development, iii) a thin film deposition process, and iv) a dry or wet etching process. That is to say, the hot plate 110 may be a clamping device that supports the wafer W and maintains the temperature of the wafer W during the semiconductor device manufacturing process, where the temperature of the wafer W must be maintained at the preset temperature.

[0029] The thin film deposition process to be performed on the wafer W may be, for example, at least one of the following: atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), metalorganic CVD (MOCVD), physical vapor deposition (PVD), reactive pulsed laser deposition, molecular beam epitaxy, and direct current (DC) magnetron sputtering.

[0030] The dry etching process to be performed on the wafer W may be, for example, any one of reactive ion etching (RIE), deep RIE (DRIE), ion beam etching (IBE), and argon milling. As another example, the dry etching process to be performed on the wafer W may be atomic layer etching (ALE). Additionally, the wet etching process to be performed on the wafer W may be an etching process using at least one of Cl2, HCl, CHF3, CH2F2, CH3F, H2, BCL3, SiCl4, Br2, HBr, NF3, CF4, C2F6, C4F8, SF6, O2, SO2, and COS as an etching gas.

[0031] In some embodiments, a planarization process such as a chemical mechanical polishing (CMP) process, an ion implantation process, a lithography process, etc. may also be performed on the wafer W.

[0032] The wafer W may include, for example, silicon (Si). The wafer W may include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the wafer W may have a silicon-on-insulator (SOI) structure. The wafer W may include a buried oxide layer. In some embodiments, the wafer W may include a conductive region, such as a well doped with impurities. In some embodiments, the wafer W may have various device isolation structures, such as shallow trench isolation (STI), which isolate the above-mentioned doped wells from each other. The wafer W may have a first surface and a second surface, the first surface being an active surface and the second surface being opposite to the first surface and being an inactive surface. The wafer W may be disposed on the heating plate 110 such that the second surface of the wafer W faces the heating plate 110.

[0033] Reference Figure 1A , shows that the wafer W bulges in the downward direction (i.e., in the direction facing the heating plate 110). However, the embodiments are not limited thereto. The wafer W may have an upwardly convex shape or may have a saddle-shaped shape.

[0034] A plurality of support pins 115 may be disposed on the top surface of the heating plate 110. The plurality of support pins 115 may support the wafer W disposed on the heating plate 110. The plurality of support pins 115 may prevent the wafer W from directly contacting the heating plate 110, thereby preventing the wafer W from being contaminated by the heating plate 110.

[0035] In some embodiments, a heating device 117 having a patterned thin plate shape may be disposed below the heating plate 110. However, the embodiments are not limited thereto, and the heating device 117 may be provided in the heating plate 110 or above the heating plate 110. The heating device 117 may be, for example, an electric heating device and may have various predetermined shapes to provide uniform heat to the wafer W loaded on the heating plate 110.

[0036] In some embodiments, the heating device 117 may be divided into a plurality of regions corresponding to a plurality of regions of the heating plate 110. An exemplary division structure of the heating device 117 is shown by dashed lines in Figure 2A , Figure 2B and Figure 2C . Accordingly, the heating device 117 may provide different heat outputs to different parts of the heating plate 110. Even when one region of the heating plate 110 has a higher or lower temperature than other regions of the heating plate 110, the heating device 117 may control the heat output such that the entire surface of the heating plate 110 has a uniform temperature distribution.

[0037] A plurality of vacuum ports 111 may be formed on the heating plate 110, and a vacuum pressure is provided to the plurality of vacuum ports from the outside. The plurality of vacuum ports 111 may penetrate the heating plate 110 and may be used as a path for providing the vacuum pressure. Figure 1A The vacuum pressure is indicated by using a dashed arrow. In some embodiments, the vacuum ports 111 may be arranged on the heating plate 110 in various shapes. Reference will be made below to Figure 2A , Figure 2B and Figure 2C to describe example shapes of the vacuum ports 111. The vacuum ports 111 may pull the wafer W via the vacuum pressure such that the wafer W is fixed on the plurality of support pins 115.

[0038] A temperature sensor 113 may be disposed in the heating plate 110. However, the embodiment is not limited thereto, and the temperature sensor 113 may be arranged on the top surface or the bottom surface of the heating plate 110. The temperature sensor 113 may detect the temperature of the heating plate 110. The temperature sensor 113 may be arranged in a specific arrangement in the central region CR (see Figure 2A ), the edge region ER (see Figure 2A ), and the intermediate region MR (see Figure 2A ) between the central region CR and the edge region ER.

[0039] The first temperature controller 121 and the second temperature controller 123 may generate a first temperature control signal TCS1 and a second temperature control signal TCS2 for controlling the power output of the first power supply 131 and the second power supply 133 according to a process recipe by receiving a first temperature control command TCC1 and a second temperature control command TCC2. Here, the first temperature control signal TCS1 may be a signal for controlling the output of the part corresponding to the central region CR (see Figure 2A ) of the heating device 117; and the second temperature control signal TCS2 may be a signal for controlling the output of the part corresponding to the edge region ER (see Figure 2A ) of the heating device 117.

[0040] The first temperature controller 121 and the second temperature controller 123 may receive a first temperature T1 and a second temperature T2 as temperature measurement values from the temperature sensor 113. The first temperature T1 may be the temperature measured by the temperature sensor 113 disposed in the central region CR (see Figure 2A ) of the heating plate 110, and the second temperature T2 may be the temperature measured by the temperature sensor 113 corresponding to the edge region ER (see Figure 2A ) of the heating plate 110.

[0041] The first temperature controller 121 and the second temperature controller 123 can generate a first feedback temperature control signal FTCS1 and a second feedback temperature control signal FTCS2 based on the first temperature T1 and the second temperature T2. The first feedback temperature control signal FTCS1 can be a signal corresponding to the central region CR of the heating plate 110 (see Figure 2A ), and the second feedback temperature control signal FTCS2 can be a signal corresponding to the edge region ER of the heating plate 110 (see Figure 2A ).

[0042] The first feedback temperature control signal FTCS1 and the second feedback temperature control signal FTCS2 can be feedback signals based on the first temperature T1 and the second temperature T2. For example, when the first temperature T1 is lower than the temperature according to the process recipe, the first temperature controller 121 can generate the first feedback temperature control signal FTCS1 to increase the power output of the first power supply 131. Conversely, when the second temperature T2 is higher than the temperature according to the process recipe, the second temperature controller 123 can generate the second feedback temperature control signal FTCS2 to decrease the power output of the second power supply 133.

[0043] The first power supply 131 and the second power supply 133 can generate a power output according to the first temperature control signal TCS1 and the second temperature control signal TCS2 or the first feedback temperature control signal FTCS1 and the second temperature control signal FTCS2, and can supply the power output to the heating device 117. The first power supply 131 can transmit the power output to the part of the heating device 117 corresponding to the central region CR of the heating plate 110 (see Figure 2A ). The second power supply 133 can transmit the power output to the part of the heating device 117 corresponding to the edge region ER of the heating plate 110 (see Figure 2A ).

[0044] The wafer clamping controller 140 can control the electronic pressure regulator 150. The wafer clamping controller 140 can generate a pressure control signal PCS for controlling the electronic pressure regulator 150 based on an external wafer clamping command WCC.

[0045] The wafer clamping controller 140 can generate a feedback pressure control signal FPCS based on the first feedback temperature control signal FCS1 and the second feedback temperature control signal FCS2, and the feedback pressure control signal FPCS is a signal for controlling the electronic pressure regulator 150. The wafer clamping controller 140 can perform specific calculations based on the first feedback temperature control signal FTCS1 and the second feedback temperature control signal FTCS2 of the first temperature controller 121 and the second temperature controller 123. The wafer clamping controller 140 can determine the warpage of the wafer W through the above calculations. According to one or more embodiments, the wafer clamping controller 140 can generate the feedback pressure control signal FPCS based on the determined warpage of the wafer W. According to other embodiments, the wafer clamping controller 140 can generate the feedback pressure control signal FPCS based on the results of the above calculations without determining the warpage of the wafer W. The calculations of the wafer clamping controller 140 will be described again below.

[0046] In some embodiments, the electronic pressure regulator 150 can adjust the intensity of the vacuum pressure of the vacuum port 111 based on the pressure control signal PCS or the feedback pressure control signal FPCS. In some embodiments, the electronic pressure regulator 150 can include a servo valve or a solenoid valve. According to other embodiments, the electronic pressure regulator 150 can include an electronic vacuum pressure sensor. The electronic pressure regulator 150 can also include an internal pressure sensor for monitoring the pressure output.

[0047] When the wafer processing apparatus according to the prior art fixes the wafer W by using the vacuum pressure method, the wafer processing apparatus can fix the wafer W by applying the maximum pressure with a vacuum valve controlled by a switching method without considering the warpage of the wafer W. Fixing the wafer W by using the vacuum pressure method generates turbulent air and causes uneven heat loss at the edge of the wafer W, thereby deteriorating the uniform heat distribution on the entire surface of the wafer W.

[0048] According to one or more embodiments, it is possible to determine whether the wafer W has warpage and the degree of warpage based on the first feedback temperature control signal FTCS1 and the second feedback temperature control signal FTCS2, and the wafer pressure control signal FPCS can be generated based on the determined warpage of the wafer W. Therefore, the wafer W can be fixed by using the optimal vacuum pressure. Here, the optimal vacuum pressure can be any one of the minimum pressure for fixing the wafer W and the minimum pressure for reducing the warpage of the wafer W and uniformly processing the wafer W. Therefore, an excessive vacuum pressure exceeding the necessary amount does not have to be applied to the wafer W, and the turbulent air between the wafer W and the heating plate 110 can be minimized. Therefore, the reliability of the uniform processing of the wafer W can be improved.

[0049] The first temperature controller 121, the second temperature controller 123, and the wafer clamping controller 140 may include hardware, firmware, software, or a combination thereof.

[0050] For example, the first temperature controller 121, the second temperature controller 123, and the wafer clamping controller 140 may include computing devices such as a workstation computer, a desktop computer, a laptop computer, a tablet computer, etc. The first temperature controller 121, the second temperature controller 123, and the wafer clamping controller 140 may include simple controllers (e.g., hardware controllers), microprocessors, complex processors (e.g., central processing unit (CPU), graphics processing unit (GPU), etc.), processors including software, dedicated hardware, or firmware. The first temperature controller 121, the second temperature controller 123, and the wafer clamping controller 140 may include general-purpose computers or dedicated hardware such as digital signal processors (DSPs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), etc.

[0051] In some embodiments, the operations of the first temperature controller 121, the second temperature controller 123, and the wafer clamping controller 140 may be implemented by using commands that can be read and executed by one or more processors and stored on a computer-readable recording medium. Here, the computer-readable recording medium may include certain mechanisms for storing and / or transmitting information in a machine (e.g., a computing device) readable form. For example, the computer-readable recording medium may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash devices, electrical, optical, acoustic, or other radio wave signals (e.g., carrier waves, infrared signals, digital signals, etc.), and other random signals.

[0052] The firmware, software, routines, or instructions may be configured to perform the operations described with respect to the first temperature controller 121, the second temperature controller 123, and the wafer clamping controller 140 or other processes to be described below. For example, with respect to processing the wafer W, the first temperature controller 121, the second temperature controller 123, and the wafer clamping controller 140 may be implemented by using software for generating signals, receiving data for feedback, performing certain calculations, and adjustment processes.

[0053] However, this is for ease of explanation. The operations of the first temperature controller 121, the second temperature controller 123, and the wafer clamping controller 140 may be performed by using a computing device, a processor, a controller, or other devices that execute firmware, software, routines, instructions, etc.

[0054] Figure 1B It is a schematic diagram for describing the wafer processing apparatus 100b according to other embodiments.

[0055] For ease of description, aspects that are the same as those described in the reference Figure 1A will not be repeated.

[0056] Reference Figure 1B , in addition to Figure 1A the components of the wafer processing apparatus 100a shown, the wafer processing apparatus 100b may further include a first measuring device 132 (i.e., a meter) and a second measuring device 134.

[0057] The first measuring device 132 may be disposed between the first power supply 131 and the heating plate 110. The first measuring device 132 may be connected to a path through which the power output of the first power supply 131 is supplied to the heating plate 110. The second measuring device 134 may be disposed between the second power supply 133 and the heating plate 110. The second measuring device 134 may be connected to a path through which the power output of the second power supply 133 is supplied to the heating plate 110.

[0058] The first measuring device 132 and the second measuring device 134 may be any one of a voltmeter, an ammeter, and a wattmeter. In some embodiments, the first measuring device 132 may measure a first power output O1, which is the power output of the first power supply 131. The first power output O1 may be the power output of the portion corresponding to the central region CR of the heating plate 110 (see Figure 2A ) that is transmitted to the heating device 117, and may be any one of voltage, current, or power. In some embodiments, the second measuring device 134 may measure a second power output O2, which is the power output of the second power supply 133. The second power output O2 may be the power output of the portion corresponding to the edge region ER of the heating plate 110 (see Figure 2A ) that is transmitted to the heating device 117, and may be any one of voltage, current, and power.

[0059] The wafer clamping controller 140 may generate a feedback pressure control signal FPCS based on the first power output O1 and the second power output O2. More specifically, the wafer clamping controller 140 may perform a specific calculation based on the first power output O1 and the second power output O2, and then may generate a feedback pressure control signal FPCS for controlling the electronic pressure regulator 150 based on the calculation result.

[0060] Figure 1C is a schematic diagram for describing a wafer processing apparatus 100c according to other embodiments.

[0061] For ease of description, aspects that are the same as those described in the reference Figure 1A will not be repeated.

[0062] Reference Figure 1C, different from the wafer processing apparatus 100a shown in Figure 1A , the wafer processing apparatus 100c may include a process controller 120 configured to control the temperature of the hot plate 110 and control the output pressure of the electronic pressure regulator 150. In some embodiments, the process controller 120 may perform the functions of the first temperature controller 121 and the second temperature controller 123 and the wafer clamping controller 140 shown in Figure 1A .

[0063] The process controller 120 may include various types of computing devices or processor devices, as described above with respect to the first temperature controller 121, the second temperature controller 123, and the wafer clamping controller 140 in Figure 1A . The process controller 120 may include software and / or firmware for controlling the temperature of the hot plate 110 and controlling the pressure output of the electronic pressure regulator 150.

[0064] In some embodiments, the process controller 120 may generate a first temperature control signal TCS1, a second temperature control signal TCS2, and a pressure control signal PCS according to a process recipe by receiving a wafer processing command WPC.

[0065] In some embodiments, the process controller 120 may receive signals regarding the first temperature T1 and the second temperature T2 from the temperature sensors 113; generate a first feedback temperature control signal FTCS1 and a second feedback temperature control signal FTCS2 for controlling the temperature of the hot plate 110 by using the signals regarding the first temperature T1 and the second temperature T2; and send the first feedback temperature control signal FTCS1 and the second feedback temperature control signal FTCS2 to the first power supply 131 and the second power supply 133, respectively.

[0066] In some embodiments, the process controller 120 may generate a feedback pressure control signal FPCS for controlling the electronic pressure regulator 150 based on the first feedback temperature control signal FTCS1 and the second feedback temperature control signal FTCS2.

[0067] Figure 2A , Figure 2B and Figure 2C are plan views for describing the hot plate 110 according to an embodiment.

[0068] Referring to Figure 2A , Figure 2B and Figure 2C , a central region CR, an edge region ER, and an intermediate region MR between the central region CR and the edge region ER may be defined on the hot plate 110.

[0069] In some embodiments, as shown in Figure 2A ,Figure 2B and Figure 2C As shown, the vacuum port 111 can be arranged symmetrically with respect to the central circle of the heating plate 110. Based on this arrangement of the vacuum port 111, the wafer W loaded on the heating plate 110 can be fixed via a uniform pressure (see Figure 1A ).

[0070] In Figure 2A the example of Figure 2B the vacuum port 111 can be arranged at the middle region MR of the heating plate 110. In Figure 2C the example of

[0071] Figure 3 is a flowchart of a wafer processing method according to an embodiment.

[0072] Referring to Figure 1A and Figure 3 the heating plate 110 can be heated in operation P110.

[0073] As described above, the first temperature controller 121 and the second temperature controller 123 can respectively generate a first temperature control signal TCS1 and a second temperature control signal TCS2 based on the first temperature control command TCC1 and the second temperature control command TCC2 according to the process recipe.

[0074] Based on the received first temperature control signal TSC1 and second temperature control signal TSC2, the first power supply 131 and the second power supply 133 can heat the heating plate 110 to have a uniform temperature over the entire surface of the heating plate 110.

[0075] Figure 4 is a graph showing the results of an experimental example for describing a wafer processing method according to an embodiment. More specifically, Figure 4 the temperature of the edge region ER of the heating plate 110 (see Figure 2A ) and the power output of the second power supply 133 with respect to the processing instruction of the wafer W over time.

[0076] In Figure 4 the graph, the vertical axis indicates the temperature of the heating plate 110 or the power output of the second power supply 133, and the horizontal axis indicates time. In addition, in Figure 4 the graph, the solid line indicates the temperature of the edge region ER of the heating plate 110 (see Figure 2A ), and the dashed line indicates the power output of the second power supply 133.

[0077] Referring to Figure 1A andFigure 2A , Figure 3 and Figure 4 , in operation P120, the wafer W can be loaded onto the hot plate 110. The loading of the wafer W can be performed by a transfer robot, and the loaded wafer can be fixed by the vacuum pressure of the vacuum port 111.

[0078] In Figure 4 the experimental example, a substantially flat (i.e., without warpage) wafer is loaded at the first time point t1, and a wafer with warpage is loaded at the second time point t2.

[0079] When the wafer W loaded at the second time point t2 is loaded such that its inactive surface faces the hot plate 110, the distance between the edge region ER of the hot plate 110 and the wafer W is greater than the distance between the central region CR of the hot plate 110 and the wafer W. The wafer W in the experimental example can have a warpage of approximately 350 μm. Here, a warpage of approximately 350 μm indicates a height difference of approximately 350 μm between the highest point and the lowest point relative to the top surface of the wafer W.

[0080] Generally, according to the process recipe, the temperature of the wafer W is lower than the temperature of the hot plate 110 immediately before the wafer W is loaded onto the hot plate 110. Therefore, immediately after the wafer W is loaded, the temperature of the edge region ER of the hot plate 110 can decrease.

[0081] Compared with the first time point t1 when a flat wafer is loaded, the second time point t2 shows a relatively small temperature drop in the edge region ER of the hot plate 110 immediately after the wafer W is loaded. Therefore, the power output of the second power supply 133 at the second time point t2 is less than the power output of the first power supply 131 at the first time point t1.

[0082] Table 1 below shows the temperatures of the central region CR, the middle region MR, and the edge region ER of the hot plate 110 immediately after a flat wafer is loaded, the temperatures of the central region CR, the middle region, and the edge region ER immediately after a wafer with warpage is loaded, and the ratios of the corresponding temperatures.

[0083] [Table 1]

[0084]

[0085] As described above, a plurality of temperature sensors are arranged at predetermined positions on the entire surface of the hot plate 110, and Table 1 shows the minimum values of the measured values of the temperature sensors arranged in the central region CR, the middle region MR, and the edge region ER.

[0086] The ratio of the temperature after the change immediately following the loading of the flat wafer W and the warped wafer W is from about 100.5% to about 100.9%, indicating rather low recognition characteristics.

[0087] Next, referring to Figure 1A and Figure 3 , in operation P130, the heating device 117 can be controlled such that the heating plate 110 has a preset temperature.

[0088] Operation P130 can be performed substantially simultaneously with the loading of the wafer W in operation P120, or immediately following the loading of the wafer W in operation P120.

[0089] As described above, controlling the heating device 117 can include: measuring the temperature of the heating plate 110 for each region, the temperature including a first temperature T1 and a second temperature T2; generating a first feedback temperature control signal FTCS1 and a second feedback temperature control signal FTCS2 based on the temperature for each region; and providing a power output to portions of the heating device 117 corresponding to different regions of the heating plate 110 based on the first feedback temperature control signal FTCS1 and the second feedback temperature control signal FTCS2.

[0090] Next, referring to Figure 1A and Figure 3 , in operation P140, the vacuum pressure for clamping the wafer W can be adjusted based on the power output of the heating device 117.

[0091] Table 2 below shows the power outputs of the heating device 117 corresponding to the central region CR, the middle region MR, and the edge region ER of the heating plate 110 immediately following the first time point t1 and the second time point t2, where a flat wafer W and a warped wafer W are loaded at the first time point t1 and the second time point t2, respectively.

[0092] [Table 2]

[0093]

[0094] Compared with Table 1 in which the temperature difference between wafers is smaller for the central region CR, the middle region MR, and the edge region ER of the heating plate 110 immediately following the loading of the non-warped wafer W and the warped wafer W, it can be seen from Table 2 that for the warped wafer B and the flat wafer A, the difference in the power outputs of the heating device 117 corresponding to the central region CR and the edge region ER is larger.

[0095] For ease of description, the difference between the power output of the heating device 117 (or power supply) corresponding to the central region CR and the power output of the heating device 117 (or power supply) corresponding to the edge region ER will be referred to as the center-edge power output difference.

[0096] In some embodiments, the wafer clamping controller 140 may calculate the center-edge power output difference. Additionally, in some embodiments, the wafer clamping controller 140 may calculate the ratio of the center-edge power output difference of the warped wafer B to the center-edge power output difference of the non-warped wafer A. As shown in Table 2, the ratio of the center-edge power output difference of the wafer B with a warp of approximately 350 μm to the center-edge power output difference of the flat wafer A may be approximately 232.2%, indicating high recognition characteristics regarding whether warping occurs and the degree of warping.

[0097] In Figures 2A to 2C , the maximum power output in the power output of the heating device 117 corresponding to the central region CR is compared with the maximum power output in the power output of the heating device 117 corresponding to the edge region ER. However, the embodiments are not limited thereto. In other embodiments, the wafer clamping controller 140 may calculate the center-edge power output difference by comparing the minimum power output in the power output of the heating device 117 corresponding to the central region CR with the minimum power output in the power output of the heating device 117 corresponding to the edge region ER.

[0098] Furthermore, as described below, the wafer clamping controller 140 may determine whether the wafer is warped and the degree of warping. In some embodiments, when the wafer clamping controller 140 determines that the wafer W has a warp with a downward convex shape, the wafer clamping controller 140 may calculate the center-edge power output difference by comparing the maximum power output in the power output of the heating device 117 corresponding to the central region CR with the minimum power output in the power output of the heating device 117 corresponding to the edge region ER.

[0099] In other embodiments, when the wafer clamping controller 140 determines that the wafer W has a warp with an upward convex shape, the wafer clamping controller 140 may calculate the center-edge power output difference by comparing the minimum power output in the power output of the heating device 117 corresponding to the central region CR with the maximum power output in the power output of the heating device 117 corresponding to the edge region ER.

[0100] In other embodiments, the wafer clamping controller 140 may calculate the center-edge power output difference by comparing the average power output of the power output of the heating device 117 corresponding to the central region CR with the average power output of the power output of the heating device 117 corresponding to the edge region ER. In other embodiments, the wafer clamping controller 140 may calculate the center-edge power output difference by comparing the median power output of the power output of the heating device 117 corresponding to the central region CR with the median power output of the power output of the heating device 117 corresponding to the edge region ER.

[0101] According to an example embodiment, the wafer clamping controller 140 may determine whether the wafer W is warped based on the first feedback temperature control signal and the second feedback temperature control signal without the aid of an additional height measurement sensor. In some embodiments, the wafer clamping controller 140 may determine whether the wafer W is warped and the degree of warping by using a lookup function of data related to the center-edge power output difference of the currently processed wafer W, or by comparing previous online / offline data, etc. In other embodiments, the wafer clamping controller 140 may determine whether the wafer W is warped and the degree of warping by using a lookup function of data related to the ratio of the center-edge power output difference of the flat wafer W to the center-edge power output difference of the currently processed wafer W, or by comparing previous online / offline data, etc.

[0102] The wafer clamping controller 140 may generate a feedback pressure control signal FPCS based on the warping of the wafer W. For example, according to the feedback pressure control signal FPCS, when the wafer W has a large warping, the electronic pressure regulator 150 may be configured to output a greater vacuum pressure, and when the wafer W has a small warping, the electronic pressure regulator 150 may be configured to output a smaller vacuum pressure.

[0103] In other embodiments, the wafer clamping controller 140 may generate a feedback pressure control signal FPCS based on the first feedback temperature control signal FTCS1 and the second feedback temperature control signal FTCS2. More specifically, the wafer clamping controller 140 may generate the feedback pressure control signal FPCS by using a lookup function of data related to the optimal pressure control signal based on the center-edge power output difference of the currently processed wafer W, or by comparing previous online / offline data.

[0104] Above, a wafer processing method performed by the Figure 1A wafer processing apparatus 100a has been described. However, those of ordinary skill in the art will understand that Figure 1B and Figure 1CThe wafer processing apparatuses 100b and 100c can process wafers by using substantially the same method.

[0105] Figure 5 FIG. is a schematic view for describing the wafer processing apparatus 200 according to other embodiments.

[0106] Figure 6 FIG. is a schematic top view of a hot plate 210 included in the wafer processing apparatus 200 according to an exemplary embodiment.

[0107] For ease of description, aspects that are the same as those described with reference to Figure 1A will not be repeated.

[0108] Reference Figure 5 and Figure 6 The wafer processing apparatus 200 may include a hot plate 210, first to third temperature controllers 121 to 125, first to third power supplies 131 to 135, a wafer clamping controller 140, and first and second electronic pressure regulators 151 and 153.

[0109] The temperature sensor 213, the support pins 215, and the heating device 217 may be substantially the same as the temperature sensor 113, the support pins 115, and the heating device 117 described above with reference to Figure 1A respectively.

[0110] An inner vacuum port 211I and an outer vacuum port 211O may be formed on the hot plate 210. Each of the inner vacuum port 211I and the outer vacuum port 211O may be symmetrically arranged with respect to the central circle of the top surface of the hot plate 210. Figure 6 FIG. shows the inner vacuum port 211I formed in the middle region MR and the outer vacuum port 211O formed in the edge region ER. However, the embodiments are not limited thereto.

[0111] According to a process recipe, the first to third temperature controllers 121 to 125 may generate first to third temperature control signals TCS1, TCS2, and TCS3 based on first to third temperature control commands TCC1, TCC2, and TCC3, respectively. The first temperature control signal TCS1 may be a signal for controlling the power output of the first power supply 131 corresponding to the central region CR of the hot plate 210. The second temperature control signal TCS2 may be a signal for controlling the power output of the second power supply 133 corresponding to the edge region ER of the hot plate 210. The third temperature control signal TCS3 may be a signal for controlling the power output of the third power supply 135 corresponding to the middle region MR of the hot plate 210.

[0112] The first power supply 131 to the third power supply 135 may supply operating power to portions of the heating device 217 corresponding to the central region CR, the edge region ER, and the middle region MR of the heating plate 210 in response to the first temperature control signal to the third temperature control signals TCS1, TCS2, and TCS3, respectively.

[0113] A plurality of temperature sensors 213 may measure the first temperature to the third temperature T1, T2, and T3, which are the temperatures of the central region CR, the edge region ER, and the middle region MR of the heating plate 210, respectively.

[0114] The first temperature controller 121 to the third temperature controller 125 may read signals regarding the first temperature to the third temperature T1, T2, and T3, and generate the first feedback temperature control signal to the third feedback temperature control signals FTCS1, FTCS2, and FTCS3 based on the read signals. Since the first power supply 131 to the third power supply 135 supply power output to the heating device 217 according to the first feedback temperature control signal to the third feedback temperature control signals FTCS1, FTCS2, and FTCS3, a uniform temperature distribution may be achieved over the entire surface of the heating plate 210. Accordingly, uniform processing of the wafer W is feasible.

[0115] The wafer clamping controller 140 may generate a first pressure control signal PCS1 and a second pressure control signal PCS2 based on the wafer clamping command WCC. The first electronic pressure regulator 151 may regulate the vacuum pressure of the inner vacuum port 211I based on the first pressure control signal PCS1. The second electronic pressure regulator 153 may regulate the vacuum pressure of the outer vacuum port 211O based on the second pressure control signal PCS2. Optionally, the pressure of the outer vacuum port 211O and the pressure of the inner vacuum port 211I may be different from each other.

[0116] The wafer clamping controller 140 can generate a first feedback pressure control signal FPCS1 and a second feedback pressure control signal FPCS2 based on the first to third feedback temperature control signals FTCS1, FTCS2, and FTCS3. The wafer clamping controller 140 can determine whether the wafer W is warped based on the first to third feedback temperature control signals FTCS1, FTCS2, and FTCS3. The wafer clamping controller 140 can determine the vertical distance from a specific position on the wafer W to the heating plate 210 based on the first to third feedback temperature control signals FTCS1, FTCS2, and FTCS3. In some embodiments, the wafer clamping controller 140 can determine the three-dimensional shape of the wafer W and, based on the three-dimensional shape of the wafer W, generate a first feedback pressure signal FPCS1 and a second feedback pressure signal FPCS2 for clamping the wafer W with an optimal vacuum pressure. The first electronic pressure regulator 151 and the second electronic pressure regulator 153 can respectively adjust the pressure of the inner vacuum port 211I and the pressure of the outer vacuum port 211O based on the first feedback pressure signal FPCS1 and the second feedback pressure signal FPCS2.

[0117] Figure 5 and Figure 6 shows that two electronic pressure regulators are provided to respectively adjust the pressure of the inner vacuum port 211I and the pressure of the outer vacuum port 211O. However, the embodiment is not limited thereto. For example, each vacuum port can be connected to a different electronic pressure regulator, and different pressures can be applied to each vacuum port. In addition, in addition to the edge region ER and the middle region MR, additional vacuum ports can be provided at the center region CR.

[0118] Figure 7 is a flowchart of a wafer processing method according to an embodiment.

[0119] For ease of description, aspects that are the same as those described with reference to Figure 3 will not be repeated.

[0120] Figure 7 The operations P210 and P220 can be respectively substantially the same as Figure 3 the operations P110 and P120.

[0121] Referring to Figures 5 to 7 , in operation P230, the heating device 217 can be controlled such that the heating plate 210 has a preset temperature.

[0122] Operation P230 can be performed substantially simultaneously with loading the wafer W in operation P220, or immediately after loading the wafer W in operation P220.

[0123] Controlling the heating device 217 can be similar to the operations described above. More specifically, controlling the heating device 217 can include: measuring the temperature of the heating plates 210 for each region, the temperature including a first temperature T1 to a third temperature T3; generating a first feedback temperature control signal FTCS1 to a third feedback temperature control signal FTCS3 based on the temperature for each region; and based on the first feedback temperature control signal FTCS1 to the third feedback temperature control signal FTCS3, providing a power output to portions of the heating device 217 corresponding to different regions of the heating plates 210.

[0124] Next, referring to Figure 1A and Figure 3 , in operation P240, the vacuum pressure for clamping the wafer W can be adjusted based on the power output of the heating device 217.

[0125] In some embodiments, the wafer clamping controller 140 can compare the power outputs of the heating device 217 corresponding to the central region CR, the edge region ER, and the middle region MR of the heating plate 210, respectively, with a reference value. The reference value can be the power outputs of the heating device 217 corresponding to the central region CR, the edge region ER, and the middle region MR of the heating plate 210, respectively, immediately after loading a non-warped wafer W onto the heating plate 210.

[0126] In some embodiments, the wafer clamping controller 140 can calculate the distance from a specific position on the wafer W to the heating plate 210 based on the difference between the power outputs of the heating device 217 corresponding to the central region CR, the edge region ER, and the middle region MR of the heating plate 210, respectively, and the reference value. In some embodiments, the wafer clamping controller 140 can determine the three-dimensional shape of the wafer W based on the calculated distance.

[0127] In other embodiments, the wafer clamping controller 140 can determine the three-dimensional shape of the wafer W by using a lookup function regarding data related to the difference between the reference value and the power outputs of the heating device 217 corresponding to the central region CR, the edge region ER, and the middle region MR of the heating plate 210, respectively, or by comparing previous online / offline data.

[0128] The wafer clamping controller 140 can generate a first feedback pressure control signal FPCS1 and a second feedback pressure control signal FPCS2 based on the three-dimensional shape of the wafer W. Based on the first feedback pressure control signal FPCS1 and the second feedback pressure control signal FPCS2, the first electronic pressure regulator 151 and the second electronic pressure regulator 153 can output a vacuum pressure for minimizing the warping of the wafer W.

[0129] According to an exemplary embodiment, even when the wafer W to be processed has warpage with an irregular shape, the first electronic pressure regulator 151 and the second electronic pressure regulator 153 can perform a control operation to minimize the warpage. Accordingly, the reliability of uniform processing of the wafer W can be improved.

[0130] Figure 8A and Figure 8B is a plan view showing the top surface of the hot plate 110 for clamping the wafer W according to an embodiment.

[0131] Figure 8A and Figure 8B The inner vacuum ports 211I and the outer vacuum ports 211O indicated by relatively thick lines among the inner vacuum port 211I and the outer vacuum port 211O in [[ ]] indicate that control operations are performed thereon based on the feedback pressure control signals FPCS1 and FPCS2. Further, the inner vacuum ports 211I and the outer vacuum ports 211O indicated by relatively thin lines among the inner vacuum port 211I and the outer vacuum port 211O indicate that control operations are performed thereon based on the feedback pressure control signals FPCS1 and FPCS2.

[0132] Operations of controlling the first electronic pressure regulator 151 and the second electronic pressure regulator 153 based on the first feedback pressure control signal FPCS1 and the second feedback pressure control signal FPCS2 can be sequentially performed. For example, as Figure 8A shown, after controlling the inner vacuum port 211I based on the first feedback pressure control signal FPCS1 to receive an optimal vacuum pressure, as Figure 8B shown, the outer vacuum port 211O can be controlled based on the second feedback pressure control signal FPCS2 to receive an optimal vacuum pressure.

[0133] However, the embodiment is not limited thereto. Optimization operations based on the first feedback pressure control signal FPCS1 and the second feedback pressure control signal FPCS2 can be substantially simultaneously performed on the inner vacuum port 211I and the outer vacuum port 211O, or the optimization operation can be first performed on the outer vacuum port 211O and then on the inner vacuum port 211I.

[0134] Figure 9 is a schematic diagram for describing a wafer processing apparatus 300 according to an embodiment.

[0135] For ease of description, aspects that are the same as those described with reference to Figure 1A will not be repeated.

[0136] Reference Figure 9, the wafer processing apparatus 300 may include a hot plate 110, a vacuum port 111, support pins 115, a heating device 117, a temperature controller 320, a first power supply 131 and a second power supply 133, and a pressure valve 350.

[0137] The hot plate 110, the vacuum port 111, the support pins 115, the heating device 117, and the first power supply 131 and the second power supply 133 are substantially the same as the components described with reference to Figure 1A description.

[0138] The pressure valve 350 may be connected to an external device such as a vacuum pump, and the vacuum pressure generated by the vacuum pump may be supplied to the vacuum port 111 through the pressure valve 350. Different from Figure 1A the electronic pressure regulator 160 in, the pressure valve 350 may supply a substantially constant pressure to the vacuum port 111.

[0139] The temperature controller 320 may generate a first temperature control signal TCS1 and a second temperature control signal TCS2 for respectively controlling the first power supply 131 and the second power supply 133 based on a process recipe according to a wafer processing command WPC.

[0140] The temperature controller 320 may use the same method as the method described with reference to Figure 1A , Figure 1B , Figure 1C , Figure 2A , Figure 2B , Figure 2C , Figure 3 and Figure 4 description to determine whether the wafer W has warpage and the degree of warpage. More specifically, the wafer warpage controller 340 may generate a first warpage-based temperature control signal WBTCS1 and a second warpage-based temperature control signal WBTCS2 based on the degree of warpage of the wafer W.

[0141] According to the prior art, when the temperature drop of the hot plate 110 due to the loading of the wafer W is small, the temperature controller 320 may generate a signal for controlling the first power supply 131 and the second power supply 133 to output a relatively low power output.

[0142] According to an embodiment, the temperature controller 320 may determine the warpage of the wafer W based on the first temperature T1 and the second temperature T2 of the hot plate 110. The temperature controller 320 may generate a first warpage-based temperature control signal WBTCS1 and a second warpage-based temperature control signal WBTCS2 to heat the entire surface of the wafer W substantially uniformly.

[0143] More specifically, when the first temperature T1 (i.e., the central region CR of the hot plate 110 (see Figure 2A), the decrease in temperature of the first temperature T1 (i.e., the center region CR of the heating plate 110 (see Figure 2A ), when the decrease in temperature of the second temperature T2 (i.e., the edge region ER of the heating plate 110 (see

[0144] ), the temperature controller 320 can determine that the wafer W has a downward convex warp. Figure 2A ), the power output of the part corresponding to the edge region ER of the heating plate 110 (see Figure 2A ), which is transmitted to the heating device 117, is greater than the power output of the part corresponding to the center region CR of the heating plate 110 (see

[0145] Figure 10 is a flowchart of a wafer processing method according to an embodiment.

[0146] Figure 10 The operations P310 and P320 can be substantially the same as Figure 3 the operations P110 and P120.

[0147] Refer to Figure 9 and Figure 10 , in operation P330, the warp of the wafer W can be determined based on the measured value of the temperature sensor 113.

[0148] The temperature controller 320 can determine the warp of the wafer W based on the first temperature T1 and the second temperature T2 of the heating plate 110, based on the data on the previous feedback temperature control signal.

[0149] Next, in operation P340, the heating device 117 can be controlled based on the warp of the wafer W.

[0150] The control of the heating device 117 can include: generating a first warp-based temperature control signal WBTCS1 and a second warp-based temperature control signal WBTCS2 via the temperature controller 320, and supplying the power output generated based on the first warp-based temperature control signal WBTCS1 and the second warp-based temperature control signal WBTCS2 to the heating device 117 via the first power supply 131 and the second power supply 133. As described above, the heating device 117 can be controlled to output relatively more heat to the part of the heating plate 110 that is relatively far from the wafer W.

[0151] Figure 11 is an exploded perspective view schematically showing the main components of a baking apparatus BA according to an exemplary embodiment.

[0152] Reference Figure 11 , in addition to the components included in the wafer processing apparatus 100a of Figure 1A , the baking apparatus BA may further include a chamber 170, a transfer robot 180, and a substrate module 190.

[0153] However, the embodiments are not limited thereto. In addition to the components included in Figure 1B , Figure 1C , Figure 5 and Figure 9 of the wafer processing apparatuses 100b, 100c, 200, and 300, the baking apparatus BA may further include a chamber 170, a transfer robot 180, and a substrate module 190.

[0154] The transfer robot 180 can introduce a wafer into the baking apparatus BA or take out a fully processed wafer from the baking apparatus BA.

[0155] The chamber 170 may include an exhaust structure for discharging the gas generated during the heating of the wafer. During the execution of the processing operation, the chamber 170 can isolate the wafer from the outside. The chamber 170 can prevent the heat used for processing the wafer from being discharged to the outside of the chamber 170 and can prevent the wafer from being contaminated by particles outside the chamber 170. The chamber 170 can cover both the heating plate 110 and the wafer, or can cover only the wafer.

[0156] The substrate module 190 can support various components included in the baking apparatus BA, such as the heating plate 110, the chamber 170, etc.

[0157] When the wafer is transferred by the transfer robot 180, the chamber 170 can be opened, the wafer can be loaded onto the heating plate by the transfer robot 180, and the chamber 170 can be closed. Next, when the wafer is sufficiently heated, the chamber 170 can be opened again, and the wafer can be taken out by the transfer robot 180.

[0158] Figure 12 is a block diagram of a system SYS including a baking apparatus BA according to an embodiment.

[0159] Reference Figure 12 , the system SYS may include a spin coater SC, a lithography apparatus LA, a baking apparatus BA, and a developing device DA.

[0160] The processes performed by the system SYS may include manufacturing a semiconductor wafer or a semiconductor structure including a wafer having a circuit structure. The processes performed by the system SYS may include, for example, semiconductor processes based on deep ultraviolet (DUV) or extreme ultraviolet (EUV).

[0161] The spin coater SC can set a photoresist layer on the semiconductor structure SS by using a spin coating method.

[0162] The baking apparatus BA can be the baking apparatus BA described in Figure 12 In some embodiments, after the photoresist layer is coated on the wafer by the spin coater SC, the baking apparatus BA can perform a soft baking process. In some embodiments, the baking apparatus BA can also perform a post-exposure bake (POB) process after the exposure process of the lithography apparatus LA, and a hard baking process after the development process of the developing apparatus DA.

[0163] The lithography apparatus LA can perform an EUV lithography process. The lithography apparatus LA can include a measurement station and an exposure station.

[0164] The lithography apparatus LA can be a dual-stage apparatus including two wafer stages. The wafer stages can be an exposure station for exposure and a measurement station for measurement, respectively. Thus, when the semiconductor structure SS on one wafer stage is exposed, the semiconductor structure SS on the other wafer stage can be measured before being exposed. Since measuring alignment marks takes a lot of time and the lithography process is a bottleneck process in the entire semiconductor process, the productivity of semiconductor devices can be significantly improved when two wafer stages are provided. However, the embodiments are not limited thereto. The lithography apparatus LA can include a single-stage lithography apparatus having a single wafer stage.

[0165] The developing apparatus DA can form a photoresist pattern by developing the exposed photoresist layer.

[0166] The system SYS can also include an inspection apparatus for inspection after exposure as needed. The inspection apparatus can include a scatterometer, such as an angle-resolved scatterometer or a spectroscopic scatterometer.

[0167] The system SYS can also include, for example, an etching apparatus. The etching apparatus can etch the wafer by using the developed photoresist layer as an etching mask. According to other embodiments, the system SYS can also include apparatuses for performing ion implantation processes, deposition processes, etc.

[0168] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it should be understood that various changes in form and detail can be made without departing from the spirit and scope of the appended claims.

Claims

1. A wafer processing apparatus, comprising: A heating plate, through which a plurality of vacuum ports are formed and a central region and an edge region surrounding the central region are defined; A plurality of temperature sensors assembled in the heating plate; Heating equipment configured to heat the heating plate; A first power supply and a second power supply configured to respectively supply operating power to different parts of the heating equipment to maintain the heating plate at a preset temperature; A first temperature controller configured to generate a first feedback temperature control signal for controlling the power output of the first power supply based on a first measurement value generated by the plurality of temperature sensors; A second temperature controller configured to generate a second feedback temperature control signal for controlling the power output of the second power supply based on a second measurement value generated by the plurality of temperature sensors; An electronic pressure regulator configured to provide a vacuum pressure for fixing a wafer disposed on the heating plate to the plurality of vacuum ports and regulate the pressure of the plurality of vacuum ports; And A wafer clamping controller configured to control the electronic pressure regulator and generate a feedback pressure control signal for controlling the pressure of the electronic pressure regulator based on the first feedback temperature control signal and the second feedback temperature control signal.

2. The wafer processing apparatus according to claim 1, wherein, The wafer clamping controller is further configured to: identify a power difference between the first power supply and the second power supply based on the first feedback temperature control signal and the second feedback temperature control signal.

3. The wafer processing apparatus according to claim 1, wherein, The plurality of temperature sensors include: a first temperature sensor corresponding to the central region and a second temperature sensor corresponding to the edge region, wherein the first temperature sensor is configured to generate the first measurement value, and the second temperature sensor is configured to generate the second measurement value, wherein the first temperature controller is further configured to generate the first feedback temperature control signal based on the first measurement value, and wherein the second temperature controller is further configured to generate the second feedback temperature control signal based on the second measurement value.

4. The wafer processing apparatus according to claim 1, wherein, The wafer clamping controller is further configured to: determine whether the wafer is warped based on the first feedback temperature control signal and the second feedback temperature control signal immediately after loading the wafer.

5. The wafer processing apparatus according to claim 1, wherein, The wafer clamping controller is further configured to: identify a difference between a first power output of the first power supply and a second power output of the second power supply immediately after loading the wafer.

6. The wafer processing apparatus according to claim 5, wherein, The wafer clamping controller is further configured to: identify a ratio of the difference to a reference value immediately after loading the wafer.

7. The wafer processing apparatus according to claim 6, wherein, The reference value corresponds to a difference between a first power output of the first power supply and a second power output of the second power supply immediately after loading a flat wafer.

8. The wafer processing apparatus according to claim 1, wherein, The wafer clamping controller is further configured to: identify a warpage degree of the wafer based on the first feedback temperature control signal and the second feedback temperature control signal immediately after loading the wafer.

9. The wafer processing apparatus according to claim 8, wherein, The wafer clamping controller is further configured to: generate the feedback pressure control signal based on the warpage degree of the wafer.

10. The wafer processing apparatus according to claim 1, wherein, The first power supply is configured to supply first power to a central portion of the heating device corresponding to the central region, and wherein the second power supply is configured to supply second power to an edge portion of the heating device corresponding to the edge region.

11. A wafer processing apparatus, comprising: a heating plate, through which a plurality of vacuum ports are formed and which defines a central region, an edge region surrounding the central region, and an intermediate region between the central region and the edge region; a plurality of temperature sensors configured to measure the temperature of the heating plate; a heating device configured to heat the heating plate; a first power supply, a second power supply, and a third power supply configured to supply operating power to different positions of the heating device respectively to maintain the heating plate at a preset temperature; a first temperature controller configured to generate a first feedback temperature control signal for controlling the first power output of the first power supply based on a first measurement value of the plurality of temperature sensors; a second temperature controller configured to generate a second feedback temperature control signal for controlling the second power output of the second power supply based on a second measurement value of the plurality of temperature sensors; a third temperature controller configured to generate a third feedback temperature control signal for controlling the third power output of the third power supply based on a third measurement value of the plurality of temperature sensors; an electronic pressure regulator configured to regulate the pressure of the plurality of vacuum ports; and a wafer clamping controller configured to control the electronic pressure regulator, wherein the plurality of vacuum ports includes: a plurality of first vacuum ports arranged in a circular symmetry with respect to the center of the heating plate; and a plurality of second vacuum ports arranged in a circular symmetry with respect to the center of the heating plate and being farther from the central region of the heating plate than the plurality of first vacuum ports, wherein the electronic pressure regulator includes: a first electronic pressure regulator configured to regulate the pressure of the plurality of first vacuum ports; and a second electronic pressure regulator configured to regulate the pressure of the plurality of second vacuum ports, and wherein the wafer clamping controller is further configured to: generate a first feedback pressure control signal and a second feedback pressure control signal based on the first feedback temperature control signal, the second feedback temperature control signal, and the third feedback temperature control signal, the first feedback pressure control signal and the second feedback pressure control signal being configured to control the pressures of the first electronic pressure regulator and the second electronic pressure regulator respectively.

12. The wafer processing apparatus according to claim 11, wherein, The plurality of temperature sensors includes: a first temperature sensor corresponding to the central region, a second temperature sensor corresponding to the edge region, and a third temperature sensor corresponding to the intermediate region, wherein the first temperature sensor is configured to generate the first measurement value, the second temperature sensor is configured to generate the second measurement value, and the third temperature sensor is configured to generate the third measurement value, Wherein, the first temperature controller is further configured to generate the first feedback temperature control signal based on the first measurement value. Wherein, the second temperature controller is further configured to generate the second feedback temperature control signal based on the second measurement value, and Wherein, the third temperature controller is further configured to generate the third feedback temperature control signal based on the third measurement value.

13. The wafer processing apparatus according to claim 12, wherein, The first power supply is configured to provide operating power to a central portion of the heating device corresponding to the central region based on the first feedback temperature control signal. Wherein, the second power supply is configured to provide operating power to an edge portion of the heating device corresponding to the edge region based on the second feedback temperature control signal, and Wherein, the third power supply is configured to provide operating power to an intermediate portion of the heating device corresponding to the intermediate region based on the third feedback temperature control signal.

14. The wafer processing apparatus according to claim 11, wherein, The wafer clamping controller is further configured to: identify a vertical distance from a temperature detection position of a wafer disposed on the heating plate to the heating plate based on the first feedback temperature control signal, the second feedback temperature control signal, and the third feedback temperature control signal.

15. The wafer processing apparatus according to claim 11, wherein, The wafer clamping controller is further configured to: identify a three-dimensional shape of the wafer based on the first feedback temperature control signal, the second feedback temperature control signal, and the third feedback temperature control signal.

16. The wafer processing apparatus according to claim 15, wherein, The wafer clamping controller is further configured to: generate the first feedback pressure control signal and the second feedback pressure control signal corresponding to the first electronic pressure regulator and the second electronic pressure regulator respectively based on the three-dimensional shape.

17. A wafer processing apparatus, comprising: A heating plate, wherein a plurality of vacuum ports are formed through the heating plate and a central region and an edge region surrounding the central region are defined. A plurality of temperature sensors configured to measure the temperature of the heating plate. A heating device configured to heat the heating plate. A first power supply and a second power supply configured to provide operating power to different positions of the heating device respectively to maintain the heating plate at a preset temperature. A first measuring device and a second measuring device configured to measure a first power output of the first power supply and a second power output of the second power supply respectively. A first temperature controller and a second temperature controller configured to: generate a first feedback temperature control signal and a second feedback temperature control signal based on measurement values of the plurality of temperature sensors, the first feedback temperature control signal and the second feedback temperature control signal being configured to control the first power output and the second power output. An electronic pressure regulator configured to regulate the pressure of the plurality of vacuum ports. And A wafer clamping controller configured to control the pressure of the electronic pressure regulator and generate a feedback pressure control signal for controlling the pressure of the electronic pressure regulator based on the first power output and the second power output.

18. The wafer processing apparatus according to claim 17, wherein, The wafer clamping controller is further configured to: identify the warpage of the wafer based on the first power output measured by the first measuring device and the second power output measured by the second measuring device, and control the electronic pressure regulator according to the warpage.

19. The wafer processing apparatus according to claim 18, wherein, The wafer clamping controller is further configured to: generate the feedback pressure control signal based on the warpage of the wafer.

20. The wafer processing apparatus according to claim 18, wherein, The first power supply is further configured to supply operating power to the central portion of the heating device corresponding to the central region based on the first feedback temperature control signal, and wherein the second power supply is further configured to supply operating power to the edge portion of the heating device corresponding to the edge region based on the second feedback temperature control signal.

21. A wafer processing method, comprising: heating a heating plate via a heating device, wherein a plurality of vacuum ports are formed through the heating plate and a vacuum pressure is applied to the plurality of vacuum ports; loading a wafer onto the heating plate; corresponding to the temperature change of the heating plate caused by loading the wafer onto the heating plate, controlling the power output at different positions of the heating device to heat the heating plate to a preset temperature and maintaining the heating plate at the preset temperature; identifying the warpage of the wafer based on the power output of the heating device; and adjusting the vacuum pressure in the plurality of vacuum ports based on the warpage of the wafer.

22. The wafer processing method according to claim 21, wherein, Identifying the warpage of the wafer includes: comparing the power output of the heating device corresponding to the central region of the heating plate with the power output of the heating device corresponding to the edge region of the heating plate.

23. The wafer processing method according to claim 21, wherein, Identifying the warpage of the wafer includes: identifying the difference between the maximum value of the power output of the heating device corresponding to the central region of the heating plate and the maximum value of the power output of the heating device corresponding to the edge region of the heating plate.

24. The wafer processing method according to claim 21, wherein, Identifying the warpage of the wafer includes: identifying the difference between the maximum value of the power output of the heating device corresponding to the central region of the heating plate and the minimum value of the power output of the heating device corresponding to the edge region of the heating plate.

25. The wafer processing method according to claim 21, wherein, Identifying the warpage of the wafer includes: identifying the difference between the minimum value of the power output of the heating device corresponding to the central region of the heating plate and the maximum value of the power output of the heating device corresponding to the edge region of the heating plate.

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