Integrated circuit structure and method of manufacturing the same

Abstract

The present disclosure relates to integrated circuit structures and methods of manufacturing the same. One method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process such that a bottom of the metal layer reacts with a semiconductor region underneath the metal layer to form a source / drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metal material on the silicon-and-nitrogen-containing layer.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit structures and methods of manufacturing the same. Background Art

[0002] In the manufacture of integrated circuits, contact plugs are used to connect to the source and drain regions and gates of transistors. Source / drain contact plugs are typically connected to source / drain silicide regions and are formed by forming contact openings to expose the source / drain regions, depositing a metal layer, depositing a barrier layer over the metal layer, performing an anneal to react the metal layer with the source / drain regions, filling the remaining contact openings with metal (e.g., tungsten or cobalt), and performing a chemical mechanical polishing (CMP) process to remove excess metal. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a method for manufacturing an integrated circuit structure is provided, comprising: etching a dielectric layer of a substrate to form an opening in the dielectric layer; forming a metal layer extending into the opening; performing an annealing process so that a bottom portion of the metal layer reacts with a semiconductor region below the metal layer to form a source / drain region; performing a plasma treatment process on the substrate using a process gas containing hydrogen and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer; and depositing a metal material on the silicon-and-nitrogen-containing layer.

[0004] According to another embodiment of the present disclosure, a method for manufacturing an integrated circuit structure is provided, comprising: performing a thermal soaking process using a silicon-containing gas to deposit a silicon layer on a surface of a lower layer; performing a plasma treatment process on the silicon layer to form a layer containing silicon and nitrogen; and depositing a metal layer on the silicon-and-nitrogen-containing layer, wherein the plasma treatment process and the depositing of the metal layer are performed in situ in the same process chamber without vacuum breaking in between.

[0005] According to another embodiment of the present disclosure, an integrated circuit structure is provided, comprising: a dielectric layer; a metal ring in contact with a sidewall of the dielectric layer; a metal region surrounded by the metal ring; and a silicon-and-nitrogen-rich layer located between the metal ring and the metal region, wherein a silicon atomic percentage in the silicon-and-nitrogen-rich layer is higher than both a silicon atomic percentage in the metal ring and the metal region, and a first nitrogen atomic percentage in the silicon-and-nitrogen-rich layer is higher than a second nitrogen atomic percentage in the metal ring and the metal region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1-8 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10-18 and Figure 24 are perspective and cross-sectional views of intermediate stages in the formation of a transistor and corresponding contact plugs according to some embodiments.

[0008] Figures 19 to 23 is a cross-sectional view of an intermediate stage in the formation of a transistor and corresponding contact plug according to some embodiments.

[0009] Figure 25 A process flow for forming a transistor according to some embodiments is shown. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different components of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, represent a relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, to simplify the description, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to describe the relationship of one element or component relative to another element or component(s) shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0012] According to various embodiments, a fin field effect transistor (FinFET) and a method for forming the same are provided. According to some embodiments, intermediate stages in the formation of a FinFET are shown. Some variations of some embodiments are discussed. In the various views and exemplary embodiments, the same reference numerals are used to represent the same elements. According to some embodiments of the present disclosure, a FinFET and a corresponding contact plug are formed. The formation of the contact plug includes etching (one or more) dielectric layers to form an opening, and performing a thermal soaking process using a silicon-containing process gas to add silicon to the exposed surface of the (one or more) dielectric layers. If the exposed surface of the (one or more) dielectric layers already contains sufficient silicon, the soaking process can be skipped. A plasma treatment is then performed on the surface using hydrogen (H2) and nitrogen (N2) as process gases, so that the nitrogen atoms are connected to the silicon atoms. A deposition process is then performed to deposit metal into the opening, thereby forming an ultra-thin covalent Si-N-metal bond. No barrier layer (e.g., a TiN barrier layer) is formed in the resulting contact plug. Therefore, the width of the resulting contact plug is increased. By forming an ultra-thin Si-N-metal bond and thus eliminating the barrier layer, the resistivity of the contact plug is reduced.

[0013] The embodiments will be described with respect to a specific context, namely the formation of contact plugs. The concepts of the embodiments discussed may also be applied to the processing of structures and other structures, including but not limited to the formation of metal lines, metal vias, etc. The embodiments discussed herein provide examples of how the subject matter of the present disclosure can be made or used, and those skilled in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. Like reference numerals and characters in the following figures represent like components. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figure 1-8 、 Figure 9A 、 Figure 9B 、 Figure 10-18 and Figure 24 The perspective view and cross-sectional view of the intermediate stages in the formation of FinFET according to some embodiments of the present disclosure are shown. The corresponding process is also exemplarily reflected in Figure 25 In the process flow shown in .

[0015] Figure 1 A perspective view of an initial structure formed on a wafer 10 is shown. The wafer 10 includes a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with p-type or n-type impurities. An isolation region 22 (e.g., a shallow trench isolation (STI) region) may be formed to extend from the top surface of the substrate 20 into the substrate 20. The corresponding process is shown as follows. Figure 25. The portion of substrate 20 located between adjacent STI regions 22 is referred to as semiconductor strip 24. According to some embodiments, the top surface of semiconductor strip 24 and the top surface of STI region 22 may be substantially flush with each other. According to some embodiments of the present disclosure, semiconductor strip 24 is a portion of original substrate 20, and thus the material of semiconductor strip 24 is the same as the material of substrate 20. According to an optional embodiment of the present disclosure, semiconductor strip 24 is a replacement strip formed by etching the portion of substrate 20 located between STI regions 22 to form a groove, and performing epitaxy to re-grow another semiconductor material in the groove. Thus, semiconductor strip 24 is formed of a semiconductor material different from the semiconductor material of substrate 20. According to some embodiments, semiconductor strip 24 is formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0016] STI regions 22 may include a pad oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. For example, the pad oxide may also be a deposited silicon oxide layer formed using atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. STI regions 22 may also include a dielectric material over the pad oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc.

[0017] refer to Figure 2 , the STI region 22 is recessed so that the top of the semiconductor strip 24 protrudes above the top surface 22A of the remaining portion of the STI region 22 to form a protruding fin 24'. The corresponding process is shown as Figure 25 204 in the process flow 200 shown in FIG. Etching can be performed using a dry etching process, wherein HF3 and NH3 are used as etching gases. During the etching process, plasma can be generated. Argon can also be included. According to an alternative embodiment of the present disclosure, recessing of the STI region 22 is performed using a wet etching process. For example, the etching chemical can include HF.

[0018] In the embodiments shown above, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a smaller spacing than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0019] refer to Figure 3 , the dummy gate stack 30 is formed to extend on the top surface and sidewalls of the (protruding) fin 24 ′. The corresponding process is shown as Figure 25 . The dummy gate stacks 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 located above the corresponding dummy gate dielectric 32. For example, polysilicon may be used and other materials may also be used to form the dummy gate electrode 34. Each dummy gate stack 30 may also include one (or more) hard mask layers 36 located above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon oxynitride, or multiple layers of the foregoing. The dummy gate stack 30 may span a single or multiple of the protruding fins 24' and / or STI regions 22. The dummy gate stack 30 also has a length direction that is perpendicular to the length direction of the protruding fins 24'.

[0020] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacers 38 are formed of one or more dielectric materials (e.g., silicon nitride, silicon carbonitride, etc.) and can have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0021] An etching step is then performed to etch the portions of the protruding fins 24' not covered by the dummy gate stack 30 and the gate spacers 38, resulting in Figure 4 The corresponding process is shown as Figure 25 200 . The recess can be anisotropic, and thus the portion of fin 24 ′ directly below dummy gate stack 30 and gate spacer 38 is protected and not etched. According to some embodiments, the top surface of recessed semiconductor strip 24 can be lower than top surface 22A of STI region 22. The space left by the etched protruding fin 24 ′ and semiconductor strip 24 is referred to as recess 40. Recess 40 is located on opposite sides of dummy gate stack 30.

[0022] Next, if Figure 5 As shown, epitaxial regions (source / drain regions) 42 are formed by selectively growing (by epitaxy) semiconductor material in the recesses 40. The corresponding process is shown as Figure 25Process 210 in the process flow 200 shown. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 42 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination of the foregoing items, or multiple layers of the foregoing items. After the groove 40 is filled with the epitaxial region 42, further epitaxial growth of the epitaxial region 42 causes the epitaxial region 42 to expand horizontally, and a small facet can be formed. Further growth of the epitaxial region 42 can also cause adjacent epitaxial regions 42 to merge with each other. According to some embodiments of the present disclosure, when the top surface of the epitaxial region 42 is still wavy, or when the top surface of the merged epitaxial region 42 becomes flat (e.g., Figure 6 As shown, which is achieved by further growth on the epitaxial region 42), the formation of the epitaxial region 42 can be completed.

[0023] According to alternative embodiments, instead of etching the protruding fins 24' and then epitaxially growing the source / drain regions, cladding source / drain regions are formed. According to these embodiments, as Figure 3 The protruding fin 24' is not recessed, and an epitaxial region is grown on the protruding fin 24' to form the source / drain region. The material of the epitaxial region can be similar to the material of the epitaxial semiconductor material 42, such as Figure 5 As shown, this depends on whether the resulting FinFET is p-type or n-type. Thus, the resulting source / drain region 42 includes the protruding fin 24' and the epitaxial regions grown on the sidewalls and top surface of the protruding fin 24'. Implantation may (or may not) be performed to implant n-type impurities or p-type impurities. Adjacent cladding source / drain regions may also merge with each other, or remain separate from each other.

[0024] After the epitaxy step, the epitaxy region 42 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also denoted by reference numeral 42. According to an alternative embodiment of the present disclosure, when the epitaxy region 42 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation step is skipped.

[0025] Figure 7 4 shows a perspective view of the structure after forming a contact etch stop layer (CESL) 46 and an interlayer dielectric (ILD) 48. The corresponding process is shown as Figure 25 212 in the process flow 200 shown in FIG. CESL 46 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. ILD 48 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. ILD 48 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based dielectric material, such as silicon oxide (formed, for example, using tetraethylorthosilicate (TEOS) as a process gas), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. A planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) may be performed to make the top surfaces of ILD 48, dummy gate stack 30, and gate spacers 38 flush with each other.

[0026] Next, the dummy gate stack 30 including the hard mask layer 36, the dummy gate electrode 34 and the dummy gate dielectric 32 is replaced with a replacement gate stack 56 including the metal gate electrode 54 and the gate dielectric 52, as shown in FIG. Figure 8 The corresponding process is shown as Figure 25 When forming the replacement gate stack 56, the first step is to remove the gate electrodes 56 in one or more etching processes. Figure 7 The hard mask layer 36, dummy gate electrode 34, and dummy gate dielectric 32 are shown such that trenches / openings are formed between the gate spacers 38. The top surfaces and sidewalls of the protruding semiconductor fins 24' are exposed in the resulting trenches.

[0027] Next, a (replacement) gate dielectric layer 52 is formed, which extends into the trenches between the gate spacers 38. According to some embodiments of the present disclosure, each gate dielectric layer 52 includes an interfacial layer (IL) as its lower portion, which contacts the exposed surface of the corresponding protruding fin 24'. The IL may include an oxide layer (e.g., a silicon oxide layer) formed by thermal oxidation, chemical oxidation process, or deposition process of the protruding fin 24'. The gate dielectric layer 52 may also include a high-k dielectric layer formed above the IL. The high-k dielectric layer may include a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9 and may be higher than about 7.0. The high-k dielectric layer is formed as a conformal layer and extends on the sidewalls of the protruding fin 24' and the sidewalls of the gate spacers 38. According to some embodiments of the present disclosure, ALD or CVD is used to form the high-k dielectric layer.

[0028] Further references Figure 8, a gate electrode 54 is formed over the gate dielectric 52, the gate electrode 54 including a conductive sublayer. The sublayers are not shown individually and are distinct from each other. The deposition of the sublayers can be performed using (one or more) conformal deposition methods (e.g., ALD or CVD).

[0029] The stacked conductive layers may include a diffusion barrier layer and one (or more) work function layers located above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (or may not) be doped with silicon. The work function layer determines the work function of the gate and includes at least one layer or multiple layers formed of different materials. The material of the work function layer is selected according to whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer may include a TaN layer and a titanium aluminum (TiAl) layer located above the TaN layer. When the FinFET is a p-type FinFET, the work function layer may include a TaN layer, a TiN layer located above the TaN layer, and a TiAl layer located above the TiN layer. After depositing the (one or more) work function layers, a barrier layer is formed, which may be another TiN layer.

[0030] The deposited gate dielectric layer and conductive layer are formed as conformal layers that extend into the trenches and include portions above ILD 48. Next, a metal material is deposited to fill the remaining trenches between gate spacers 38. For example, the metal material can be formed of tungsten or cobalt. Subsequently, a planarization process (e.g., a CMP process or a mechanical grinding process) is performed to remove the gate dielectric layer, the conductive sublayer, and the portion of the metal material located above ILD 48. Thus, a metal gate electrode 54 and a gate dielectric 52 are formed. The combination of gate electrode 54 and gate dielectric 52 is referred to as a replacement gate stack 56. The top surfaces of replacement gate stack 56, gate spacers 38, CESL 46, and ILD 48 can now be substantially coplanar.

[0031] Figure 8 Also shown is the formation of a (self-aligned) hard mask 58 according to some embodiments. The corresponding process is shown as Figure 25 The hard mask 58 may be formed by performing an etching process to recess the gate stack 56 so as to form a groove between the gate spacers 38, filling the groove with a dielectric material, and then performing a planarization process (e.g., a CMP process or a mechanical grinding process) to remove excess portions of the dielectric material. The hard mask 58 may be formed of silicon nitride, silicon oxynitride, silicon oxycarbon nitride, or the like.

[0032] Figure 9A The formation of source / drain contact openings 60 is shown. The corresponding process is shown as Figure 25The formation of contact opening 60 includes etching ILD 48 to expose the underlying portion of CESL 46, and then etching the exposed portion of CESL 46 to reveal epitaxial region 42. According to some embodiments of the present disclosure, as shown in FIG. Figure 9A As shown, gate spacers 38 are spaced apart from the nearest contact opening 60 by some remaining portion of ILD 48. According to other embodiments, sidewalls of contact opening 60 are exposed at contact opening 60.

[0033] Figure 9B Shows the display Figure 9A Cross-sectional view of reference cross section 9B-9B in. Figure 9C Shows the display Figure 9A A cross-sectional view of the reference cross section 9C-9C in FIG. Figure 9C , the levels of the top surface 22A and the bottom surface 22B of the STI region 22 are shown, and the semiconductor fin 24' is located above the top surface 22A. Figures 10 to 18 The subsequent process is shown, and Figures 10 to 18 The cross section shown in Figure 9A The reference cross section 9C-9C in is the same.

[0034] refer to Figure 10 For example, a metal layer 62 (eg, a titanium layer or a cobalt layer) is deposited using physical vapor deposition (PVD) or a similar method. The corresponding process is shown as Figure 25 The process 220 in the process flow 200 is shown in FIG. The metal layer 62 is a conformal layer and extends onto the top surface of the source / drain regions 42 and the sidewalls of the ILD 48 and CESL 46, which are exposed to the opening. An annealing process is then performed to form the source / drain silicide regions 64, as shown in FIG. Figure 11 The corresponding process is shown as Figure 25 222 in the process flow 200 shown in FIG. The annealing process may include a rapid thermal annealing (RTA) annealing process, a furnace annealing process, or the like. As a result, the bottom portion of metal layer 62 reacts with source / drain regions 42 to form silicide regions 64. Sidewall portions of metal layer 62 remain after the silicidation process. According to some embodiments, the bottom portion of metal layer 62 is fully silicided, and the resulting silicide regions 64 are exposed to opening 60. According to some embodiments, portions of metal layer 62 may remain overlapping and contacting silicide regions 64.

[0035] Figure 12 A heat soak process 66 is shown, which is performed using a silicon-containing process gas (e.g., silane (SiH4), disilane (Si2H6), dichlorosilane (DCS, H2SiCl2), etc.). The corresponding process is shown as Figure 25Process 224 in process flow 200 is shown. A carrier gas, such as argon, may be added. The hot soak process may be performed without a plasma. According to some embodiments of the present disclosure, the pressure of the hot soak process is in a range between about 10 Torr and about 100 Torr. The temperature of wafer 10 may be greater than about 200°C and may be in a range between about 250°C and about 350°C. The hot soak duration may be in a range between about 30 seconds and about 120 seconds.

[0036] The elevated temperature in the thermal soak causes decomposition of the silicon-containing process gas, which causes a single silicon layer 68 (or several single silicon layers, such as 2, 3, 4, or 5 single silicon layers) to adhere to the exposed surface of the wafer 10. The thickness T1 of the silicon layer 68 may be less than about 1 nm. Figure 12 As shown, a silicon layer 68 may be formed on top surfaces of the source / drain silicide regions 64 and the metal layer 62 .

[0037] Figure 13 A plasma treatment process 70 is shown. The corresponding process is shown as Figure 25 226 in the process flow 200 shown in . According to some embodiments, the plasma treatment process 70 is performed using a process gas including hydrogen (H2) and a nitrogen-containing gas. The nitrogen-containing gas may include N2. Other types of nitrogen-containing gases, such as ammonia (NH3), may also be used. The treatment is performed with the plasma turned on. In addition, direct plasma may be used, wherein the plasma is generated in the same process chamber in which the wafer 10 is placed for the plasma treatment process. According to some embodiments of the present disclosure, the flow rate of hydrogen is in a range between about 10 sccm and about 50 sccm, and the flow rate of the nitrogen-containing gas is in a range between about 10 sccm and about 50 sccm. The treatment duration may be in a range between about 100 seconds and about 150 seconds. The temperature of the wafer 10 during the plasma treatment may be room temperature (e.g., about 21°C), or may be elevated and in a range between about 400°C and about 450°C.

[0038] During the plasma treatment process, hydrogen has the function of performing a reduction reaction on silicon atoms, thereby generating dangling bonds of silicon atoms for the silicon layer 68. Therefore, the nitrogen atoms in the nitrogen-containing gas are more likely to bond with the dangling bonds of silicon atoms. Thus, Si-N bonds are generated. This results in the generation of a SiN layer 72, which may be a single layer of Si-N or may include several layers (e.g., 2, 3, 4, or 5) of SiN. Si-N has good adhesion to the underlying metal layer 62 and is also good for the subsequently formed metal region 73 ( Figure 14 ) also has good adhesion. The thickness T2 of the SiN layer 72 can be less than about 1 nm. The SiN layer 72 is also a conformal layer, for example, the thickness variation between its horizontal and vertical portions is less than about 20%.

[0039] Figure 14 The formation of the metal material 73 is shown, and the metal material 73 includes a metal seed layer and an overlying metal region. The corresponding process is shown as Figure 25 . According to some embodiments, the metal seed layer is a cobalt layer or includes cobalt. According to other embodiments, tungsten, copper, molybdenum, etc. may be used. The formation method may include physical vapor deposition (PVD), ALD, or a PVD process followed by an ALD process. According to some embodiments, electrochemical plating (ECP) is performed to plate a metal region on the metal seed layer and fill the remaining contact opening 60. The material of the metal region may be the same as or different from the material of the metal seed layer and may be selected from cobalt, tungsten, copper, molybdenum, etc., a composite layer of the foregoing items, or an alloy of the foregoing items.

[0040] The metal seed layer forms covalent bonds with the previously formed Si-N bonds, thereby generating Si-N-metal bonds that are conductive due to the small thickness of the Si-N bonds / layer. For example, when the metal seed layer contains cobalt or is formed of cobalt, Si-N-Co bonds (in the form of a thin layer) can be formed. Si-N-Co has good adhesion to the underlying metal layer 62, and therefore the bonding of contact plug 74 to metal layer 62 is excellent.

[0041] According to some embodiments, in order to efficiently form Si-N bonds, and then bond metal to the Si-N bonds, Figure 13 and Figure 14 The process shown in (including plasma treatment process ( Figure 13 ) and the formation of a metal seed layer ( Figure 14 )) are performed in situ in the same process chamber without vacuum breaking in between. The plasma treatment and metal seed layer formation performed in situ ensure that the Si-N bonds are not connected to other elements (e.g., oxygen) (e.g., to form Si-NO bonds), thereby making the dangling Si-N bonds available for metal atoms to be bonded thereto. According to some embodiments, the hot soak process ( Figure 12 ) is also related to plasma treatment process ( Figure 13 ) and the formation of a metal seed layer ( Figure 14 ) is performed in situ to form a clean silicon layer.

[0042] In a subsequent process, a planarization process (eg, a CMP process or a mechanical grinding process) is performed to remove excess portions of the metal layer 62 and the metal material 73, leaving the contact plug 74. Figure 15 The corresponding process is shown as Figure 25 Process 230 in the process flow 200 shown in FIG. Figure 15 A perspective view of the lower portion of the structure shown in FIG. Figure 24 In addition to Figure 24 Other than the etch stop layer 76 and the ILD 78 , not shown.

[0043] Further references Figure 15 According to some embodiments of the present disclosure, an etch stop layer 76 is formed. The etch stop layer 76 may be formed of a silicon-containing material (e.g., SiN, SiCN, SiC, SiOCN, etc.). The formation method may include PECVD, ALD, CVD, etc. Next, an ILD 78 is formed over the etch stop layer 76. The formation of the etch stop layer 76 and the ILD 78 is shown as Figure 25 Process 232 in process flow 200 is shown. The material of ILD 78 can be selected from the same candidate materials (and methods) used to form ILD 48. For example, ILD 78 can include silicon oxide, PSG, BSG, BPSG, etc., including silicon. According to some embodiments, ILD 78 is formed using PECVD, FCVD, spin-on coating, etc.

[0044] Figure 16 The etching of ILD 78 and etch stop layer 76 to form upper source / drain contact openings 80A is shown. The corresponding process is shown as Figure 25 200. Furthermore, ILD 78, etch stop layer 76, and hard mask 58 may be etched to form contact gate openings 80B. Source / drain contact openings 80A and gate openings 80B are collectively referred to as contact openings 80. Thus, gate electrode 54 and source / drain contact plug 74 are exposed in source / drain contact openings 80A and gate openings 80B, respectively.

[0045] Next, do something like Figure 13 Another plasma treatment process 70' of the plasma treatment process shown in FIG is to form a SiN layer 72'. The corresponding process is shown as Figure 25 236 in the process flow 200 shown in . According to some embodiments of the present disclosure, the plasma treatment process 70' is performed using a process gas including hydrogen (H2) and a nitrogen-containing gas. The nitrogen-containing gas may include N2, ammonia (NH3), etc. The treatment is performed with the plasma turned on. In addition, direct plasma may be used, wherein the plasma is generated in the same process chamber in which the wafer 10 is placed for the plasma treatment process. According to some embodiments of the present disclosure, the flow rate of hydrogen is in a range between about 10 sccm and about 50 sccm, and the flow rate of the nitrogen-containing gas is in a range between about 10 sccm and about 50 sccm. The treatment duration may be in a range between about 100 seconds and about 150 seconds. The temperature of the wafer 10 during the plasma treatment may be room temperature (e.g., about 21°C), or may be elevated and in a range between about 400°C and about 450°C.

[0046] According to some embodiments, a thermal soak process using silicon-containing process(es) is not performed between forming opening 80 and plasma treatment process 70'. Since ILD 78, etch stop layer 76, and hard mask 58 may be formed of a silicon-containing material, the silicon atoms in ILD 78, etch stop layer 76, and hard mask 58 are reduced by hydrogen (in a reduction reaction) to form dangling bonds for the silicon atoms, and the dangling bonds are then connected to nitrogen atoms. Thus, Si-N bonds are formed. In these embodiments, the silicon atoms in the Si-N bonds are part of ILD 78, etch stop layer 76, and hard mask 58. On the other hand, since the exposed surfaces of contact plug 74 and gate electrode 54 (e.g., including cobalt) may not include silicon, SiN layer 72' may not extend above the top surfaces of contact plug 74 and gate electrode 54.

[0047] According to an alternative embodiment in which the ILD 78, the etch stop layer 76 and / or the hard mask 58 do not contain silicon, or contain silicon but with a negligible atomic percentage of silicon, a thermal soak process is performed prior to the plasma treatment process 70'. The corresponding process is shown as Figure 25 The process 235 in the process flow 200 shown in FIG. The process 235 is shown using a dashed box to indicate that the process can be performed or can be skipped. The process conditions can be similar to Figure 12 The process conditions of the hot soaking process 66 in FIG. 6 are similar to those of FIG. 66 and are therefore not repeated here. Figure 16 , except that a similar dielectric layer is formed between the SiN layer 72′ and the dielectric layer including the ILD 78, the etch stop layer 76, and the hard mask 58. Figure 12 6 and 58). Due to diffusion, the silicon layer will be in the form of a compound of silicon and adjacent layers (e.g., ILD 78, etch stop layer 76, and hard mask 58). Portions of the silicon layer may be observed when the silicon atomic percentage of the compound of the corresponding portion is higher than any of ILD 78, etch stop layer 76, and / or hard mask 58. If the silicon atomic percentage in SiN layer 72' and ILD 78, etch stop layer 76, and hard mask 58 is higher, the silicon layer may not be observed. According to some embodiments of the present disclosure, after the plasma treatment, the deposited silicon layer is converted to SiN layer 72'. According to these embodiments, SiN layer 72' may extend over the top surface of contact plug 74 and gate electrode 54.

[0048] Figure 17 The deposition of a metal material 82 is shown, which can be deposited using PVD, CVD, plating, a combination of the foregoing, etc., which forms a Si-N-metal bond with the SiN layer 72'. The corresponding process is shown as Figure 25The metal material 82 may include cobalt, tungsten, molybdenum, copper, or alloys thereof. According to some embodiments of the present disclosure, at least the bottom portion (e.g., seed layer) of the metal material 82 is treated with a plasma treatment process 70' ( Figure 16 ) is formed in situ to ensure the effective formation of Si-N-metal bonds. In the subsequent process, a planarization process (eg, a CMP process or a mechanical grinding process) is performed to remove the metal material 82 and the excess portion of the SiN layer 72', thereby forming an upper contact plug 84. The resulting structure is Figure 18 Shown in.

[0049] like Figure 18 As shown, metal layer 62 forms a ring (in plan view) surrounding metal region 73. Metal layer 62 and metal region 73 can be formed of the same metal or different metals. Si- and N-containing layer 72 is located between metal region 73 and metal layer 62. When metal region 73 and metal layer 62 are formed, both metal region 73 and metal layer 62 can be free of silicon. Therefore, in the final structure, Si- and N-containing layer 72 is observed as a silicon- and nitrogen-rich layer, wherein both silicon and nitrogen have higher atomic percentages than in metal layer 62 and metal region 73, regardless of whether silicon and nitrogen diffuse into metal layer 62 and metal region 73 during subsequent processing. In addition, due to the presence of the bottom of layer 72 directly above and in contact with silicide region 64, the atomic percentage of nitrogen in layer 72 can be higher than the atomic percentage of nitrogen in the overlying metal region 73 and the underlying silicide region 64. In the embodiment shown, contact plug 74 does not include a deposited barrier layer (e.g., a TiN layer).

[0050] In such Figure 1-8 、 Figure 9A 、 Figure 9B and Figure 10-18 In the embodiment shown, the metal layer 62 remains unremoved after the annealing process used to form the silicide regions 64. Since the remaining metal layer 62 prevents the silicon atoms in the ILD 48 and CESL 46 (if present) from being exposed to the plasma treatment process, the thermal soak process ( Figure 12 ) to form a silicon layer 68. Figures 19 to 23 A cross-sectional view of an intermediate stage in the formation of a FinFET and corresponding contact plug according to some embodiments of the present disclosure is shown, where the exposed layer contains silicon and the thermal soak process can therefore be skipped. Unless otherwise noted, the materials and formation processes of the components in these embodiments are the same as those in the Figure 1-8 、 Figure 9A 、 Figure 9B and Figure 10-18 The same components as those in the previous embodiments shown in FIG. 1 are substantially the same as those in the previous embodiments shown in FIG. Figures 19 to 23Details of the formation processes and materials of the components shown in can be found in the discussion of the previous embodiments.

[0051] The initial process is basically the same as Figure 1-8 、 Figure 9A 、 Figure 9B 、 Figure 10 and Figure 11 The process is the same as that shown in FIG, wherein an annealing process is performed to form the silicide region 64. Next, the unreacted portion of the metal layer 62 is removed in an etching process to obtain Figure 19 The structure shown. The silicide region 64 is not etched. The top surface and sidewalls of the ILD 48 (and possibly the sidewalls of the CESL 46) are therefore exposed.

[0052] Next, if Figure 20 As shown, a plasma treatment process 70 is performed to form a SiN layer 72 (a layer containing silicon and nitrogen) formed by attaching nitrogen atoms to the surface layers of the ILD 48 and possibly the CESL 46. According to some embodiments, the ILD 48 (and possibly the CESL 46) is formed of a silicon-containing compound and therefore contains silicon therein. Therefore, the plasma treatment process 70 is performed without a previous hot soak process using a silicon-containing process gas. Since the silicon atoms in the Si-N bonds are part of the ILD 48 and possibly the CESL 46, the bonding of the SiN layer 72 to the ILD 48 and the CESL 46 is strong. The process conditions of the plasma treatment process 70 may be similar to those of the reference process. Figure 13 The discussion is essentially the same and will not be repeated here.

[0053] According to other embodiments, a heat soak process (using a silicon-containing process gas) is also performed to add silicon atoms, followed by Figure 13 The plasma treatment process 70 in the heat soak process can be basically the same as Figure 12 When ILD 48 and CESL 46 do not contain silicon, or when the atomic percentage of silicon in ILD 48 and CESL 46 is low, a thermal soak process may be performed.

[0054] Figure 21 The formation of metal material 73 is shown. Metal material 73 includes a metal material and may include cobalt, tungsten, molybdenum, copper, etc. The metal atoms in metal material 73 bond with the Si-N bonds in SiN layer 72 to form covalent Si-N-metal bonds. Since at least some of the silicon atoms in the Si-N-metal bonds may be part of ILD 48 and CESL 46, the bonding of metal material 73 to ILD 48 and CESL 46 is strong. No barrier layer (e.g., a TiN layer) is formed before depositing metal material 73. Figure 22A planarization process for forming source / drain contact plugs 74 is shown.

[0055] Figure 23 The formation of the etch stop layer 76, the ILD 78, the SiN layer 72' and the contact plug 84 is shown. Figures 15 to 18 The process details and materials are discussed in the previous embodiments and are not repeated here.

[0056] Experimental results show that Si-N-metal (e.g., Si-N-cobalt) covalent bonds have good thermal stability. In a durability test performed at 400°C for 30 minutes, no separation or extrusion was observed in the contact plugs formed according to the embodiment. In addition, no Co-N separation or delamination was observed. The resulting contact plugs were free of a barrier layer (e.g., a barrier layer formed of TiN). Eliminating the barrier layer increased the lateral dimensions of the low-resistance portion of the contact plug by, for example, 2 nm or more. The overall resistance of the contact plug was reduced.

[0057] Embodiments of the present disclosure have several advantageous features. Through plasma treatment and possibly a heat soak process, no barrier layer is required. This allows for increased lateral dimensions and reduced resistance of the contact plug. Due to the excellent adhesion of the Si-N-metal bond to the dielectric layer and metal, the contact plug exhibits good adhesion to the ILD and CESL.

[0058] According to some embodiments of the present disclosure, a method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer; forming a metal layer extending into the opening; performing an annealing process so that a bottom portion of the metal layer reacts with a semiconductor region below the metal layer to form source / drain regions; performing a plasma treatment process on the substrate using a process gas comprising hydrogen and a nitrogen-containing gas to form a layer comprising silicon and nitrogen; and depositing a metal material on the silicon-nitrogen-containing layer. In one embodiment, the method further includes performing a thermal soak process on the substrate using a silicon-containing process gas prior to the plasma treatment process. In one embodiment, the thermal soak process is performed using silane as part of the process gas. In one embodiment, the dielectric layer comprises silicon, and wherein, when the plasma treatment process is performed, sidewalls of the dielectric layer are exposed to the opening and to the hydrogen and nitrogen-containing gas. In one embodiment, at least a portion of the deposition of the metal material and the plasma treatment process are performed in situ without a vacuum break. In one embodiment, the deposition of the metal material includes depositing a metal seed layer, and the deposition of the metal seed layer and the plasma treatment process are performed in situ without a vacuum break. In one embodiment, the nitrogen-containing gas comprises nitrogen (N2) gas. In one embodiment, the plasma treatment process forms a single layer of Si-N bonds.

[0059] According to some embodiments of the present disclosure, a method includes performing a hot soak process using a silicon-containing gas to deposit a silicon layer on the surface of a lower layer; performing a plasma treatment process on the silicon layer to form a layer containing silicon and nitrogen; and depositing a metal layer on the silicon and nitrogen-containing layer to form a Si-N-metal bond, wherein the plasma treatment process and the deposited metal layer are performed in situ in the same process chamber without a vacuum break in between. In one embodiment, the silicon layer is deposited as a single layer. In one embodiment, the Si-N-metal bond is formed as a single layer. In one embodiment, the hot soak process is performed using silane as part of the silicon-containing gas. In one embodiment, the plasma treatment process is performed using hydrogen (H2) and nitrogen (N2) as process gases. In one embodiment, no vacuum break occurs between the hot soak process and the deposited metal layer. In one embodiment, depositing the metal layer includes depositing a cobalt layer.

[0060] According to some embodiments of the present disclosure, an integrated circuit structure includes a dielectric layer; a metal ring in contact with a sidewall of the dielectric layer; a metal region surrounded by the metal ring; and a silicon-and-nitrogen-rich layer located between the metal ring and the metal region, wherein the silicon atomic percentage in the silicon-and-nitrogen-rich layer is higher than the silicon atomic percentage in both the metal ring and the metal region, and a first nitrogen atomic percentage in the silicon-and-nitrogen-rich layer is higher than a second nitrogen atomic percentage in both the metal ring and the metal region. In one embodiment, the integrated circuit structure includes a semiconductor region located below the dielectric layer; a metal silicide region located atop the semiconductor region, wherein the metal silicide region overlaps the metal region; and a nitrogen-rich layer overlapping and in contact with the metal silicide region, wherein a third nitrogen atomic percentage in the nitrogen-rich layer is higher than a fourth nitrogen atomic percentage in the metal silicide region and higher than the second nitrogen atomic percentage in the metal region. In one embodiment, the metal ring and the metal region are formed of different metals. In one embodiment, the metal ring comprises titanium, and the metal region comprises cobalt. In one embodiment, the dielectric layer comprises a silicon-based dielectric material.

[0061] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis to design or modify other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0062] Example 1. A method for manufacturing an integrated circuit structure, comprising: etching a dielectric layer of a substrate to form an opening in the dielectric layer; forming a metal layer extending into the opening; performing an annealing process so that the bottom of the metal layer reacts with a semiconductor region below the metal layer to form a source / drain region; performing a plasma treatment process on the substrate using a process gas containing hydrogen and a nitrogen-containing gas to form a silicon- and nitrogen-containing layer; and depositing a metal material on the silicon- and nitrogen-containing layer.

[0063] Example 2. The method according to Example 1 further includes: performing a thermal soaking process on the substrate using a silicon-containing process gas before the plasma treatment process.

[0064] Example 3. The method of Example 2, wherein the thermal soak process is performed using silane as part of the process gas.

[0065] Example 4. The method of Example 1, wherein the dielectric layer comprises silicon, and wherein, when performing the plasma treatment process, sidewalls of the dielectric layer are exposed to the opening and to the hydrogen gas and the nitrogen-containing gas.

[0066] Example 5. The method of Example 1, wherein at least a portion of depositing the metal material and the plasma treatment process are performed in situ without a vacuum break.

[0067] Example 6. The method of Example 5, wherein depositing the metal material comprises depositing a metal seed layer, and the depositing the metal seed layer and the plasma treatment process are performed in situ without a vacuum break in between.

[0068] Example 7. The method of Example 1, wherein the nitrogen-containing gas comprises nitrogen N2 gas.

[0069] Example 8. The method of Example 1, wherein the plasma treatment process forms a monolayer of Si-N bonds.

[0070] Example 9. A method for manufacturing an integrated circuit structure, comprising: performing a thermal soak process using a silicon-containing gas to deposit a silicon layer on the surface of a lower layer; performing a plasma treatment process on the silicon layer to form a layer containing silicon and nitrogen; and depositing a metal layer on the silicon and nitrogen-containing layer, wherein the plasma treatment process and the deposited metal layer are performed in situ in the same process chamber without vacuum breakdown in between.

[0071] Example 10. The method of Example 9, wherein the silicon layer is deposited as a single layer.

[0072] Example 11. The method of Example 9, wherein the metal layer forms a Si—N-metal bond with the silicon and nitrogen containing layer.

[0073] Example 12. The method of Example 9, wherein the thermal soak process is performed using silane as part of the silicon-containing gas.

[0074] Example 13. The method according to Example 9, wherein the plasma treatment process is performed using hydrogen H2 and nitrogen N2 as process gases.

[0075] Example 14. The method of Example 9, wherein no vacuum break occurs between the thermal soak process and the deposited metal layer.

[0076] Example 15. The method of Example 9, wherein depositing a metal layer comprises depositing a cobalt layer.

[0077] Example 16. An integrated circuit structure comprising: a dielectric layer; a metal ring in contact with a sidewall of the dielectric layer; a metal region surrounded by the metal ring; and a silicon-and-nitrogen-rich layer located between the metal ring and the metal region, wherein the silicon atomic percentage in the silicon-and-nitrogen-rich layer is higher than the silicon atomic percentage in both the metal ring and the metal region, and a first nitrogen atomic percentage in the silicon-and-nitrogen-rich layer is higher than a second nitrogen atomic percentage in the metal ring and the metal region.

[0078] Example 17. The integrated circuit structure according to Example 16 further includes: a semiconductor region, wherein the semiconductor region is located below the dielectric layer; a metal silicide region, wherein the metal silicide region is located on top of the semiconductor region, wherein the metal silicide region overlaps with the metal region; and a nitrogen-rich layer, wherein the nitrogen-rich layer overlaps with the metal silicide region and contacts the metal silicide region, wherein the third nitrogen atomic percentage in the nitrogen-rich layer is higher than the fourth nitrogen atomic percentage in the metal silicide region and higher than the second nitrogen atomic percentage in the metal region.

[0079] Example 18. The integrated circuit structure of Example 16, wherein the metal ring and the metal region are formed of different metals.

[0080] Example 19. The integrated circuit structure of Example 16, wherein the metal ring comprises titanium and the metal region comprises cobalt.

[0081] Example 20. The integrated circuit structure of Example 16, wherein the dielectric layer comprises a silicon-based dielectric material.

Claims

1. A method for manufacturing an integrated circuit structure, comprising: etching a dielectric layer of a substrate to form an opening in the dielectric layer; forming a metal layer extending into the opening; performing an annealing process so that the bottom of the metal layer reacts with the semiconductor region below the metal layer to form a source / drain silicide region; performing a plasma treatment process on the substrate using a process gas containing hydrogen and a nitrogen-containing gas to form a layer containing silicon and nitrogen; as well as depositing a metallic material on the silicon and nitrogen containing layer, Wherein, at least a portion of the deposition of the metal material and the plasma treatment process are performed in situ without vacuum breaking.

2. The method according to claim 1, further comprising: Prior to the plasma treatment process, a thermal soaking process is performed on the substrate using a silicon-containing process gas.

3. The method according to claim 2, wherein: The heat soak process is performed using silane as part of the process gas.

4. The method according to claim 1, wherein The dielectric layer includes silicon, and wherein, when the plasma treatment process is performed, a sidewall of the dielectric layer is exposed to the opening and to the hydrogen gas and the nitrogen-containing gas.

5. The method according to claim 1, wherein Depositing the metal material includes depositing a metal seed layer, and the depositing the metal seed layer and the plasma treatment process are performed in situ without vacuum breaking.

6. The method according to claim 1, wherein The nitrogen-containing gas includes nitrogen.

7. The method according to claim 1, wherein The plasma treatment process allows the formation of a single layer of Si-N bonds.

8. A method of manufacturing an integrated circuit structure, comprising: performing a thermal soak process using a silicon-containing gas to deposit a silicon layer on a surface of the underlying layer; performing a plasma treatment process on the silicon layer to form a layer containing silicon and nitrogen; as well as A metal layer is deposited on the silicon and nitrogen containing layer, wherein the plasma treatment process and the depositing of the metal layer are performed in situ in the same process chamber without a vacuum break in between.

9. The method according to claim 8, wherein The silicon layer is deposited as a single layer.

10. The method according to claim 8, wherein The metal layer forms a Si—N-metal bond with the silicon and nitrogen containing layer.

11. The method according to claim 8, wherein The thermal soak process is performed using silane as part of the silicon-containing gas.

12. The method according to claim 8, wherein The plasma treatment process is performed using hydrogen H 2 and nitrogen N 2 as process gases.

13. The method according to claim 8, wherein No vacuum break occurs between the heat soak process and the deposited metal layer.

14. The method according to claim 8, wherein The depositing of the metal layer includes depositing a cobalt layer.

15. An integrated circuit structure comprising: dielectric layer; a metal ring in contact with a sidewall of the dielectric layer; a metal region, the metal region being surrounded by the metal ring; a metal silicide region, the metal silicide region overlapping the metal region; as well as a silicon and nitrogen rich layer, the silicon and nitrogen rich layer being located between the metal ring and the metal region, wherein a silicon atomic percentage in the silicon and nitrogen rich layer is higher than a silicon atomic percentage in both the metal ring and the metal region, and a first nitrogen atomic percentage in the silicon and nitrogen rich layer is higher than a second nitrogen atomic percentage in the metal ring and the metal region, The metal region and the layer rich in silicon and nitrogen form a Si—N-metal bond.

16. The integrated circuit structure according to claim 15, further comprising: a semiconductor region, the semiconductor region being located below the dielectric layer; The metal silicide region is located on top of the semiconductor region; as well as A nitrogen-rich layer overlapping and contacting the metal silicide region, wherein a third nitrogen atomic percentage in the nitrogen-rich layer is higher than a fourth nitrogen atomic percentage in the metal silicide region and higher than the second nitrogen atomic percentage in the metal region.

17. The integrated circuit structure according to claim 15, wherein: The metal ring and the metal region are formed of different metals.

18. The integrated circuit structure according to claim 15, wherein: The metal ring comprises titanium, and the metal region comprises cobalt.

19. The integrated circuit structure according to claim 15, wherein: The dielectric layer includes a silicon-based dielectric material.

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