Semiconductor device

Abstract

A semiconductor device includes: a substrate including a first cell region, a second cell region adjacent to the first cell region in a first direction, and a comparison region adjacent to the first cell region and the second cell region in a second direction; bit lines on the substrate in a first metal layer and extending in the first direction; and a first ground rail in a second metal layer at a vertical layer different from the first metal layer. The first ground rail includes: a first sub-ground rail extending in the second direction over the first cell region; a second sub-ground rail extending in the second direction over the second cell region; a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail over the first cell region and the second cell region; and a fourth sub-ground rail branching from the third sub-ground rail and extending in the second direction.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including a ground rail. Background Art

[0002] A content addressable memory (CAM) cell may include a static random access memory (SRAM) part responsible for storage and a CAM part responsible for comparison to form a CAM cell. The CAM cell includes a NOR type CAM and a NAND type CAM.

[0003] Since the NOR type CAM has a higher speed than the NAND type CAM, relatively more NOR type CAMs are used. A 16T (16 transistors) NOR type CAM may be referred to as a ternary CAM, also known as a TCAM, and a 10T NOR type CAM may be referred to as a binary CAM, also known as a BCAM. Summary of the Invention

[0004] Aspects of the present disclosure provide a semiconductor device having improved integration by forming a ground rail in a mesh shape on the same metal level.

[0005] According to an exemplary embodiment of the present disclosure, there is provided a semiconductor device including: a substrate including a first cell region, a second cell region adjacent to the first cell region in a first direction, and a comparison region adjacent to the first cell region and the second cell region in a second direction different from the first direction; bit lines in a first metal level on the substrate, the bit lines extending in the first direction; and a first ground rail in a second metal level at a vertical level different from the first metal level, wherein the first ground rail includes: a first sub-ground rail extending in the second direction on the first cell region; a second sub-ground rail extending in the second direction on the second cell region; a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail on the first cell region and the second cell region; and a fourth sub-ground rail branching from the third sub-ground rail and extending in the second direction.

[0006] According to an exemplary embodiment of the present disclosure, a semiconductor device is provided, including: a substrate including a first unit region and a second unit region adjacent to the first unit region in a first direction; a first nanowire and a second nanowire extending in the first direction and stacked on the substrate with a sequential spacing from each other; gate electrodes extending in a second direction different from the first direction and surrounding each of the first nanowire and the second nanowire; bit lines in a first metal layer on the substrate, the bit lines extending in the first direction; and a first ground rail in a second metal layer located on the first metal layer, wherein the first ground rail includes: a first sub-ground rail extending in the second direction on the first unit region; a second sub-ground rail extending in the second direction on the second unit region; a third sub-ground rail on the first unit region and the second unit region and connecting the first sub-ground rail to the second sub-ground rail; and a fourth sub-ground rail branching from the third sub-ground rail and extending in the second direction.

[0007] According to an exemplary embodiment of the present disclosure, a semiconductor device is provided, including: a substrate including a first unit region, a second unit region adjacent to the first unit region in a first direction, and a comparison region adjacent to the first unit region and the second unit region in a second direction different from the first direction; a first nanowire and a second nanowire extending in the first direction and stacked on the substrate with a sequential spacing from each other; gate electrodes extending in the second direction and surrounding each of the first nanowire and the second nanowire; bit lines in a first metal layer on the substrate, the bit lines extending in the first direction; and a first ground rail in a second metal layer at a vertical level different from the first metal layer, wherein the first ground rail includes a first sub-ground rail extending in the second direction on the first unit region; a second sub-ground rail extending in the second direction on the second unit region; a third sub-ground rail extending in the first direction on the first unit region and the second unit region and connecting the first sub-ground rail to the second sub-ground rail; and a fourth sub-ground rail branching from the third sub-ground rail and extending in the second direction.

[0008] The scope of the present disclosure is not limited to the above embodiments, and other unmentioned embodiments can be clearly understood by those skilled in the art according to the following description. Description of the Drawings

[0009] By describing the exemplary embodiments of the present disclosure in detail with reference to the drawings, the above and other aspects and features of the present disclosure will become more apparent, in which:

[0010] Figures 1 to 11 is a view for describing a semiconductor device according to some exemplary embodiments of the present disclosure; and

[0011] Figures 12 to 17is a view for describing a semiconductor device according to some other example embodiments of the present disclosure. Detailed Description

[0012] In the drawings of a semiconductor device according to some example embodiments of the present disclosure, examples of transistors including nanowires (multi-bridge channel field effect transistors (MBCFET TM )) and examples of fin field effect transistors (FinFETs) including a channel region having a fin pattern are shown, but the present disclosure is not limited thereto. A semiconductor device according to some other example embodiments may further include a tunneling field effect transistor (tunneling FET) or a three-dimensional (3D) transistor. Additionally, a semiconductor device according to some other example embodiments may include a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS) transistor, and the like.

[0013] Hereinafter, reference will be made to Figures 1 to 11 describe a semiconductor device according to some example embodiments of the present disclosure.

[0014] Figure 1 is a view showing a front-end-of-line (FEOL) stage of a semiconductor device according to some example embodiments of the present disclosure. In some embodiments, the FEOL stage of semiconductor device processing may include the portion of semiconductor device processing before depositing a metal interconnect layer. Figure 2 is a view showing a middle-of-line (MOL) stage of a semiconductor device according to some example embodiments of the present disclosure. In some embodiments, the MOL stage of semiconductor device processing may include processing for connecting elements formed during the FEOL stage, such as to a contact structure. Figure 3 and Figure 5 is a cross-sectional view taken along line Figure 2 A-A' of. Figure 4 and Figure 6 is a cross-sectional view taken along line Figure 2 B-B' of. In some embodiments, generating an interconnect between elements of a semiconductor device may involve forming one or more stacked metal levels, where each metal level in the metal levels is at a different vertical height in the stack. Figure 7 is a view showing a first metal level of a semiconductor device according to some example embodiments of the present disclosure. Figure 8 is a view of the first to third metal levels of a semiconductor device according to some example embodiments of the present disclosure. Figure 9 is a view showing a first metal level of a semiconductor device according to some example embodiments of the present disclosure. Figure 10 is a view showing a second metal level of a semiconductor device according to some example embodiments of the present disclosure. Figure 11A view of a third metal level of a semiconductor device according to some example embodiments of the present disclosure.

[0015] Referring Figures 1 to 11 , a semiconductor device according to some example embodiments of the present disclosure may include first to sixteenth gate electrodes G1 to G16, first to eleventh fin patterns F1 to F11, first to tenth source / drain contacts CA1 to CA10, first to tenth gate contacts CB1 to CB10, first to eighth gate cut portions GC1 to GC8, first to twelfth source / drain vias VA1 to VA12, first to sixth gate vias VB1 to VB6, first to fifth ground pads VSP1 to VSP5, first to tenth word line pads WLP1 to WLP10, first to fifth ground vias VSV1 to VSV5, first to tenth word line vias WLV1 to WLV10, a first bit line BL1, a second bit line BL2, a power rail VDD, a first search line SL1, a second search line SL2, first to third word lines WL1 to WL3, a substrate 100, a field insulating film 105, a first ground rail 110, first to seventh sub-ground rails 111 to 117, first to third nanowires 131 to 133, a gate insulating film 141, gate spacers 142, a cap pattern 143, source / drain regions 150, a silicide layer 160, a first interlayer insulating film 170, and a second interlayer insulating film 180. It will be understood that although terms such as "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms; rather, these terms are only used to distinguish one element from another. Thus, without departing from the scope of the inventive concept, the first element discussed may be referred to as the second element.

[0016] The substrate 100 may include bulk silicon or silicon-on-insulator (SOI). In some embodiments, the substrate 100 may be a silicon substrate, or may include another material such as silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, the present disclosure is not limited thereto.

[0017] The substrate 100 may include a first unit region R1, a second unit region R2, and a comparison region R3. The first unit region R1 and the second unit region R2 may be disposed adjacent to each other in a first direction DR1. The comparison region R3 may be disposed adjacent to each of the first unit region R1 and the second unit region R2 in a second direction DR2 different from the first direction DR1.

[0018] The first unit region R1 and the second unit region R2 may be storage regions. That is, a storage device may be formed in each of the first unit region R1 and the second unit region R2. In this case, the storage device may be a static random access memory (SRAM).

[0019] A comparator for comparing signals of the first unit region R1 and the second unit region R2 with each other may be formed in the comparison region R3. That is, in a semiconductor device according to some example embodiments of the present disclosure, a ternary content addressable memory (TCAM) cell may be formed.

[0020] will be described with reference to Figure 1 a description of the FEOL stage of a semiconductor device according to some example embodiments of the present disclosure will be given. Refer to Figure 1 , each of the first to eleventh fin patterns F1 to F11 may extend in a first direction DR1.

[0021] The first fin pattern F1 may extend in the first direction DR1 over the first unit region R1 and the second unit region R2. The second fin pattern F2 may extend in the first direction DR1 over the first unit region R1 and the second unit region R2, and may be spaced apart from the first fin pattern F1 in a second direction DR2. The third fin pattern F3 may extend in the first direction DR1 over the first unit region R1, and may be spaced apart from the second fin pattern F2 in the second direction DR2. The fourth fin pattern F4 may extend in the first direction DR1 over the second unit region R2, may be spaced apart from the third fin pattern F3 in the first direction DR1, and may be spaced apart from the second fin pattern F2 in the second direction DR2.

[0022] The fifth fin pattern F5 may extend in the first direction DR1 over the first unit region R1, and may be spaced apart from the third fin pattern F3 in the second direction DR2. The sixth fin pattern F6 may extend in the first direction DR1 over the first unit region R1 and the second unit region R2, may be spaced apart from the fifth fin pattern F5 in the first direction DR1, and may be spaced apart from the third fin pattern F3 and the fourth fin pattern F4 in the second direction DR2. The seventh fin pattern F7 may extend in the first direction DR1 over the second unit region R2, may be spaced apart from the sixth fin pattern F6 in the first direction DR1, and may be spaced apart from the fourth fin pattern F4 in the second direction DR2.

[0023] The eighth fin-shaped pattern F8 can extend in the first direction DR1 over the first unit region R1 and the second unit region R2, and can be spaced apart from the fifth to seventh fin-shaped patterns F5, F6, and F7 in the second direction DR2. The ninth fin-shaped pattern F9 can extend in the first direction DR1 over the first unit region R1 and the second unit region R2, and can be spaced apart from the eighth fin-shaped pattern F8 in the second direction DR2. The tenth fin-shaped pattern F10 can extend in the first direction DR1 over the comparison region R3, and can be spaced apart from the ninth fin-shaped pattern F9 in the second direction DR2. The eleventh fin-shaped pattern F11 can extend in the first direction DR1 over the comparison region R3, and can be spaced apart from the tenth fin-shaped pattern F10 in the second direction DR2.

[0024] Each of the first to sixteenth gate electrodes G1 to G16 can extend in the second direction DR2.

[0025] The first gate electrode G1 can extend in the second direction DR2 over the first unit region R1. The second gate electrode G2 can extend in the second direction DR2 over the first unit region R1, and can be spaced apart from the first gate electrode G1 in the second direction DR2. The second gate electrode G2 can cross each of the first fin-shaped pattern F1, the second fin-shaped pattern F2, the third fin-shaped pattern F3, and the sixth fin-shaped pattern F6. The third gate electrode G3 can extend in the second direction DR2 over the first unit region R1, and can be spaced apart from the second gate electrode G2 in the second direction DR2. The third gate electrode G3 can cross each of the eighth fin-shaped pattern F8 and the ninth fin-shaped pattern F9. The fourth gate electrode G4 can extend in the second direction DR2 over the comparison region R3, and can be spaced apart from the third gate electrode G3 in the second direction DR2. The fourth gate electrode G4 can cross each of the tenth fin-shaped pattern F10 and the eleventh fin-shaped pattern F11. The fifth gate electrode G5 can extend in the second direction DR2 over the comparison region R3, and can be spaced apart from the fourth gate electrode G4 in the second direction DR2.

[0026] The sixth gate electrode G6 can extend in the second direction DR2 over the first unit region R1 and can be spaced apart from each of the first gate electrode G1 and the second gate electrode G2 in the first direction DR1. The sixth gate electrode G6 can cross each of the first fin pattern F1 and the second fin pattern F2. The seventh gate electrode G7 can extend in the second direction DR2 over the first unit region R1 and the comparison region R3, can be spaced apart from the sixth gate electrode G6 in the second direction DR2, and can be spaced apart from each of the second to fourth gate electrodes G2, G3, and G4 in the first direction DR1. The seventh gate electrode G7 can cross each of the third fin pattern F3, the sixth fin pattern F6, and the eighth to eleventh fin patterns F8 to F11. The eighth gate electrode G8 can extend in the second direction DR2 over the comparison region R3, can be spaced apart from the seventh gate electrode G7 in the second direction DR2, and can be spaced apart from the fifth gate electrode G5 in the first direction DR1.

[0027] The ninth gate electrode G9 can extend in the second direction DR2 over the second unit region R2 and can be spaced apart from the sixth gate electrode G6 in the first direction DR1. The ninth gate electrode G9 can cross each of the first fin pattern F1 and the second fin pattern F2. The tenth gate electrode G10 can extend in the second direction DR2 over the second unit region R2 and the comparison region R3, can be spaced apart from the ninth gate electrode G9 in the second direction DR2, and can be spaced apart from the seventh gate electrode G7 in the first direction DR1. The tenth gate electrode G10 can cross each of the fourth fin pattern F4, the sixth fin pattern F6, and the eighth to eleventh fin patterns F8 to F11. The eleventh gate electrode G11 can extend in the second direction DR2 over the comparison region R3, can be spaced apart from the tenth gate electrode G10 in the second direction DR2, and can be spaced apart from the eighth gate electrode G8 in the first direction DR1.

[0028] The twelfth gate electrode G12 may extend in a second direction DR2 over a second cell region R2 and may be spaced apart from a ninth gate electrode G9 in a first direction DR1. The thirteenth gate electrode G13 may extend in the second direction DR2 over the second cell region R2, may be spaced apart from each of the ninth gate electrode G9 and the tenth gate electrode G10 in the first direction DR1, and may be spaced apart from the twelfth gate electrode G12 in the second direction DR2. The thirteenth gate electrode G13 may cross each of a first fin pattern F1, a second fin pattern F2, a fourth fin pattern F4, and a sixth fin pattern F6. The fourteenth gate electrode G14 may extend in the second direction DR2 over the second cell region R2, may be spaced apart from the tenth gate electrode G10 in the first direction DR1, and may be spaced apart from the thirteenth gate electrode G13 in the second direction DR2. The fourteenth gate electrode G14 may cross each of an eighth fin pattern F8 and a ninth fin pattern F9. The fifteenth gate electrode G15 may extend in the second direction DR2 over a comparison region R3, may be spaced apart from the tenth gate electrode G10 in the first direction DR1, and may be spaced apart from the fourteenth gate electrode G14 in the second direction DR2. The fifteenth gate electrode G15 may cross each of a tenth fin pattern F10 and an eleventh fin pattern F11. The sixteenth gate electrode G16 may extend in the second direction DR2 over the comparison region R3, may be spaced apart from an eleventh gate electrode G11 in the first direction DR1, and may be spaced apart from the fifteenth gate electrode G15 in the second direction DR2.

[0029] A first gate cut GC1 may extend in the first direction DR1 over a first cell region R1 and may be disposed between a first gate electrode G1 and a second gate electrode G2. A second gate cut GC2 may extend in the first direction DR1 over the second cell region R2 and may be disposed between the twelfth gate electrode G12 and the thirteenth gate electrode G13. A third gate cut GC3 may extend in the first direction DR1 over the first cell region R1 and the second cell region R2 and may be disposed between a sixth gate electrode G6 and a seventh gate electrode G7 and between the ninth gate electrode G9 and the tenth gate electrode G10.

[0030] The fourth gate cutting part GC4 can extend in the first direction DR1 on the first unit area R1, and can be disposed between the second gate electrode G2 and the third gate electrode G3. The fifth gate cutting part GC5 can extend in the first direction DR1 on the second unit area R2, and can be disposed between the thirteenth gate electrode G13 and the fourteenth gate electrode G14. The sixth gate cutting part GC6 can extend in the first direction DR1 on the first unit area R1, and can be disposed between the third gate electrode G3 and the fourth gate electrode G4. The seventh gate cutting part GC7 can extend in the first direction DR1 on the second unit area R2, and can be disposed between the fourteenth gate electrode G14 and the fifteenth gate electrode G15. The eighth gate cutting part GC8 can extend in the first direction DR1 on the comparison area R3. The eighth gate cutting part GC8 can be disposed between the fourth gate electrode G4 and the fifth gate electrode G5, between the seventh gate electrode G7 and the eighth gate electrode G8, between the tenth gate electrode G10 and the eleventh gate electrode G11, and between the fifteenth gate electrode G15 and the sixteenth gate electrode G16.

[0031] The first fin pattern Fl, the second fin pattern F2, and the thirteenth gate electrode G13 can form a first pull-down transistor PDl. The fourth fin pattern F4 and the thirteenth gate electrode G13 can form a first pull-up transistor PU1. The first fin pattern F1, the second fin pattern F2, and the ninth gate electrode G9 can form a first transfer transistor PS1. The eighth fin pattern F8, the ninth fin pattern F9, and the tenth gate electrode G10 can form a second pull-down transistor PD2. The sixth fin pattern F6 and the tenth gate electrode G10 can form a second pull-up transistor PU2. The eighth fin pattern F8, the ninth fin pattern F9, and the fourteenth gate electrode G14 can form a second transfer transistor PS2.

[0032] The first fin pattern Fl, the second fin pattern F2, and the second gate electrode G2 can form a third pull-down transistor PD3. The third fin pattern F3 and the second gate electrode G2 can form a third pull-up transistor PU3. The first fin pattern F1, the second fin pattern F2, and the sixth gate electrode G6 can form a third transfer transistor PS3. The eighth fin pattern F8, the ninth fin pattern F9, and the seventh gate electrode G7 can form a fourth pull-down transistor PD4. The sixth fin pattern F6 and the seventh gate electrode G7 can form a fourth pull-up transistor PU4. The eighth fin pattern F8, the ninth fin pattern F9, and the third gate electrode G3 can form a fourth transfer transistor PS4.

[0033] The tenth fin pattern F10, the tenth fin pattern F11, and the fifteenth gate electrode G15 can form the fifth pull-down transistor PD5. The tenth fin pattern F10, the tenth fin pattern F11, and the tenth gate electrode G10 can form the fifth transfer transistor PS5. The tenth fin pattern F10, the eleventh fin pattern F11, and the fourth gate electrode G4 can form the sixth pull-down transistor PD6. The tenth fin pattern F10, the eleventh fin pattern F11, and the seventh gate electrode G7 can form the sixth transfer transistor PS6.

[0034] Reference will be made to Figure 2 give a description of the MOL stage of a semiconductor device according to some example embodiments of the present disclosure.

[0035] Referring to Figure 2 , the first source / drain contact CA1 can extend in the second direction DR2 over the first unit region R1. The first source / drain contact CA1 can cross each of the first gate cut GC1 and the fourth gate cut GC4, and each of the first fin pattern F1, the second fin pattern F2, the third fin pattern F3, the eighth fin pattern F8, and the ninth fin pattern F9. The first source / drain contact CA1 can include first to third protrusions CR1, CR2, and CR3 protruding in the third direction DR3. The third direction DR3 can be different from the first direction DR1 and the second direction DR2.

[0036] The second source / drain contact CA2 can extend in the second direction DR2 over the first unit region R1 and can be spaced apart from the first source / drain contact CA1 in the first direction DR1. The second source / drain contact CA2 can be on and / or cross each of the first gate cut GC1, the third gate cut GC3, and the fourth gate cut GC4, and each of the first fin pattern F1, the second fin pattern F2, the third fin pattern F3, the sixth fin pattern F6, the eighth fin pattern F8, and the ninth fin pattern F9. The second source / drain contact CA2 can include a fifth protrusion CR5 and a sixth protrusion CR6 protruding in the third direction DR3.

[0037] The third source / drain contact CA3 can extend in the second direction DR2 over the first unit region R1 and the second unit region R2 and can be spaced apart from the second source / drain contact CA2 in the first direction DR1. The third source / drain contact CA3 can cross the third gate cut GC3 and each of the first fin pattern F1, the second fin pattern F2, the sixth fin pattern F6, the eighth fin pattern F8, and the ninth fin pattern F9. The third source / drain contact CA3 can include seventh to ninth protrusions CR7, CR8, and CR9 protruding in the third direction DR3.

[0038] The fourth source / drain contact CA4 can extend in the second direction DR2 over the second cell region R2 and can be spaced apart from the third source / drain contact CA3 in the first direction DR1. The fourth source / drain contact CA4 can be on and / or cross each of the second gate cut GC2, the third gate cut GC3, and the fifth gate cut GC5, and each of the first fin pattern F1, the second fin pattern F2, the fourth fin pattern F4, the sixth fin pattern F6, the eighth fin pattern F8, and the ninth fin pattern F9. The fourth source / drain contact CA4 can include an eleventh protrusion CR11 and a twelfth protrusion CR12 protruding in the third direction DR3.

[0039] The fifth source / drain contact CA5 can extend in the second direction DR2 over the second cell region R2 and can be spaced apart from the fourth source / drain contact CA4 in the first direction DR1. The fifth source / drain contact CA5 can cross each of the second gate cut GC2 and the fifth gate cut GC5, and each of the first fin pattern F1, the second fin pattern F2, the fourth fin pattern F4, the eighth fin pattern F8, and the ninth fin pattern F9. The fifth source / drain contact CA5 can include thirteenth to fifteenth protrusions CR13, CR14, and CR15 protruding in the third direction DR3.

[0040] The sixth source / drain contact CA6 can extend in the second direction DR2 over the comparison region R3 and can be spaced apart from the first source / drain contact CA1 in the second direction DR2. The sixth source / drain contact CA6 can include a fourth protrusion CR4 protruding in the third direction DR3.

[0041] The seventh source / drain contact CA7 can extend in the second direction DR2 over the comparison region R3, can be spaced apart from the sixth source / drain contact CA6 in the first direction DR1, and can be spaced apart from the second source / drain contact CA2 in the second direction DR2.

[0042] The eighth source / drain contact CA8 can extend in the second direction DR2 over the comparison region R3, can be spaced apart from the seventh source / drain contact CA7 in the first direction DR1, and can be spaced apart from the third source / drain contact CA3 in the second direction DR2. The eighth source / drain contact CA8 can include a tenth protrusion CR10 protruding in the third direction DR3.

[0043] The ninth source / drain contact CA9 can extend in the second direction DR2 over the comparison region R3, can be spaced apart from the eighth source / drain contact CA8 in the first direction DR1, and can be spaced apart from the fourth source / drain contact CA4 in the second direction DR2.

[0044] The tenth source / drain contact CA10 may extend in a second direction DR2 over a comparison region R3, may be spaced apart from the ninth source / drain contact CA9 in a first direction DR1, and may be spaced apart from the fifth source / drain contact CA5 in the second direction DR2. The tenth source / drain contact CA10 may include a sixteenth protrusion CR16 protruding in a third direction DR3.

[0045] Each of the sixth to tenth source / drain contacts CA6 to CA10 may be on and / or cross each of the eighth gate cut GC8 and the tenth fin pattern F10 and the eleventh fin pattern F11.

[0046] The first gate contact CB1 may be disposed on the sixth gate electrode G6. The second gate contact CB2 may be disposed on the seventh gate electrode G7 and may contact a fifth protrusion CR5 formed on the second source / drain contact CA2. The third gate contact CB3 may be disposed on the second gate electrode G2 and may contact a sixth protrusion CR6 formed on the second source / drain contact CA2. The fourth gate contact CB4 may be disposed on the third gate electrode G3. The fifth gate contact CB5 may be disposed on the fourth gate electrode G4.

[0047] The sixth gate contact CB6 may be disposed on the ninth gate electrode G9. The seventh gate contact CB7 may be disposed on the tenth gate electrode G10 and may contact an eleventh protrusion CR11 formed on the fourth source / drain contact CA4. The eighth gate contact CB8 may be disposed on the thirteenth gate electrode G13 and may contact a twelfth protrusion CR12 formed on the fourth source / drain contact CA4. The ninth gate contact CB9 may be disposed on the fourteenth gate electrode G14. The tenth gate contact CB10 may be disposed on the fifteenth gate electrode G15.

[0048] The semiconductor device along Figure 1 and Figure 2 Examples of cross-sectional structures taken along line A-A' and line B-B' will be described with reference to Figure 3 and Figure 4 description.

[0049] A semiconductor device according to some example embodiments of the present disclosure may have a transistor structure including a plurality of nanowires (e.g., MBCFET TM structure). A semiconductor device according to some example embodiments of the present disclosure may include a field insulating film 105, first to third nanowires 131, 132, and 133, a gate insulating film 141, gate spacers 142, a capping pattern 143, source / drain regions 150, a silicide layer 160, a first interlayer insulating film 170, and a second interlayer insulating film 180.

[0050] Each of the eighth fin pattern F8 and the ninth fin pattern F9 may protrude from the substrate 100. Sidewalls of each of the eighth fin pattern F8 and the ninth fin pattern F9 may be in contact with the field insulating film 105. Each of the eighth fin pattern F8 and the ninth fin pattern F9 may be formed by etching a part of the substrate 100, and / or may include an epitaxial layer grown from the substrate 100.

[0051] In Figure 3 and Figure 4 an example is shown in which three nanowires 131, 132, and 133 are sequentially disposed on the substrate 100, but the present disclosure is not limited thereto. That is, in some other exemplary embodiments, the number of nanowires disposed on the substrate 100 may vary.

[0052] The first to third nanowires 131, 132, and 133 may be sequentially disposed on the substrate 100 in the third direction DR3 with spaces therebetween. Each of the first to third nanowires 131, 132, and 133 may extend in the first direction DR1.

[0053] Each of the tenth gate electrode G10 and the fourteenth gate electrode G14 may extend on the substrate 100 in the second direction DR2. Each of the tenth gate electrode G10 and the fourteenth gate electrode G14 may surround the first to third nanowires 131, 132, and 133. It will be understood that when used herein, "element A surrounds element B" (or similar language) means that element A at least partially surrounds element B, but does not necessarily mean that element A completely encloses element B.

[0054] Gate spacers 142 may be disposed on two sidewalls of each of the tenth gate electrode G10 and the fourteenth gate electrode G14. The gate spacers 142 may extend in the second direction DR2 along the two sidewalls of each of the tenth gate electrode G10 and the fourteenth gate electrode G14.

[0055] In Figure 3 the gate spacers 142 are shown as being formed as a single film, but the present disclosure is not limited thereto. That is, in some other exemplary embodiments, the gate spacers 142 may be formed as multiple films.

[0056] The gate insulating film 141 can be disposed between each of the tenth gate electrode G10 and the fourteenth gate electrode G14 and the gate spacer 142, between each of the tenth gate electrode G10 and the fourteenth gate electrode G14 and the third nanowire 133, between each of the tenth gate electrode G10 and the fourteenth gate electrode G14 and the second nanowire 132, between each of the tenth gate electrode G10 and the fourteenth gate electrode G14 and the first nanowire 131, and between each of the tenth gate electrode G10 and the fourteenth gate electrode G14 and the ninth fin pattern F9.

[0057] The cap pattern 143 can be disposed on each of the tenth gate electrode G10 and the fourteenth gate electrode G14. In Figure 3 the gate insulating film 141 is shown not to be disposed between the gate spacer 142 and the cap pattern 143, but the present disclosure is not limited thereto. That is, in some other exemplary embodiments, the gate insulating film 141 can be disposed between the gate spacer 142 and the cap pattern 143.

[0058] The source / drain regions 150 can be disposed on at least one side of the fourteenth gate electrode G14. The source / drain regions 150 can be disposed on at least one side of each of the first to third nanowires 131, 132, and 133. The source / drain regions 150 can be in contact with each of the first to third nanowires 131, 132, and 133.

[0059] The first interlayer insulating film 170 can be disposed on the source / drain regions 150 and the field insulating film 105. The first interlayer insulating film 170 can be disposed on the sidewalls of the gate spacer 142 and / or disposed to surround the sidewalls of the gate spacer 142. The upper surface of the first interlayer insulating film 170 can be coplanar with the upper surface of the cap pattern 143. The second interlayer insulating film 180 can be disposed on the first interlayer insulating film 170. The second interlayer insulating film 180 can be disposed on the upper surfaces of the gate spacer 142 and the cap pattern 143, and in some embodiments is disposed to cover the upper surfaces of the gate spacer 142 and the cap pattern 143.

[0060] The fourth source / drain contact CA4 and the fifth source / drain contact CA5 can be disposed in the second interlayer insulating film 180 and the first interlayer insulating film 170. The fourth source / drain contact CA4 can extend into the source / drain region 150 disposed on one side of the fourteenth gate electrode G14. The fifth source / drain contact CA5 can extend into the source / drain region 150 disposed on the other side of the fourteenth gate electrode G14.

[0061] The upper surface of each of the fourth source / drain contact CA4 and the fifth source / drain contact CA5 can be coplanar with the upper surface of the second interlayer insulating film 180, but the present disclosure is not limited thereto.

[0062] A silicide layer 160 may be disposed between a fourth source / drain contact CA4 and a source / drain region 150 and between a fifth source / drain contact CA5 and the source / drain region 150.

[0063] Along Figure 1 and Figure 2 Examples of cross-sectional structures of semiconductor devices taken along lines A-A' and B-B' will be described with reference to Figure 5 and Figure 6 Description. Figure 5 and Figure 6 The differences between the semiconductor devices shown in Figure 3 and Figure 4 and the semiconductor devices shown in

[0064] With reference to Figure 5 and Figure 6 According to some other example embodiments of the present disclosure, a semiconductor device may have a fin field-effect transistor (FinFET) structure including a channel region having a fin pattern. According to some other example embodiments of the present disclosure, a semiconductor device may include a field insulating film 105, a gate insulating film 241, gate spacers 242, a capping pattern 243, source / drain regions 250, a silicide layer 160, a first interlayer insulating film 170, and a second interlayer insulating film 180.

[0065] Each of a tenth gate electrode G10 and a fourteenth gate electrode G14 may extend on a substrate 100 in a second direction DR2. Each of the tenth gate electrode G10 and the fourteenth gate electrode G14 may extend on each of an eighth fin pattern F8 and a ninth fin pattern F9 in the second direction DR2.

[0066] Gate spacers 242 may be disposed on two sidewalls of each of the tenth gate electrode G10 and the fourteenth gate electrode G14. The gate spacers 242 may extend along two sidewalls of each of the tenth gate electrode G10 and the fourteenth gate electrode G14 in the second direction DR2.

[0067] The gate insulating film 241 may be disposed between each of the tenth gate electrode G10 and the fourteenth gate electrode G14 and the gate spacers 242 and between each of the tenth gate electrode G10 and the fourteenth gate electrode G14 and each of the eighth fin pattern F8 and the ninth fin pattern F9.

[0068] The capping pattern 243 may be disposed on each of the tenth gate electrode G10 and the fourteenth gate electrode G14. The source / drain region 250 may be disposed on at least one side of the fourteenth gate electrode G14.

[0069] With reference to Figure 2 ,Figure 7 and Figure 9 ,the first to fifth ground pads VSP1 to VSP5, the first to fifth word line pads WLP1 to WLP5, the first bit line BL1, the power supply rail VDD, the second bit line BL2, the first search line SL1, and the second search line SL2 can be disposed in the first metal layer LV1. The first metal layer LV1 can be disposed on the Figure 2 MOL stage shown.

[0070] The first ground pad VSP1 can be disposed on the first unit region R1. The first ground pad VSP1 can be connected to the first protrusion CR1 of the first source / drain contact CA1 through the first source / drain via VA1. The second ground pad VSP2 can be disposed on the second unit region R2. The second ground pad VSP2 can be connected to the thirteenth protrusion CR13 of the fifth source / drain contact CA5 through the ninth source / drain via VA9. The third ground pad VSP3 can be disposed on the comparison region R3. The third ground pad VSP3 can be connected to the fourth protrusion CR4 of the sixth source / drain contact CA6 through the fourth source / drain via VA4. The fourth ground pad VSP4 can be disposed on the comparison region R3. The fourth ground pad VSP4 can be connected to the sixteenth protrusion CR16 of the tenth source / drain contact CA10 through the twelfth source / drain via VA12. The fifth ground pad VSP5 can be disposed on the first unit region R1 and the second unit region R2. The fifth ground pad VSP5 can be connected to the ninth protrusion CR9 of the third source / drain contact CA3 through the seventh source / drain via VA7.

[0071] The first word line pad WLP1 can be disposed on the first unit region R1. The first word line pad WLP1 can be connected to the first gate contact CB1 through the first gate via VB1. The second word line pad WLP2 can be disposed on the second unit region R2. The second word line pad WLP2 can be connected to the sixth gate contact CB6 through the second gate via VB2. The third word line pad WLP3 can be disposed on the first unit region R1. The third word line pad WLP3 can be connected to the fourth gate contact CB4 through the third gate via VB3. The fourth word line pad WLP4 can be disposed on the second unit region R2. The fourth word line pad WLP4 can be connected to the ninth gate contact CB9 through the fourth gate via VB4. The fifth word line pad WLP5 can be disposed on the comparison region R3. The fifth word line pad WLP5 can be connected to the tenth protrusion CR10 of the eighth source / drain contact CA8 through the eighth source / drain via VA8.

[0072] The first bit line BL1 can extend in a first direction DR1 over a first cell region R1 and a second cell region R2. The first bit line BL1 can be connected to a seventh protrusion CR7 of a third source / drain contact CA3 through a fifth source / drain via VA5. The second bit line BL2 can extend in a first direction DR1 over the first cell region R1 and the second cell region R2, and can be spaced apart from the first bit line BL1 in a second direction DR2. The second bit line BL2 can be connected to a third protrusion CR3 of a first source / drain contact CA1 through a third source / drain via VA3. The second bit line BL2 can be connected to a fifteenth protrusion CR15 of a fifth source / drain contact CA5 through an eleventh source / drain via VA11.

[0073] The power supply rail VDD can extend in a first direction DR1 over the first cell region R1 and the second cell region R2, and can be disposed between the first bit line BL1 and the second bit line BL2. The power supply rail VDD can be connected to a second protrusion CR2 of a first source / drain contact CA1 through a second source / drain via VA2. The power supply rail VDD can be connected to an eighth protrusion CR8 of a third source / drain contact CA3 through a sixth source / drain via VA6. The power supply rail VDD can be connected to a fourteenth protrusion CR14 of a fifth source / drain contact CA5 through a tenth source / drain via VA10.

[0074] The first search line SL1 can extend in a first direction DR1 over a comparison region R3. The first search line SL1 can be connected to a tenth gate contact CB10 through a sixth gate via VB6. The second search line SL2 can extend in a first direction DR1 over the comparison region R3, and can be spaced apart from the first search line SL1 in a second direction DR2. The second search line SL2 can be connected to a fifth gate contact CB5 through a fifth gate via VB5.

[0075] Reference Figure 8 and Figure 10 , the sixth to tenth word line pads WLP6 to WLP10 and a first ground rail 110 can be disposed in a second metal layer LV2. The second metal layer LV2 can be located Figure 9 on the first metal layer LV1 as shown.

[0076] The sixth word line pad WLP6 can be disposed on the first cell region R1. The sixth word line pad WLP6 can be connected to a first word line pad WLP1 through a first word line via WLV1. The seventh word line pad WLP7 can be disposed on the second cell region R2. The seventh word line pad WLP7 can be connected to a second word line pad WLP2 through a second word line via WLV2.

[0077] The eighth word line pad WLP8 can be disposed on the first unit region R1. The eighth word line pad WLP8 can be connected to the third word line pad WLP3 through the third word line via WLV3. The ninth word line pad WLP9 can be disposed on the second unit region R2. The ninth word line pad WLP9 can be connected to the fourth word line pad WLP4 through the fourth word line via WLV4. The tenth word line pad WLP10 can be disposed on the comparison region R3. The tenth word line pad WLP10 can be connected to the fifth word line pad WLP5 through the fifth word line via WLV5.

[0078] The first ground rail 110 can include first to seventh sub-ground rails 111 to 117. The first ground rail 110 can have a grid shape.

[0079] The first sub-ground rail 111 can extend in the second direction DR2 on the first unit region R1. The first sub-ground rail 111 can cross the first bit line BL1 and the power supply rail VDD. However, the present disclosure is not limited thereto. The first sub-ground rail 111 can be connected to the first ground pad VSP1 through the first ground via VSV1.

[0080] The second sub-ground rail 112 can extend in the second direction DR2 on the second unit region R2. The second sub-ground rail 112 can be spaced apart from the first sub-ground rail 111 in the first direction DR1. The second sub-ground rail 112 can cross the first bit line BL1 and the power supply rail VDD. However, the present disclosure is not limited thereto. The second sub-ground rail 112 can be connected to the second ground pad VSP2 through the second ground via VSV2.

[0081] The third sub-ground rail 113 can extend in the first direction DR1 above the first unit region R1 and the second unit region R2. The third sub-ground rail 113 can connect the first sub-ground rail 111 to the second sub-ground rail 112. The third sub-ground rail 113 can overlap the power supply rail VDD in the third direction DR3. However, the present disclosure is not limited thereto.

[0082] The fourth sub-ground rail 114 can branch from the third sub-ground rail 113 and extend in the second direction DR2. The fourth sub-ground rail 114 can be disposed above the first unit region R1, the second unit region R2, and the comparison region R3. However, the present disclosure is not limited thereto. In some embodiments, the fourth sub-ground rail 114 may not be collinear with the first sub-ground rail 111 or the second sub-ground rail 112. The fourth sub-ground rail 114 can be connected to the fifth ground pad VSP5 through the fifth ground via VSV5.

[0083] The fifth sub-ground rail 115 may extend in the second direction DR2 over the comparison region R3. The fifth sub-ground rail 115 may be spaced apart from the first sub-ground rail 111 in the second direction DR2. The fifth sub-ground rail 115 may cross the second search line SL2. However, the present disclosure is not limited thereto. The fifth sub-ground rail 115 may be connected to the third ground pad VSP3 through the third ground via VSV3.

[0084] The sixth sub-ground rail 116 may extend in the second direction DR2 over the comparison region R3. The sixth sub-ground rail 116 may be spaced apart from the second sub-ground rail 112 in the second direction DR2 and may be spaced apart from the fifth sub-ground rail 115 in the first direction DR1. The sixth sub-ground rail 116 may cross the second search line SL2. However, the present disclosure is not limited thereto. The sixth sub-ground rail 116 may be connected to the fourth ground pad VSP4 through the fourth ground via VSV4.

[0085] The seventh sub-ground rail 117 may extend in the first direction DR1 over the comparison region R3. The seventh sub-ground rail 117 may connect the fourth sub-ground rail 114, the fifth sub-ground rail 115, and the sixth sub-ground rail 116 to each other. The seventh sub-ground rail 117 may overlap the second search line SL2 in the third direction DR3. However, the present disclosure is not limited thereto.

[0086] Referring to Figure 8 and Figure 11 , the first to third word lines WL1 to WL3 may be provided in the third metal layer LV3. The third metal layer LV3 may be located on Figure 10 the second metal layer LV2 shown.

[0087] The first word line WL1 may extend in the second direction DR2 over the second cell region R2 and the comparison region R3. The first word line WL1 may cross the third sub-ground rail 113 and the seventh sub-ground rail 117. However, the present disclosure is not limited thereto. The first word line WL1 may be connected to the seventh word line pad WLP7 through the seventh word line via WLV7. Additionally, the first word line WL1 may be connected to the ninth word line pad WLP9 through the ninth word line via WLV9.

[0088] The second word line WL2 may extend in the second direction DR2 over the first cell region R1, the second cell region R2, and the comparison region R3. The second word line WL2 may be spaced apart from the first word line WL1 in the first direction DR1. The second word line WL2 may cross the third sub-ground rail 113 and the seventh sub-ground rail 117. The second word line WL2 may overlap the fourth sub-ground rail 114 in the third direction DR3. However, the present disclosure is not limited thereto. The second word line WL2 may be connected to the tenth word line pad WLP10 through the tenth word line via WLV10.

[0089] The third word line WL3 may extend in the second direction DR2 over the first cell region R1 and the comparison region R3. The third word line WL3 may be spaced apart from the second word line WL2 in the first direction DR1. The third word line WL3 may cross the third sub-ground rail 113 and the seventh sub-ground rail 117. However, the present disclosure is not limited thereto. The third word line WL3 may be connected to the sixth word line pad WLP6 through the sixth word line via WLV6. Additionally, the third word line WL3 may be connected to the eighth word line pad WLP8 through the eighth word line via WLV8.

[0090] The first width d1 of the first word line WL1 in the first direction DR1 may be greater than the second width d2 of the second word line WL2 in the first direction DR1. Additionally, the third width d3 of the third word line WL3 in the first direction DR1 may be greater than the second width d2 of the second word line WL2 in the first direction DR1. In this case, for example, the first width d1 of the first word line WL1 in the first direction DR1 may be the same as the third width d3 of the third word line WL3 in the first direction DR1. However, the present disclosure is not limited thereto.

[0091] In a semiconductor device according to some example embodiments of the present disclosure, the first ground rail 110 provided in the second metal level LV2 is formed in a grid shape, and thus the integration degree can be improved.

[0092] Hereinafter, reference will be made to Figure 12 describe a semiconductor device according to some other example embodiments of the present disclosure. Figure 12 The differences between the semiconductor device shown and Figures 1 to 11 the semiconductor device shown will be mainly described.

[0093] Figure 12 is a view for describing a semiconductor device according to some other example embodiments of the present disclosure.

[0094] Refer to Figure 12 In a semiconductor device according to some other example embodiments of the present disclosure, a first ground rail 210 may be provided in the second metal level LV2, and a second ground rail 220 may be provided in the first metal level LV1.

[0095] The second ground rail 220 may extend in the first direction DR1 over the comparison region R3 and may be spaced apart from the second search line SL2 in the second direction DR2. The first ground rail 210 may include first to fourth sub-ground rails 211 to 214.

[0096] The first sub-ground rail 211 may extend in a second direction DR2 over a first unit region R1 and a comparison region R3. The first sub-ground rail 211 may intersect each of a first bit line BL1, a power supply rail VDD, a second bit line BL2, a first search line SL1, a second search line SL2, and a second ground rail 220. However, the present disclosure is not limited thereto. The first sub-ground rail 211 may be connected to a first ground pad VSP1 through a first ground via VSV1. Additionally, the first sub-ground rail 211 may be connected to the second ground rail 220 through a sixth ground via VSV6.

[0097] The second sub-ground rail 212 may extend in a second direction DR2 over a second unit region R2 and a comparison region R3. The second sub-ground rail 212 may be spaced apart from the first sub-ground rail 211 in a first direction DR1. The second sub-ground rail 212 may intersect each of a first bit line BL1, a power supply rail VDD, a second bit line BL2, a first search line SL1, a second search line SL2, and a second ground rail 220. However, the present disclosure is not limited thereto. The second sub-ground rail 212 may be connected to a second ground pad VSP2 through a second ground via VSV2. Additionally, the second sub-ground rail 212 may be connected to the second ground rail 220 through a seventh ground via VSV7.

[0098] The third sub-ground rail 213 may extend in a first direction DR1 above the first unit region R1 and the second unit region R2. The third sub-ground rail 213 may connect the first sub-ground rail 211 to the second sub-ground rail 212.

[0099] The fourth sub-ground rail 214 may branch from the third sub-ground rail 213 and extend in a second direction DR2. The fourth sub-ground rail 214 may be disposed above the first unit region R1, the second unit region R2, and the comparison region R3.

[0100] Hereinafter, reference will be made to Figure 13 to describe a semiconductor device according to some other exemplary embodiments of the present disclosure. Figure 13 The differences between the semiconductor device shown and Figures 1 to 11 the semiconductor device shown will be mainly described.

[0101] Figure 13 is a view for describing a semiconductor device according to some other exemplary embodiments of the present disclosure.

[0102] Referring to Figure 13 , in a semiconductor device according to some other exemplary embodiments of the present disclosure, a first ground rail 310 may include first to seventh sub-ground rails 311 to 317.

[0103] The first sub-ground rail 311 may extend in a second direction DR2 over a first unit region R1. The first sub-ground rail 311 may cross a first bit line BL1 and a power supply rail VDD. The second sub-ground rail 312 may extend in a second direction DR2 over a second unit region R2. The second sub-ground rail 312 may be spaced apart from the first sub-ground rail 311 in a first direction DR1. The second sub-ground rail 312 may cross the first bit line BL1 and the power supply rail VDD. The third sub-ground rail 313 may extend in a first direction DR1 over the first unit region R1 and the second unit region R2. The third sub-ground rail 313 may connect the first sub-ground rail 311 to the second sub-ground rail 312. The third sub-ground rail 313 may overlap the power supply rail VDD in a third direction DR3.

[0104] A fourth sub-ground rail 314 may branch from the third sub-ground rail 313 and extend in a second direction DR2. The fourth sub-ground rail 314 may be disposed over the first unit region R1, the second unit region R2, and a comparison region R3. A fifth sub-ground rail 315 may extend in a second direction DR2 over the comparison region R3. The fifth sub-ground rail 315 may be spaced apart from the first sub-ground rail 311 in a second direction DR2. In some embodiments, the fifth sub-ground rail 315 may be spaced apart from a second search line SL2 in a second direction DR2. A sixth sub-ground rail 316 may extend in a second direction DR2 over the comparison region R3. The sixth sub-ground rail 316 may be spaced apart from the second sub-ground rail 312 in a second direction DR2, and may be spaced apart from the fifth sub-ground rail 315 in a first direction DR1. In some embodiments, the sixth sub-ground rail 316 may be spaced apart from the second search line SL2 in a second direction DR2.

[0105] A seventh sub-ground rail 317 may connect the fourth sub-ground rail 314 to each of the fifth sub-ground rail 315 and the sixth sub-ground rail 316 over the comparison region R3. The seventh sub-ground rail 317 may include a first portion 317_1 and a second portion 317_2. The first portion 317_1 of the seventh sub-ground rail 317 may extend in a fourth direction DR4 different from the first direction DR1 and the second direction DR2, and connect the fourth sub-ground rail 314 to the sixth sub-ground rail 316. The second portion 317_2 of the seventh sub-ground rail 317 may extend in a fifth direction DR5 different from the first direction DR1, the second direction DR2, and the fourth direction DR4, and connect the fourth sub-ground rail 314 to the fifth sub-ground rail 315.

[0106] Hereinafter, reference will be made to Figure 14 describe semiconductor devices according to some other exemplary embodiments of the present disclosure. Figure 14 The semiconductor device shown is related to Figures 1 to 11The differences between the semiconductor devices shown will be mainly described.

[0107] Figure 14 is a view for describing a semiconductor device according to some other exemplary embodiments of the present disclosure.

[0108] Referring Figure 14 , in a semiconductor device according to some other exemplary embodiments of the present disclosure, the first ground rail 410 may include first to seventh sub-ground rails 411 to 417.

[0109] The first sub-ground rail 411 may extend in a second direction DR2 over a first unit region R1. The first sub-ground rail 411 may be on and / or cross a first bit line BL1. The second sub-ground rail 412 may extend in the second direction DR2 over a second unit region R2. The second sub-ground rail 412 may be spaced apart from the first sub-ground rail 411 in a first direction DR1. The second sub-ground rail 412 may be on and / or cross the first bit line BL1.

[0110] The third sub-ground rail 413 may connect the first sub-ground rail 411 and the second sub-ground rail 412 to the fourth sub-ground rail 414 over the first unit region R1 and the second unit region R2. The third sub-ground rail 413 may include a first portion 413_1 and a second portion 413_2. The first portion 413_1 of the third sub-ground rail 413 may extend in a fourth direction DR4 and connect the first sub-ground rail 411 to the fourth sub-ground rail 414. The second portion 413_2 of the third sub-ground rail 413 may extend in a fifth direction DR5 and connect the second sub-ground rail 412 to the fourth sub-ground rail 414.

[0111] The fourth sub-ground rail 414 can branch from the third sub-ground rail 413 and extend in the second direction DR2. The fourth sub-ground rail 414 can be disposed above the first unit region R1, the second unit region R2, and the comparison region R3. The fifth sub-ground rail 415 can extend in the second direction DR2 over the comparison region R3. The fifth sub-ground rail 415 can be spaced apart from the first sub-ground rail 411 in the second direction DR2. The fifth sub-ground rail 415 can cross the second search line SL2. The sixth sub-ground rail 416 can extend in the second direction DR2 over the comparison region R3. The sixth sub-ground rail 416 can be spaced apart from the second sub-ground rail 412 in the second direction DR2, and can be spaced apart from the fifth sub-ground rail 415 in the first direction DR1. The sixth sub-ground rail 416 can cross the second search line SL2. The seventh sub-ground rail 417 can extend in the first direction DR1 over the comparison region R3. The seventh sub-ground rail 417 can connect the fourth sub-ground rail 414, the fifth sub-ground rail 415, and the sixth sub-ground rail 416 to each other. The seventh sub-ground rail 417 can overlap the second search line SL2 in the third direction DR3.

[0112] Hereinafter, reference will be made to Figure 15 describe semiconductor devices according to some other exemplary embodiments of the present disclosure. Figure 15 The semiconductor device shown and Figures 1 to 11 The differences between the semiconductor devices shown will be mainly described.

[0113] Figure 15 is a view for describing semiconductor devices according to some other exemplary embodiments of the present disclosure.

[0114] Referring to Figure 15 , in a semiconductor device according to some other exemplary embodiments of the present disclosure, the first ground rail 510 can include first to seventh sub-ground rails 511 to 517.

[0115] The first sub-ground rail 511 can extend in the second direction DR2 over the first unit region R1. The first sub-ground rail 511 can be on and / or cross the first bit line BL1. The second sub-ground rail 512 can extend in the second direction DR2 over the second unit region R2. The second sub-ground rail 512 can be spaced apart from the first sub-ground rail 511 in the first direction DR1. The second sub-ground rail 512 can be on and / or cross the first bit line BL1.

[0116] The third sub-ground rail 513 can connect the first sub-ground rail 511 and the second sub-ground rail 512 to the fourth sub-ground rail 514 in the first unit region R1 and the second unit region R2. The third sub-ground rail 513 can include a first portion 513_1 and a second portion 513_2. The first portion 513_1 of the third sub-ground rail 513 can extend in the fourth direction DR4 and connect the first sub-ground rail 511 to the fourth sub-ground rail 514. The second portion 513_2 of the third sub-ground rail 513 can extend in the fifth direction DR5 and connect the second sub-ground rail 512 to the fourth sub-ground rail 514.

[0117] The fourth sub-ground rail 514 can branch from the third sub-ground rail 513 and extend in the second direction DR2. The fourth sub-ground rail 514 can be disposed above the first unit region R1, the second unit region R2, and the comparison region R3. The fifth sub-ground rail 515 can extend in the second direction DR2 in the comparison region R3. The fifth sub-ground rail 515 can be spaced apart from the first sub-ground rail 511 in the second direction DR2. The sixth sub-ground rail 516 can extend in the second direction DR2 in the comparison region R3. The sixth sub-ground rail 516 can be spaced apart from the second sub-ground rail 512 in the second direction DR2 and can be spaced apart from the fifth sub-ground rail 515 in the first direction DR1.

[0118] The seventh sub-ground rail 517 can connect the fourth sub-ground rail 514 to the fifth sub-ground rail 515 and the sixth sub-ground rail 516 in the comparison region R3. The seventh sub-ground rail 517 can include a first portion 517_1 and a second portion 517_2. The first portion 517_1 of the seventh sub-ground rail 517 can extend in the fourth direction DR4 and connect the fourth sub-ground rail 514 to the sixth sub-ground rail 516. The second portion 517_2 of the seventh sub-ground rail 517 can extend in the fifth direction DR5 and connect the fourth sub-ground rail 514 to the fifth sub-ground rail 515.

[0119] Hereinafter, reference will be made to Figure 16 describe semiconductor devices according to some other exemplary embodiments of the present disclosure. Figure 16 The differences between the semiconductor devices shown and Figures 1 to 11 the semiconductor devices shown will be mainly described.

[0120] Figure 16 is a view for describing semiconductor devices according to some other exemplary embodiments of the present disclosure.

[0121] Refer to Figure 16, in a semiconductor device according to some other example embodiments of the present disclosure, the first ground rail 610 may be disposed in the second metal layer LV2, and the second ground rail 620 may be disposed in the first metal layer LV1.

[0122] The second ground rail 620 may extend in a first direction DR1 over a comparison region R3 and may be spaced apart from a second search line SL2 in a second direction DR2. The first ground rail 610 may include first to fourth sub-ground rails 611 to 614.

[0123] The first sub-ground rail 611 may extend in the second direction DR2 over a first unit region R1 and a comparison region R3. The first sub-ground wire 611 may cross each of a first bit line BL1, a power rail VDD, a second bit line BL2, a first search line SL1, a second search line SL2, and the second ground rail 620.

[0124] The second sub-ground rail 612 may extend in the second direction DR2 over a second unit region R2 and a comparison region R3. The second sub-ground rail 612 may be spaced apart from the first sub-ground rail 611 in the first direction DR1. The second sub-ground wire 612 may cross each of a first bit line BL1, a power rail VDD, a second bit line BL2, a first search line SL1, a second search line SL2, and the second ground rail 620.

[0125] The third sub-ground rail 613 may connect the first sub-ground rail 611 and the second sub-ground rail 612 to the fourth sub-ground rail 614 over the first unit region R1 and the second unit region R2. The third sub-ground rail 613 may include a first portion 613_1 and a second portion 613_2. The first portion 613_1 of the third sub-ground rail 613 may extend in a fourth direction DR4 and connect the first sub-ground rail 611 to the fourth sub-ground rail 614. The second portion 613_2 of the third sub-ground rail 613 may extend in a fifth direction DR5 and connect the second sub-ground rail 612 to the fourth sub-ground rail 614.

[0126] The fourth sub-ground rail 614 may branch from the third sub-ground rail 613 and extend in the second direction DR2. The fourth sub-ground rail 614 may be disposed above the first unit region R1, the second unit region R2, and the comparison region R3.

[0127] Hereinafter, reference will be made to Figure 17 a description of a semiconductor device according to some other example embodiments of the present disclosure. Figure 17 The differences between the semiconductor device shown and Figures 1 to 11 the semiconductor device shown will be mainly described.

[0128] Figure 17It is a view for describing a semiconductor device according to some other example embodiments of the present disclosure.

[0129] Referring to Figure 17 , in a semiconductor device according to some other example embodiments of the present disclosure, widths of first to third word lines WL1, WL4, and WL3 in a first direction DR1 may be the same as each other.

[0130] Specifically, a first width d1 of the first word line WL1 in the first direction DR1, a fourth width d4 of the second word line WL4 in the first direction DR1, and a third width d3 of the third word line WL3 in the first direction DR1 may be the same as each other.

[0131] Although example embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the example embodiments disclosed herein, but may be implemented in various different forms. Those skilled in the art will understand that various modifications can be made without departing from the scope of the present disclosure defined by the appended claims. Accordingly, the above example embodiments should be considered only in a descriptive sense and not for the purpose of limitation.

[0132] This application claims the benefit of Korean Patent Application No. 10-2019-0088859, filed on Jul. 23, 2019, in the Korean Intellectual Property Office, and claims the benefit of Korean Patent Application No. 10-2019-0141482, filed on Nov. 7, 2019, in the Korean Intellectual Property Office, the entire contents of each of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: a substrate including a first unit region, a second unit region adjacent to the first unit region in a first direction, and a comparison region adjacent to the first unit region and the second unit region in a second direction different from the first direction; bit lines on the substrate in a first metal layer, the bit lines extending in the first direction; a power rail disposed on the substrate in the first metal layer and extending in the first direction; and a first ground rail in a second metal layer at a vertical level different from the first metal layer, wherein the first ground rail includes: a first sub - ground rail extending in the second direction over the first unit region, a second sub - ground rail extending in the second direction over the second unit region, a third sub - ground rail connecting the first sub - ground rail to the second sub - ground rail over the first unit region and the second unit region, and a fourth sub - ground rail branching from the third sub - ground rail and extending in the second direction.

2. The semiconductor device according to claim 1, wherein The third sub - ground rail extends in the first direction.

3. The semiconductor device according to claim 1, wherein The third sub - ground rail includes: a first portion extending in a third direction different from the first direction and the second direction and connecting the first sub - ground rail to the fourth sub - ground rail; and a second portion extending in a fourth direction different from the first direction, the second direction, and the third direction and connecting the second sub - ground rail to the fourth sub - ground rail.

4. The semiconductor device according to claim 1, wherein, The first ground rail further includes: a fifth sub - ground rail extending in the second direction over the comparison region; a sixth sub - ground rail extending in the second direction over the comparison region and spaced apart from the fifth sub - ground rail in the first direction; and a seventh sub - ground rail connected to each of the fourth sub - ground rail, the fifth sub - ground rail, and the sixth sub - ground rail.

5. The semiconductor device according to claim 4, wherein The seventh sub - ground rail extends in the first direction.

6. The semiconductor device according to claim 4, wherein, The seventh sub - ground rail includes: a first portion extending in a third direction different from the first direction and the second direction and connecting the sixth sub - ground rail to the fourth sub - ground rail; and a second portion extending in a fourth direction different from the first direction, the second direction, and the third direction and connecting the fifth sub - ground rail to the fourth sub - ground rail.

7. The semiconductor device according to claim 1, further comprising a second ground rail extending in the first direction over the comparison region in the first metal layer.

8. The semiconductor device according to claim 1 further includes a first word line, a second word line, and a third word line in a third metal level at a vertical level different from the first metal level and the second metal level, wherein, The first word line, the second word line, and the third word line each extend in the second direction and are sequentially spaced apart from each other in the first direction, and wherein a first width of the first word line in the first direction is greater than a second width of the second word line in the first direction.

9. The semiconductor device according to claim 8, wherein, The first width of the first word line in the first direction is equal to a third width of the third word line in the first direction.

10. The semiconductor device according to claim 1 further includes a first word line, a second word line, and a third word line in a third metal level at a vertical level different from the first metal level and the second metal level, wherein, The first word line, the second word line, and the third word line each extend in the second direction and are sequentially spaced apart from each other in the first direction, and wherein a first width of the first word line in the first direction, a second width of the second word line in the first direction, and a third width of the third word line in the first direction are equal to each other.

11. The semiconductor device according to claim 1, further comprising: a first nanowire and a second nanowire, extending in the first direction and stacked on the substrate to be sequentially spaced apart from each other; and a gate electrode, extending in the second direction and surrounding each of the first nanowire and the second nanowire.

12. A semiconductor device, comprising: a substrate including a first unit region and a second unit region adjacent to the first unit region in a first direction; a first nanowire and a second nanowire, extending in the first direction and stacked on the substrate to be sequentially spaced apart from each other; a gate electrode, extending in a second direction different from the first direction and surrounding each of the first nanowire and the second nanowire; a bit line in a first metal layer on the substrate, the bit line extending in the first direction; a power rail, provided on the substrate in the first metal layer and extending in the first direction; and a first ground rail in a second metal layer on the first metal layer, wherein the first ground rail includes: a first sub-ground rail, extending in the second direction over the first unit region, a second sub-ground rail, extending in the second direction over the second unit region, a third sub-ground rail, over the first unit region and the second unit region and connecting the first sub-ground rail to the second sub-ground rail, and a fourth sub-ground rail, branching from the third sub-ground rail and extending in the second direction.

13. The semiconductor device according to claim 12, wherein, The third sub-ground rail extends in the first direction.

14. The semiconductor device according to claim 12, wherein, The third sub-ground rail includes: a first portion, extending in a third direction different from the first direction and the second direction, the first portion connecting the first sub-ground rail to the fourth sub-ground rail; and a second portion, extending in a fourth direction different from the first direction, the second direction, and the third direction, the second portion connecting the second sub-ground rail to the fourth sub-ground rail.

15. The semiconductor device according to claim 12, further comprising a comparison region adjacent to the first unit region and the second unit region in the second direction, Among them, wherein the first ground rail further includes: a fifth sub-ground rail, extending in the second direction over the comparison region; a sixth sub-ground rail, extending in the second direction over the comparison region and spaced apart from the fifth sub-ground rail in the first direction; and a seventh sub-ground rail, connected to each of the fourth sub-ground rail, the fifth sub-ground rail, and the sixth sub-ground rail.

16. The semiconductor device according to claim 12, further comprising: A comparison region, adjacent to the first unit region and the second unit region in the second direction; and A second ground rail, in the first metal layer and extending in the first direction.

17. The semiconductor device according to claim 12 further includes a first word line, a second word line, and a third word line in a third metal level located on the second metal level, wherein, The first word line, the second word line, and the third word line each extend in the second direction and are sequentially spaced apart from each other in the first direction, wherein the first width of the first word line in the first direction is greater than the second width of the second word line in the first direction.

18. A semiconductor device, comprising: A substrate, including a first unit region, a second unit region adjacent to the first unit region in a first direction, and a comparison region adjacent to the first unit region and the second unit region in a second direction different from the first direction; A first nanowire and a second nanowire, extending in the first direction and stacked on the substrate to be sequentially spaced apart from each other; A gate electrode, extending in the second direction and surrounding each of the first nanowire and the second nanowire; A bit line on the substrate in a first metal layer, the bit line extending in the first direction; A power rail, disposed on the substrate in the first metal layer and extending in the first direction; and A first ground rail, in a second metal layer at a vertical layer different from the first metal layer, wherein the first ground rail includes: A first sub-ground rail, extending in the second direction over the first unit region, A second sub-ground rail, extending in the second direction over the second unit region, A third sub-ground rail, extending in the first direction over the first unit region and the second unit region and connecting the first sub-ground rail to the second sub-ground rail, and A fourth sub-ground rail, branching from the third sub-ground rail and extending in the second direction.

19. The semiconductor device according to claim 18, wherein, The first ground rail further includes: A fifth sub-ground rail, extending in the second direction over the comparison region; A sixth sub-ground rail, extending in the second direction over the comparison region and spaced apart from the fifth sub-ground rail in the first direction; and A seventh sub-ground rail, connected to each of the fourth sub-ground rail, the fifth sub-ground rail, and the sixth sub-ground rail.

20. The semiconductor device according to claim 19, wherein, The seventh sub-ground rail includes: A first portion, extending in a third direction different from the first direction and the second direction and connecting the sixth sub-ground rail to the fourth sub-ground rail; and A second portion, extending in a fourth direction different from the first direction, the second direction, and the third direction and connecting the fifth sub-ground rail to the fourth sub-ground rail.

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