Three-dimensional semiconductor memory device

Abstract

A semiconductor memory device includes horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction. A memory structure is disposed on the horizontal patterns. The memory structure includes a source structure and an electrode structure. A division structure is disposed between the horizontal patterns adjacent in the first direction and is configured to separate the source structures of the adjacent memory structures from each other. An etch stop pattern is disposed between the horizontal patterns at a height lower than a height of the source structure. The etch stop pattern is connected to a lower portion of the division structure.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0094346, filed with the Korean Patent Office on August 2, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to three-dimensional semiconductor memory devices and methods for manufacturing the same, and more specifically, to highly integrated three-dimensional semiconductor memory devices and methods for manufacturing the same. Background Technology

[0004] Consumer demand for high-performance and relatively inexpensive electronic devices has led to a need for higher integration levels in semiconductor devices. In the case of two-dimensional or planar semiconductor devices, their integration level is largely determined by the area occupied by a single memory cell, and is therefore greatly influenced by the level of fine patterning technology. However, increasing pattern fineness requires very expensive equipment, and there are practical limitations to pattern fineness. Therefore, three-dimensional semiconductor memory devices incorporating three-dimensionally arranged memory cells have recently been proposed. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a three-dimensional semiconductor memory device with increased integration density.

[0006] An exemplary embodiment of the present invention provides a method for reducing process failures in the manufacturing process of three-dimensional semiconductor memory devices.

[0007] According to an exemplary embodiment of the present invention, a semiconductor memory device includes horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction. A memory structure is disposed on the horizontal patterns. The memory structure includes a source structure and an electrode structure. A partition structure is disposed between adjacent horizontal patterns in the first direction and is configured to separate the source structures of adjacent memory structures from each other. An etch stop pattern is disposed between the horizontal patterns at a height below the height of the source structures. The etch stop pattern is connected to the lower portion of the partition structure.

[0008] According to an exemplary embodiment of the present invention, a semiconductor memory device includes horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, wherein partition regions are interposed between the horizontal patterns in a first direction. Each partition region includes a first insulating through-layer. A memory structure is disposed on the horizontal patterns. The memory structure includes a source structure and electrode structures on the source structure. A vertical structure penetrates the electrode structures and is connected to the source structures. A partition structure is disposed in the partition regions and configured to separate the source structures of adjacent memory structures from each other. Etch-stop patterns are disposed between the horizontal patterns and at a height below the height of the horizontal patterns. The etch-stop patterns are connected to the lower portion of the partition structure. Through-hole plugs are configured to connect the memory structure to the peripheral circuit structure. The source structure includes a first power supply pattern disposed on the horizontal patterns and a second power supply pattern disposed between the first power supply pattern and the horizontal patterns. The first power supply pattern extends to the partition regions and is connected to the sidewalls of the partition structure.

[0009] According to an exemplary embodiment of the present invention, a semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction. A memory structure is disposed on the horizontal patterns. The memory structure includes a source structure and electrode structures on the source structure. A partition structure is disposed between adjacent horizontal patterns in the first direction. The partition structure is configured to separate the source structures of adjacent memory structures from each other. An etch stop pattern is disposed between the horizontal patterns and connected to the lower portion of the partition structure. A through-hole connects the memory structure to the peripheral circuit structure. The etch stop pattern is disposed at the same height as the horizontal patterns.

[0010] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor memory device includes forming a peripheral circuit structure on a substrate. Horizontal patterns are formed on the peripheral circuit structure and spaced apart from each other in a first direction. A portion of the horizontal pattern contacts an edge of the substrate. A memory structure is formed on the horizontal patterns. The memory structure includes a source structure and electrode structures on the source structure. A vertical structure is formed such that it penetrates the electrode structures and connects to the source structures. A partition structure is formed between adjacent horizontal patterns in the first direction. The partition structure is configured to separate the source structures of adjacent memory structures from each other. Etch-stop patterns are formed between the horizontal patterns and disposed at a height below the height of the source structures. The etch-stop patterns are connected to the lower portion of the partition structure. The horizontal patterns are configured to release charge on the surface of the horizontal patterns to the semiconductor substrate. Attached Figure Description

[0011] The exemplary embodiments will be more clearly understood through the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments described herein.

[0012] Figure 1This is a top view illustrating an exemplary embodiment of a substrate according to a concept of the present invention, the substrate including a three-dimensional semiconductor memory device integrated thereon.

[0013] Figure 2 This is a perspective view illustrating an exemplary embodiment of a three-dimensional semiconductor device according to a concept of the present invention.

[0014] Figure 3 This is a top view illustrating an exemplary embodiment of a three-dimensional semiconductor memory device according to a concept of the present invention.

[0015] Figure 4A and Figure 4B This is a top view illustrating a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the concept of the present invention.

[0016] Figure 5 This is an exemplary embodiment of the concept of the present invention. Figure 4A A magnified top view of the area "Q".

[0017] Figures 6 to 8 These are exemplary embodiments of the present invention, respectively along... Figure 5 The sectional views taken from lines I-I', II-II', and III-III'.

[0018] Figure 9A This illustrates an exemplary embodiment of the concept according to the present invention. Figure 8 An enlarged sectional view of part of the "P".

[0019] Figure 9B This illustrates an exemplary embodiment of the concept according to the present invention. Figure 7 An enlarged sectional view of part of the "R".

[0020] Figures 10 to 12 This is a top view illustrating a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the concept of the present invention.

[0021] Figure 13 and Figure 14 These are exemplary embodiments of the present invention, respectively along... Figure 5 A cross-sectional view of a three-dimensional semiconductor memory device taken along lines I-I' and II-II'.

[0022] Figure 15 , Figure 18 , Figure 21 and Figure 24 This is a cross-sectional view illustrating an exemplary embodiment of the invention. Figure 5 A method for manufacturing three-dimensional semiconductor memory devices by cutting the line I-I'.

[0023] Figure 16 , Figure 19 , Figure 22 and Figure 25 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 5 A cross-sectional view of a method for manufacturing a three-dimensional semiconductor memory device, taken from line II-II'.

[0024] Figure 17 , Figure 20 , Figure 23 and Figure 26 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 5 A cross-sectional view of a method for manufacturing a three-dimensional semiconductor memory device, taken from line III-III'.

[0025] Figure 27 This is an exemplary embodiment of the concept of the present invention. Figure 5 A cross-sectional view of a three-dimensional semiconductor memory device taken from line II-II'.

[0026] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in some exemplary embodiments and to supplement the written description provided below. However, these figures may not be drawn to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as defining or limiting the range of values ​​or performances covered by the exemplary embodiments conceived in this invention. For example, the relative thickness and location of molecules, layers, regions, and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in different figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0027] Figure 1 This is a top view showing a substrate on which a three-dimensional semiconductor memory device, according to an exemplary embodiment of the present invention, is integrated.

[0028] Reference Figure 1 The semiconductor substrate 1 (e.g., a wafer, etc.) may include: chip regions 10, including semiconductor chips formed thereon; and scribing regions 20, located between the chip regions 10. In an exemplary embodiment, the semiconductor substrate 1 may include a plurality of discrete chip regions arranged in two different directions (e.g., a first direction D1 and a second direction D2). Each chip region 10 may be surrounded by a scribing region 20. In other words, the scribing region 20 may be disposed between each pair of adjacent chip regions 10 that are adjacent to each other in the first direction D1 and / or the second direction D2. Although the chip regions 10 are arranged in two different directions (e.g., a first direction D1 and a second direction D2), the semiconductor substrate 1 may include: chip regions 10, including semiconductor chips formed thereon; and scribing regions 20, located between the chip regions 10. Figure 1The exemplary embodiment is shown as including a plurality of square chip regions arranged in rows and columns, but the exemplary embodiment of the inventive concept is not limited thereto. For example, chip regions 10 may have different shapes in a plan view (e.g., when viewed from a third party toward D3), and the plurality of chip regions may have various different arrangements.

[0029] In an exemplary embodiment, the semiconductor substrate 1 may be a bulk silicon wafer, a silicon-on-insulator (SOI) wafer, a germanium wafer, a germanium-on-insulator (GOI) wafer, a silicon-germanium wafer, or a thin wafer including an epitaxial layer formed by a selective epitaxial growth (SEG) process. In a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention, memory cells may be arranged three-dimensionally on each chip region 10 of the semiconductor substrate 1.

[0030] Figure 2 This is a perspective view schematically illustrating a three-dimensional semiconductor device according to an embodiment of the present invention.

[0031] Reference Figure 2 A three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS. When viewed in a planar view, the cell array structure CS may overlap with the peripheral circuit structure PS. For example, as... Figure 2 As shown in the exemplary implementation, the cell array structure CS can be (e.g., on the third-party D3) directly disposed on the peripheral circuit structure.

[0032] In an exemplary embodiment, the peripheral circuit structure PS may include row and column decoders, page buffers, control circuitry, and peripheral logic circuitry. However, the exemplary embodiments of this invention are not limited thereto; the peripheral circuit structure PS may exclude one or more of these components, or may include additional components. The peripheral logic circuitry of the peripheral circuit structure PS may be integrated on a semiconductor substrate.

[0033] A cell array structure (CS) may include multiple memory cells arranged in a three-dimensional manner. A cell array structure (CS) may include one or more clusters (mats), each cluster comprising multiple memory blocks BLK0-BLKn. Each of the memory blocks BLK0-BLKn may include multiple memory cells arranged in a three-dimensional manner.

[0034] For example, in an exemplary embodiment, each of the memory blocks BLK0-BLKn may include a plurality of electrode structures, a vertical pattern perpendicularly intersecting the electrode structures, and a memory element interposed between the sidewalls of the electrode structures and the vertical pattern. Each electrode structure may be formed of at least one conductive material such as doped silicon or a metallic material, or may include at least one conductive material such as doped silicon or a metallic material, and may be provided in the form of a line or a plate. However, exemplary embodiments of the inventive concept are not limited thereto.

[0035] The peripheral circuit structure PS and the cell array structure CS can be sequentially formed on the same wafer. However, in other exemplary embodiments, a first wafer having the peripheral circuit structure PS and a second wafer having the cell array structure CS can be prepared separately, and then the first wafer can be bonded to the second wafer to form a semiconductor device.

[0036] Figure 3 This is a schematic top view illustrating an exemplary embodiment of a three-dimensional semiconductor memory device according to the concept of the present invention.

[0037] Reference Figure 1 and Figure 3 ,refer to Figure 2 The described peripheral circuit structure PS and cell array structure CS can be disposed on each chip region 10 of the semiconductor substrate 1.

[0038] In each chip region 10, the peripheral circuit structure PS (e.g., see...) Figure 2 It can be disposed on semiconductor substrate 1. For example... Figure 3 As shown in the exemplary embodiments, the peripheral circuit structure PS may include a row decoder (ROW DEC) and a column decoder (COLDEC), a page buffer (PBR), and a control circuit (CTRL). However, the exemplary embodiments of the present invention are not limited thereto.

[0039] The cell array structure CS (for example, see Figure 2 Multiple cluster region MTRs can be set in each chip region 10. Multiple cluster region MTRs can be arranged in a first direction D1 and a second direction D2. Multiple cluster MTRs can be configured to interact with the peripheral circuit structure PS (e.g., see...). Figure 2 Overlap. For example, multiple cluster MTRs can be set on the peripheral circuit structure PS on a third-direction D3. Figure 3As shown in the exemplary embodiments, components of the peripheral circuit structure PS, such as the row decoder ROW DEC and column decoder COL DEC, the page buffer PBR, and the control circuit CTRL, can be disposed below each cluster region MTR. However, in other exemplary embodiments, multiple cluster regions MTRs can share a single peripheral circuit structure. According to the exemplary embodiments conceived in this invention, the peripheral logic circuits constituting the peripheral circuit structure PS can be freely disposed below the cluster region MTR (e.g., on the third-direction D3).

[0040] Figure 4A and Figure 4B This is a top view, each of which schematically illustrates a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the concept of the present invention. Figure 5 yes Figure 4A A magnified view of the region "Q".

[0041] Reference Figure 4A and Figure 5 The cell array structure CS may include multiple horizontal patterns 100a and 100b. The horizontal patterns 100a and 100b can be set in relation to... Figure 3 The cluster region MTR corresponds to each region. For example, the memory structure MS on each of the horizontal patterns 100a and 100b can each correspond to a single cluster region MTR. Alternatively, a pair of first horizontal patterns 100a and their memory structures MS adjacent to each other in the second direction D2 can together constitute a first cluster region MTR, and a pair of second horizontal patterns 100b and their memory structures MS adjacent to each other in the second direction D2 can together constitute a second cluster region MTR. In an exemplary embodiment, the first horizontal patterns 100a share Figure 2 The peripheral circuit structure of the second horizontal pattern 100b can share another peripheral circuit structure.

[0042] Multiple horizontal patterns 100a and 100b may be spaced apart from each other in a first direction D1 and / or a second direction D2. In the following text, the region including horizontal patterns 100a and 100b will be referred to as the cluster region MTR, and the region between the cluster regions MTR will be referred to as the dividing region DV.

[0043] In an exemplary embodiment, a chip region 10 may include four or more cluster regions MTR. For example, a chip region 10 may include eight cluster regions MTR. Figure 4B As shown in the exemplary embodiment, a chip region 10 may include four cluster regions MTR. In this exemplary embodiment, as Figure 4B As shown, for reference Figure 1The described scribing region 20 can be formed in the region corresponding to the edge region of the chip, and therefore, with Figure 4A Due to differences in structure, some structures can be removed near the edge regions of the chip. The following description will refer to... Figure 4A Examples.

[0044] Separate source structures SC can be set on each of horizontal patterns 100a and 100b. For example, as Figure 6-7 As shown in the exemplary implementation, separate source structures SC can be (e.g., on third-direction D3) directly disposed on horizontal pattern 110a. The source structure SC can be part of a memory structure, which will be described below. Each source structure SC may include a protruding pattern PP that protrudes from the cluster region MTR and extends into the partition region DV. The source structures SC can be separated from each other by a partition structure DIT disposed in the partition region DV and interposed between the source structures SC. For example, the protruding pattern PP of a source structure SC from an adjacent cluster region MTR may directly contact the opposite side of the partition structure DIT. An etch stop pattern ES can be provided in the partition region DV. The etch stop pattern ES can be (e.g., on third-direction D3) disposed below the partition structure DIT. Figure 4A As shown in the exemplary embodiment, the etch stop pattern ES may include a first sub-pattern ES1 extending in a first direction D1 and a second sub-pattern ES2 extending in a second direction D2. The first sub-pattern ES1 may extend along a first edge EG1 parallel to the first direction D1 of the horizontal patterns 100a and 100b, and the second sub-pattern ES2 may extend along a second edge EG2 parallel to the second direction D2 of the horizontal patterns 100a and 100b. In the exemplary embodiment, the etch stop pattern ES may be a grid pattern in which the first sub-pattern ES1 and the second sub-pattern ES2 are provided to intersect each other.

[0045] Figures 6 to 8 They are respectively along Figure 5 The sectional views taken from lines I-I', II-II', and III-III'. Figure 9A It is shown Figure 8 An enlarged sectional view of part of the "P". Figure 9B It is shown Figure 7 An enlarged sectional view of part of the "R". Refer to the following text. Figure 4A , Figures 5 to 8 , Figure 9A and Figure 9B A three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention will be described in more detail.

[0046] Reference Figure 4A , Figures 5 to 8 , Figure 9A and Figure 9B The peripheral circuit structure PS, including the peripheral logic circuit PTR, can be disposed on the semiconductor substrate 1, and the cell array structure CS can be disposed on the peripheral circuit structure PS. The peripheral circuit structure PS may include the peripheral logic circuit PTR integrated on the semiconductor substrate 1 and a lower interlayer insulating layer 50 provided to cover the peripheral logic circuit PTR.

[0047] In an exemplary embodiment, the semiconductor substrate 1 may be a silicon wafer, a silicon-germanium wafer, a germanium wafer, or a single-crystal epitaxial layer grown on a single-crystal silicon wafer.

[0048] As described above, the peripheral logic circuit PTR can be a row decoder and a column decoder, a page buffer, and control circuitry. The peripheral logic circuit PTR can include NMOS and PMOS transistors, low-voltage and high-voltage transistors, and resistors integrated on the semiconductor substrate 1. Peripheral circuit lines 33 can be electrically connected to the peripheral logic circuit PTR via peripheral contact plugs 31. For example, peripheral contact plugs 31 and peripheral circuit lines 33 can be connected to NMOS and PMOS transistors.

[0049] The lower interlayer insulating layer 50 may cover the peripheral logic circuit PTR, peripheral contact plugs 31, and peripheral circuit lines 33. In an exemplary embodiment, the lower interlayer insulating layer 50 may include multiple stacked insulating layers. For example, the lower interlayer insulating layer 50 may include at least one layer selected from silicon oxide layers, silicon nitride layers, silicon oxide nitride layers, and low-k dielectric layers.

[0050] The etch stop layer 60 and the intermediate interlayer insulating layer 65 can be sequentially stacked on the lower interlayer insulating layer 50. For example, as Figure 6 As shown in the exemplary embodiment, the bottom surface of the etch stop layer 60 can directly contact the top surface of the lower interlayer insulating layer 50. The bottom surface of the intermediate interlayer insulating layer 65 can directly contact the top surface of the etch stop layer 60. In the exemplary embodiment, the etch stop layer 60 may be formed of an insulating material having etch selectivity relative to the lower interlayer insulating layer 50, or may include an insulating material having etch selectivity relative to the lower interlayer insulating layer 50. For example, the etch stop layer 60 may include a silicon nitride layer or a silicon oxide nitride layer. However, the exemplary embodiments of the present invention are not limited thereto. In the exemplary embodiment, the intermediate interlayer insulating layer 65 may be formed of the same material as the lower interlayer insulating layer 50, or may include the same material as the lower interlayer insulating layer 50.

[0051] The cell array structure CS may include cluster regions MTRs respectively provided on horizontal patterns 100a and 100b, and partition regions DV provided between the cluster regions MTRs (e.g., in the first direction Dl). Each cluster region MTR may include an electrode structure ST and a vertical structure VS of a penetrating electrode structure ST. The electrode structure ST may include a cell array region CAR and a connecting region CNR, such as... Figure 5 As shown. For example, as Figure 5 As shown in the exemplary embodiment, the cell array region CAR and the connection region CNR may be spaced apart in the first direction D1. The connection region CNR may be adjacent to the division region DV in the first direction D1.

[0052] Horizontal patterns 100a and 100b can be disposed on the intermediate interlayer insulating layer 65. For example, as shown... Figure 6 As shown in the exemplary embodiment, horizontal patterns 100a and 100b can be (e.g., on the third direction D3) directly disposed on the intermediate interlayer insulating layer 65. In the exemplary embodiment, horizontal patterns 100a and 100b can be formed or comprise at least one semiconductor material such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or combinations thereof. Horizontal patterns 100a and 100b can have at least one of a single-crystal structure, an amorphous structure, and a polycrystalline structure. As an example, horizontal patterns 100a and 100b can be formed from a polycrystalline silicon layer doped with n-type impurities. Horizontal patterns 100a and 100b can also include a metal layer. Horizontal patterns 100a and 100b can be provided on the cell array region CAR and the connection region CNR. A first insulating penetration layer 105 can be (e.g., on the first direction D1) provided in the partition region DV between horizontal patterns 100a and 100b. In an exemplary embodiment, the first insulating penetration layer 105 may be formed of or include silicon oxide.

[0053] Each electrode structure ST may include an insulating layer ILD and an electrode EL alternately stacked in a third direction D3 (e.g., a vertical direction) perpendicular to the first direction D1 and the second direction D2. In each electrode structure ST, the electrode EL may have a stepped structure in the edge region of the cluster region MTR (e.g., in the connection region CNR).

[0054] Each electrode EL of the electrode structure ST may have a length that decreases with increasing distance from the horizontal pattern 100a or 100b (e.g., a length extending toward the dividing region DV in the first direction D1). Each electrode EL may have a pad portion located at the end closest to the dividing region DV, and the pad portion of each electrode EL may be exposed by another electrode located directly thereon with a reduced length (e.g., a reduced length in the first direction D1). The pad portion of the electrode EL may be located at different positions in the horizontal and vertical directions. In an exemplary embodiment, the electrode EL may be formed of or include at least one conductive material such as a doped semiconductor material, a metal silicide, a metallic material, a metal nitride, etc. The insulating layer ILD may be formed of or include silicon oxide. However, exemplary embodiments of the inventive concept are not limited thereto.

[0055] A vertical structure VS can be provided to penetrate the electrode structure ST in each cluster region MTR and can be connected to horizontal patterns 100a and 100b. When viewed in plan view, the vertical structure VS can be arranged in a specific direction or in a zigzag pattern. For example, the vertical structure VS can extend in a third direction D3 to the horizontal patterns 100a, 100b and can penetrate electrodes extending in a first direction D1 of the electrode structure ST. The vertical structure VS can include semiconductor materials such as silicon (Si), germanium (Ge), or combinations thereof. In an exemplary embodiment, the vertical structure VS can be formed of or include doped semiconductor materials or intrinsic semiconductor materials. A vertical structure VS including semiconductor materials can be used as a channel region of transistors constituting a NAND cell string. A gap-filling pattern VI can be provided to fill the internal space of the vertical structure VS. The gap-filling pattern VI can be formed of, for example, silicon oxide or include, for example, silicon oxide. Contact pads 128 can be disposed on or in the upper portion of the vertical structure VS. Contact pads 128 can be formed of, for example, doped polysilicon or include, for example, doped polysilicon.

[0056] The source structure SC can (e.g., on a third-party D3) be provided between the electrode structure ST and the horizontal patterns 100a and 100b. The source structure SC may include a first power supply pattern SCP1 and a second power supply pattern SCP2. For example... Figure 6 As shown in the exemplary embodiment, the bottom surface of the second conductive power pattern SCP2 may contact the top surfaces of the horizontal patterns 100a and 100b. The bottom surface of the first conductive power pattern SCP1 may contact the top surface of the second conductive power pattern SCP2.

[0057] In an exemplary embodiment, the first conductive power pattern SCP1 and the second conductive power pattern SCP2 may be formed of or comprise a doped semiconductor material, which is doped with a dopant different from the dopant in the semiconductor substrate 1, such as phosphorus (P) or arsenic (As), and thus has a second conductivity type different from that of the semiconductor substrate 1. In an exemplary embodiment, the first conductive power pattern SCP1 and the second conductive power pattern SCP2 may be formed of an n-type doped polysilicon layer. In this exemplary embodiment, the concentration of the n-type dopant in the second conductive power pattern SCP2 may be higher than the concentration of the n-type dopant in the first conductive power pattern SCP1. The sidewalls of the second conductive power pattern SCP2 may be disposed on the horizontal patterns 100a and 100b, and the sidewalls of the first conductive power pattern SCP1 may be in direct contact with the sidewalls of the partitioned structure, as will be described below.

[0058] The second conductive pattern SCP2 can directly contact portions of the sidewalls of the vertical structure VS. For example, as Figure 9A and Figure 9B As shown in the exemplary embodiment, the second conductive power pattern SCP2 may include a sidewall portion SP that contacts and surrounds a portion of the sidewall of the vertical structure VS. For example, as Figure 9A As shown in the exemplary embodiment, the sidewall portion SP may include a lateral end extending in the third direction D3, which directly contacts the outer wall surface of the vertical structure VS. The second power conduction pattern SCP2 may also include a horizontal portion HP, which may extend in the second direction D2 and (e.g., in the third direction D3) be provided below the electrode structure ST. In the second power conduction pattern SCP2, the top surface of the horizontal portion HP may contact the bottom surface of the first power conduction pattern SCP1. The sidewall portion SP of the second power conduction pattern SCP2 may have a width greater than the width of the horizontal portion HP (e.g., the length in the third direction D3) and may extend to cover portions of the sidewalls of the first power conduction pattern SCP1 (e.g., the sidewalls extending in the third direction D3) and portions of the sidewalls of the horizontal patterns 100a and 100b (e.g., the sidewalls extending in the third direction D3). At least one of the electrodes EL adjacent to the source structure SC (e.g., adjacent on the third direction D3) can be used as an erase control gate electrode, and an electrode directly disposed on the erase control gate electrode (e.g., disposed on the third direction D3 directly above the insulating layer ILD on the erase control gate electrode) can be used as a ground selection gate electrode.

[0059] A protruding pattern PP (e.g., on the first direction D1) protrudes from the source structure SC into the partition region DV. In an exemplary embodiment, the protruding pattern PP may be a portion of the first conductive power pattern SCP1 extending within the partition region DV. In an exemplary embodiment, the second conductive power pattern SCP2 may not extend into the partition region DV. For example, the second conductive power pattern SCP2 may terminate at or adjacent to the edge of a cluster region MTR adjacent to the partition region DV. A residual pattern RM may (e.g., on the third direction D3) be provided between the protruding pattern PP and the first insulating penetration layer 105. For example, as... Figure 9B As shown in the exemplary embodiment, the residual pattern RM may include first to third residual sacrificial patterns 52, 54, and 56. The first to third residual sacrificial patterns 52, 54, and 56 may be directly stacked on top of each other (e.g., on the third-direction D3). The first residual sacrificial pattern 52 may be directly disposed on the first insulating penetration layer 105 (e.g., on the third-direction D3). The protruding pattern PP may be directly disposed on the third residual sacrificial pattern 56 (e.g., on the third-direction D3). The second residual sacrificial pattern 54 may be disposed between the first residual sacrificial pattern 52 and the third residual sacrificial pattern 56 (e.g., on the third-direction D3). In the exemplary embodiment, the first residual sacrificial pattern 52 and the third residual sacrificial pattern 56 may be formed of silicon oxide or include silicon oxide. The second residual sacrificial pattern 54 may be formed of silicon nitride or polysilicon, or include silicon nitride or polysilicon. The residual pattern RM may be disposed at the same height as the second conductive power pattern SCP2 in the cluster region MTR (e.g., the distance from the substrate 1 on the third-direction D3). The top surface of the residual pattern RM (e.g., the top surface of the third residual sacrificial pattern 56) may contact the bottom surface of the first conductive pattern SCP1.

[0060] The second insulating penetration layer 107 can be provided in the region between adjacent source structures SC. For example, as Figure 6 As shown in the exemplary embodiment, the second insulating penetration layer 107 may be formed in the partition region DV between source structures SC directly in adjacent cluster regions MTR (e.g., in the first direction D1). Figure 6 As shown in the exemplary embodiment, the second insulating penetration layer 107 may have the same width as the adjacent source structure SC (e.g., length in the third direction D3). In the exemplary embodiment, the second insulating penetration layer 107 may be formed of, for example, silicon oxide, or include, for example, silicon oxide. The second insulating penetration layer 107 may fill areas in which no protruding pattern PP protruding from the source structure SC to the dividing region DV is provided.

[0061] like Figure 9AAs shown in the exemplary embodiment, a data storage pattern DSP can be provided between the electrode structure ST and the vertical structure VS. The data storage pattern DSP can extend in a third direction D3 to surround the sidewalls (e.g., outer sidewalls) of each vertical structure VS. For example, in the exemplary embodiment, the data storage pattern DSP can be a tubular pattern with an open top and bottom. The bottom surface of the data storage pattern DSP can be in direct contact with the sidewall portion SP of the second conductive power pattern SCP2. For example, as... Figure 9A As shown in the exemplary embodiment, the bottom surface of the data storage pattern DSP can directly contact the top edge of the sidewall portion SP (e.g., in the third direction D3). In the exemplary embodiment, the lower portion of the data storage pattern DSP can be (e.g., in the second direction D2) positioned between the vertical structure VS and the first conductive power pattern SCP1.

[0062] The data storage pattern DSP can consist of one or more layers. In an exemplary embodiment, the data storage pattern DSP can be part of a data storage layer. For example, such as... Figure 9A As shown in the exemplary embodiments, the data storage pattern DSP may include a tunnel insulating layer (TIL), a charge storage layer (CIL), and a barrier insulating layer (BLK), which are sequentially stacked on the sidewalls of a vertical structure (VS) to serve as a data storage layer for a NAND flash memory device. In an exemplary embodiment, the charge storage layer (CIL) may be a trap insulating layer, a floating gate electrode, or an insulating layer with conductive nanodots. In an exemplary embodiment, the charge storage layer (CIL) may include at least one of a silicon nitride layer, a silicon oxide nitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, or a stacked trap layer. The tunnel insulating layer (TIL) may be formed of at least one material having a band gap larger than that of the charge storage layer (CIL), and the barrier insulating layer (BLK) may be formed of a high-k dielectric material (e.g., aluminum oxide, hafnium oxide, etc.).

[0063] According to an exemplary embodiment of the present invention, a dummy data storage pattern DSPa can be disposed within horizontal patterns 100a and 100b, and can be vertically spaced from the data storage pattern DSP, with sidewall portions SP (e.g., on the third direction D3) located between them. The dummy data storage pattern DSPa can have a substantially "U"-shaped cross-section. The dummy data storage pattern DSPa can be disposed between the bottom surface of the vertical structure VS and the horizontal patterns 100a and 100b. For example, as Figure 9AAs shown in the exemplary embodiment, the top surface of the dummy data storage pattern DSPa can be in direct contact with the bottom edge of the sidewall portion SP of the second conductive power pattern SCP2. Horizontal patterns 100a and 100b can surround the dummy storage pattern DSPa in the second direction D2 and the third direction D3. The dummy data storage pattern DSPa can have a layer structure substantially the same as the data storage pattern DSP. For example, the dummy data storage pattern DSPa may include a tunnel insulating layer TILa, a charge storage layer CILa, and a barrier insulating layer BLKa stacked sequentially.

[0064] In an exemplary embodiment, the three-dimensional semiconductor memory device may be a three-dimensional NAND flash memory device and may include NAND cell strings integrated on horizontal patterns 100a and 100b. In other words, the electrode structure ST, the vertical structure VS, and the data storage pattern DSP may constitute a memory cell arranged three-dimensionally on horizontal patterns 100a and 100b.

[0065] The upper interlayer insulating layer 150 may cover the end of the electrode EL that is configured to form a stepped structure, and may cover the horizontal patterns 100a and 100b, the second insulating penetrating layer 107, and the protruding pattern PP. The first interlayer insulating layer 160 may be disposed on the upper interlayer insulating layer 150 to cover the top surface of the vertical structure VS.

[0066] like Figure 8 and Figure 9A As shown, the common source electrode CSP can penetrate the electrode structure ST in the third direction D3, can extend in the first direction D1, and can be connected to the horizontal patterns 100a and 100b. The common source electrode CSP can penetrate the entire source structure SC in the third direction D3, and then can extend to the horizontal patterns 100a and 100b. A first insulating spacer SS1 can be (e.g., in the second direction D2) inserted between the common source electrode CSP and the electrode structure ST. In an exemplary embodiment, the first insulating spacer SS1 can be formed of or comprise silicon oxide.

[0067] In the partitioned region DV, the partition structure DIT can be provided between the protruding patterns PP of adjacent source structures SC. In an exemplary embodiment, the partition structure DIT can have a strip or rectangular shape. Figure 5 As shown, the width W1 of the dividing structure DIT in the second direction D2 can be greater than the width W2 of the protruding pattern PP. In an exemplary embodiment, the dividing structure DIT can be formed of at least one of silicon oxide, silicon nitride, or silicon nitride, or include at least one of silicon oxide, silicon nitride, or silicon nitride. Figure 4AAs shown, the dividing structure DIT can be arranged adjacent to the four edges of each of the horizontal patterns 100a and 100b. However, exemplary embodiments of the present invention are not limited thereto.

[0068] like Figure 9B As shown, the width of the partition structure DIT (e.g., the distance between the lateral side surfaces in the first direction D1) can vary depending on the layer in contact with the partition structure DIT. For example, the partition structure DIT may have a first width t1 at the height of the upper interlayer insulating layer 150 and a second width t2 at the height of the first conductive power pattern SCP1, the second width t2 being smaller than the first width t1. Furthermore, the partition structure DIT may have a third width t3 at the height of the etch stop pattern ES, the third width t3 being smaller than the second width t2. In an exemplary embodiment, the partition structure DIT may have a first stepped structure TS1 at or near the interface between the upper interlayer insulating layer 150 and the first conductive power pattern SCP1, and may have a second stepped structure TS2 at or near the interface between the intermediate interlayer insulating layer 65 and the etch stop pattern ES.

[0069] The etch stop pattern ES, connected to the lower part of the partition structure DIT, can be set between the peripheral circuit structure PS and the source structure SC. For example... Figure 7 and Figure 9B As shown in the exemplary embodiments, the top surface of the etch stop pattern ES may be located at a lower height than the bottom surfaces of the horizontal patterns 100a and 100b. For example, the etch stop pattern ES may be disposed in an intermediate interlayer insulating layer 65, and the intermediate interlayer insulating layer 65 may cover the top and side surfaces of the etch stop pattern ES. In the exemplary embodiments, the etch stop pattern ES may be formed of, or include, a material selected to have etch selectivity relative to the insulating layer ILD and the sacrificial layer, as will be described below. For example, the etch stop pattern ES may be formed of, or include, a material having etch selectivity relative to silicon oxide and silicon nitride. The etch stop pattern ES may be formed of a non-metallic element (e.g., a substantially metal-free material). As an example, the etch stop pattern ES may include a semiconductor material such as polycrystalline silicon. The etch stop pattern ES may not be electrically connected to adjacent interconnects and contacts and may be in an electrically isolated state.

[0070] like Figure 5 As shown in the exemplary embodiment, the width W4 of the etch stop pattern ES in the first direction D1 can be greater than the width W3 of the dividing structure DIT in the first direction D1. For example... Figure 4AAs shown in the exemplary embodiment, the etch stop pattern ES may include a first sub-pattern ES1 extending in a first direction D1 and a second sub-pattern ES2 extending in a second direction D2. In the exemplary embodiment, the etch stop pattern ES may be thinner than the horizontal patterns 100a and 100b (e.g., in length in the first direction D1). In the exemplary embodiment, the thickness of the etch stop pattern ES may be approximately 1 / 6 to 1 / 2 of the thickness of the horizontal patterns 100a and 100b. For example, in the exemplary embodiment, the thickness of the etch stop pattern ES may be from approximately... up to approximately Within a certain range. In another exemplary embodiment, the thickness of the etch stop pattern ES can be from approximately up to approximately Within a certain range. In an exemplary embodiment, the thickness of the horizontal patterns 100a and 100b can range from approximately up to approximately Within the range. In another exemplary embodiment, the thickness of the horizontal patterns 100a and 100b can be from approximately To about Within the range. The etch stop pattern ES can be thicker than the etch stop layer 60. In an exemplary embodiment, the thickness of the etch stop pattern ES can be approximately 10 to 90 times the thickness of the etch stop layer 60.

[0071] The second interlayer insulation layer 165, the third interlayer insulation layer 170, and the fourth interlayer insulation layer 175 can be sequentially stacked on the first interlayer insulation layer 160. For example... Figure 6 As shown in the exemplary embodiment, the cell contact plug PLG can extend vertically (e.g., in the third direction D3) and can penetrate the first and second interlayer insulating layers 160 and 165 and the upper interlayer insulating layer 150, and can be connected to the ends of the electrode EL, respectively. The bit line BL can be disposed on the second interlayer insulating layer 165 to intersect the electrode structure ST and extend in the second direction D2. The bit line BL can be electrically connected to the vertical structure VS via the bit line contact plug BPLG extending through the first and second interlayer insulating layers 160 and 165. The third interlayer insulating layer 170 can cover the bit line BL. The upper interconnect TW can be disposed on the third interlayer insulating layer 170. For example, as... Figure 6 As shown in the exemplary embodiment, the bottom of the upper interconnect TW can directly contact the top of the third interlayer insulating layer 170. The upper interconnect TW can be connected to the bit line BL or the connection line CL via a through-hole plug. In the exemplary embodiment, at least one of the first to fourth interlayer insulating layers 160, 165, 170 and 175 can be formed of or include silicon oxide.

[0072] The through-hole region TVS includes multiple through-hole plugs TPLG. The through-hole plugs TPLG can extend vertically (e.g., in the third direction D3) to penetrate the first interlayer insulation layer 160 and the second interlayer insulation layer 165, the upper interlayer insulation layer 150, the first insulating through-hole layer 105 and the second insulating through-hole layer 107, the intermediate interlayer insulation layer 65, and the etch stop layer 60, and can be connected to the peripheral circuitry 33. Each through-hole plug TPLG can be surrounded by a second insulating spacer SS2, which is formed of an insulating material. The through-hole plugs TPLG can be connected to the cell contact plugs PLG via connecting lines CL on the second interlayer insulation layer 165, which can extend from the cluster region MTR to the through-hole plug TPLG (e.g., in the first direction D1). The through-hole plugs TPLG can electrically connect the electrodes EL of the electrode structure ST to the peripheral circuitry 33. The through-hole plug TPLG, cell contact plug PLG, and bit line contact plug BPLG can be formed of or include at least one metallic material (e.g., tungsten, aluminum, etc.). The through-hole plug TPLG can be (e.g., in the first direction D1) horizontally spaced from the etch stop pattern ES and the partition structure DIT. In an exemplary embodiment, the bottom surface of the partition structure DIT can be positioned at a height higher than the bottom surface of the through-hole plug TPLG. The bottom surface of the vertical structure VS can be positioned at a height higher than the bottom surface of the partition structure DIT. In an exemplary embodiment, the bottom surface of the partition structure DIT can be placed between the bottom surface of the through-hole plug TPLG and the bottom surface of the vertical structure VS.

[0073] like Figure 5 As shown in the exemplary embodiment, the through-hole region TVS can be disposed in the portion of the partitioned region DV in which the etch stop pattern ES and the source structure SC are not provided, such as Figure 5 As shown. However, exemplary embodiments of the present invention are not limited thereto. For example, in some exemplary embodiments, the through-plug region TVS can provide a connection region CNR or a cell array region CAR in the cluster region MTR.

[0074] Figures 10 to 12 This is a top view, each schematically illustrating a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention. For the sake of brevity, previously described elements may be identified by the same reference numerals without repetition of their descriptions.

[0075] like Figures 10 to 12 As shown, the etch stop pattern ES can be provided in different shapes. Figure 10An island-shaped etch stop pattern ES is shown, wherein all first sub-patterns ES1 and second sub-patterns ES2 extending along a first direction D1 and a second direction D2 are spaced apart from each other. Alternatively, Figure 11 and Figure 12 Two structures for the etch stop pattern ES are shown, where one of the first sub-pattern ES1 and the second sub-pattern ES2 has a linear shape. For example, in Figure 11 In the exemplary embodiment shown, the first sub-pattern ES1 has a linear shape and extends continuously in the first direction D1. The second sub-pattern ES2 has an island-like structure in which each second sub-pattern (e.g., in the first direction D1 and / or the second direction D2) is separated from each other. Figure 12 In an exemplary embodiment, the second sub-pattern ES2 has a linear shape and extends continuously in the second direction D2, while the first sub-pattern ES1 has an island-like structure in which each sub-pattern (e.g., in the first direction D1) is separated from the others. However, the exemplary embodiments of the inventive concept are not limited to these example structures of the etch stop pattern ES, and the structure of the etch stop pattern ES can be varied depending on the arrangement and shape of the dividing structure DIT.

[0076] Figure 13 and Figure 14 It is a sectional view, which is shown along... Figure 5 Lines I-I' and II-II' are cut off to illustrate a three-dimensional semiconductor memory device according to an exemplary embodiment of the concept of the present invention. For the sake of brevity, the previously described elements may be identified by the same reference numerals without repeating their description.

[0077] Reference Figure 13 and Figure 14 The etch stop pattern ES, connected to the lower part of the partition structure DIT, can be set between the peripheral circuit structure PS and the source structure SC. Figure 13 and Figure 14 In the exemplary embodiment shown, the etch stop pattern ES can be disposed at the same height as the horizontal patterns 100a and 100b. For example, the etch stop pattern ES can have a top surface at the same height as the top surfaces of the horizontal patterns 100a and 100b, and a bottom surface at the same height as the bottom surfaces of the horizontal patterns 100a and 100b. This is in contrast to the embodiment where the etch stop pattern ES is directly disposed on the top surface of the etch stop layer 60 and the intermediate interlayer insulating layer 65 covers the top and side surfaces of the etch stop pattern ES. Figure 6Compared to the exemplary embodiment, the bottom surface of the etch stop pattern ES can be (e.g., on the third direction D3) disposed on the top surface of the intermediate interlayer insulating layer 65. In the exemplary embodiment, the etch stop pattern ES and the horizontal patterns 100a and 100b can be formed simultaneously using the same material and can be patterned to form patterns that are separate from each other. In the exemplary embodiment, the etch stop pattern ES can have the same thickness (e.g., length on the third direction D3) as the horizontal patterns 100a and 100b. For example, the thickness of the etch stop pattern ES and the horizontal patterns 100a and 100b can be from approximately up to approximately Within the range.

[0078] Figure 15 , Figure 18 , Figure 21 and Figure 24 This is a cross-sectional view of an exemplary embodiment of the present invention, along... Figure 5 The line I-I' is cut off to illustrate a method for manufacturing three-dimensional semiconductor memory devices. Figure 16 , Figure 19 , Figure 22 and Figure 25 It is along Figure 15 The sectional view taken from line II-II'. Figure 17 , Figure 20 , Figure 23 and Figure 26 It is along Figure 5 The sectional view taken from line III-III'.

[0079] Reference Figures 15 to 17 The peripheral circuit structure PS can be formed on the semiconductor substrate 1. The semiconductor substrate 1 may include a chip region and a scribing region, as previously referenced. Figure 1 The semiconductor substrate 1 may be a silicon wafer. The formation of the peripheral circuit structure PS may include: forming a peripheral logic circuit PTR on the semiconductor substrate 1; forming peripheral interconnect structures, such as peripheral contact plugs 31 and peripheral circuit lines 33 connected to the peripheral logic circuit PTR; and forming a lower interlayer insulating layer 50. In an exemplary embodiment, a first wafer including the peripheral circuit structure PS may be prepared separately, and a cell array structure CS, which will be described below, may be formed on a second wafer. A bonding process may then be performed to bond the first wafer and the second wafer to each other to form a semiconductor device.

[0080] Row and column decoders, page buffers, and control circuitry used as peripheral logic circuits (PTRs) can be formed on each chip region of the semiconductor substrate 1. In an exemplary embodiment, the formation of the peripheral logic circuit (PTR) may include: forming a device isolation layer 11 in the semiconductor substrate 1 to define an active region; and then forming a peripheral gate electrode on the semiconductor substrate 1.

[0081] The formation of the peripheral interconnect structure may include: forming a peripheral contact plug 31 to penetrate a portion of the lower interlayer insulating layer 50; and forming peripheral circuit lines 33 connected to the peripheral contact plug 31. After forming the peripheral logic circuit PTR and the peripheral interconnect structures 31 and 33, the lower interlayer insulating layer 50 may be formed to cover the entire top surface of the semiconductor substrate 1 (e.g., on the third direction D3). The lower interlayer insulating layer 50 may include a single insulating layer or multiple stacked insulating layers. In an exemplary embodiment, the lower interlayer insulating layer 50 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, and a low-k dielectric layer.

[0082] An etch stop layer 60 and an intermediate interlayer insulating layer 65 may be sequentially formed on the lower interlayer insulating layer 50. For example, the etch stop layer 60 may be formed directly on the lower interlayer insulating layer (e.g., on the third-direction D3). The intermediate interlayer insulating layer 65 may be formed directly on the etch stop layer 60 (e.g., on the third-direction D3). In an exemplary embodiment, the etch stop layer 60 may be formed of, or include, an insulating material having etch selectivity relative to the lower interlayer insulating layer 50. For example, the etch stop layer 60 may include a silicon nitride layer or a silicon oxide nitride layer. In an exemplary embodiment, the intermediate interlayer insulating layer 65 may be formed of, or include, the same material as the lower interlayer insulating layer 50.

[0083] An etch stop pattern ES can be formed on the etch stop layer 60. For example, the etch stop pattern ES can be formed by forming a polysilicon layer directly on the top surface of the etch stop layer 60 and patterning the polysilicon layer. Subsequently, an intermediate interlayer insulating layer 65 can be formed on the etch stop layer 60, on which the etch stop pattern ES is provided. In an alternative embodiment, the etch stop layer 60 can be formed simultaneously with a horizontal pattern, which will be described below, and then patterned to form patterns that are separate from each other.

[0084] After forming the peripheral circuit structure PS, horizontal patterns 100a and 100b can be formed to cover the peripheral circuit structure PS (e.g., on the third-direction D3). In an exemplary embodiment, the horizontal patterns 100a and 100b can be formed by forming a semiconductor layer on the intermediate interlayer insulating layer 65 and patterning the semiconductor layer. In an exemplary embodiment, the horizontal patterns 100a and 100b can be formed by depositing a polysilicon layer to cover the entire top surface of the semiconductor substrate 1 (e.g., on the third-direction D3). In an exemplary embodiment, during the deposition of the polysilicon layer, the polysilicon layer can be doped with impurities of a first conductivity type.

[0085] In an exemplary embodiment, horizontal patterns 100a and 100b may be formed to be spaced apart from each other in the first direction D1 and / or the second direction D2, such as Figure 4A As shown. The first insulating penetration layer 105 can be formed to fill the region between horizontal patterns 100a and 100b. In an exemplary embodiment, the first insulating penetration layer 105 can be formed of or include silicon oxide. Thereafter, a planarization process can be performed to expose the top surfaces of the horizontal patterns 100a and 100b. In an exemplary embodiment, the horizontal patterns 100a and 100b can be formed in a cluster region MTR, and the first insulating penetration layer 105 can be formed in a partition region DV between the cluster regions MTR (e.g., cluster regions MTR in the first direction D1 and / or the second direction D2).

[0086] The first sacrificial pattern 51 and the second sacrificial pattern 53 can be sequentially formed on the horizontal patterns 100a and 100b, and the opening OP1 can be formed to penetrate the second sacrificial pattern 53. For example... Figure 17 As shown in the exemplary embodiment, opening OP1 may expose a first sacrificial pattern 51 (e.g., the top surface of the first sacrificial pattern). Subsequently, a third sacrificial pattern 55 may be formed to fill opening OP1 and cover the second sacrificial pattern 53. In the exemplary embodiment, the first sacrificial pattern 51 and the third sacrificial pattern 55 may be formed of or comprise silicon oxide. The second sacrificial pattern 53 may be formed of, for example, silicon nitride or polysilicon, or comprise, for example, silicon nitride or polysilicon.

[0087] The initial power conduction pattern PSC can be formed on the third sacrificial pattern 55. In the cluster region MTR, the initial power conduction pattern PSC can be formed to cover the horizontal patterns 100a and 100b. The initial power conduction pattern PSC can extend to the dividing region DV to form a protruding pattern PP. In an exemplary embodiment, the initial power conduction patterns PSC in adjacent cluster regions MTR can be connected to each other via protruding patterns PP extending to the dividing region DV. The first to third sacrificial patterns 51, 53, and 55 can also be patterned using a patterning process for forming the initial power conduction pattern PSC; therefore, the first to third sacrificial patterns 51, 53, and 55 can have substantially the same planar shape as the initial power conduction pattern PSC.

[0088] In an exemplary embodiment, the initial power conduction pattern (PSC) can cover the top surface of the edge of the semiconductor substrate 1 at the edge of the wafer. In other words, the initial power conduction pattern (PSC) can be in direct contact with the semiconductor substrate 1 at the edge of the wafer.

[0089] The second insulating penetration layer 107 may be formed on the first insulating penetration layer 105 to fill the areas in which the initial conductive power pattern PSC and the first to third sacrificial patterns 51, 53 and 55 are not formed. The second insulating penetration layer 107 may be formed of, for example, silicon oxide or include, for example, silicon oxide.

[0090] Reference Figures 18 to 20 A mold structure 120 can be formed on an initial conductive power pattern PSC. The mold structure 120 can be formed on horizontal patterns 100a and 100b, respectively. Each mold structure 120 may include (e.g., on a third direction D3) alternately and repeatedly stacked sacrificial layers SL and insulating layers ILD. In an exemplary embodiment, the sacrificial layer SL and insulating layer ILD can be formed using a thermochemical vapor deposition (thermal CVD) process, a plasma-enhanced chemical vapor deposition (PE-CVD) process, or an atomic layer deposition (ALD) process. The sacrificial layer SL can be formed of a material that can be etched with etch selectivity relative to the insulating layer ILD. For example, the sacrificial layer SL can be formed of a material that can be selectively etched without over-etching the insulating layer ILD. In an exemplary embodiment, the sacrificial layer SL and insulating layer ILD can have high etch selectivity in a wet etching process using a chemical solution and low etch selectivity in a dry etching process using an etching gas. In an exemplary embodiment, the sacrificial layer SL and insulating layer ILD can be formed of different insulating materials that have etch selectivity relative to each other. For example, the sacrificial layer SL can be formed from a silicon nitride layer, and the insulating layer ILD can be formed from a silicon oxide layer.

[0091] Forming the mold structure 120 may include performing a trimming process. In an exemplary embodiment, the trimming process may include the steps of: forming a mask pattern on the layered structure; etching a portion of the layered structure; reducing the horizontal region of the mask pattern; and removing the mask pattern. Prior to the step of removing the mask pattern, the steps of etching a portion of the layered structure and reducing the horizontal region of the mask pattern may be repeated several times. As a result of the trimming process, each mold structure 120 may have a stepped structure in the edge portion of each cluster region MTR.

[0092] The upper interlayer insulating layer 150 can be formed to fill the regions between the mold structures 120. The formation of the upper interlayer insulating layer 150 may include depositing a thick insulating layer to cover the mold structure 120 and performing a planarization process on the insulating layer. The upper interlayer insulating layer 150 can be formed of an insulating material that has etch selectivity relative to the sacrificial layer SL.

[0093] Reference Figures 21 to 23 Multiple vertical structures VS can be formed to penetrate the mold structure 120. Forming the vertical structures VS may include forming (e.g., on a third direction D3) vertical holes VH penetrating the mold structure 120. For example, forming the vertical holes VH may include forming a hard mask pattern to cover the mold structure 120 and using the hard mask pattern as an etching mask to anisotropically etch the mold structure 120. In an exemplary embodiment, the anisotropic etching process on the mold structure 120 may be a plasma etching process, a reactive ion etching (RIE) process, an inductively coupled plasma reactive ion etching (ICP-RIE) process, or an ion beam etching (IBE) process.

[0094] In an exemplary embodiment of the invention, where an anisotropic etching process is performed using high-power plasma, the surfaces of horizontal patterns 100a and 100b exposed by the vertical aperture VH can be charged by positive charges generated by ions and / or free radicals in the plasma. Additionally, in an exemplary embodiment of the invention, during the fabrication of a three-dimensional semiconductor device, a semiconductor substrate 1 can be placed on a support of a semiconductor manufacturing apparatus, and a ground voltage from the support can be applied to the semiconductor substrate 1 during anisotropic etching to form the vertical aperture VH.

[0095] During anisotropic etching process using plasma, horizontal patterns 100a and 100b can be connected to each other via an initial conductive power pattern PSC including a protruding pattern PP, and can directly contact the top surface of the edge of the semiconductor substrate 1 at the edge of the wafer. Therefore, the positive charge that causes the surfaces of horizontal patterns 100a and 100b to become charged during the formation of the vertical hole VH can be released to the outside through the semiconductor substrate 1.

[0096] As described above, since a grounding voltage can be applied to the initial conductive power pattern PSC during the formation of the vertical hole VH, the problem of arc discharge caused by positive charges on the horizontal patterns 100a and 100b can be prevented.

[0097] Then, a vertical structure VS can be formed in the vertical hole VH. As described above, the vertical structure VS can be formed of at least one of a semiconductor material or a conductive material, or include at least one of a semiconductor material or a conductive material. In an exemplary embodiment, before forming the vertical structure VS, the data storage pattern DSP described with reference to FIG9 can be formed in the vertical hole VH.

[0098] The first interlayer insulating layer 160 can be formed to cover the vertical structure VS, and a dividing trench DH can be formed in the dividing region DV. The dividing trench DH can be formed to penetrate the first interlayer insulating layer 160 and the upper interlayer insulating layer 150, and divide the initial conductive power pattern PSC into first conductive power patterns SCP1 that are separated from each other in the dividing region DV. Furthermore, the dividing trench DH can be formed to expose the top surface of the etch stop pattern ES. In an exemplary embodiment, the dividing trench DH may not penetrate the etch stop pattern ES, and the etch stop pattern ES can prevent damage to the interconnects that may occur when the peripheral circuit line 33 is exposed by the dividing trench DH. Therefore, the etch stop pattern ES can prevent metal contamination problems caused by damaged interconnects.

[0099] Subsequently, the gate partition region GIR can be formed to extend from the cluster region MTR in the first direction D1 and penetrate the mold structure 120 vertically (e.g., in the third direction D3). In an exemplary embodiment, the gate partition region GIR can be formed by the same etching process as that used for partitioning the trench DH. However, exemplary embodiments of the inventive concept are not limited thereto. The gate partition region GIR can penetrate the first conductive power pattern SCP1 and can expose horizontal patterns 100a and 100b. At least a portion of the gate partition region GIR can expose the first to third sacrificial patterns 51, 53, and 55.

[0100] Reference Figures 24 to 26The first to third sacrificial patterns 51, 53, and 55 can be replaced with the second power conductive pattern SCP2. For example, the first to third sacrificial patterns 51, 53, and 55 can be removed, and the second power conductive pattern SCP2 can be formed in the regions where the first to third sacrificial patterns 51, 53, and 55 have been removed. The first to third sacrificial patterns 51, 53, and 55 can be selectively removed. For example, in an exemplary embodiment, the second sacrificial pattern 53 exposed by the partition region DV can be selectively removed, and subsequently the first sacrificial pattern 51 and the third sacrificial pattern 55 can be selectively removed together. The portions of the first to third sacrificial patterns 51, 53, and 55 located in regions relatively far from the gate partition region GIR can be retained in the partition region DV. In other words, a residual pattern RM including the first to third remaining sacrificial patterns 51, 53, and 55 can be formed in the partition region DV. During the removal of the first to third sacrificial patterns 51, 53, and 55, the sidewalls of the sacrificial layer SL and the insulating layer ILD can be covered with a protective layer.

[0101] Refer to the return Figure 5 Referring to Figure 9, a replacement process can be performed to replace the sacrificial layer SL of the mold structure 120 with the electrode EL. Thus, an electrode structure ST comprising electrodes EL vertically stacked on horizontal patterns 100a and 100b can be formed. For example, the sacrificial layer SL exposed by the dividing trench DH can be removed to form a gate region between the insulating layers ILD. In embodiments where the sacrificial layer SL is a silicon nitride layer and the insulating layer ILD is a silicon oxide layer, the removal of the sacrificial layer SL can be performed by an isotropic etching process using an etching solution comprising phosphoric acid.

[0102] Electrodes EL can then be formed in the gate region. Each electrode EL may include sequentially deposited barrier metal layers and metal layers. The electrode structure ST may have a stepped structure at the edge of each cluster region MTR.

[0103] The first insulating spacer SS1 and the common source electrode CSP can be formed in the gate partition region GIR, respectively. The common source electrode CSP can be connected to horizontal patterns 100a and 100b. In an exemplary embodiment, the common source electrode CSP can be formed of at least one compound selected from doped polysilicon, metal, or conductive metal nitride, or include said at least one compound. The second interlayer insulating layer 165 can be formed to cover the common source electrode CSP.

[0104] The through-hole plug TPLG can be formed to vertically (e.g., on the third direction D3) penetrate the first and second interlayer insulating layers 160 and 165, the upper interlayer insulating layer 150, the first and second insulating through-hole layers 105 and 107, the intermediate interlayer insulating layer 65, and the etch stop layer 60, and connect to the peripheral circuit line 33. In an exemplary embodiment, the second insulating spacer SS2 can be formed to cover the side surface of the through-hole, and the through-hole plug TPLG can then be formed.

[0105] The unit contact plug PLG can be formed to penetrate the first interlayer insulation layer 160, the second interlayer insulation layer 165, and the upper interlayer insulation layer 150 vertically (e.g., in the third direction D3) and be respectively connected to the end of the electrode EL. Additionally, the bit line contact plug BPLG can be formed to be electrically connected to the vertical structure VS.

[0106] The aforementioned bit lines BL and connecting lines CL can be formed on the second interlayer insulating layer 165. Thereafter, they can be cut or diced along the diced area 20 (e.g., see...). Figure 1 The semiconductor substrate 1 is cut, so that the three-dimensional semiconductor device formed on the semiconductor substrate 1 can be separated from multiple semiconductor chips.

[0107] Figure 27 It is a sectional view, which is along Figure 5 Line II-II' is cut off to illustrate a three-dimensional semiconductor memory device according to an exemplary embodiment of the concept of the present invention.

[0108] like Figure 27 As shown in the exemplary embodiment, the electrode structure may include a first electrode structure ST1 and a second electrode structure ST2 (e.g., on a third direction D3) on the first electrode structure ST1. The distance between the uppermost electrode EL of the first electrode structure ST1 and the lowermost electrode EL of the second electrode structure ST2 (e.g., the distance on the third direction D3) may be greater than the corresponding distance between the uppermost electrode EL and the lowermost electrode EL of the first electrode structure ST1.

[0109] The data storage pattern DSP and vertical structure VS provided for penetrating the first electrode structure ST1 and the second electrode structure ST2 may have a stepped structure TS3 near the interface between the first electrode structure ST1 and the second electrode structure ST2. For example, the data storage pattern DSP and vertical structure VS may be provided in a channel hole penetrating each of the first electrode structure ST1 and the second electrode structure ST2. In an exemplary embodiment, separate patterning processes may be performed on the first electrode structure ST1 and the second electrode structure ST2 to form a channel hole in each of the first electrode structure ST1 and the second electrode structure ST2. The stepped structure TS3 may be the result of performing patterning processes on the first electrode structure ST1 and the second electrode structure ST2 respectively.

[0110] According to an exemplary embodiment of the present invention, during a process using high-frequency power, a horizontal pattern comprising multiple cluster regions can be grounded through a source structure. Therefore, when performing a process using high-frequency power to fabricate a three-dimensional semiconductor memory device, arcing problems caused by positive charges in the horizontal pattern can be prevented.

[0111] According to exemplary embodiments of the present invention, damage to interconnects that may occur when peripheral circuit lines are exposed during the separation of horizontal patterns can be prevented, and metal contamination problems caused by damaged interconnects can be prevented.

[0112] Although exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device, comprising: horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction; memory structures disposed on the horizontal patterns, the memory structures including source structures and electrode structures; partition structures disposed between adjacent horizontal patterns in the first direction, the partition structures configured to separate the source structures of adjacent memory structures from each other; and etch stop patterns disposed between the horizontal patterns and at a height lower than that of the source structures, the etch stop patterns connected to lower portions of the partition structures, wherein the etch stop patterns include first sub-patterns extending in the first direction and second sub-patterns extending in a second direction intersecting the first direction.

2. The semiconductor memory device of claim 1, wherein: each of the horizontal patterns includes a first edge parallel to the first direction and a second edge parallel to the second direction; the first sub-patterns extend along the first edges; and the second sub-patterns extend along the second edges.

3. The semiconductor memory device of claim 1, wherein: the first sub-patterns include a plurality of first sub-patterns; the second sub-patterns include a plurality of second sub-patterns; and the etch stop patterns have a mesh shape formed by the plurality of first sub-patterns and the plurality of second sub-patterns intersecting each other. the etch stop patterns are formed of a non-metallic material having etch selectivity with respect to a silicon oxide layer and a silicon nitride layer.

4. The semiconductor memory device according to claim 1, wherein, the etch stop patterns include polysilicon.

5. The semiconductor memory device according to claim 4, wherein, a width of the etch stop patterns in the first direction is greater than a width of the partition structures in the first direction.

6. The semiconductor memory device according to claim 1, wherein, a width of the etch stop patterns in the second direction is greater than a width of the partition structures in the second direction.

7. The semiconductor memory device according to claim 1, wherein, the partition structures have a bar shape or a rectangular shape.

8. The semiconductor memory device according to claim 1, wherein, a top surface of the etch stop patterns is at a height lower than a bottom surface of the horizontal patterns.

9. The semiconductor memory device according to claim 1, wherein, 10. The semiconductor memory device of claim 1, wherein: a top surface of the etch stop patterns is at a same height as a top surface of the horizontal patterns; and a bottom surface of the etch stop patterns is at a same height as a bottom surface of the horizontal patterns.

11. The semiconductor memory device of claim 1, further comprising: residual mode patterns disposed between adjacent horizontal patterns in the first direction and between the source structures and the etch stop patterns in a direction of a thickness of the semiconductor memory device, wherein the partition structures are configured to separate the residual mode patterns in the first direction.

12. The semiconductor memory device of claim 11, wherein: the source structures include first conductive source patterns disposed on the horizontal patterns and second conductive source patterns disposed between the first conductive source patterns and the horizontal patterns, and the second conductive source patterns are at a same height as a height of the residual mode patterns. a top surface of the residual mode patterns is in contact with a bottom surface of the first conductive source patterns.

13. The semiconductor memory device according to claim 12, wherein, 14. The semiconductor memory device of claim 12, wherein: ​ a sidewall of the second conductive source pattern is disposed on the horizontal pattern; and a sidewall of the first conductive source pattern is in contact with a sidewall of the division structure.

15. The semiconductor memory device of claim 1, further comprising: a through plug connecting the memory structure to the peripheral circuit structure, wherein the through plug is spaced apart from the etch stop pattern and the division structure in the first direction.

16. The semiconductor memory device according to claim 15, wherein, a bottom surface of the division structure is located at a higher level than a bottom surface of the through plug.

17. The semiconductor memory device according to claim 1, wherein, a thickness of the etch stop pattern is in a range of 800 Å to 2000 Å.

18. A semiconductor memory device, comprising: horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, wherein a division region is interposed between the horizontal patterns in a first direction, the division region including a first insulating penetration layer; a memory structure disposed on the horizontal patterns, the memory structure including a source structure and an electrode structure on the source structure; a vertical structure penetrating the electrode structure and connected to the source structure; a division structure disposed in the division region, the division structure configured to separate the source structures of adjacent memory structures from each other; an etch stop pattern disposed between the horizontal patterns and at a level lower than a level of the horizontal patterns, the etch stop pattern connected to a lower portion of the division structure; and a through plug configured to connect the memory structure to the peripheral circuit structure, wherein the source structure includes a first conductive source pattern disposed on the horizontal pattern and a second conductive source pattern disposed between the first conductive source pattern and the horizontal pattern, and the first conductive source pattern extends to the division region and is connected to a sidewall of the division structure.

19. The semiconductor memory device of claim 18, further comprising: a remaining mode pattern disposed between the first conductive source pattern and the first insulating penetration layer and located at a same level as the second conductive source pattern, wherein the division structure separates the remaining mode pattern in a horizontal direction. ​

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