Gate structure, semiconductor device and method for forming the same

Abstract

A gate structure and a method for forming the gate structure are provided. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed above the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer includes at least an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. Furthermore, a semiconductor device including the gate structure is provided.

Description

Technical Field

[0001] Embodiments of the present invention relate to a gate structure, a semiconductor device, and a method for forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material on a semiconductor substrate; and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be addressed. Summary of the Invention

[0004] An embodiment of the present invention provides a gate structure comprising a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed above the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer comprises at least an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figures 1A to 1K is a perspective view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0007] Figures 2A to 2K It shows Figures 1A to 1K A cross-sectional view of a method for manufacturing a semiconductor device.

[0008] Figures 3A to 3E It shows Figure 1K A cross-sectional view of a method for manufacturing a gate structure of a semiconductor device.

[0009] Figures 4A to 4D It shows Figure 3C A schematic enlarged view of a region of a method of forming a cluster material for a semiconductor device.

[0010] Figure 5 is a schematic plan view of an atomic layer deposition (ALD) tool for forming cluster materials for semiconductor devices.

[0011] Figure 6 is used to form Figure 4A Flowchart of the ALD process for the work function metal material in the cluster material.

[0012] Figure 7 is used to form Figure 4B Flowchart of the ALD process for the barrier material in the cluster material.

[0013] Figure 8 is used to form Figure 4C Flowchart of the ALD process for the cap material of the cluster material.

[0014] Figure 9 is used to form Figure 4D Flowchart of the ALD process for the bonding material in the cluster material.

[0015] Figure 10 is a schematic enlarged view of a cluster material of a gate structure according to an alternative embodiment of the present disclosure.

[0016] Figure 11 is a schematic enlarged view of a cluster material of a gate structure according to other embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0019] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. Generally, a double patterning process or a multiple patterning process combines a photolithography process with a self-aligned process, thereby allowing for the production of patterns having, for example, smaller pitches than would otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

[0020] According to some embodiments, a cluster layer is formed between the gate dielectric layer and the metal layer. The cluster layer may include a work function metal layer, a barrier layer, a cap layer, and an adhesion layer stacked in sequence. The cap layer may include an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer, and may be sandwiched between the barrier layer and the adhesion layer. In this case, the cap layer can prevent Al atoms and / or Ti atoms from the work function metal layer from diffusing into the gate dielectric layer (e.g., the interface (IL) layer) and into the gap (i.e., the metal (W) layer), thereby preventing the threshold voltage (Vt) of the transistor from shifting, improving the controllability of the gate structure, preventing leakage, and preventing gate dielectric layer burnout.

[0021] Figures 1A to 1K is a perspective view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Figures 2A to 2K It shows Figures 1A to 1K The semiconductor device shown in the following embodiments can be applied to fin field-effect transistors (FinFETs), but is not limited thereto. In other embodiments, the semiconductor device can also be applied to planar transistors, gate-all-around (GAA) FETs, or other transistors including metal gates.

[0022] refer to Figure 1A and Figure 2A, providing a substrate 100. In some embodiments, the substrate 100 includes a crystalline silicon substrate (e.g., a wafer). Depending on design requirements (e.g., a p-type semiconductor substrate or an n-type semiconductor substrate), the substrate 100 may include various doped regions. In some embodiments, the doped regions may be doped with p-type dopants or n-type dopants. For example, the doped regions may be doped with: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. The doped regions may be configured for n-type FinFETs, or alternatively, for p-type FinFETs. In some alternative embodiments, the substrate 100 includes: elemental semiconductors, such as silicon or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP, or combinations thereof.

[0023] In some embodiments, a liner layer 102a and a mask layer 102b are sequentially formed on a substrate 100. The liner layer 102a may be a silicon oxide film formed, for example, by a thermal oxidation process. The liner layer 102a may serve as an adhesion layer between the substrate 100 and the mask layer 102b. The liner layer 102a may also serve as an etch stop layer for etching the mask layer 102b. In some embodiments, the mask layer 102b may be a silicon nitride layer formed by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The mask layer 102b serves as a hard mask during subsequent photolithography processes. A patterned photoresist layer 104 having a predetermined pattern is formed on the mask layer 102b.

[0024] refer to Figure 1A to Figure 1B as well as Figure 2A to Figure 2B , the mask layer 102b and the liner layer 102a not covered by the patterned photoresist layer 104 are sequentially etched to form a patterned mask layer 102b' and a patterned liner layer 102a'. The patterned mask layer 102b' and the patterned liner layer 102a' expose the substrate 100 below. By using the patterned photoresist layer 104, the patterned mask layer 102b' and the patterned liner layer 102a' as masks, a portion of the substrate 100 is exposed and etched to form a plurality of trenches 106 and a plurality of fins 108 between the trenches 106. After forming the trenches 106 and the fins 108, the patterned photoresist layer 104 is subsequently removed. In the case described, as Figure 1BAs shown in FIG, the fins 108 are patterned into semiconductor strips and separated by trenches 106. The patterned mask layer 102b' and the patterned liner layer 102a' are still disposed on the fins 108. Figure 1B Only three fins 108 are shown in the figure, but the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of fins 108 can be adjusted as needed, such as one fin, two fins, four fins, or more fins.

[0025] refer to Figure 1C and Figure 2C , an insulating material 110 is formed over the substrate 101 to cover the fins 108 and fill the trenches 106. In addition to the fins 108, the insulating material 110 further covers the patterned liner layer 102a' and the patterned mask layer 102b'. The insulating material 110 may include silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-k dielectric material. In this article, a low-k dielectric material is generally a dielectric material with a dielectric constant lower than 3.9. The insulating material 110 can be formed by high-density-plasma chemical vapor deposition (HDP-CVD), low-pressure CVD (SACVD), or by spin coating.

[0026] refer to Figure 1C to Figure 1D as well as Figure 2C to Figure 2D , a planarization process may be performed to remove a portion of the insulating material 110, the patterned mask layer 102b', and the patterned liner layer 102a' until the fin 108 is exposed. Figure 1D and Figure 2D As shown in FIG, the top surface 108t of the fin 108 is substantially coplanar with the top surface 110t of the planarized insulating material 110. In some embodiments, the planarization process includes chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like.

[0027] refer to Figure 1D to Figure 1E as well as Figure 2D to Figure 2E, the insulating material 110 is etched back to form a plurality of isolation regions 111. After the insulating material 110 is etched back, the fins 108 protrude from between adjacent isolation regions 111. That is, the top surface 111t of the isolation region 111 may be lower than the top surface 108t of the fin 108. In addition, the top surface 111t of the isolation region 111 may have a flat surface (as shown), a convex surface, a concave surface (e.g., a butterfly shape), or a combination thereof. In some embodiments, the insulating material 110 is etched back using an appropriate etching process, such as a wet etching process using hydrofluoric acid (HF), a dry etching process, or a combination thereof. In some embodiments, the height difference between the top surface 108t of the fin 108 and the top surface 111t of the isolation region 111 is in a range from about 1 nanometer to about 300 nanometers.

[0028] refer to Figure 1F and Figure 2F A dummy gate structure 112 is formed above a portion of the fin 108 and a portion of the isolation region 111. The dummy gate structure 112 may extend along an extension direction D1 (or along an extension direction D2) perpendicular to the extension direction D1 of the fin 108. Figure 1F That is, the dummy gate structure 112 may span the fin 108. In some embodiments, the dummy gate structure 112 covers the middle portion M of the fin 108 (e.g., Figure 2F The other portion of the fin 108 at the opposite side of the middle portion M may be referred to as an exposed portion E. Figure 1F shown in.

[0029] Specifically, the dummy gate structure 112 may include a dummy gate dielectric layer 112a and a dummy gate 112b disposed above the dummy gate dielectric layer 112a. In some embodiments, the dummy gate dielectric layer 112a may separate the fin 108 from the dummy gate 112b and may serve as an etch stop layer. The dummy gate dielectric layer 112a may include silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the dummy gate dielectric layer 112a is formed using a suitable process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV ozone oxidation, or a combination thereof. In some embodiments, the dummy gate 112b includes a silicon-containing material, such as polysilicon, amorphous silicon, or a combination thereof. The dummy gate 112b may be formed using a suitable process, such as ALD, CVD, PVD, plating, or a combination thereof. Although Figure 1FThe dummy gate 112b shown in FIG is a single-layer structure, but the embodiments of the present disclosure are not limited thereto. In other embodiments, the dummy gate 112b may be a multi-layer structure.

[0030] In addition to the dummy gate structure 112, a pair of spacers 113 are also formed over a portion of the fin 108 and a portion of the isolation region 111. Figure 1F As shown in FIG, the spacer 113 is disposed on the sidewall of the dummy gate structure 112. In some embodiments, the spacer 113 and the dummy gate structure 112 have the same extension direction D1. Similar to the dummy gate structure 112, the spacer 113 also spans the fin 108. In some embodiments, the spacer 113 is formed of a dielectric material, such as silicon oxide, silicon nitride, carbonized silicon nitride (SiCN), SiCON, or a combination thereof. Although Figure 1F The spacer 113 shown in FIG. 1 is a single-layer structure, but the embodiments of the present disclosure are not limited thereto. In other embodiments, the spacer 113 may be a multi-layer structure.

[0031] refer to Figure 1F to Figure 1G as well as Figure 2F to Figure 2G , the exposed portion E of the fin 108 is removed and recessed to form a recessed portion R. In some embodiments, the exposed portion E may be removed using an anisotropic etching process, an isotropic etching process, or a combination thereof. In some embodiments, the exposed portion E of the fin 108 is recessed below the top surface 111t of the isolation region 111. The depth of the recessed portion R is less than the thickness of the isolation region 111. In other words, the exposed portion E of the fin 108 is not completely removed, and the remaining fin at the opposite side of the dummy gate structure 112 may be referred to as a source / drain region 120. In some alternative embodiments, the exposed portion E of the fin 108 may be omitted. Figure 1G and Figure 2G The recessing step is shown in FIG.

[0032] refer to Figure 1H and Figure 2H A strained material 114 (or a highly doped, low-resistance material) is grown over the recessed portion R of the semiconductor fin 108. The strained material 114 extends beyond the top surface 111t of the isolation region 111, subjecting the fin 108 to tension or compression. In other words, the strained material 114 is formed over the source / drain regions 120 of the semiconductor fin 108. In this embodiment, the strained material 114 includes a source disposed on one side of the dummy gate structure 112 and a drain disposed on the other side of the dummy gate structure 112. The source covers one end of the fin 108, and the drain covers the other end of the fin 108.

[0033] In some embodiments, strained material 114 comprises any acceptable material, such as that suitable for p-type FinFETs. For example, if fin 108 is silicon, strained material 114 may comprise SiGe, SiGeB, Ge, GeSn, or the like. In some alternative embodiments, strained material 114 comprises any acceptable material, such as that suitable for n-type FinFETs. For example, if fin 108 is silicon, strained material 114 may comprise silicon, SiC, SiCP, SiP, or the like.

[0034] In some embodiments, the strained material 114 may be doped with a conductive dopant. For example, the strained material 114 (e.g., SiGe) may be epitaxially grown with a p-type dopant to strain a p-type FinFET. That is, the strained material 114 is doped with a p-type dopant to form the source and drain of the p-type FinFET. The p-type dopant may include boron or BF2, and the strained material 114 may be epitaxially grown using in-situ doping via an LPCVD process. In some alternative embodiments, the strained material 114 (e.g., SiC, SiP, a combination of SiC / SiP, or SiCP) may be epitaxially grown with an n-type dopant to strain an n-type FinFET. That is, the strained material 114 is doped with an n-type dopant to form the source and drain of the n-type FinFET. The n-type dopant may include arsenic and / or phosphorus, and the strained material 114 may be epitaxially grown using in-situ doping via an LPCVD process.

[0035] Since the strained material 114 is formed using an epitaxial growth process, the cross section of the strained material 114 along line II-II' may have a diamond shape or a pentagonal shape as shown. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the cross section of the strained material 114 may also have a hexagonal shape, a columnar shape, or a rod shape. In some embodiments, as shown in FIG. Figure 2H As shown in FIG, adjacent strained materials 114 are separated from each other after the epitaxial growth process is completed. Alternatively, adjacent strained materials 114 may be merged.

[0036] refer to Figure 1I and Figure 2IAn interlayer dielectric (ILD) layer 150 is formed over the strained material 114 and the isolation region 111. In some embodiments, the ILD layer 150 comprises silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide, and / or combinations thereof. In some other embodiments, the ILD layer 150 comprises a low-k dielectric material. Examples of low-k dielectric materials include BLACK (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, Amorphous fluorinated carbon, Parylene, bis-benzocyclobutene (BCB), Fluorinated polyarylether (Flare), (Dow Chemical, Midland, Mich.), hydrogen silsesquioxane (HSQ), or fluorinated silicon oxide (SiOF), and / or combinations thereof. In alternative embodiments, the ILD layer 150 includes one or more dielectric materials and / or one or more dielectric layers. In some embodiments, the ILD layer 150 is formed to a suitable thickness by flowable CVD (FCVD), CVD, HDPCVD, SACVD, spin coating, sputtering, or other suitable methods. For example, an interlayer dielectric material layer (not shown) is initially formed to cover the isolation region 111, the dummy gate structure 112, and the spacer 113. Subsequently, the thickness of the interlayer dielectric material layer is reduced until the dummy gate structure 112 is exposed, thereby forming the ILD layer 150. Reducing the thickness of the interlayer dielectric material layer can be accomplished by a chemical mechanical polishing (CMP) process, an etching process, or other suitable process.

[0037] refer to Figure 1J and Figure 2J , the dummy gate structure 112 is removed to form a hollow portion H exposing a portion of the fin 108. For example, the dummy gate 112b and the dummy gate dielectric layer 112a are removed, and the hollow portion H exposes a portion of the middle portion M of the fin 108. Figure 1J As shown in FIG, the fin 108 exposed by the hollow portion H may be referred to as a channel region 130. In some embodiments, the dummy gate 112b and the dummy gate dielectric layer 112a are removed by an etching process or other suitable process. For example, the dummy gate 112b and the dummy gate dielectric layer 112a may be removed by a wet etching process or a dry etching process. Examples of wet etching processes include chemical etching, and examples of dry etching processes include plasma etching. However, the present disclosure is not limited thereto. Other commonly known etching methods may also be suitable for removing the dummy gate 112b and the dummy gate dielectric layer 112a.

[0038] refer to Figure 1J to Figure 1K as well as Figure 2J to Figure 2K , a gate dielectric layer 210, a cluster layer 220, and a metal layer 230 are sequentially deposited into the hollow portion H to form a gate structure 200, thereby obtaining the FinFET 10. In some embodiments, the gate dielectric layer 210 includes an interface layer 212 and a high dielectric constant (high-k) dielectric layer 214. Figure 1K and Figure 2K As shown in FIG, the gate structure 200 is disposed across the fin 108 and sandwiched between the pair of spacers 113. A process for forming the gate structure 200 will be described in detail below.

[0039] Figures 3A to 3E It is shown along Figure 1K A cross-sectional view of a method for manufacturing a gate structure 200 of a FinFET 10 taken along line III-III'. Figure 3A , the interface material 212' may be conformally formed over the hollow portion H and extended to cover the top surface of the ILD layer 150 and the spacer 113. In addition, the interface material 212' also conformally covers Figure 1J In some embodiments, the interface material 212' comprises a dielectric material, such as a silicon oxide layer (SiO2) or silicon oxynitride (SiON). In some embodiments, the interface material 212' is formed by a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable deposition methods. In some alternative embodiments, the interface material 212' is formed by oxidizing the interface material using chemical oxidation or thermal oxidation. Figure 1J The interface material 212' is formed by the channel region 130 of the fin 108 shown in FIG. When the interface material 212' is formed by the oxidation process, the interface material 212' can be formed according to Figure 3A That is, the interface material 212' may be formed only on the top surface of the channel region 130 and does not extend to cover the sidewalls of the hollow portion H. In some embodiments, the interface material 212' is suitable for being formed on the semiconductor surface (ie, Figure 2K108) and the gate insulator (ie, Figure 2K The high-k dielectric layer 214 shown in FIG. 2 provides a good interface between the two layers and suppresses the decrease in the mobility of the channel carriers of the FinFET 10.

[0040] refer to Figure 3B A high-k dielectric material 214' is conformally disposed on the interface material 212' to form the structure 10a. In some embodiments, the high-k dielectric material 214' has a dielectric constant greater than approximately 4, greater than approximately 7, greater than approximately 12, greater than approximately 16, or even greater than approximately 20. For example, the high-k dielectric material 214' may include a metal oxide such as ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, combinations thereof, or suitable materials. In alternative embodiments, the high-k dielectric material 214' may optionally include a silicate such as HfSiO, HfSiON, LaSiO, AlSiO, combinations thereof, or suitable materials. In some embodiments, the high-k dielectric material 214 ′ is formed by performing at least one suitable deposition technique, such as CVD, PECVD, metal oxide chemical vapor deposition (MOCVD), ALD, remote plasma atomic layer deposition (RPALD), plasma-enhanced atomic layer deposition (PEALD), molecular beam deposition (MBD), or the like.

[0041] refer to Figure 3C , the cluster material 220' is conformally formed on the high-k dielectric material 214'. Figures 4A to 4D The process of forming the cluster material 220' is described in detail. Figures 4A to 4D It shows Figure 3C FIG. 1 is a schematic enlarged view of a region 225 of a method of forming a cluster material 220 ′ in a gate structure 200 of a FinFET 10 .

[0042] refer to Figure 4A, a work function metal material 222' is conformally deposited on the high-k dielectric material 214' to form structure 20a. In some embodiments, the work function metal material 222' comprises an N-type work function metal, such as Ti, Al, TiAl, TiAlN, TiAlC, Ta, TaC, TaCN, TaSiN, or a combination thereof. In some alternative embodiments, the work function metal material 222' comprises a P-type work function metal, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, or a combination thereof. In some embodiments, the method of forming the work function metal material 222' comprises performing at least one suitable deposition technique, such as CVD, PECVD, ALD, RPALD, PEALD, MBD, or the like. For example, the work function metal material 222' is a TiAl layer (hereinafter referred to as TiAl layer 222'), and the TiAl layer 222' is formed by ALD. The following will be combined with Figure 5 and Figure 6 The process of forming the TiAl layer 222 ′ is described in detail. Figure 5 is a schematic plan view of an ALD tool 500 for forming the cluster material 220 ′ of the FinFET 10 . Figure 6 is used to form Figure 4A Flowchart of an ALD process 600 for depositing a work function metal material (eg, TiAl layer 222 ′) in FIG.

[0043] refer to Figure 5 The ALD tool 500 is configured to include: one or more load lock chambers 502; one or more first processing chambers 512, 514, 516 (collectively referred to as "first chambers 510"); one or more second processing chambers 522, 524 (collectively referred to as "second chambers 520"); one or more third processing chambers 532, 534 (collectively referred to as "third chambers 530"); a first robot arm 506; a second robot arm 508; and one or more transfer chambers 542, 544.

[0044] Specifically, the load lock chamber 502 can be used to transfer substrates into and out of the ALD tool 500. A first robot 506 can transfer substrates between the load lock chamber 502 and third chambers 530 (two are shown). Each third chamber 530 can be configured to perform a variety of substrate processing operations, such as periodic layer deposition including atomic layer deposition (ALD), pre-cleaning, degassing, and other substrate processes. The first robot 506 also transfers substrates to and from transfer chambers 542 and 544.

[0045] The transfer chamber 542 and the transfer chamber 544 can be used to maintain ultra-high vacuum conditions while allowing substrates to be transferred within the ALD tool 500. The second robot arm 508 can transfer substrates between the transfer chambers 542 and 544 and the first chamber 510 and the second chamber 520. Similar to the third chamber 530, the first chamber 510 and the second chamber 520 can be configured to perform various substrate processing operations, such as periodic layer deposition including atomic layer deposition (ALD), pre-cleaning, degassing, and other substrate processes. In some embodiments, the number of the first chamber 510, the second chamber 520, and the third chamber 530 can be adjusted according to manufacturing needs, but the embodiments of the present disclosure are not limited thereto.

[0046] refer to Figure 5 , the ALD tool 500 may be configured to deposit Figure 3C In order to improve the efficiency and yield of the system, a configuration includes: three first chambers 510 configured to deposit work function metal materials 222', two second chambers 520 configured to deposit barrier materials 224' and cap materials 226', and two third chambers 530 configured to deposit adhesive materials 228'. In an embodiment of the present invention, the first chamber 510 is a TiAl ALD chamber, the second chamber 520 is an ALD chamber for TiN and Si caps, and the third chamber 530 is a TiNALD chamber. In the case described, the work function metal material 222', barrier material 224', cap material 226', and adhesive material 228' are referred to as in-situ formation. As used herein, the term "in-situ" refers to performing multiple ALD processes in the same processing system or a single ALD tool 500. In other words, Figure 3B The structure 10a shown in FIG. 5 can be transferred between different chambers 510, 520, and 530 in a single processing tool 500 and maintained under vacuum conditions. Therefore, during the formation of the work function metal material 222′, the barrier material 224′, the cap material 226′, and the adhesive material 228′, the structure 10a is not exposed to the external environment or the oxygen-containing environment.

[0047] refer to Figure 5 and Figure 6 ,Will Figure 3BThe structure 10a shown in FIG is loaded into the first chamber 510 of the ALD tool 500, wherein the first chamber 510 is prepared for forming a work function metal material, such as a TiAl layer 222'. For example, the structure 10a is loaded into the first chamber 510, wherein the structure 10a is heated to a desired temperature. In some embodiments, the temperature maintained in the first chamber 510 is about 250° C. to about 600° C., and the pressure in the first chamber 510 is set to about 0.001 Torr to about 100 Torr. At block 602, when the structure 10a is loaded into the first chamber 510, a first precursor is introduced into the first chamber 510. In some embodiments, the first precursor comprises titanium (Ti). In such a case, the structure 10a may be exposed to the titanium-containing precursor. At block 604, the first precursor is purged. Specifically, a purge process is performed to remove any remaining titanium-containing precursor and any byproducts from the first chamber 510. At block 606, a second precursor is introduced into the first chamber 510. In some embodiments, the second precursor comprises aluminum (Al). In such cases, the structure 10a may be exposed to the aluminum-containing precursor. At block 608, the second precursor is purged. Specifically, another purge process is performed to remove any remaining aluminum-containing precursor and any byproducts from the first chamber 510. Blocks 602 through 608 constitute an ALD cycle, which includes two deposition phases (blocks 602 and 606) and two purge phases (blocks 604 and 608). Each ALD cycle is a self-limiting process, wherein less than or equal to approximately one titanium-containing and aluminum-containing monolayer is deposited during each ALD cycle. The ALD cycle is repeated until the TiAl layer 222′ reaches the desired (target) thickness. For example, at block 610, if the thickness of the TiAl layer 222′ is equal to the target thickness (or within a given threshold of the target thickness), the ALD process 600 ends at block 612. If the thickness of the TiAl layer 222' is not equal to the target thickness (or is not within a given threshold of the target thickness), the ALD process 600 returns to block 602 to begin another ALD cycle. In some embodiments, the ALD cycle (blocks 602 to 608) is repeated until the TiAl layer 222' has a thickness of about 1 angstrom to about 500 angstroms. Additional steps may be provided before, during, and after the ALD process 600, and some of the described steps may be moved, replaced, or eliminated for additional embodiments of the ALD process 600.

[0048] In some embodiments, the titanium-containing precursor at block 602 comprises titanium tetrachloride (TiCl4), tetrakis(dimethylamino)titanium (TDMAT) (e.g., Ti[N(CH3)2]4), tetrakis(diethylamido)titanium (TDEAT), tetrakis(ethylmethylamino)titanium (TEMAT), or other suitable titanium-containing precursors. In some embodiments, the flow rate of the titanium-containing precursor is from about 5 standard cubic centimeters per minute (sccm) to about 5000 sccm. In some embodiments, a carrier gas is used to deliver the titanium-containing precursor to the first chamber 510. In some embodiments, the carrier gas is an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, the pulse duration of the titanium-containing precursor is from about 0.1 seconds to about 1500 seconds. In some embodiments, the pressure maintained in first chamber 510 during the titanium-containing pulse duration is about 0.001 Torr to about 100 Torr. In some embodiments, the temperature maintained in first chamber 510 during the titanium-containing pulse duration is about 250°C to about 600°C.

[0049] In some embodiments, the purge process at box 604 removes any remaining titanium-containing precursor and various byproducts from the first chamber 510. The purge process uses an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. For example, in an embodiment of the present invention, the purge process uses an argon-containing gas, such as Ar. In some embodiments, the flow rate of the inert gas is from about 5 standard cubic centimeters per minute to about 5000 standard cubic centimeters per minute. In some embodiments, the purge process lasts for about 0.1 seconds to about 1500 seconds. In some embodiments, the purge process and the titanium-containing pulse have approximately the same duration. In some embodiments, the pressure maintained in the first chamber 510 during the purge process is from about 0.001 Torr to about 1000 Torr.

[0050] In some embodiments, the aluminum-containing precursor at box 606 comprises triethylaluminum (TMA) (e.g., Al(C2H5)3), Aviato (e.g., AlCl3), or other suitable aluminum-containing precursors. In some embodiments, the flow rate of the aluminum-containing precursor is from about 5 standard cubic centimeters per minute to about 5000 standard cubic centimeters per minute. In some embodiments, a carrier gas is used to deliver the aluminum-containing precursor to the first chamber 510. In some embodiments, the carrier gas is an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, the pulse duration of the aluminum-containing precursor is from about 0.1 seconds to about 1500 seconds. In some embodiments, the pressure maintained in the first chamber 510 during the duration of the aluminum-containing pulse is from about 0.001 Torr to about 1000 Torr. In some embodiments, the temperature maintained in the first chamber 510 during the duration of the aluminum-containing pulse is from about 250°C to about 600°C.

[0051] In some embodiments, the purge process at block 608 removes any remaining aluminum-containing precursor and various byproducts from the first chamber 510. The purge process uses an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. For example, in an embodiment of the present invention, the purge process uses an argon-containing gas, such as Ar. In some embodiments, the flow rate of the inert gas is from about 5 standard cubic centimeters per minute to about 5000 standard cubic centimeters per minute. In some embodiments, the purge process lasts from about 0.1 seconds to about 1500 seconds. In some embodiments, the purge process and the aluminum-containing pulse have approximately the same duration. In some embodiments, the pressure maintained in the first chamber 510 during the purge process is from about 0.001 Torr to about 1000 Torr.

[0052] refer to Figure 4B After forming the work function metal material 222', a barrier material 224' is conformally deposited on the work function metal material 222' to form the structure 20b. In some embodiments, the barrier material 224' comprises TiN, Aviato (e.g., AlCl3), or a combination thereof. In some embodiments, the method of forming the barrier material 224' comprises performing at least one suitable deposition technique, such as CVD, PECVD, ALD, RPALD, PEALD, MBD, or the like. For example, the barrier material 224' is a TiN layer (hereinafter referred to as the first TiN layer 224'), and the first TiN layer 224' is formed by ALD. Figure 5 and Figure 7 The process of forming the first TiN layer 224 ′ is described in detail. Figure 7 is used to form Figure 4BFlowchart of an ALD process 700 for depositing a barrier material (eg, first TiN layer 224') in FIG.

[0053] refer to Figure 5 and Figure 7 ,Will Figure 4A The structure 20a shown in FIG is transferred from the first chamber 510 to the second chamber 520 of the ALD tool 500. The second chamber 520 is prepared for forming a barrier material, such as the first TiN layer 224'. For example, the structure 20a is loaded into the second chamber 520, where the structure 20a is heated to a desired temperature. In some embodiments, the temperature maintained in the second chamber 520 is between about 250°C and about 600°C, and the pressure in the second chamber 520 is set to between about 0.001 Torr and about 1000 Torr. At block 702, while the structure 20a is loaded into the second chamber 520, a third precursor is introduced into the second chamber 520. In some embodiments, the third precursor comprises titanium (Ti). In such a case, the structure 20a may be exposed to the titanium-containing precursor. At block 704, the third precursor is purged. Specifically, a purge process is performed to remove any remaining titanium-containing precursor and any byproducts from the second chamber 520. At block 706, a fourth precursor is introduced into the second chamber 520. In some embodiments, the fourth precursor comprises nitrogen (N). In such cases, the structure 20a may be exposed to the nitrogen-containing precursor. At block 708, the fourth precursor is purged. Specifically, another purge process is performed to remove any remaining nitrogen-containing precursor and any byproducts from the second chamber 520. Blocks 702 through 708 constitute an ALD cycle, which includes two deposition phases (blocks 702 and 706) and two purge phases (blocks 704 and 708). Each ALD cycle is a self-limiting process, wherein less than or equal to approximately one titanium- and nitrogen-containing monolayer is deposited during each ALD cycle. The ALD cycle is repeated until the first TiN layer 224′ reaches the desired (target) thickness. For example, at block 710, if the thickness of the first TiN layer 224′ is equal to the target thickness (or within a given threshold of the target thickness), the ALD process 700 ends at block 712. If the thickness of the first TiN layer 224' is not equal to the target thickness (or is not within a given threshold of the target thickness), the ALD process 700 returns to block 702 to begin another ALD cycle. In some embodiments, the ALD cycle (blocks 702 to 708) is repeated until the first TiN layer 224' has a thickness of about 0.1 nanometers to about 50 nanometers. Additional steps may be provided before, during, and after the ALD process 700, and some of the described steps may be moved, replaced, or eliminated for additional embodiments of the ALD process 700.

[0054] In some embodiments, the titanium-containing precursor at box 702 comprises TiCl4, TDMAT, TDEAT, TEMAT, or other suitable titanium-containing precursors. In some embodiments, the flow rate of the titanium-containing precursor is from about 5 standard cubic centimeters per minute to about 5000 standard cubic centimeters per minute. In some embodiments, a carrier gas is used to deliver the titanium-containing precursor to the second chamber 520. In some embodiments, the carrier gas is an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, the pulse duration of the titanium-containing precursor is from about 0.1 seconds to about 1500 seconds. In some embodiments, the pressure maintained in the second chamber 520 during the titanium-containing pulse duration is from about 0.001 Torr to about 1000 Torr. In some embodiments, the temperature maintained in the second chamber 520 during the titanium-containing pulse duration is from about 250°C to about 600°C.

[0055] In some embodiments, the purge process at box 704 removes any remaining titanium-containing precursor and various byproducts from the second chamber 520. The purge process uses an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. For example, in an embodiment of the present invention, the purge process uses an argon-containing gas, such as Ar. In some embodiments, the flow rate of the inert gas is from about 5 standard cubic centimeters per minute to about 5000 standard cubic centimeters per minute. In some embodiments, the purge process lasts for about 0.1 seconds to about 1500 seconds. In some embodiments, the purge process and the titanium-containing pulse have approximately the same duration. In some embodiments, the pressure maintained in the second chamber 520 during the purge process is from about 0.001 Torr to about 1000 Torr.

[0056] In some embodiments, the nitrogen-containing precursor at block 706 comprises NH3, NF3, or other suitable nitrogen-containing precursors. In some embodiments, the flow rate of the nitrogen-containing precursor is between about 5 standard cubic centimeters per minute and about 5000 standard cubic centimeters per minute. In some embodiments, a carrier gas is used to deliver the nitrogen-containing precursor to the second chamber 520. In some embodiments, the carrier gas is an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, the pulse duration of the nitrogen-containing precursor is between about 0.1 seconds and about 1000 seconds. In some embodiments, the pressure maintained in the second chamber 520 during the nitrogen-containing pulse duration is between about 0.001 Torr and about 1000 Torr. In some embodiments, the temperature maintained in the second chamber 520 during the nitrogen-containing pulse duration is between about 250° C. and about 600° C. In some alternative embodiments, after performing blocks 702 through 704, the structure 20a is exposed to a nitrogen-containing plasma to nitride the surface of the structure 20a. For example, the nitrogen-containing plasma is generated by a nitrogen-containing gas (e.g., N2).

[0057] In some embodiments, the purge process at block 708 removes any remaining nitrogen-containing precursor and various byproducts from the second chamber 520. The purge process uses an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. For example, in an embodiment of the present invention, the purge process uses an argon-containing gas, such as Ar. In some embodiments, the flow rate of the inert gas is from about 5 standard cubic centimeters per minute to about 5000 standard cubic centimeters per minute. In some embodiments, the purge process lasts from about 0.1 seconds to about 1500 seconds. In some embodiments, the purge process and the nitrogen-containing pulse have approximately the same duration. In some embodiments, the pressure maintained in the second chamber 520 during the purge process is from about 0.001 Torr to about 1000 Torr.

[0058] In one embodiment, if the ALD process 600 and the ALD process 700 are performed "ex-situ", then the exposed surface of the structure 20a may be exposed to the external environment or oxygen-containing environment when the structure 20a is transferred between the processing system and / or processing chamber. For example, the TiAl layer 222' may be undesirably oxidized when exposed to the oxygen environment, which may change the work function of the TiAl layer 222', thereby affecting the threshold voltage of the NMOS transistor. In addition, the undesirable titanium oxide, aluminum oxide, or titanium aluminum oxide may also increase the resistance of the gate structure. In order to minimize these situations, in an embodiment of the present invention, the ALD process 600 and the ALD process 700 are performed "in situ", and the "in situ" execution refers to the structure 10a (such as in different chambers 510, chambers 520 within the same processing system or processing tool 500) being oxidized. Figure 3B ), thereby allowing the structure 10 a to be maintained under vacuum conditions during the ALD processes 600 and 700. That is, the ALD processes 600 and 700 are performed on the structure 10 a without exposing the structure 10 a to an external environment or an oxygen-containing environment.

[0059] refer to Figure 4C, after forming the barrier material 224', a top cap material 226' is conformally deposited on the barrier material 224' to form the structure 20c. In some embodiments, the top cap material 226' comprises an amorphous material having a Group IVA element, such as Si, C, Ge, or a combination thereof. In some embodiments, the method of forming the top cap material 226' comprises performing at least one suitable deposition technique, such as CVD, PECVD, ALD, RPALD, PEALD, MBD, or the like. For example, when the top cap material 226' is formed by ALD, the top cap material 226' (hereinafter referred to as the Si layer 226') is an amorphous silicon material rather than a crystalline silicon material. Unlike the crystalline silicon material having an ordered lattice, the amorphous silicon material may have silicon atoms arranged in a disordered manner to form a continuous random network. In some embodiments, the amorphous silicon material may have some dangling bonds for forming the bonding material 228' to be formed by ALD. This will be described below in conjunction with Figure 5 and Figure 8 The process of forming the Si layer 226 ′ is described in detail. Figure 8 is used to form Figure 4C Flowchart of an ALD process for forming a cap material (eg, Si layer 226') of the cluster material 220'.

[0060] refer to Figure 5 and Figure 8 , Figure 4BThe structure 20b shown in FIG. 1 is still in the second chamber 520 for subsequent formation of a cap material, such as a Si layer 226′. That is, the Si layer 226′ and the first TiN layer 224′ are formed in the same chamber 520. In some embodiments, the temperature maintained in the second chamber 520 is about 250° C. to about 600° C., and the pressure in the second chamber 520 is set to about 0.001 Torr to about 1000 Torr. At block 802, after the first TiN layer 224′ is formed in the second chamber 520, a fifth precursor is introduced into the second chamber 520. In some embodiments, the fifth precursor comprises a silane gas selected from the group consisting of dichlorosilane (DCS), tetrachlorosilane (TCS), hexachlorodisliane (HCD), and monosilane. In some embodiments, the flow rate of the silane gas is about 0.001 standard cubic centimeters per minute to about 1000 standard cubic centimeters per minute. In some embodiments, the pulse duration of the silane gas is about 0.1 seconds to about 1500 seconds. In some embodiments, the pressure maintained in the second chamber 520 during the silane gas pulse duration is about 0.001 Torr to about 1000 Torr. In some embodiments, the temperature maintained in the second chamber 520 during the silane gas pulse duration is about 250° C. to about 600° C.

[0061] At block 804, the fifth precursor is purged. Specifically, a purge process is performed to remove any remaining silane gas and any byproducts from the second chamber 520. The purge process uses an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, the flow rate of the inert gas is between about 5 standard cubic centimeters per minute and about 5,000 standard cubic centimeters per minute. In some embodiments, the purge process lasts for between about 0.1 seconds and about 1,500 seconds. In some embodiments, the purge process and the duration of the silane gas pulse are approximately the same. In some embodiments, the pressure maintained in the second chamber 520 during the purge process is between about 0.001 Torr and about 1,000 Torr. Blocks 802 through 804 constitute an ALD cycle, which includes a deposition phase (block 802) and a purge phase (block 804). Each ALD cycle is a self-limiting process, wherein less than or equal to about one silicon monolayer is deposited during each ALD cycle. The ALD cycle is repeated until the Si layer 226' reaches a desired (target) thickness. For example, at block 806, if the thickness of the Si layer 226' is equal to the target thickness (or is within a given threshold of the target thickness), the ALD process 800 ends at block 808. If the thickness of the Si layer 226' is not equal to the target thickness (or is not within a given threshold of the target thickness), the ALD process 800 returns to block 802 to begin another ALD cycle. In some embodiments, the ALD cycle (blocks 802 to 804) is repeated until the Si layer 226' has a thickness of approximately 0.1 nanometers to approximately 10 nanometers (alternatively, a thickness of approximately 5 angstroms to approximately 500 angstroms). Additional steps may be provided before, during, and after the ALD process 800, and some of the described steps may be moved, replaced, or eliminated for additional embodiments of the ALD process 800. For example, after block 804, Si-H bonds are formed on the surface of the silicon monolayer, which restricts silicon growth. Therefore, H2 desorption (e.g., electron stimulated desorption (ESD)) is required to create dangling bonds, thereby adsorbing additional silane precursors to allow silicon to grow to the target thickness. In some embodiments, the Si layer 226' grown by the ALD process 800 is a pure Si layer. That is, the primary element of the Si layer 226' is silicon. Alternatively, the Si layer 226' may contain some impurities.

[0062] It should be noted that the ALD process 700 and the ALD process 800 are performed "in situ," which means that the structure 20a (e.g., Figure 4A), thereby allowing the structure 20 a to remain under vacuum conditions during the ALD processes 700 and 800. That is, the ALD processes 700 and 800 are performed on the structure 20 a without exposing the structure 20 a to an external environment or an oxygen-containing environment.

[0063] As mentioned above, the ALD process 700 and the ALD process 800 are performed in situ without removing the structure 20a from the second chamber 520 between the deposition steps. By depositing the first TiN layer 224' and the Si layer 226' in the same reaction chamber 520, the formation of an undesirable interface between the first TiN layer 224' and the Si layer 226' can be avoided. In some embodiments, a plurality of silicon-nitrogen (Si-N) bonds are formed between the first TiN layer 224' and the Si layer 226'. Depositing both layers in one reaction chamber can reduce manufacturing costs. Additionally, eliminating the intermediate structure transfer step can simplify process logistics and increase yield. In some alternative embodiments, when the cap material 226' is an amorphous carbon material, a plurality of carbon-nitrogen (CN) bonds are formed between the first TiN layer 224' and the cap material 226'. In some alternative embodiments, when the cap material 226 ′ is an amorphous germanium material, a plurality of germanium-nitrogen (Ge—N) bonds are formed between the first TiN layer 224 ′ and the cap material 226 ′.

[0064] refer to Figure 4D After forming the cap material 226', the bonding material 228' is conformally deposited on the cap material 226' to obtain the cluster material 220'. In some embodiments, the bonding material 228' comprises TiN, Aviato (e.g., AlCl3), or a combination thereof. In some embodiments, the method of forming the bonding material 228' comprises performing at least one suitable deposition technique, such as CVD, PECVD, ALD, RPALD, PEALD, MBD, or the like. For example, the bonding material 228' is a TiN layer (hereinafter referred to as the second TiN layer 228'), and the second TiN layer 228' is formed by ALD. Figure 5 and Figure 9 The process of forming the second TiN layer 228 ′ is described in detail. Figure 9 is used to form Figure 4D Flowchart of an ALD process for forming an adhesion material (eg, second TiN layer 228') of the cluster material 220' in FIG.

[0065] refer to Figure 5 and Figure 9 , Figure 4CThe structure 20c shown in FIG is transferred from the second chamber 520 to the third chamber 530 of the ALD tool 500. The third chamber 530 is prepared for forming an adhesive material, such as the second TiN layer 228'. For example, the structure 20c is loaded into the third chamber 530, where the structure 20c is heated to a desired temperature. In some embodiments, the temperature maintained in the third chamber 530 is about 250°C to about 600°C, and the pressure in the third chamber 530 is set to about 0.001 Torr to about 1000 Torr. At block 902, while the structure 20c is loaded into the third chamber 530, a sixth precursor is introduced into the third chamber 530. In some embodiments, the sixth precursor comprises titanium (Ti). In such a case, the structure 20c may be exposed to the titanium-containing precursor. At block 904, the sixth precursor is purged. Specifically, a purge process is performed to remove any remaining titanium-containing precursor and any byproducts from the third chamber 530. At block 906, a seventh precursor is introduced into the third chamber 530. In some embodiments, the seventh precursor comprises nitrogen. In such cases, the structure 20c may be exposed to a nitrogen-containing precursor. At block 908, the seventh precursor is purged. Specifically, another purge process is performed to remove any remaining nitrogen-containing precursor and any byproducts from the third chamber 530. Blocks 902 through 908 constitute an ALD cycle, which includes two deposition phases (blocks 902 and 906) and two purge phases (blocks 904 and 908). Each ALD cycle is a self-limiting process, wherein less than or equal to approximately one titanium- and nitrogen-containing monolayer is deposited during each ALD cycle. The ALD cycle is repeated until the second TiN layer 228′ reaches the desired (target) thickness. For example, at block 910, if the thickness of the second TiN layer 228′ is equal to the target thickness (or within a given threshold of the target thickness), the ALD process 900 ends at block 912. If the thickness of the second TiN layer 228' is not equal to the target thickness (or is not within a given threshold of the target thickness), the ALD process 900 returns to block 902 to begin another ALD cycle. In some embodiments, the ALD cycle (blocks 902 to 908) is repeated until the second TiN layer 228' has a thickness of about 5 angstroms to about 500 angstroms. Additional steps may be provided before, during, and after the ALD process 900, and some of the described steps may be moved, replaced, or eliminated for additional embodiments of the ALD process 900.

[0066] In some embodiments, the titanium-containing precursor at block 902 comprises TiCl4, TDMAT, TDEAT, TEMAT, or other suitable titanium-containing precursors. The flow rate, carrier gas, pulse duration, pressure, and temperature of the titanium-containing precursor at block 902 are similar to the flow rate, carrier gas, pulse duration, pressure, and temperature of the titanium-containing precursor at block 702 and have been described in detail in the above embodiments. Therefore, the details are omitted herein. In some alternative embodiments, the deposition parameters at block 902 differ from the deposition parameters at block 702.

[0067] In some embodiments, the purge process at block 904 removes any remaining titanium-containing precursor and various byproducts from the third chamber 530. The purge inert gas, the flow rate of the inert gas, the duration of the purge process, and the pressure at block 904 are similar to the purge inert gas, the flow rate of the inert gas, the duration of the purge process, and the pressure at block 704, and have been described in detail in the above embodiments. Therefore, the details are omitted herein. In some alternative embodiments, the purge parameters at block 904 are different from the purge parameters at block 704.

[0068] In some embodiments, the nitrogen-containing precursor at block 906 comprises ammonia (NH 3 ), NF 3 , or other suitable nitrogen-containing precursors. The flow rate, carrier gas, pulse duration, pressure, and temperature of the nitrogen-containing precursor at block 906 are similar to the flow rate, carrier gas, pulse duration, pressure, and temperature of the nitrogen-containing precursor at block 706 and have been described in detail in the above embodiments. Therefore, the details are omitted herein. In some alternative embodiments, the deposition parameters at block 906 are different from the deposition parameters at block 706. In some alternative embodiments, after performing blocks 902 through 904 , structure 20 c is exposed to a nitrogen-containing plasma to nitride the surface of structure 20 c. For example, the nitrogen-containing plasma is generated by a nitrogen-containing gas (e.g., N 2 ).

[0069] In some embodiments, the purge process at block 908 removes any remaining nitrogen-containing precursor and various byproducts from the third chamber 530. The inert gas, flow rate, duration, and pressure of the purge at block 908 are similar to the inert gas, flow rate, duration, and pressure of the purge at block 708 and have been described in detail in the above embodiments. Therefore, the details are omitted herein. In some alternative embodiments, the purge parameters at block 908 are different from the purge parameters at block 708.

[0070] In one embodiment, if the ALD process 800 and the ALD process 900 are performed "ex situ," the exposed surface of the structure 20c may be exposed to an external environment or an oxygen-containing environment when the structure 20c is transferred between processing systems and / or processing chambers. In such a case, the Si layer 226' may be undesirably oxidized when exposed to an oxygen environment, which may change the physical and chemical properties of the Si layer 226'. In detail, the Si layer may be oxidized to a silicon oxide (SiO) layer, which increases the thickness of the cap material and the resistance of the gate structure. The SiO layer may continuously cover the exposed surface of the structure 20c, which results in the adhesive material being unable to easily stand on the SiO layer and requiring a thicker adhesive material to cover the SiO layer, thereby preventing delamination between the adhesive material and the subsequently formed metal material. However, the thicker adhesive material faces the problem of filling Figure 3C In addition, the formation of the SiO layer requires more waiting time (queue time) for oxidation, which leads to a longer process time and reduced yield. In order to minimize these situations, in an embodiment of the present invention, the ALD process 800 and the ALD process 900 are performed "in situ", which means that the structure 20b (such as the structure 20b) is processed in different chambers 520 and 530 within the same processing system or processing tool 500. Figure 4B ), thereby allowing the structure 20 b to remain under vacuum conditions during the ALD processes 800 and 900. That is, the ALD processes 800 and 900 are performed on the structure 20 b without exposing the structure 20 b to an external environment or an oxygen-containing environment.

[0071] As mentioned above, by depositing the Si layer 226' and the second TiN layer 228' in the same ALD tool 500, the formation of undesirable interfaces or undesirable oxides between the Si layer 226' and the second TiN layer 228' can be avoided. Furthermore, because all of the materials 222', 224', 226', and 228' of the cluster material 220' are formed in situ, no undesirable interfaces or undesirable oxides form between any two adjacent materials 222', 224', 226', and 228'. In other words, all of the materials 222', 224', 226', and 228' can be referred to as a single layer without any interfaces therebetween. In some embodiments, a plurality of silicon-nitrogen (Si-N) bonds are formed between the Si layer 226' and the second TiN layer 228'. In some alternative embodiments, when the cap material 226' is an amorphous carbon material, multiple carbon-nitrogen (CN) bonds are formed between the cap material 226' and the second TiN layer 228'. In some other embodiments, when the cap material 226' is an amorphous germanium material, multiple germanium-nitrogen (Ge-N) bonds are formed between the cap material 226' and the second TiN layer 228'. In such cases, no native oxide is formed between the Si layer 226' and the second TiN layer 228', thereby reducing the resistance of the gate structure 200 of the FinFET 10 and improving the conductivity of the gate structure 200 of the FinFET 10 by approximately 20%. Therefore, the adhesion material (i.e., the second TiN layer 228') can easily stand on the Si layer 226', and a thinner adhesion material (e.g., 10 to 50 angstroms) is used to prevent delamination between the adhesion material and the subsequently formed metal material 230'. Since the Si layer 226' and the second TiN layer 228' are formed in situ, no waiting time for oxidation is required, thereby simplifying the process steps, saving process time and improving yield. In addition, especially in the case of a narrow gate structure in advanced technology nodes, a thinner adhesive material is beneficial for filling Figure 3C Herein, the term "technology node" may refer to the geometry of a process, such as a critical dimension.

[0072] It should be noted that in some embodiments, the Si layer 226' can attract and / or prevent Al atoms and / or Ti atoms of the work function metal material 222' (ie, the TiAl layer 222') from diffusing into the interface material 212' and / or diffusing into the gaps (ie, Figure 3B In the hollow portion H) shown in FIG, the threshold voltage (Vt) of the device is avoided from shifting and the control capability of the gate structure is improved. In addition, the Si layer 226' can further prevent the Al atoms and / or Ti atoms of the work function metal material 222' from diffusing into the fin 108, thereby reducing leakage current, increasing the breakdown voltage (Vbd) of the device and avoiding the gate dielectric layer 210 (such as Figure 1K (as shown in the figure) is burned out.

[0073] Return Reference Figure 3C and Figure 3D After the cluster material 220' is deposited, a metal material 230' is formed above the cluster material 220' to fill the remaining hollow portion H. In some embodiments, the metal material 230' comprises W, Cu, AlCu, or a combination thereof. The metal material 230' can be formed by using a suitable process, such as ALD, CVD, PVD, plating, or a combination thereof. When the metal material 230' is a tungsten metal material, the precursor for forming the tungsten metal material 230' can include tungsten hexafluoride (WF6) and hydrogen (H2). In some embodiments, the formation of the metal material 230' is performed at a temperature of 250°C to 600°C.

[0074] It should be noted that the metal material 230' is formed ex-situ. As used herein, the term "ex-situ" refers to performing a different deposition process in a different processing system or tool. In other words, Figure 3C The structure 10b shown in FIG. 1 can be transferred between different processing tools. Therefore, during the formation of the metal material 230', the cluster material 220' is exposed to an external environment or an oxygen-containing environment. In this case, an additional TiON layer (not shown) may be formed between the metal material 230' and the bonding material 228'. Since the cluster material 220' is exposed to an external environment or an oxygen-containing environment, external oxygen may diffuse into the cluster material 220'. In some embodiments, the Si layer 226' may prevent external oxygen from diffusing into the work function metal material 222', thereby preventing a shift in the device's threshold voltage (Vt) and improving the control capability of the gate structure. In some alternative embodiments, the Si layer 226' may react with a small amount of external oxygen to form a small amount of silicon oxide (SiO) segments in the Si layer 226'. In this case, in alternative embodiments, the ratio of the silicon content to the oxygen content in the Si layer 226' is at least greater than 3. In other words, only a small amount of oxygen atoms are distributed in the Si layer 226'. Furthermore, since the cluster material 220' is formed in situ, the oxygen content of the entire cluster material 220' is lower than that of an ex-situ formed structure.

[0075] On the other hand, the Si layer 226' also prevents the internal oxygen of the interface material 212' from diffusing into the metal material 230', thereby preventing the gate dielectric layer 210 (eg, Figure 1K Therefore, the oxygen content of the bonding material 228' (eg, the second TiN layer) may be less than or equal to the nitrogen content thereof.

[0076] refer to Figure 3D and Figure 3E, remove the excess layers outside the hollow portion H to form the gate structure 200. In some embodiments, a portion of the interface material 212', a portion of the high-k dielectric material 214', a portion of the cluster material 220', and a portion of the metal material 230' outside the hollow portion H are removed by a planarization process to form an interface layer 212, a high-k layer 214, a cluster layer 220, and a metal layer 230. The cluster layer 220 may sequentially include a work function metal layer formed by a work function metal material 222', a barrier layer formed by a barrier material 224', a cap layer formed by a cap material 226', and an adhesion layer formed by an adhesion material 228'. In some embodiments, the planarization process may include performing a CMP process. In some embodiments, the metal layer 230 may be used as a gate electrode. As Figure 3E As shown in FIG, the interface layer 212, the high-k layer 214, and the cluster layer 220 have U-shaped cross sections. The high-k dielectric layer 214 is sandwiched between the interface layer 212 and the cluster layer 220, and the cluster layer 220 is sandwiched between the high-k dielectric layer 214 and the metal layer 230.

[0077] As mentioned above, the precursor gas used to form the metal layer 230 includes WF6. In some embodiments, fluorine atoms in WF6 may be introduced into the metal layer 230 as impurities. During the formation process of the metal material 230' or in subsequent thermal processes, the fluorine atoms may diffuse into the work function metal material 222' (e.g., Figure 4D ), thereby causing the threshold voltage (Vt) in the device to shift. Therefore, the performance of the device is impaired. However, as mentioned above, since the cap material 226' having amorphous silicon, amorphous carbon or amorphous germanium is sandwiched between the work function metal material 222' and the metal layer 230, the cap material 226' can prevent the fluorine in the metal layer 230 from diffusing into the work function metal layer 222', thereby avoiding the threshold voltage (Vt) shift. Therefore, the performance of the FinFET 10 can be ensured. In addition, since the silicon atoms or aluminum atoms in the cap material 226' can capture fluorine impurities, the cluster layer 220 can be a thin layer while maintaining a sufficient blocking function. In this case, the thin cluster layer 220 is beneficial for filling Figure 3C The hollow portion H shown in FIG. 1 increases the gap filling margin for forming the metal gate.

[0078] Figure 1J to Figure 1K as well as Figure 2J to Figure 2K The process shown in FIG. 1 is generally referred to as a metal replacement process. In some embodiments, the dummy gate structure 112 comprising polysilicon is replaced with a gate structure 200 comprising metal. Since the dummy gate structure 112 is replaced by the gate structure 200, subsequent processes for forming metal interconnects (not shown) can be performed. For example, other conductive lines (not shown) are formed to electrically connect the metal layer 230 to other components in the FinFET 10.

[0079] Figure 10 is a schematic enlarged view of a cluster material of a gate structure according to an alternative embodiment of the present disclosure.

[0080] refer to Figure 10 , the cluster material 320' is similar to Figure 4D That is, the structure, material and function of the cluster material 320' are similar to those of the cluster material 220', and will not be described in detail here. The main difference between the cluster material 320' and the cluster material 220' is the position of the top cover material. Specifically, the cluster material 320' has a top cover material 326' sandwiched between the work function metal material 222' and the barrier material 224'. In some embodiments, the top cover material 326' has the same material as the top cover material 226'. In the case described, the top cover material 326' can attract and / or prevent Al atoms and / or Ti atoms of the work function metal material 222' (i.e., the TiAl layer 222') from diffusing into the interface material 212' and / or diffusing into the gap (i.e., Figure 3B The hollow portion H) is shown in the figure, thereby avoiding the threshold voltage (Vt) shift of the device and improving the control capability of the gate structure.

[0081] Figure 11 is a schematic enlarged view of a cluster material of a gate structure according to other embodiments of the present disclosure.

[0082] refer to Figure 11 , the cluster material 420' is similar to Figure 4D That is, the structure, material and function of the cluster material 420' are similar to those of the cluster material 220', and will not be described in detail here. The main difference between the cluster material 420' and the cluster material 220' is that the cluster material 420' has two top cap materials 226' and the top cap material 326', wherein one top cap material 226' is sandwiched between the barrier material 224' and the adhesive material 228', and the other top cap material 326' is sandwiched between the work function metal material 222' and the barrier material 224'. In some embodiments, the top cap material 226' and the top cap material 326' have the same material or different materials. In the case, both the top cap material 226' and the top cap material 326' can attract and / or prevent Al atoms and / or Ti atoms of the work function metal material 222' (i.e., the TiAl layer 222') from diffusing into the interface material 212' and / or diffusing into the gaps (i.e., Figure 3B The hollow portion H) is shown in the figure, thereby avoiding the threshold voltage (Vt) shift of the device and improving the control capability of the gate structure.

[0083] According to some embodiments, a gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed above the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer includes at least an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer.

[0084] In some embodiments, the cluster layer comprises: a work function metal layer disposed on the gate dielectric layer; a barrier layer disposed on the work function layer; an adhesion layer disposed above the barrier layer; and a first cap layer sandwiched between the barrier layer and the adhesion layer, wherein the first cap layer comprises a first amorphous silicon layer, a first amorphous carbon layer, or a first amorphous germanium layer. In some embodiments, the cluster layer further comprises a plurality of silicon-nitrogen (Si-N) bonds, a plurality of carbon-nitrogen (CN) bonds, or a plurality of germanium-nitrogen (Ge-N) bonds between the first cap layer and the adhesion layer. In some embodiments, the work function metal layer comprises an N-type work function metal layer, and the N-type work function metal layer comprises titanium, aluminum, titanium aluminum, titanium aluminum nitride, aluminum titanium carbide, tantalum, tantalum carbide, tantalum carbonitride, tantalum nitride silicon, or a combination thereof. In some embodiments, the adhesion layer comprises an in-situ adhesion layer, and the in-situ adhesion layer is in direct contact with the first cap layer. In some embodiments, the cluster layer further includes a second cap layer disposed between the work function metal layer and the barrier layer, and the second cap layer includes a second amorphous silicon layer, a second amorphous carbon layer, or a second amorphous germanium layer. In some embodiments, the cluster layer includes: a work function metal layer disposed on the gate dielectric layer; a barrier layer disposed on the work function layer; an adhesion layer disposed on the barrier layer; and a cap layer sandwiched between the work function metal layer and the barrier layer, wherein the cap layer includes the amorphous silicon layer, the amorphous carbon layer, or the amorphous germanium layer.

[0085] According to some embodiments, a method for forming a gate structure includes: forming a gate dielectric layer on a substrate; sequentially and in-situ forming a work function metal layer, a barrier layer, a cap layer, and an adhesion layer by an atomic layer deposition (ALD) process, wherein the cap layer includes an amorphous layer having an IVA group element; and forming a metal layer on the adhesion layer.

[0086] In some embodiments, forming the work function metal layer includes: introducing a first precursor into a first chamber, wherein the first precursor includes titanium; purging the first precursor from the first chamber; introducing a second precursor into the first chamber, wherein the second precursor includes aluminum; and purging the second precursor from the first chamber to form the work function metal layer, wherein the work function metal layer includes at least titanium aluminum. In some embodiments, forming the barrier layer includes: introducing a third precursor into a second chamber, wherein the third precursor includes titanium tetrachloride; purging the third precursor from the second chamber; introducing a fourth precursor into the second chamber, wherein the fourth precursor includes ammonia; and purging the fourth precursor from the second chamber to form the barrier layer, wherein the barrier layer includes titanium nitride. In some embodiments, after forming the barrier layer, the method further includes forming the cap layer by introducing a fifth precursor into the second chamber, wherein the fifth precursor comprises a silane gas selected from the group consisting of dichlorosilane (DCS), tetrachlorosilane (TCS), hexachlorodisilane (HCD), and monosilane, and the cap layer comprises the amorphous silicon layer. In some embodiments, the barrier layer and the cap layer are formed in the same chamber. In some embodiments, forming the adhesion layer includes: introducing a sixth precursor into a third chamber, wherein the sixth precursor comprises titanium tetrachloride; purging the sixth precursor from the third chamber; introducing a seventh precursor into the third chamber, wherein the seventh precursor comprises ammonia; and purging the seventh precursor from the third chamber to form the adhesion layer, wherein the adhesion layer comprises titanium nitride. In some embodiments, the substrate is transferred between different chambers in a single processing tool and maintained under vacuum conditions during the in-situ formation of the work function metal layer, the barrier layer, the cap layer, and the adhesion layer. In some embodiments, the substrate is not exposed to an external environment or an oxygen-containing environment during the in-situ formation of the work function metal layer, the barrier layer, the cap layer, and the adhesion layer. In some embodiments, the forming of the metal layer is an ex-situ process, and a titanium oxynitride layer is formed between the metal layer and the adhesion layer.

[0087] According to some embodiments, a semiconductor device includes a substrate, a gate structure, and a source / drain (S / D) region. The substrate includes at least one fin located thereon. The gate structure covers a portion of the at least one fin, wherein the gate structure includes a gate dielectric layer contacting the at least one fin, a metal layer, and a cluster layer sandwiched between the metal layer and the gate dielectric layer. The cluster layer includes: a work function metal layer disposed on the gate dielectric layer; a barrier layer disposed on the work function layer; an adhesion layer disposed above the barrier layer; and a first cap layer sandwiched between the barrier layer and the adhesion layer. The first cap layer includes an IVA group element, and a plurality of silicon-nitrogen (Si-N) bonds, a plurality of carbon-nitrogen (CN) bonds, or a plurality of germanium-nitrogen (Ge-N) bonds are formed between the first cap layer and the adhesion layer. The source / drain (S / D) region is disposed on an opposite side of the at least one fin relative to the gate structure.

[0088] In some embodiments, the semiconductor device comprises an N-type metal oxide semiconductor (NMOS) fin field effect transistor, the work function metal layer comprises an N-type work function metal layer, and the N-type work function metal layer comprises titanium, aluminum, titanium aluminum, titanium aluminum nitride, titanium aluminum carbide, tantalum, tantalum carbide, tantalum carbonitride, tantalum nitride silicon, or a combination thereof. In some embodiments, the first cap layer comprises a first amorphous silicon layer, a first amorphous carbon layer, or a first amorphous germanium layer. In some embodiments, the cluster layer further comprises a second cap layer disposed between the work function metal layer and the barrier layer, and the second cap layer comprises a second amorphous silicon layer, a second amorphous carbon layer, or a second amorphous germanium layer.

[0089] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A gate structure comprising: a metal layer disposed above the gate dielectric layer; a cluster layer, sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer comprises at least a work function metal layer, a barrier layer, an adhesion layer and a cap layer; as well as A titanium oxynitride layer is disposed between the metal layer and the cluster layer.

2. The gate structure according to claim 1, wherein: The work function metal layer is disposed on the gate dielectric layer; The barrier layer is disposed on the work function metal layer; The adhesive layer is disposed above the barrier layer; as well as The top cap layer is a first top cap layer sandwiched between the barrier layer and the adhesion layer, wherein the first top cap layer includes a first amorphous silicon layer, a first amorphous carbon layer or a first amorphous germanium layer. 3 . The gate structure according to claim 2 , wherein the cluster layer further comprises a plurality of silicon-nitrogen (Si—N) bonds, a plurality of carbon-nitrogen (CN) bonds, or a plurality of germanium-nitrogen (Ge—N) bonds between the first cap layer and the adhesion layer.

4. The gate structure according to claim 2, wherein the work function metal layer comprises an N-type work function metal layer, and the N-type work function metal layer comprises titanium, aluminum, titanium aluminum, titanium aluminum nitride, titanium aluminum carbide, tantalum, tantalum carbide, tantalum carbonitride, tantalum nitride silicon, or a combination thereof. 5 . The gate structure according to claim 2 , wherein the adhesion layer comprises an in-situ adhesion layer, and the in-situ adhesion layer is in direct contact with the first cap layer. 6 . The gate structure according to claim 2 , wherein the cluster layer further comprises a second capping layer disposed between the work function metal layer and the barrier layer, and the second capping layer comprises a second amorphous silicon layer, a second amorphous carbon layer, or a second amorphous germanium layer.

7. The gate structure according to claim 1 , wherein: The work function metal layer is disposed on the gate dielectric layer; The barrier layer is disposed on the work function metal layer; the adhesive layer disposed on the barrier layer; and The top cover layer is sandwiched between the work function metal layer and the barrier layer, wherein the top cover layer includes an amorphous silicon layer, an amorphous carbon layer or an amorphous germanium layer.

8. A method for forming a gate structure, comprising: forming a gate dielectric layer on the substrate; sequentially and in-situ forming a work function metal layer, a barrier layer, a cap layer, and an adhesion layer by an atomic layer deposition (ALD) process, wherein the cap layer comprises an amorphous layer having a Group IVA element; as well as A metal layer is formed on the adhesion layer, wherein the forming of the metal layer is an ex-situ process, and a titanium oxynitride layer is formed between the metal layer and the adhesion layer.

9. The method for forming a gate structure according to claim 8, wherein forming the work function metal layer comprises: introducing a first precursor into a first chamber, wherein the first precursor comprises titanium; purging the first precursor in the first chamber; introducing a second precursor into the first chamber, wherein the second precursor comprises aluminum; and The second precursor is purged in the first chamber to form the work function metal layer, wherein the work function metal layer includes at least titanium aluminum.

10. The method for forming a gate structure according to claim 9, wherein forming the barrier layer comprises: introducing a third precursor into the second chamber, wherein the third precursor comprises titanium tetrachloride; purging the third precursor in the second chamber; introducing a fourth precursor into the second chamber, wherein the fourth precursor comprises ammonia gas; and The fourth precursor in the second chamber is purged to form the barrier layer, wherein the barrier layer comprises titanium nitride.

11. The method for forming a gate structure according to claim 10 , after forming the barrier layer, further comprising forming the cap layer by introducing a fifth precursor into the second chamber, wherein the fifth precursor comprises a silane gas selected from the group consisting of dichlorosilane (DCS), tetrachlorosilane (TCS), hexachlorodisilane (HCD), and monosilane, and the cap layer comprises an amorphous silicon layer. 12 . The method for forming a gate structure according to claim 11 , wherein the barrier layer and the cap layer are formed in a same chamber.

13. The method for forming a gate structure according to claim 11, wherein forming the adhesion layer comprises: introducing a sixth precursor into the third chamber, wherein the sixth precursor comprises titanium tetrachloride; purging the sixth precursor in the third chamber; introducing a seventh precursor into the third chamber, wherein the seventh precursor comprises ammonia gas; and The seventh precursor in the third chamber is purged to form the adhesion layer, wherein the adhesion layer includes titanium nitride.

14. The method of forming a gate structure according to claim 8, wherein the substrate is transferred between different chambers in a single processing tool and maintained under vacuum conditions during the in-situ formation of the work function metal layer, the barrier layer, the cap layer, and the adhesion layer. 15 . The method for forming a gate structure according to claim 8 , wherein during the in-situ forming of the work function metal layer, the barrier layer, the cap layer, and the adhesion layer, the substrate is not exposed to an external environment or an oxygen-containing environment.

16. A semiconductor device comprising: a substrate including at least one fin located thereon; a gate structure covering a portion of the at least one fin, wherein the gate structure includes a gate dielectric layer contacting the at least one fin, a metal layer, and a cluster layer sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer includes: a work function metal layer disposed on the gate dielectric layer; a barrier layer disposed on the work function metal layer; an adhesive layer disposed over the barrier layer; and a first cap layer sandwiched between the barrier layer and the adhesion layer, wherein the first cap layer and the adhesion layer have a plurality of silicon-nitrogen (Si-N) bonds, a plurality of carbon-nitrogen (CN) bonds, or a plurality of germanium-nitrogen (Ge-N) bonds; a source / drain (S / D) region disposed on an opposite side of the at least one fin relative to the gate structure; and A titanium oxynitride layer is disposed between the metal layer and the adhesive layer.

17. The semiconductor device according to claim 16, wherein the fin field effect transistor comprises an N-type metal oxide semiconductor (NMOS) fin field effect transistor, the work function metal layer comprises an N-type work function metal layer, and the N-type work function metal layer comprises titanium, aluminum, titanium aluminum, titanium aluminum nitride, titanium aluminum carbide, tantalum, tantalum carbide, tantalum carbonitride, tantalum nitride silicon or a combination thereof. 18 . The semiconductor device according to claim 16 , wherein the first cap layer comprises a first amorphous silicon layer, a first amorphous carbon layer, or a first amorphous germanium layer. 19 . The semiconductor device according to claim 16 , wherein the cluster layer further comprises a second cap layer disposed between the work function metal layer and the barrier layer, and the second cap layer comprises a second amorphous silicon layer, a second amorphous carbon layer, or a second amorphous germanium layer.

20. A method for forming a gate structure, comprising: forming a gate dielectric layer on the substrate; forming a cluster layer on the gate dielectric layer by an atomic layer deposition (ALD) process, wherein the cluster layer comprises at least: a work function metal layer, a first cap layer, a barrier layer, and an adhesion layer, wherein the work function metal layer directly contacts the gate dielectric layer, the first cap layer directly contacts the work function metal layer, and the first cap layer comprises a first amorphous layer having an IVA group element; and A metal layer is formed on the adhesive layer.

21. A method of forming a semiconductor device, comprising: providing a substrate including at least one fin thereon; forming a gate structure covering a portion of the at least one fin, wherein the gate structure includes a gate dielectric layer contacting the at least one fin, a metal layer, and a cluster layer sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer includes at least: A work function metal layer is formed on the gate dielectric layer; A barrier layer is formed on the work function metal layer; an adhesive layer formed over the barrier layer; and a first cap layer formed between the barrier layer and the adhesion layer, wherein the first cap layer includes an amorphous carbon layer, and a plurality of carbon-nitrogen (CN) bonds are formed between the first cap layer and the adhesion layer, wherein the metal layer is formed in an ex-situ process, and a titanium oxynitride layer is formed between the metal layer and the adhesion layer; and Source / drain (S / D) regions are formed on opposite sides of the at least one fin relative to the gate structure.

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