Variable resistance memory device

Abstract

A variable resistance memory device is provided, including a first conductive line structure having an adiabatic line therein on a substrate, a variable resistance pattern contacting an upper surface of the first conductive line structure, a low resistance pattern contacting an upper surface of the variable resistance pattern, a selection structure on the low resistance pattern, and a second conductive line on the selection structure.

Description

[0001] Korean Patent Application No. 10-2019-0088777, entitled "Variable resistance memory device and method of manufacturing variable resistance memory device," filed on July 23, 2019, in the Korean Intellectual Property Office, is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments relate to a variable resistance memory device and a method of manufacturing the same. BACKGROUND

[0003] In the method of manufacturing the PRAM device, the lower electrode, the variable resistance pattern, and / or the upper electrode can be formed by a damascene process, and a height-to-width ratio of a mold in which the lower electrode, the variable resistance pattern, and / or the upper electrode can be formed can increase. SUMMARY

[0004] Embodiments can be realized by providing a variable resistance memory device including a first wire structure on a substrate, the first wire structure having an adiabatic line therein, at least one variable resistance pattern contacting an upper surface of the first wire structure, a low resistance pattern contacting an upper surface of the at least one variable resistance pattern, a selection structure on the low resistance pattern, and a second wire on the selection structure.

[0005] Embodiments can be realized by providing a variable resistance memory device including a first wire structure on a substrate, the first wire structure extending in a first direction substantially parallel to an upper surface of the substrate, variable resistance patterns spaced apart from each other in the first direction, each of the variable resistance patterns contacting the upper surface of the first wire structure, a mold and a fill structure on the first wire structure, the mold and the fill structure alternately arranged in respective spaces between adjacent ones of the variable resistance patterns in the first direction, an etch stop pattern on the mold, a low resistance pattern contacting an upper surface of a respective one of the variable resistance patterns, and a selection structure on the low resistance pattern.

[0006] Embodiments can be realized by providing a variable resistance memory device including: first conductive line structures spaced apart from each other in a second direction on a substrate, each of the first conductive line structures extending in a first direction, each of the first and second directions being substantially parallel to an upper surface of the substrate, and the first direction crossing the second direction; second conductive lines spaced apart from each other in the first direction on the first conductive line structures, each of the second conductive lines extending in the second direction; variable resistance patterns between the first conductive line structures and the second conductive lines at respective regions where the first conductive line structures and the second conductive lines are stacked on each other in a third direction substantially perpendicular to the upper surface of the substrate, the variable resistance patterns respectively contacting upper surfaces of the first conductive line structures; a fill structure including first portions extending in the first direction on the substrate between the first conductive line structures and second portions extending from the first portions in the second direction on the first conductive line structures, the first portions contacting each of opposite sidewalls of the variable resistance patterns in the second direction, each of the second portions contacting a sidewall of a corresponding one of the variable resistance patterns in the first direction; a mold on each of the first conductive line structures, each of the molds contacting the sidewall of the corresponding one of the variable resistance patterns in the first direction and the sidewall not contacting each of the second portions; a low resistance pattern contacting the upper surfaces of each of the variable resistance patterns; and a selection structure on the low resistance pattern, wherein each of the first conductive line structures includes an adiabatic line between the first conductive lines in the third direction, and wherein the selection structure includes a first buffer, a selection pattern, and a second buffer sequentially stacked in the third direction.

[0007] Embodiments can be realized by providing a method of manufacturing a variable resistance memory device, the method including: forming first conductive layer structures on a substrate; forming spacer lines, mold lines, and first fill lines on the first conductive layer structures, the spacer lines being spaced apart from each other in a first direction substantially parallel to an upper surface of the substrate, and the mold lines and the first fill lines being alternately arranged in respective spaces between the spacer lines in the first direction; patterning the spacer lines, the first fill lines, the mold lines, and the first conductive layer structures to respectively form spacer patterns, first fill patterns, molds, and first conductive line structures, the first conductive line structures being spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, each of the first conductive line structures extending in the first direction, and each of the first conductive line structures and the spacer patterns, the first fill patterns, and the molds on each of the first conductive line structures forming a first stack structure; forming second fill lines on the substrate in a second direction between adjacent ones of the first stack structures; replacing the spacer patterns with variable resistance patterns, respectively; and forming a low resistance pattern and a selection pattern sequentially stacked on each of the variable resistance patterns.

[0008] Embodiments can be realized by providing a method of manufacturing a variable resistance memory device, the method including: forming conductor line structures on a substrate, each conductor line structure extending in a first direction substantially parallel to an upper surface of the substrate, and the conductor line structures being spaced apart from each other by first insulating interlayers in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction; forming spacer lines, mold lines, and first fill lines on the conductor line structures and the first insulating interlayers, the spacer lines being spaced apart from each other along the first direction, the mold lines and the first fill lines being alternately arranged in respective spaces between the spacer lines along the first direction, and each mold line having an etch stop line thereon; patterning the spacer lines, the first fill lines, the mold lines, and the etch stop lines to form stack structures spaced apart from each other in the second direction by first openings each exposing an upper surface of the first insulating interlayers and extending in the first direction, a spacer pattern, a first fill pattern, a mold piece, and an etch stop pattern being formed from the spacer lines, the first fill lines, the mold lines, and the etch stop lines, respectively, on each conductor line structure; forming a second fill layer on the first insulating interlayers and the exposed upper surfaces of the stack structures to fill the first openings; planarizing the second fill layer until the etch stop patterns are exposed to form second fill lines in the first openings, respectively; replacing the spacer patterns with variable resistance patterns, respectively; and forming a low resistance pattern and a selection structure sequentially stacked on each variable resistance pattern.

[0009] Embodiments can be realized by providing a method of manufacturing a variable resistance memory device, the method including: forming conductor line structures on a substrate, each conductor line structure extending in a first direction substantially parallel to an upper surface of the substrate, and the conductor line structures being spaced apart from each other by first insulating interlayers in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction; forming spacer lines, mold lines, and first fill lines on the conductor line structures and the first insulating interlayers, the spacer lines being spaced apart from each other along the first direction, the mold lines and the first fill lines being alternately arranged in respective spaces between the spacer lines along the first direction, and each mold line having an etch stop line thereon; patterning the spacer lines, the first fill lines, the mold lines, and the etch stop lines to form stack structures spaced apart from each other in the second direction by first openings each exposing an upper surface of the first insulating interlayers and extending in the first direction, a spacer pattern, a first fill pattern, a mold piece, and an etch stop pattern being formed from the spacer lines, the first fill lines, the mold lines, and the etch stop lines, respectively, on each conductor line structure; forming a second fill layer on the first insulating interlayers and the exposed upper surfaces of the stack structures to fill the first openings; planarizing the second fill layer until the etch stop patterns are exposed to form second fill lines in the first openings, respectively; replacing the spacer patterns with variable resistance patterns, respectively; and forming a low resistance pattern and a selection structure sequentially stacked on each variable resistance pattern. BRIEF DESCRIPTION OF DRAWINGS

[0010] Features will become apparent to those of ordinary skill in the art upon examination of the following detailed description of example embodiments taken in conjunction with the accompanying drawings.

[0011] Figures 1 to 15 Perspective views showing stages in a method of manufacturing a variable resistance memory device according to an example embodiment are shown.

[0012] Figures 16 to 20 Perspective views showing stages in a method of manufacturing a variable resistance memory device according to an example embodiment are shown.

[0013] Figures 21 to 23 Perspective views showing stages in a method of manufacturing a variable resistance memory device according to an example embodiment are shown. DETAILED DESCRIPTION

[0014] Figures 1 to 15 Perspective views showing stages in a method of manufacturing a variable resistance memory device according to an example embodiment are shown.

[0015] Hereinafter, in the specification (but not in the claims), two directions intersecting each other among horizontal directions substantially parallel to the upper surface of the substrate are defined as a first direction and a second direction, respectively, and a vertical direction substantially perpendicular to the upper surface of the substrate is defined as a third direction. In example embodiments, the first direction and the second direction can be orthogonal to each other.

[0016] REFERENCE Figure 1 The first insulating interlayer 110, the first conductive layer structure 140, the molding layer 160, the etching stop layer 170, and the first mask layer 180 can be sequentially stacked on the substrate 100.

[0017] The substrate 100 can include a semiconductor material (e.g., silicon, germanium, silicon-germanium, etc.) or a III-V compound (e.g., GaP, GaAs, GaSb, etc.). In an implementation, the substrate 100 can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0018] In an implementation, various other elements (e.g., gate structures, source / drain layers, contact plugs, vias, wiring, etc.) can be formed on the substrate 100 and can be covered by the first insulating interlayer 110. The first insulating interlayer 110 can include an oxide, e.g., silicon oxide.

[0019] The first conductive layer structure 140 can include the first conductive layer 120, the thermal insulation layer 130, and another first conductive layer 120, which are sequentially stacked. For example, the first conductive layer structure 140 can have a structure in which the thermal insulation layer 130 is interposed or sandwiched between two of the first conductive layers 120, and can have a low thermal conductivity.

[0020] The first conductive layer 120 can include a metal, for example, tungsten (W), platinum (Pt), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), etc. In an embodiment, a first barrier layer including a metal nitride or a metal silicon nitride, for example, titanium nitride (TiN x ), titanium silicon nitride (TiSiN x ), tungsten nitride (WN x ), tungsten silicon nitride (WSiN x ), tantalum nitride (TaN x ), tantalum silicon nitride (TaSiN x ), etc., can be further formed between the first insulating interlayer 110 and the first conductive layer 120.

[0021] The thermal insulation layer 130 can include a material having a thermal conductivity smaller than that of the first conductive layer 120, and can prevent heat transferred from the first conductive layer 120 from being discharged by the first conductive layer structure 140. In an embodiment, the thermal insulation layer 130 can include, for example, carbon (e.g., pure carbon), a carbon compound, or a carbon-containing metal. In an embodiment, the thermal insulation layer 130 can include, for example, carbon, carbon nitride, titanium carbon nitride, tantalum carbon nitride. As used herein, the term "or" is not an exclusive term, for example, "A or B" will include A, B, or A and B.

[0022] The molding layer 160 can include a nitride, for example, silicon nitride, the etching stop layer 170 can include, for example, carbon, a carbon compound, polysilicon, etc., and the first mask layer 180 can include an oxide, for example, silicon oxide.

[0023] Referring to Figure 2 , the first mask layer 180 can be patterned to form a plurality of first masks 182 spaced apart from each other in the first direction by using a double patterning process or a photolithography process of EUV, each of the plurality of first masks 182 can extend in the second direction (e.g., longitudinally), and the etching stop layer 170 and the molding layer 160 can be patterned to form etching stop lines 172 and molding lines 162, respectively, using the first masks 182 as etching masks, each of the etching stop lines 172 and the molding lines 162 can extend in the second direction.

[0024] The molding lines 162, the etching stop lines 172, and the first masks 182 sequentially stacked on the first conductive layer structure 140 can be referred to as a first stacked structure. In an embodiment, the first stacked structure can extend in the second direction (e.g., longitudinally), and a plurality of first stacked structures can be spaced apart from each other in the first direction. The first openings 190 can be located between adjacent ones of the first stacked structures in the first direction to expose an upper surface of the first conductive layer structure 140.

[0025] Referring to Figure 3 A spacer layer 200 can be formed on the sidewalls of the first openings 190, the exposed upper surface of the first conductive layer structure 140 by the first openings 190, and the upper surface of the first mask 182.

[0026] In an embodiment, the spacer layer 200 can be formed by an atomic layer deposition (ALD) process. The spacer layer 200 can include an oxide (e.g., silicon oxide), and can include substantially the same material as the material of the first mask 182 to merge with the first mask 182.

[0027] Referring to Figure 4 The spacer layer 200 can be partially removed by, for example, an etch-back process.

[0028] The spacer layer 200 can be removed by the etch-back process on the upper surface of the first mask 182 and the exposed upper surface of the first conductive layer structure 140, and can also remove a portion of the first mask 182, for example, the upper sidewall of the first mask 182. Through the etch-back process, the spacer layer 200 can become a spacer line 202 extending in the second direction on each of the opposite sidewalls of the first stack structure in the first direction, for example, the etch-back process can convert the spacer layer 200 into the spacer line 202.

[0029] In an embodiment, the entrance of the first opening 190, for example, the upper portion of the first opening 190, for example, the opening end, can be enlarged by the etch-back process.

[0030] Referring to Figure 5 A first fill layer 210 can be formed on the first conductive layer structure 140, the spacer line 202, and the first stack structure to fill the first opening 190.

[0031] As described above, the upper portion of the first opening 190 can be enlarged, and the first fill layer 210 can completely fill the first opening 190, for example, in which a gap or a void can not be generated. In an embodiment, even if a gap or a void is generated, it can be formed only at the upper portion of the first opening 190.

[0032] The first fill layer 210 can include an insulating material, for example, silicon nitride, silicon oxycarbide, or the like.

[0033] Referring to Figure 6 An upper portion of the first fill layer 210 can be planarized to form a plurality of first fill lines 212, each of which can extend in the second direction and can be spaced apart from each other in the first direction.

[0034] The planarization process can include a chemical mechanical polishing (CMP) process and / or an etch-back process. The planarization process can be performed until the upper surface of the etch stop line 172 is exposed, and the first mask 182 of the first stack structure can also be removed. The etch stop line 172 can be located on the molding line 162, and the molding line 162 can have a uniform height without or with little distribution according to its location.

[0035] Through the planarization process, the molding lines 162 and the first filling lines 212 can be alternately arranged on the first conductive layer structure 140 along the first direction, the spacer lines 202 can be located between the molding lines 162 and the first filling lines 212, and the etch stop line 172 can be located on each molding line 162.

[0036] Because the gap or void is formed at the upper portion of the first opening 190 (e.g., further away from the substrate 100 than the etch stop line 172), if the gap or void is generated in the first filling layer 210, the gap or void can be removed during the planarization process.

[0037] Referring to Figure 7 A second mask layer can be formed on the etch stop line 172, the first filling line 212, and the spacer line 202, and the second mask layer can be patterned to form a plurality of second masks spaced apart from each other in a second direction by using, for example, a double patterning process or a lithography process of EUV, each of the plurality of second masks can extend in the first direction. The etch stop line 172, the molding line 162, the first filling line 212, the spacer line 202, and the first conductive layer structure 140 can be etched using the second mask as an etching mask.

[0038] The etching process can be performed until the upper surface of the first insulating interlayer 110 is exposed, and then the upper portion of the first insulating interlayer 110 can also be etched. Through the etching process, the etch stop line 172, the molding line 162, the first filling line 212, and the spacer line 202, each of which can extend in the second direction, can be transformed into a plurality of etch stop patterns 174, a plurality of moldings 164, a plurality of first filling patterns 214, and a plurality of spacers 204, each of which can be spaced apart from each other in the second direction.

[0039] In an embodiment, the first conductive layer structure 140 can be transformed into a plurality of first wire structures 142, each of which can extend in the first direction (e.g., longitudinally) and can be spaced apart from each other in the second direction, e.g., an etching process can transform the first conductive layer structure 140 into the plurality of first wire structures 142. Each first wire structure 142 can include a first wire 122, an adiabatic line 132, and another first wire 122 sequentially stacked. In an embodiment, each first wire structure 142 can function as a word line of the variable resistance memory device. In an embodiment, each first wire structure 142 can function as a bit line of the variable resistance memory device.

[0040] The first wire structure 142, the molding 164, the etching stop pattern 174, the first fill pattern 214, and the spacer 204 stacked on the first insulating interlayer 110 can be referred to as a second stacked structure. In an embodiment, the second stacked structure can extend in the first direction, and a plurality of second stacked structures can be spaced apart from each other in the second direction. The second opening 220 can be located between adjacent second stacked structures among the second stacked structures in the second direction to expose the upper surface of the first insulating interlayer 110.

[0041] Referring to Figure 8 A second fill layer 230 can be formed on the first insulating interlayer 110 and the second stacked structure to fill the second opening 220.

[0042] The second fill layer 230 can include, for example, silicon nitride, silicon oxycarbide, etc. In an embodiment, the second fill layer 230 can include substantially the same material as that of the first fill pattern 214, and can be merged with the first fill pattern 214.

[0043] Referring to Figure 9 An upper portion of the second fill layer 230 can be planarized to form a plurality of second fill lines 232 spaced apart from each other in the second direction, each of which can extend in the first direction.

[0044] The planarization process can include, for example, a CMP process and / or a back-etching process. The planarization process can be performed until the upper surface of the etching stop pattern 174 is exposed. For example, each of the molding 164 and the first fill pattern 214 can have a uniform height without or with little distribution according to its position when the planarization process is performed.

[0045] As described above, the second fill lines 232 can be merged with the first fill pattern 214, and a fill structure 240 can be formed. The second fill lines 232 and the first fill pattern 214 can be referred to as first and second portions 232 and 214 of the fill structure 240, respectively.

[0046] The first portion 232 of the fill structure 240 can cover each of the opposing sidewalls of the second stack structure in the second direction, and the second portion 214 of the fill structure 240 can cover the sidewall of the spacer 204 in the first direction. In an embodiment, a bottom surface of the first portion 232 of the fill structure 240 can be lower than a bottom surface of the first wire structure 142 (e.g., a distance in the third direction from the substrate 100 to the bottom surface of the first portion 232 of the fill structure 240 can be less than a distance in the third direction from the substrate 100 to the bottom surface of the first wire structure 142), and can also be lower than a bottom surface of the second portion 214 of the fill structure 240 that contacts the upper surface of the first wire structure 142. An upper surface of the fill structure 240 can be substantially coplanar with an upper surface of the etch stop pattern 174.

[0047] Referring to Figure 10 The spacer 204 can be removed to form the third openings 250, respectively, exposing the upper surfaces of the first wire structures 142.

[0048] In an embodiment, the spacer 204 can be removed by a wet etching process. The first wire structures 142 under the spacer 204 can serve as an etch stop pattern, and the third openings 250 formed by the wet etching process can have a uniform depth without or with little distribution according to their positions.

[0049] Referring to Figure 11 A variable resistance layer 260 can be formed on the first wire structures 142, the etch stop pattern 174, and the fill structure 240 to fill the third openings 250.

[0050] In an embodiment, the variable resistance layer 260 can include a phase change material whose resistance can vary according to its phase. In an embodiment, the variable resistance layer 260 can include a chalcogenide-based material in which germanium (Ge), antimony (Sb), or tellurium (Te) can be combined in a given ratio. In an embodiment, the variable resistance layer 260 can include a superlattice in which germanium telluride (GeTe) and antimony telluride (SbTe) can be repeatedly stacked. In an embodiment, the variable resistance layer 260 can include IST including indium-antimony-tellurium or BST including bismuth-antimony-tellurium. The variable resistance layer 260 can further include, for example, carbon (C), nitrogen (N), boron (B), oxygen (O), etc.

[0051] In an embodiment, the variable resistance layer 260 can include a perovskite material or a transition metal oxide. The perovskite material can include, for example, STO (SrTiO3), BTO (BaTiO3), PCMO (Pr 1-x Ca x MnO3), etc. The transition metal oxide can include, for example, titanium oxide (TiOx ), zirconium oxide (ZrO x ), aluminum oxide (AlO x ), hafnium oxide (HfO x ), etc. These can be used alone or in combination thereof.

[0052] Referring to Figure 12 The upper portion of the variable resistance layer 260 can be planarized to form a plurality of variable resistance patterns 264 arranged in each of the first direction and the second direction.

[0053] The planarization process can include a CMP process and / or a back-etching process. The planarization process can be performed until the upper surface of the etch stop pattern 174 is exposed. For example, the variable resistance patterns 264 can have a uniform height without or with little distribution according to their positions after the planarization process.

[0054] Referring to Figure 13 A low resistance layer and a selection layer structure can be formed on the etch stop pattern 174, the variable resistance patterns 264, and the fill structure 240. A third mask layer can be formed on the selection layer structure, and the third mask layer can be patterned by using a lithography process of EUV or a double patterning process to form a plurality of third masks spaced apart from each other in the second direction, each of the plurality of third masks can extend in the first direction.

[0055] The selection layer structure and the low resistance layer can be etched by an etching process using the third mask as an etching mask to form a selection line structure 312 and a low resistance line 272, respectively, and the low resistance line 272 and the selection line structure 312 sequentially stacked can be referred to as a third stacked structure. In an embodiment, the third stacked structure can extend in the first direction, and a plurality of third stacked structures can be spaced apart from each other in the second direction. A fourth opening 320 can be formed between adjacent third stacked structures among the third stacked structures in the second direction to expose the upper surface of the fill structure 240.

[0056] In an embodiment, the third stacked structure can be located on the variable resistance patterns 264 and the etch stop pattern 174 arranged along the first direction and on the portion of the fill structure 240 between the variable resistance patterns 264 arranged along the first direction. The width of the third stacked structure in the second direction can be equal to or greater than the width of each variable resistance pattern 264 and each etch stop pattern 174 in the second direction.

[0057] The low resistance line 272 can include a metal having a lower resistance than the variable resistance pattern 264. In an embodiment, the low resistance line 272 can include substantially the same metal as the metal of the first conductive layer 120, for example, tungsten, platinum, copper, aluminum, titanium, tantalum, etc.

[0058] The selection line structure 312 can include the first buffer line 282, the selection line 292, and the second buffer line 302, which are sequentially stacked.

[0059] Each of the first buffer line 282 and the second buffer line 302 can include, for example, carbon, a carbon compound, or a carbon-containing metal. For example, each of the first buffer line 282 and the second buffer line 302 can include carbon, carbon nitride, titanium carbon nitride, or tantalum carbon nitride. In an embodiment, the first buffer line 282 can include a material having low thermal conductivity, which is the same as a material of the adiabatic line 132, and can have a thermal conductivity lower than that of the low resistance line 272, can prevent heat transferred from the low resistance line 272 from being discharged by the selection line structure 312.

[0060] In an embodiment, the selection line 292 can include an OTS (Ovonic threshold switch) material, which can function as a switching function while maintaining an amorphous state due to a difference in resistance according to an applied voltage.

[0061] The OTS material can include, for example, germanium (Ge), silicon (Si), arsenic (As), or tellurium (Te), and can further include selenium (Se), sulfur (S), carbon (C), nitrogen (N), indium (In), boron (B), etc.

[0062] The OTS material can include, for example, AsTeGeSiIn, GeTe, SnTe, GeSe, SnSe, AsTeGeSiSbS, AsTeGeSiInP, AsTeGeSi, As2Te3Ge, As2Se3Ge, As 25 (Te 90 Ge 10 ) 75 , Te 40 As 35 Si 18 Ge 6.75 In 0.25 , Te 28 As 34.5 Ge 15.5 S 22 , Te 39 As 36 Si 17 Ge7P, As 10 Te 21 S2Ge 15 Se 50 Sb2, Si5Te 34 As 28 Ge 11 S 21Se1, AsTeGeSiSeNS, AsTeGeSiP, AsSe, AsGeSe, AsTeGeSe, ZnTe, GeTePb, GeSeTe, AlAsTe, SeAsGeC, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, GeAsBiSe, Ge x Se 1-x (wherein, 0 < x < 1), etc.

[0063] Referring Figure 14 The second insulating interlayer line 332 can be formed to fill the fourth opening 320, and the second conductive layer 340 can be formed on the third stack structure and the second insulating interlayer line 332.

[0064] The second insulating interlayer line 332 can include an oxide, for example, silicon oxide, and the second conductive layer 340 can include a metal, for example, tungsten, platinum, copper, aluminum, titanium, tantalum, etc. In an embodiment, a second barrier layer can also be formed to cover a bottom surface of the second conductive layer 340.

[0065] Referring Figure 15 A fourth mask layer can be formed on the second conductive layer 340, and the fourth mask layer can be patterned to form a plurality of fourth masks spaced apart from each other in the first direction by using a double patterning process or a lithography process of EUV, each of the plurality of fourth masks can extend in the second direction. The second conductive layer 340, the select line structure 312, the low resistance line 272, and the second insulating interlayer line 332 can be etched using the fourth mask as an etching mask to form a second conductive line 342, a select structure 314, a low resistance pattern 274, and a second insulating interlayer pattern 334, respectively.

[0066] The second conductive line 342 can extend in the second direction, and a plurality of second conductive lines 342 can be formed to be spaced apart from each other in the first direction. The plurality of low resistance patterns 274, the plurality of select structures 314, and the plurality of second insulating interlayer patterns 334 can be formed in each of the first direction and the second direction. The select structure 314 can include the first buffer 284, the select pattern 294, and the second buffer 304, which are sequentially stacked.

[0067] The low resistance pattern 274, the select structure 314, the second insulating interlayer pattern 334, and the second conductive line 342 can be referred to as a fourth stack structure. The fourth stack structure can extend in the second direction, and a plurality of fourth stack structures can be formed to be spaced apart from each other in the first direction. A fifth opening 350 can be located between adjacent ones of the fourth stack structures in the first direction to expose an upper surface of the fill structure 240.

[0068] In an embodiment, the fourth stack structure can be located on the variable resistance pattern 264 arranged in the second direction and on the portions of the fill structure 240 located between the variable resistance patterns 264. The width of the fourth stack structure in the first direction can be equal to or greater than the width of the variable resistance pattern 264 in the first direction.

[0069] In an embodiment, the second conductive line 342 can function as a bit line of the variable resistance memory device. In an embodiment, the second conductive line 342 can function as a word line of the variable resistance memory device.

[0070] In an embodiment, a cap layer can be formed on the etch stop pattern 174 and the fill structure 240 to cover the fourth stack structure, a third insulating interlayer can be formed on the cap layer to fill the fifth opening 350, and the third insulating interlayer and the cap layer can be planarized until the upper surface of the fourth stack structure can be exposed.

[0071] The cap layer can include, for example, amorphous silicon or a nitride such as silicon nitride, silicon oxynitride, silicon carbon nitride, silicon boron nitride, or the like. Due to the cap layer, the selection pattern 294 of the fourth stack structure can be prevented from being oxidized, and moisture or chemical residues can be prevented from penetrating into the selection pattern 294. The third insulating interlayer can include an oxide, for example, silicon oxide.

[0072] Through the above-described processes, the variable resistance memory device can be manufactured.

[0073] As described above, the upper portion of the first opening 190 can be enlarged so that a gap or a void is not generated in the first fill layer 210 in the first opening 190 or a gap or a void can be generated at the upper portion of the first opening 190 so as to remove the gap or the void during a planarization process for the first fill layer 210. The etch stop line 172 can be formed on the molding line 162 so that the first fill line 212 that can be formed by the planarization process for the first fill layer 210 can have a uniform height without or with little distribution according to its position.

[0074] When the etch stop line 172, the molding line 162, the first fill line 212, and the spacer line 202 are etched to form the etch stop pattern 174, the molding 164, the first fill pattern 214, and the spacer 204, respectively, the first conductive layer structure 140 can also be etched to form the first conductive line structure 142, and the entire process can be simplified when compared to performing an additional etching process for the first conductive layer structure 140.

[0075] In an embodiment, the etch stop pattern 174 can be formed on the mold 164, and the second fill line 232 formed by planarizing the second fill layer 230 and the mold 164 adjacent to the second fill line 232 can have a uniform height without or with little distribution according to its position.

[0076] During a wet etching process for removing the spacers 204 to form the third openings 250, the first conductive line structure 142 under the spacers 204 can serve as an etch stop pattern, and the third openings 250 can have a uniform depth without or with little distribution according to its position, and the variable resistance pattern 264 in each of the third openings 250 can also have a uniform thickness.

[0077] In an embodiment, only the variable resistance pattern 264 can be formed in the third opening 250, and the spacers 204 (through which the third openings 250 can be formed) or the mold 164 having a similar height can have a low aspect ratio. For example, each of the first fill layer 210 filling the first openings 190 between the mold lines 162, the second fill layer 230 filling the second openings 220 between the second stacked structures, and the variable resistance pattern 264 filling the third openings 250 can not have a gap or a void therein.

[0078] In the variable resistance memory device manufactured by the above process, the variable resistance pattern 264 can be located between the first conductive line structure 142 and the low resistance pattern 274, each of the first conductive line structure 142 and the low resistance pattern 274 can have a relatively low resistance. For example, when an electrical signal is applied to the first conductive line 122 and the second conductive line 342, heat can be generated in the variable resistance pattern 264 even without heating by an external electrode, and the phase of the variable resistance pattern 264 can change due to the generated heat. As a result, the variable resistance pattern 264 can serve as a memory cell of the variable resistance memory device.

[0079] To prevent the generated heat from being discharged outward, the first conductive line structure 142 (under the variable resistance pattern 264) can include the heat insulating line 132 having a low thermal conductivity, and the first buffer 284 can be located on the low resistance pattern 274 on the variable resistance pattern 264.

[0080] The variable resistance memory device can have the following structural characteristics.

[0081] The variable resistance memory device can include first conductive line structures 142 spaced apart from each other on the base 100 in a second direction, each of the first conductive line structures 142 can extend in a first direction, second conductive lines 342 spaced apart from each other on the first conductive line structures 142 in the first direction, each of the second conductive lines 342 can extend in the second direction, variable resistance patterns 264 between the first conductive line structures 142 and the second conductive lines 342 at regions where the first conductive line structures 142 and the second conductive lines 342 are stacked or crossed with each other in a third direction, and contacting upper surfaces of corresponding ones of the first conductive line structures 142, a fill structure 240 having a first portion 232 extending in the first direction on the base 100 between the first conductive line structures 142 and contacting each of opposite sidewalls of the variable resistance patterns 264 in the second direction, and a second portion 214 extending in the second direction on the first conductive line structures 142 from the first portion 232 to contact sidewalls of corresponding ones of the variable resistance patterns 264 in the first direction, moldings 164 on each of the first conductive line structures 142 and respectively contacting the sidewalls of the variable resistance patterns 264 in the first direction, not contacting the second portion 214 of the fill structure 240, etch stop patterns 174 on each of the moldings 164, low resistance patterns 274 contacting upper surfaces of each of the variable resistance patterns 264, and selection structures 314 on the low resistance patterns 274.

[0082] In an embodiment, each of the first conductive line structures 142 can include first conductive lines 122, thermally insulating lines 132, and first conductive lines 122 sequentially stacked in the third direction, and the selection structures 314 can include first buffers 284, selection patterns 294, and second buffers 304 sequentially stacked in the third direction.

[0083] In an embodiment, a bottom surface of the low resistance pattern 274 can cover an entire upper surface of a corresponding (e.g., underlying) one of the variable resistance patterns 264, and can have an area substantially equal to or greater than an area of the upper surface of the corresponding one of the variable resistance patterns 264, and can contact a portion of an upper surface of the etch stop pattern 174.

[0084] In an embodiment, a bottom surface of the first portion 232 of the fill structure 240 can be lower than a bottom surface of the first conductive line structures 142, and can be lower than a bottom surface of the second portion 214 of the fill structure 240 contacting the upper surfaces of the first conductive line structures 142.

[0085] In an embodiment, in a plan view, the selection structures 314 and the low resistance patterns 274 can have substantially the same shape and area.

[0086] In an embodiment, the moldings 164 and the fill structures 240 can be alternately formed between adjacent variable resistance patterns in the variable resistance pattern 264.

[0087] In an embodiment, the first insulating interlayer 110 can be located on the substrate 100 and can cover the bottom surface of the first conductive line structure 142 and the bottom surface of the first portion 232 of the fill structure 240.

[0088] Figures 16 to 20 Perspective views showing stages in a method of manufacturing a variable resistance memory device according to an example embodiment are shown. Such a method of manufacturing a variable resistance memory device includes substantially the same or similar processes as those used in the method of manufacturing a variable resistance memory device described in Figures 1 to 15 and a repetitive description thereof can be omitted here.

[0089] Referring to Figure 16 , substantially the same or similar processes as those shown in Figures 1 to 10 can be performed and the structure including the moldings 164 and the etch stop pattern 174 and the fill structure 240 can be partially removed by, for example, an etch-back process. For example, the entrance of the third openings 250 (e.g., the upper portion of the third openings 250) can be enlarged.

[0090] Referring to Figure 17 , substantially the same or similar processes as those shown in Figure 11 can be performed to form the variable resistance layer 260 filling the third openings 250. As shown above, the upper portion of the third openings 250 has been enlarged so that no gap or void is generated in the variable resistance layer 260.

[0091] Substantially the same or similar processes as those shown in Figure 12 can be performed to planarize the upper portion of the variable resistance layer 260 and the variable resistance pattern 264 can be formed in each of the third openings 250. In an embodiment, the etch stop pattern 174 can also be removed during the planarization process.

[0092] Referring to Figure 18 , substantially the same or similar processes as those shown in Figures 13 to 15 can be performed to complete the manufacturing of the variable resistance memory device.

[0093] In an embodiment, referring to Figure 19 , the etch stop pattern 174 remaining on the moldings 164 can be removed before the etch-back process shown in Figure 16 is performed.

[0094] Referring to Figure 20An etch-back process can be performed on the mold 164 and the fill structure 240. The etch-stop pattern 174 having been removed, the etch-back process for the mold 164 can be easily performed. Figure 16

[0095] Figures 21 to 23 Perspective views showing stages in a method of manufacturing a variable resistance memory device according to an example embodiment are shown. The method can include substantially the same or similar processes as those shown with reference to Figures 1 to 15 and repetitive description thereof can be omitted herein.

[0096] With reference to Figure 21 , the first insulating interlayer 110 and the first conductive layer structure 140 can be sequentially formed on the substrate 100.

[0097] A fifth mask layer can be formed on the first conductive layer structure 140, and the fifth mask layer can be patterned to form a plurality of fifth masks spaced apart from each other in a second direction, each of the plurality of fifth masks can extend in a first direction, by using a lithography process of EUV or a double patterning process. An etching process can be performed on the first conductive layer structure 140 using the fifth mask as an etching mask to form the first wire structure 142. An upper portion of the first insulating interlayer 110 can also be partially removed during the etching process.

[0098] A sixth opening 150 can be formed between adjacent first wire structures of the first wire structure 142 to expose an upper surface of the first insulating interlayer 110, each of the first wire structures 142 can extend in the first direction.

[0099] With reference to Figure 22 , the fourth insulating interlayer line 152 can be formed to fill the sixth opening 150, the mold layer 160, the etch-stop layer 170, and the first mask layer 180 can be sequentially stacked on the first wire structure 142 and the fourth insulating interlayer line 152, and processes substantially the same as or similar to those shown with reference to Figures 2 to 7 can be performed. The fourth insulating interlayer line 152 can include an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride).

[0100] In an embodiment, an etching process of Figure 7 can be performed until an upper surface of the fourth insulating interlayer line 152 is exposed, and an upper portion of the fourth insulating interlayer line 152 can be partially etched during the etching process. For example, the second opening 220 formed by the etching process can have a depth and an aspect ratio smaller than those of the second opening 220 formed by the etching process shown with reference to Figure 7 .

[0101] ​In an embodiment, a lowermost surface (e.g., a surface closest to the substrate 100 in the third direction) of the fourth insulating interlayer line 152 can be lower than a bottom surface of the first conductive line structure 142, and an uppermost surface (e.g., a surface farthest from the substrate 100 in the third direction) of the fourth insulating interlayer line 152 can be lower than an upper surface of the first conductive line structure 142.

[0102] Referring to Figure 23 , a process substantially the same as or similar to the process shown in Figures 8 to 15 may be performed to complete the manufacture of the variable resistance memory device. As described above, the second opening 220 can have a relatively low aspect ratio, and the possibility of forming a gap or void in the second fill layer 230 can be reduced.

[0103] In an embodiment, the process shown in Figures 16 to 20 may also be applied to the method of manufacturing the variable resistance memory device shown in Figures 21 to 23 .

[0104] The variable resistance memory device described above can be applied to a PRAM device, a ReRAM device, an MRAM device, etc.

[0105] By summarizing and reviewing, as the aspect ratio of the mold increases, a gap can be formed in the material filling the opening in the mold, and also be enlarged in a subsequent process to cause an electrical short between adjacent upper electrodes.

[0106] One or more embodiments can provide a variable resistance memory device having improved characteristics.

[0107] In the variable resistance memory device according to an example embodiment, only a variable resistance pattern (e.g., a self-heating variable resistance pattern) can be formed between a word line and a low resistance pattern, an aspect ratio of a mold or a fill structure for forming the variable resistance pattern can be reduced, and a gap or void can not be generated in the fill structure and / or the variable resistance pattern. For example, before forming the fill structure and / or the variable resistance pattern, an upper portion of an opening in which the fill structure and / or the variable resistance pattern can be formed can be enlarged, so that formation of a gap or void can be prevented.

[0108] By forming an etch stop pattern on the mold, a height distribution of the fill structure and the variable resistance pattern can be reduced, and during an etching process for removing the spacers to form the variable resistance pattern, the word line under the spacers can serve as an etch stop pattern, and a thickness distribution of the variable resistance pattern can also be reduced.

[0109] Having disclosed example embodiments herein, although in terms of a specific terminology, which is offered for the purpose of generality and description and not for limitation, in some instances, features, attributes and / or elements described in conjunction with a particular embodiment are applicable to other embodiments, except where specifically disclaimed. Moreover, unless specifically stated to the contrary, where a range of values is provided, it is meant to encompass each and every value and subrange within the range. It will be appreciated by those skilled in the art that various modifications and changes can be made without departing from the spirit and scope of the application as set forth in the claims.

Claims

1. A variable resistance memory device, the variable resistance memory device comprising: A first conductor structure is located on a substrate, and the first conductor structure has an insulating wire and a first conductor. At least one variable resistor pattern contacts the upper surface of the first conductor structure; A low-resistance pattern contacts the upper surface of the at least one variable-resistance pattern; Select a structure located on a low-resistance pattern; as well as The second conductor is located on the selection structure. The at least one variable resistance pattern and the insulating wire are spaced apart from each other by a first conductor.

2. The variable resistance memory device according to claim 1, wherein: The first conductor has a lower resistance than the resistance of the at least one variable resistor pattern. The insulating wire has a lower thermal conductivity than the first conductor, and The at least one variable resistance pattern contacts the upper surface of the first conductor.

3. The variable resistance memory device according to claim 2, wherein: The first conductor comprises metal, and Insulation wires include carbon, carbon compounds, or carbon-containing metals.

4. The variable resistance memory device according to claim 1, wherein, Low-resistance patterns include metals.

5. The variable resistance memory device according to claim 1, wherein, The selection structure includes a first buffer, a selection pattern, and a second buffer, which are stacked sequentially.

6. The variable resistance memory device according to claim 5, wherein: The first buffer has a lower thermal conductivity than the low-resistance pattern, and The bottom surface of the first buffer contacts the upper surface of the low-resistance pattern.

7. The variable resistance memory device according to claim 6, wherein, Each of the first and second buffers comprises carbon, carbon compounds, or carbon-containing metals.

8. The variable resistance memory device according to claim 5, wherein, Pattern selection includes OTS materials containing germanium, silicon, arsenic, or tellurium.

9. The variable resistance memory device according to claim 5, wherein, The selected patterns include AsTeGeSiIn, GeTe, SnTe, GeSe, SnSe, AsTeGeSiSbS, AsTeGeSiInP, AsTeGeSi, As2Te3Ge, As2Se3Ge, As 1-x , 21 , 28 , 50 , 15 , x , 11 , 34 (Te 90 Ge 10 ) 75 、Te 40 As 35 Si 18 Ge 6.75 In 0.25 、Te 28 As 34.5 Ge 15.5 S 22 、Te 39 As 36 Si 17 Ge7P、As 10 Te 21 S2Ge 15 Se 50 Sb2、Si5Te 34 As 28 Ge 11 S 21 Se1、AsTeGeSiSeNS、AsTeGeSiP、AsSe、AsGeSe、AsTeGeSe、ZnTe、GeTePb、GeSeTe、AlAsTe、SeAsGeC、SeTeGeSi、GeSbTeSe、GeBiTeSe、GeAsSbSe、GeAsBiTe、GeAsBiSe or Ge x Se 1-x where 0 < x < 1.

10. The variable resistance memory device according to claim 1, wherein: The first conductive structure extends in a first direction substantially parallel to the upper surface of the substrate. The at least one variable resistance pattern comprises a plurality of variable resistance patterns spaced apart from each other in a first direction on the first conductor structure, and The second conductor extends in a second direction that is substantially parallel to the upper surface of the substrate and intersects the first direction.

11. The variable resistance memory device according to claim 10, wherein: Multiple first conductor structures are spaced apart from each other in the second direction, and Multiple second conductors are spaced apart from each other in the first direction.

12. The variable resistance memory device according to claim 10, wherein: Multiple low-resistance patterns are spaced apart from each other along a second direction beneath each of the multiple second conductors, and The multiple selection structures are spaced apart from each other along a second direction below each of the multiple second conductors.

13. The variable resistance memory device according to claim 10, wherein, The width of the low-resistance pattern in the first and second directions is substantially equal to or greater than the width of the corresponding variable resistance pattern in the first and second directions among the plurality of variable resistance patterns.

14. The variable resistance memory device of claim 10, further comprising a molding element and a filling structure, the molding element and the filling structure being alternately arranged in a first direction in corresponding spaces between adjacent variable resistance patterns in the plurality of variable resistance patterns.

15. The variable resistance memory device according to claim 14, wherein, The filling structure includes; The first part extends in a first direction to contact each of the plurality of variable resistor patterns in opposite sidewalls in a second direction; as well as The second part covers the sidewalls of each of the plurality of variable resistor patterns in the first direction.

16. The variable resistance memory device of claim 14, further comprising an etch stop pattern on the molded part.

17. A variable resistance memory device, the variable resistance memory device comprising: A first conductive structure is located on a substrate and extends in a first direction substantially parallel to the upper surface of the substrate. Variable resistance patterns are spaced apart from each other in a first direction, and each variable resistance pattern contacts the upper surface of the first wire structure; The molding part and the filling structure are located on the first conductor structure. The molding part and the filling structure are alternately arranged in the corresponding space between adjacent variable resistor patterns in the first direction, such that the molding part is spaced apart from the filling structure in the first direction. Etched stop pattern, located on the molded part; The low-resistance pattern contacts the upper surface of the corresponding variable resistance pattern in the variable resistance pattern; as well as Choose a structure located on a low-resistance pattern.

18. The variable resistance memory device according to claim 17, wherein, A portion of the upper surface of the low-resistance patterned contact etch stop pattern.

19. The variable resistance memory device according to claim 17, wherein, The bottom surface of the low-resistance pattern covers the entire upper surface of each variable-resistance pattern and has an area that is substantially equal to or greater than the area of ​​the upper surface of each variable-resistance pattern.

20. The variable resistance memory device according to claim 17, wherein, The upper surface of the etch stop pattern is substantially coplanar with the upper surface of the filling structure.

21. The variable resistance memory device according to claim 17, wherein: The first conductor structure includes an insulating wire located between the first conductors. The first conductor has a resistance smaller than that of each variable resistor pattern. The insulating wire has a lower thermal conductivity than the first conductor, and Each variable resistor pattern contacts the upper surface of one of the first conductors in the first conductor.

22. The variable resistance memory device according to claim 17, wherein: The selection structure includes a first buffer, a selection pattern, and a second buffer, which are stacked sequentially. The first buffer has a lower thermal conductivity than the low-resistance pattern, and The bottom surface of the first buffer contacts the upper surface of the low-resistance pattern.

23. A variable resistance memory device, the variable resistance memory device comprising: First conductive structures are spaced apart from each other on a substrate along a second direction, each first conductive structure extending along a first direction, each of the first and second directions being substantially parallel to the upper surface of the substrate, and the first direction intersecting the second direction. The second conductors are spaced apart from each other along a first direction in the first conductor structure, and each second conductor extends along a second direction; The variable resistance pattern is located between the first and second conductors in a corresponding region where the first conductor structure and the second conductor overlap each other in a third direction substantially perpendicular to the upper surface of the substrate, and the variable resistance pattern contacts the upper surface of the first conductor structure respectively. The filling structure includes: a first portion extending in a first direction between first conductive structures on a substrate, the first portion contacting each of opposite sidewalls of a variable resistor pattern in a second direction; and a second portion extending from the first portion in the second direction on the first conductive structure, each second portion contacting a first sidewall of a corresponding variable resistor pattern in the first direction. A molded part is located on each first conductor structure, each molded part contacts the second sidewall of the corresponding variable resistor pattern in the first direction, and the second sidewall does not contact each second part; Low-resistance patterns contact the upper surface of each variable resistance pattern; and Choose a structure located on a low-resistance pattern. Each first conductor structure includes an insulating wire positioned between the first conductors in a third-order orientation, and The selection structure includes a first buffer, a selection pattern, and a second buffer that are stacked sequentially in a third-order upward manner.

24. The variable resistance memory device of claim 23, further comprising an etch stop pattern located on each molded part.

25. The variable resistance memory device according to claim 23, wherein, When an electrical signal is applied to the first and second conductors, heat is generated in each of the variable resistance patterns, and the phase of the variable resistance pattern changes according to the heat.

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