A supercapacitor power buffer circuit

Abstract

The present invention relates to a supercapacitor power buffer circuit, including a control circuit, a supercapacitor charging circuit, a supercapacitor group, and a boost circuit; the control circuit is responsible for detecting the real-time voltage of the supercapacitor so as to output the maximum current information (V_FI) that can be used for reception in the form of a voltage signal; the supercapacitor charging circuit charges the supercapacitor group with a specific power according to the V_FI information provided by the control circuit; the boost circuit uses the energy provided by the supercapacitor for power output. Since the charging power of the supercapacitor is constant and the supercapacitor can buffer energy, when the system load is large, there is no need to worry about the instantaneous impact of the high power consumption load on the battery, thereby realizing the buffering of the power supply energy. In addition, the boost circuit can charge the reverse energy from the output end back to the supercapacitor group, thereby realizing the energy recovery of the system load.

Description

Technical Field

[0001] The present invention relates to the fields of robots and industrial control, and can be applied in scenarios of power caching or energy recovery. Background Art

[0002] With the development of robotics and industrial technology, higher requirements are placed on battery power control. In certain specific areas, batteries are required to output stable low power to maximize battery energy utilization, but the load usually fluctuates greatly, and sometimes even remains at high power or unloaded for a long time. For this reason, it is necessary to add a certain power compensation mechanism so that the power during no-load (or energy recovery) can be cached and released when the load is continuously high, thereby improving the battery's continuous power supply capability.

[0003] Usually, some soft start methods are used to reduce the impact on the battery, but for the requirements of robots and industrial control, these methods can never meet the requirements of fast response. This design uses supercapacitors as energy storage media, and uses boost and buck methods to achieve power cache. In addition, by monitoring the terminal voltage of the supercapacitor group and sending it to the external host through CAN bus communication, the robot control can make certain adjustments based on the energy cached inside the capacitor. Summary of the invention

[0004] The technology of the present invention solves the problem: In view of the shortcomings of the prior art, a supercapacitor power cache circuit is provided to solve the problems raised in the above background technology, and the high cycle life and fast charging and discharging capabilities of the supercapacitor are utilized to realize power cache under complex load change conditions, which is suitable for motor power cache and compensation of various types of robots. The design can cache the energy provided by the power supply (usually a battery), thereby reducing the instantaneous impact of high power consumption loads on the battery during robot control, and reducing the problem of reduced battery life caused by short-term high current of batteries with low discharge rates.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: A supercapacitor power buffer circuit, characterized by comprising: a control circuit (1), a supercapacitor charging circuit (2), a supercapacitor group (3) and a boost circuit (4);

[0006] The control circuit (1) detects the voltage V of the supercapacitor group (3) in real time, receives the maximum charging power P sent from the external host through the CAN bus, obtains the maximum charging current according to I(max)=P / V, converts the maximum charging current into a voltage signal V_FI for controlling the supercapacitor charging circuit (2), and sends it to the supercapacitor charging circuit (2); and at the same time informs the external host of the current voltage of the supercapacitor group (3) through the CAN bus;

[0007] The supercapacitor charging circuit (2) receives a voltage signal V_FI from the control circuit and controls the real-time charging current flowing from the power supply to the supercapacitor group (3) through voltage reduction conversion, thereby controlling the power input to the supercapacitor group (3) to achieve the characteristic of caching power supply power; in addition, the supercapacitor charging circuit (2) presets the maximum charging voltage of the supercapacitor group (3), and when the voltage of the supercapacitor group (3) approaches the maximum voltage, the supercapacitor charging circuit (2) will reduce the charging power or stop charging;

[0008] The supercapacitor group (3) buffers the power flowing in from the supercapacitor charging circuit (2) and also outputs power to the boost circuit (4), thereby ensuring that the power output to the system load does not affect the system power supply; at the same time, the supercapacitor group (3) turns on the bleeder resistor when a single supercapacitor exceeds the maximum withstand voltage, thereby ensuring that overcharging does not occur;

[0009] The boost circuit (4) increases the voltage of the supercapacitor group (3) to the voltage required by the system load, thereby providing power to the load; the boost circuit (4) has a bidirectional characteristic, and can not only provide power to the system load, but also absorb the power recharged by the system load (such as a motor), and charge the recharged power back to the supercapacitor group (3), thereby reducing the energy waste output to the system load (such as a motor).

[0010] The control circuit comprises a main control chip (101), a super capacitor voltage attenuator (102), an output voltage follower (103) and a voltage reduction circuit (104);

[0011] The main control chip (101) adopts STM32F072C8, which includes CAN bus, ADC and DAC functions; the main control chip (101) exchanges data with an external host through the CAN bus, obtains the currently set maximum cache power P from the external host, and informs the external host of the current voltage information V of the supercapacitor group (1); the main control chip (101) uses the internal ADC to collect the voltage attenuated by the supercapacitor voltage attenuator (102) to obtain the voltage V of the supercapacitor group (3); the main control chip (101) uses the internal DAC to output the calculated maximum current information in the form of voltage to the output voltage follower (103) for following; in addition, the power supply of the main control chip (101) comes from the step-down circuit (104);

[0012] The supercapacitor voltage attenuator (102) divides the voltage of the supercapacitor group (3) using a resistor, connects the divided voltage to a follower to improve the load capacity of the divided voltage signal, and finally connects the divided voltage signal to the ADC terminal of the main control chip (101);

[0013] The output voltage follower (103) follows the voltage signal output by the main control chip (101) through the ADC, improves the load capacity and then connects it to the current control end of the super capacitor charging circuit (2);

[0014] The voltage reduction circuit (104) reduces the voltage of the power supply and distributes it to the main control chip (101) for power supply.

[0015] The supercapacitor charging circuit comprises: a supercapacitor charging management chip (201), a half-bridge circuit (202), a current feedback resistor (203) and a voltage feedback resistor (204);

[0016] The supercapacitor charging management chip (201) receives current information fed back by a current feedback resistor (203) at a current feedback end, receives maximum current information V_FI transmitted by a control circuit (1) at a maximum current setting end, receives voltage information of a supercapacitor group (3) fed back by a voltage feedback resistor (204) at a voltage feedback end, and then outputs two complementary PWM waveforms to control a half-bridge circuit (202) to achieve charging control of the supercapacitor group;

[0017] The half-bridge circuit (202) is controlled by a PWM signal sent by the supercapacitor charging management chip (201) to change the duration of power supply connection to control the current and power flowing to the supercapacitor group (3);

[0018] The current feedback resistor (203) is a low-resistance resistor capable of passing a relatively large current. The current is transmitted by connecting the half-bridge circuit (202) and the supercapacitor group (3). In addition, the voltage across the resistor can indicate the current information flowing through the resistor. The voltage is fed back to the current feedback terminal of the supercapacitor charging chip (201) to inform the real-time charging current of the supercapacitor group (3).

[0019] The voltage feedback resistor (204) is composed of two resistors to form a voltage divider circuit, which divides the voltage of the supercapacitor group (3) and feeds it back to the voltage control terminal of the supercapacitor charging management chip (201) to inform the current real-time voltage of the supercapacitor group (3);

[0020] The supercapacitor charging management chip (201) can obtain the voltage of the supercapacitor group (3), the real-time charging current of the supercapacitor group (3) and the real-time set maximum current information V_FI through a voltage acquisition terminal, a current acquisition terminal and a maximum current setting terminal respectively, and then output a PWM waveform with a certain duty cycle by comparing the difference between the real-time charging current of the supercapacitor group (3) and the maximum current information V_FI, the difference between the voltage fed back by the supercapacitor group and the internal reference voltage (about 1.2V), thereby driving the half-bridge circuit (202). The half-bridge circuit (202) adopts a BUCK structure to realize a charging function of a step-down and controllable current.

[0021] The supercapacitor group (3) comprises a supercapacitor (301), a supercapacitor management chip (302) and a bleeder resistor (303);

[0022] The supercapacitor (301) is composed of a plurality of single supercapacitors connected in series and in parallel, and is connected in parallel with the supercapacitor charging circuit (2) and the boost circuit (4);

[0023] The supercapacitor management chip (302) is connected in parallel to each supercapacitor of each cell, and its discharge terminal is connected to the discharge resistor (303);

[0024] The supercapacitor group (3) as a whole is regarded as a supercapacitor group having a certain withstand voltage value and a certain buffer power by combining single supercapacitors in series and parallel; each single supercapacitor is connected in parallel to a supercapacitor management chip (302), which can monitor the voltage of the supercapacitor to prevent the voltage from exceeding the withstand voltage value of the supercapacitor; when the voltage exceeds the withstand voltage value, the supercapacitor management chip (302) can turn on the leakage resistor (303) to bypass the supercapacitor so that it does not exceed the maximum withstand voltage. Since the supercapacitor group is connected in parallel with the supercapacitor charging circuit (2) and the boost circuit (4), power can be buffered and released at will, and power can be buffered when the system load is small, and the power can be released when the system load is large, thereby realizing the buffering of power supply power.

[0025] The boost circuit comprises: a boost chip (401), a half-bridge circuit (402) and a voltage feedback resistor (403);

[0026] The voltage feedback terminal of the boost chip (401) is connected to the voltage feedback resistor (403); the driving terminal of the boost chip (401) is connected to the half-bridge circuit (402), thereby controlling the output voltage;

[0027] The half-bridge circuit (402) is connected to the supercapacitor group (3) and is responsible for the final output to the system load;

[0028] The voltage feedback resistor (403) collects the final output voltage and feeds it back to the voltage feedback terminal of the boost chip (401) after voltage division.

[0029] The boost chip (401) controls the PWM signal used to drive the half-bridge circuit (402) according to the voltage feedback from the voltage feedback resistor (403), thereby realizing voltage boost by utilizing the BOOST circuit principle; in addition, when the output voltage of the bridge circuit is greater than a preset voltage, the power can flow in the reverse direction, thereby realizing energy recovery on the load side of the system.

[0030] The beneficial effects of the present invention compared with the prior art are as follows:

[0031] (1) The supercapacitor power cache circuit of the present invention sends the upper limit value of power to the control circuit through the CAN bus, which can control the supercapacitor group to use a specific power to cache the power of the power supply, thereby ensuring the smooth discharge power of the power supply and making the power supply of the system have a better discharge effect.

[0032] (2) The supercapacitor power cache circuit of the present invention controls the half-bridge circuit to output a constant voltage through the LM5122 boost chip. In addition, the bridge circuit can make the power flow in the opposite direction when the output voltage is greater than the preset voltage, thereby realizing energy recovery on the system load side, reducing the direct waste of system load recharging energy, and increasing the battery life. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a system block diagram of the present invention;

[0034] Figure 2 The control circuit of the present invention;

[0035] Figure 3 This is a block diagram of the supercapacitor charging circuit of the present invention;

[0036] Figure 4 This is a circuit diagram of a supercapacitor bank of the present invention;

[0037] Figure 5 This is a block diagram of the boost circuit of the present invention.

[0038] In the figure: 101 control chip (STM32F072C8), 102 supercapacitor voltage attenuator, 103 output voltage follower, 104 buck circuit, 201 supercapacitor charging management chip (BQ24640), 202 half-bridge circuit (MOS tube uses IPD079N06), 203 current feedback resistor, 204 voltage feedback resistor, 301 supercapacitor, 302 supercapacitor management chip (BW6101), 303 leakage resistor, 401 boost chip (LM5122), 402 half-bridge circuit (MOS tube uses IRLR3114), 403 voltage feedback resistor. DETAILED DESCRIPTION

[0039] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0040] like Figure 1 As shown, a supercapacitor power cache circuit of the present invention includes a control circuit 1, a supercapacitor charging circuit 2, a supercapacitor group 3, and a boost circuit 4.

[0041] The supercapacitor voltage attenuator 102 in the control circuit 1 attenuates the voltage of the supercapacitor group 3 to a range that can be collected by the main control chip 101 for ADC collection.

[0042] The control circuit 1 uses the maximum power information sent by the CAN bus and the current voltage of the supercapacitor group to calculate the required current limit information V_FI in real time. Its expression is: R f is the resistance of the current feedback resistor 203, P is the maximum power information sent by the CAN bus, 20 is the sampling voltage magnification factor inside the BQ24640 chip, and V is the real-time voltage information of the supercapacitor group collected by the main control chip 101 through the supercapacitor voltage attenuator 102. The voltage value corresponding to the internal DAC output V_FI of the main control chip 101 is fed back to the current limiting end of the supercapacitor charging circuit 2 through the output voltage follower 103.

[0043] The half-bridge circuit 202 of the supercapacitor charging circuit 2 uses an IPD079N06 MOS tube, uses a BQ24640 supercapacitor charging management chip 201 as a charging control core device, uses 10K and 90.9K voltage feedback resistors 204 to set the maximum charging voltage, and sets its charging cut-off voltage to 21.2 V. Through the supercapacitor charging circuit, the supercapacitor can finally achieve power caching according to the preset power P.

[0044] The supercapacitor bank 3 combines 16 supercapacitors 301 in a manner of 8 series and 2 parallels, and the total cache power can reach 2041.2 J. The BW6101 supercapacitor management chip 302 is used to protect the supercapacitors 301 to prevent the voltage of a single supercapacitor from exceeding its withstand voltage value.

[0045] The boost circuit 4 uses the LM5122 boost chip 401, and the half-bridge circuit 402 uses the IRLR3114 MOS tube to boost the voltage of the supercapacitor group 3 and ensure the stability of the voltage finally output to the system load. Since the boost circuit 4 uses a synchronous DCDC boost solution, it can cache the power of the system load back to the supercapacitor group 3, thereby realizing energy recovery.

[0046] The control circuit uses stm32f072c8 as the control chip, which supports CAN bus communication, ADC acquisition and DAC output. The circuit uses voltage feedback resistors to achieve the attenuation of the voltage range of the supercapacitor group, and obtains the supercapacitor terminal voltage V through the ADC of the control chip. After detecting the supercapacitor voltage V and the maximum power information P sent by the CAN bus, the maximum charging current is obtained through I(max)=P / V, and the voltage V_FI that can indicate the maximum current information is output through the DAC of the control chip, and the output voltage follower is used to follow the output to the supercapacitor charging circuit.

[0047] The supercapacitor charging circuit adopts the BQ24640 supercapacitor charging management chip, and the half-bridge circuit MOS tube of the supercapacitor charging circuit adopts IPD079N06; the voltage feedback resistor adopts the resistance value of 10KΩ and 90.9KΩ, so that the maximum voltage is set to 21.2V; when different voltage feedback resistor values ​​are selected, the maximum voltage can be adjusted, but theoretically it does not exceed the withstand voltage value of the supercapacitor charging management chip BQ24640, 26V; the current feedback resistor (R f ) uses 5mΩ, and the output current it controls can be based on get.

[0048] The supercapacitor group is composed of 16 supercapacitors with a capacitance of 35F and a withstand voltage of 2.7V, and the total maximum cache power is 2041.2J; the supercapacitor management chip is BW6101.

[0049] The boost chip of the boost circuit adopts LM5122; the MOS tube of the half-bridge circuit adopts IRLR3114; the voltage feedback resistor adopts 10KΩ and 200KΩ, so that the output voltage is set to 25.2V.

[0050] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A supercapacitor power buffer circuit, characterized in that: include: A control circuit (1), a supercapacitor charging circuit (2), a supercapacitor group (3) and a boost circuit (4); The control circuit (1) detects the voltage V of the supercapacitor group (3) in real time, receives the maximum charging power P sent from the external host via the CAN bus, obtains the maximum charging current according to I(max)=P / V, converts the maximum charging current into a voltage signal V_FI for controlling the supercapacitor charging circuit (2), and sends the voltage signal to the supercapacitor charging circuit (2); and at the same time informs the external host of the current voltage of the supercapacitor group (3) via the CAN bus; The supercapacitor charging circuit (2) receives a voltage signal V_FI from the control circuit and controls the real-time charging current flowing from the power supply to the supercapacitor group (3) through voltage reduction conversion, thereby controlling the power input to the supercapacitor group (3) to achieve the characteristic of caching the power of the power supply; in addition, the supercapacitor charging circuit (2) presets the maximum charging voltage of the supercapacitor group (3), and when the voltage of the supercapacitor group (3) approaches the maximum voltage, the supercapacitor charging circuit (2) will reduce the charging power or stop charging; The supercapacitor group (3) buffers the power flowing from the supercapacitor charging circuit (2) and also outputs power to the boost circuit (4), thereby ensuring that the power output to the system load does not affect the system power supply; at the same time, the supercapacitor group (3) turns on the bleeder resistor when a single supercapacitor exceeds the maximum withstand voltage, thereby ensuring that overcharging does not occur; The boost circuit (4) increases the voltage of the supercapacitor group (3) to the voltage required by the system load, thereby providing power to the load; the boost circuit (4) has a bidirectional characteristic, and can not only provide power to the system load, but also absorb the power recharged by the system load and charge the recharged power back to the supercapacitor group (3), thereby reducing the energy waste output to the system load; The boost circuit comprises: a boost chip (401), a half-bridge circuit (402) and a voltage feedback resistor (403); The voltage feedback terminal of the boost chip (401) is connected to the voltage feedback resistor (403); the driving terminal of the boost chip (401) is connected to the half-bridge circuit (402), thereby controlling the output voltage; The half-bridge circuit (402) is connected to the supercapacitor group (3) and is responsible for the final output to the system load; The voltage feedback resistor (403) collects the final output voltage and feeds it back to the voltage feedback terminal of the boost chip (401) after voltage division. The boost chip (401) controls a PWM signal for driving the half-bridge circuit (402) according to the voltage fed back by the voltage feedback resistor (403), thereby achieving voltage boost using the BOOST circuit principle; in addition, the half-bridge circuit (402) can cause power to flow in the reverse direction when the output voltage is greater than a preset voltage, thereby achieving energy recovery on the system load side.

2. The supercapacitor power buffer circuit according to claim 1, characterized in that: The control circuit comprises a main control chip (101), a super capacitor voltage attenuator (102), an output voltage follower (103) and a voltage reduction circuit (104); The main control chip (101) includes CAN bus, ADC and DAC functions; the main control chip (101) exchanges data with an external host via the CAN bus, obtains the currently set maximum cache power P from the external host, and informs the external host of the current voltage information V of the supercapacitor group (3); the main control chip (101) uses the internal ADC to collect the voltage attenuated by the supercapacitor voltage attenuator (102) to obtain the voltage V of the supercapacitor group (3); the main control chip (101) uses the internal DAC to output the calculated maximum current information in the form of voltage to the output voltage follower (103) for following; in addition, the power supply of the main control chip (101) comes from the step-down circuit (104); The supercapacitor voltage attenuator (102) divides the voltage of the supercapacitor group (3) using a resistor, connects the divided voltage signal to a follower to improve the load capacity of the divided voltage signal, and finally connects the divided voltage signal to the ADC terminal of the main control chip (101); The output voltage follower (103) follows the voltage signal output by the main control chip (101) through the ADC, improves the load capacity and then connects it to the current control end of the super capacitor charging circuit (2); The voltage reduction circuit (104) reduces the voltage of the power supply and distributes it to the main control chip (101) for power supply.

3. The supercapacitor power buffer circuit according to claim 1, characterized in that: The supercapacitor charging circuit comprises: a supercapacitor charging management chip (201), a half-bridge circuit (202), a current feedback resistor (203) and a voltage feedback resistor (204); The supercapacitor charging management chip (201) receives current information fed back by a current feedback resistor (203) at a current feedback end, receives maximum current information V_FI transmitted by a control circuit (1) at a maximum current setting end, receives voltage information of a supercapacitor group (3) fed back by a voltage feedback resistor (204) at a voltage feedback end, and then outputs two complementary PWM waveforms to control a half-bridge circuit (202) to achieve charging control of the supercapacitor group; The half-bridge circuit (202) is controlled by a PWM signal sent from the supercapacitor charging management chip (201) to change the duration of power supply connection to control the current and power flowing to the supercapacitor group (3); The current feedback resistor (203) is a low-resistance resistor capable of passing a relatively large current, and transmits the current by connecting the half-bridge circuit (202) and the supercapacitor group (3). In addition, the voltage across the current feedback resistor (203) can indicate the information of the current flowing through, and the voltage across the current feedback resistor (203) is fed back to the current feedback terminal of the supercapacitor charging chip (201) to inform the real-time charging current of the supercapacitor group (3). The voltage feedback resistor (204) is composed of two resistors to form a voltage divider circuit, which divides the voltage of the supercapacitor group (3) and feeds it back to the voltage control terminal of the supercapacitor charging management chip (201) to inform the current real-time voltage of the supercapacitor group (3); The supercapacitor charging management chip (201) can obtain the voltage of the supercapacitor group (3), the real-time charging current of the supercapacitor group (3) and the real-time set maximum current information V_FI through a voltage acquisition terminal, a current acquisition terminal and a maximum current setting terminal respectively, and then output a duty cycle PWM signal to drive the half-bridge circuit (202) by comparing the difference between the real-time charging current of the supercapacitor group (3) and the maximum current information V_FI, and the difference between the voltage fed back by the supercapacitor group and the internal reference voltage. The half-bridge circuit (202) adopts a BUCK structure to realize a charging function of a step-down and controllable current.

4. The supercapacitor power buffer circuit according to claim 1, characterized in that: The supercapacitor group (3) comprises a supercapacitor (301), a supercapacitor management chip (302) and a bleeder resistor (303); The supercapacitor (301) is composed of a plurality of single supercapacitors connected in series and in parallel, and the supercapacitor group (3) and the supercapacitor charging circuit (2) and the boost circuit (4) are all connected in parallel; The supercapacitor management chip (302) is connected in parallel to the supercapacitor of each cell, and the leakage terminal of the supercapacitor management chip (302) is connected to the leakage resistor (303); The supercapacitor group (3) as a whole is regarded as a supercapacitor group having a withstand voltage value and a buffer power by combining single supercapacitors in series and parallel; each single supercapacitor is connected in parallel to a supercapacitor management chip (302) which can monitor the voltage of the supercapacitor to prevent the voltage of the supercapacitor group from exceeding the withstand voltage value of the supercapacitor; When the voltage exceeds the withstand voltage value, the supercapacitor management chip (302) can turn on the leakage resistor (303) to bypass the supercapacitor so that it does not exceed the maximum withstand voltage.

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