An ultra-low power neural circuit

Abstract

The present invention discloses an ultra-low power consumption neural circuit, belonging to the field of neural circuit technology. It includes: a photoelectric receiver, an amplifier, and a comparator of a mirror current source; the photoelectric receiver, the amplifier, and the comparator of the mirror current source are cascaded, and the amplifier and the comparator of the mirror current source have a common part; the amplifier amplifies the input signal of the photoelectric receiver, the photoelectric receiver is used to generate a neural signal, and the amplifier is used to amplify the input neural signal. The circuit of the present invention combines an amplifier composed of two inverters with a comparator composed of five transistors, which effectively reduces the number of branches in the circuit while maintaining the original function, thereby reducing the power consumption of the neural module.

Description

Technical Field

[0001] The present invention relates to the technical field of neural circuits, and in particular to an ultra-low power consumption neural circuit. Background Art

[0002] The visual system is a complex apparatus that processes the complex light signals collected by the eye, processes the spatiotemporal patterns of these signals, and provides information about a rapidly changing world. This is essential for the survival of organisms. Visual circuits have evolved in response to their environment and are refined in an experience-dependent manner during development. Therefore, the functioning of the system is closely related to the properties of visual stimuli commonly found in the natural environment. Most of what is known about visual processing comes from studies using “artificial” stimuli, including sets of simple stimulus parameters (such as light spots or sinusoidal gratings) and populations of stimuli with simple statistics (e.g., white noise).

[0003] like Figure 1 As shown in the figure, the light signal is projected onto the surface of the retina through the lens. The ganglion cells and cone cells on the surface of the retina are stimulated by light and trigger neural signals. The visual neural signals are transmitted to the visual perception areas of the hypothalamus and cerebral cortex through the optic nerve, thus realizing visual perception. In recent decades, people have conducted in-depth research on the directional and direction selectivity mechanisms of visual cortical cells. In order to better test the mechanisms of visual nerve cells, well-designed simple stimuli are key to explaining the neural basis of sensory processing. In the visual system, simple stimuli such as light spots or light columns reveal the receptive field (RF) structure of retinal and thalamic neurons and the directional selectivity of cortical neurons. A major advantage of these stimuli is that they are easy to parameterize. Therefore, this stimulus helps to determine the dependence of neuronal responses on specific stimulus parameters.

[0004] The main sensory input to the visual cortex comes from the lateral geniculate nucleus. The cells here are not selective or biased towards the direction of visual stimulation or the direction of motion. However, the output of cortical cells is highly selective for both parameters. To verify the influence of direction on visual cells, neurons in the cat visual cortex (area 17) were used for intracellular recordings to compare the orientation and direction selectivity of the cell output signals with the cell receiving signals. The cat's vision is stimulated by visual stimulation in the direction of the movement of the light spot, which causes the visual cells to respond with postsynaptic potentials (PSPs). At the same time, based on the number and morphology of spikes generated during the response, the connection between the direction of motion and the visual nerve can be inferred. The direction and direction selection are determined by the response caused by the moving rod. With the stimulation, the number and morphology of action potentials can be observed.

[0005] The existing technology uses an Axon-Hillock-like neural circuit, as shown in Figure 2(a). This circuit has no comparator. After the input neural-like photoelectric signal is converted into a voltage signal, it is directly output through two inverters, inv1 and inv2. The entire circuit is a closed-loop circuit with high power consumption and is not suitable for use in large-scale integrated circuits. Summary of the invention

[0006] [Technical issues]

[0007] The neural circuit of the prior art does not have a comparator. After the input neural photoelectric signal is converted into a voltage signal, it is directly output through two inverters. The entire circuit is a closed-loop circuit with high power consumption and is not suitable for use in large-scale integrated circuits.

[0008] [Technical solution]

[0009] The present invention provides an ultra-low power consumption neural circuit, comprising: a photoelectric receiver, an amplifier, and a mirror current source comparator; the photoelectric receiver, the amplifier, and the mirror current source comparator are cascaded, and the amplifier and the mirror current source comparator have a common part; the amplifier amplifies the input signal of the photoelectric receiver, the photoelectric receiver is used to generate a neural signal, and the amplifier is used to amplify the input neural signal; the mirror current source comparator is a double-end input single-end output structure; when the membrane voltage V mem Above the threshold voltage V thr When , the comparator output voltage Vc of the mirror current source is at a low level, otherwise, it is at a high level.

[0010] In one embodiment of the present invention, the comparator of the mirror current source includes four MOS devices M0, M1, M3, and M4; the drain of MOS device M0 is connected to the drain of MOS device M3; the source of MOS device M0 is connected to the source of MOS device M1, the drain of MOS device M1 is connected to the drain of MOS device M4, the gate of MOS device M3 is connected to the gate of MOS device M4, and the gate of MOS device M3 is connected to the drain of MOS device M3; the source of MOS device M3 and the source of MOS device M4 are respectively connected to the power supply voltage, the gate of MOS device M1 is the negative terminal input, and is connected to the membrane voltage V mem The input terminal connection of

[0011] In one embodiment of the present invention, the amplifier includes four MOS devices M1, M4, M5, and M6, wherein M1 and M4 are common parts of the amplifier and the comparator of the mirror current source; the gate of the MOS device M5 is connected to the gate of the MOS device M5; the drains of the MOS devices M1 and M4 are connected to the gates of the MOS devices M5 and M6, and the output between the drains of the MOS devices M1 and M4 is used as the comparator output voltage Vc, and the drains of the MOS devices M5 and M6 are connected to the output voltage V out .

[0012] In one embodiment of the present invention, a tail current source circuit is further included, including a MOS device M2; the sources of the MOS devices M0 and M1 are connected to the drain of the MOS device M2.

[0013] In one embodiment of the present invention, a branch current source circuit is also included, including a MOS device M7; the drain of the MOS device M7 is connected to the membrane voltage V mem The input terminal is connected, and the membrane voltage V mem The input end of the MOS device M7 is provided with an input current terminal Iin, which is connected to the power supply voltage; the gate of the MOS device M7 is connected to the gate of the MOS device M2, and the gate of the MOS device M7 is also connected to the output voltage V out connect.

[0014] In one embodiment of the present invention, a feedback capacitor C fb , feedback capacitor C fb One end of the feedback capacitor C is connected to the drain of the MOS device M7. fb The other end is connected to the gate of the MOS device M7.

[0015] In one embodiment of the present invention, the bias voltage of the MOS device M2 is outputted by V out Provided; when there is no input current, V out When the current is input, the bias voltage of MOS device M2 is 0.5mV.

[0016] In one embodiment of the present invention, the gate of the MOS device M0 is the positive input, and the gate of the MOS device M0 is connected to the threshold voltage V thr When the membrane voltage V mem Above the threshold voltage V thr When , the comparator output voltage Vc is low level, otherwise, it is high level.

[0017] [Beneficial Effects]

[0018] The circuit of the present invention combines an amplifier composed of two inverters with a comparator composed of five transistors, which effectively reduces the number of branches in the circuit while maintaining the original functions, thereby reducing the power consumption of the neural-like module.

[0019] The present invention changes the problem that the bias of the traditional tail current is generally provided by the bias voltage VB, which generates relatively large power consumption. The M2 shown by the solid line is used, and its control is controlled by the output voltage, which significantly reduces the power consumption. Through simulation, it can be seen that as the input current increases, the charging speed of the current to the feedback capacitor increases, which significantly reduces the charging time t of the membrane voltage. H . The membrane voltage quickly reaches the threshold voltage, causing the output voltage to convert and start the reset current. The power of the circuit tends to increase with the increase of the input current. The total power of the present invention is the smallest when the input current is 5pA, which is 35pW. Contrary to the power, the energy consumed by a spike signal decreases with the increase of the input current and tends to 3fJ. In addition, the present invention decreases the emission frequency with the increase of the power supply voltage Vdd, and its variation range is 1.5%. The higher the temperature, the emission frequency tends to increase overall. In the range of 27-41°C, the maximum offset of the emission frequency is 6%. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is the structure of the visual signal processing system.

[0021] FIG. 2( a ) is a traditional Axon-Hillock-type neural circuit; FIG. 2( b ) is an Axon-Hillock-type neural circuit of the present invention.

[0022] Figure 3 This is a working diagram of the neural-like circuit based on Axon-Hillock in Example 1 of the present invention.

[0023] Figure 4(a) is a diagram showing the power of a neural circuit and the power consumption of each spike; Figure 4(b) is a diagram showing the relationship between the peak emission frequency and the input current.

[0024] FIG5(a) is a circuit power comparison diagram of a single bias current source and an output bias current source, where P is the circuit power of the M2 tail current source and P' is the circuit power of the M2' tail current source; FIG5(b) is a peak power consumption comparison diagram of a single bias current source and an output bias current source, where E is the peak power consumption of the M2 tail current source and E' is the peak power consumption of the M2' tail current source.

[0025] FIG6(a) is a graph showing the effect of power supply voltage on transmission frequency; FIG6(b) is a graph showing the effect of temperature on transmission frequency.

[0026] Figure 7 This is a diagram of the transient simulation results of a neural-like circuit. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0028] Example 1

[0029] In order to simulate the neural signals generated when retinal cells are exposed to light, this embodiment provides a neural-like transmitter based on retinal cells. The photodiode in the transmitter can generate a certain current according to the light intensity. The current serves as an input signal of the neural-like circuit and induces the neural-like circuit to generate a spike signal with a certain firing rate.

[0030] The neural signal generation circuit of this embodiment is shown in FIG2. FIG2(a) shows the original Axon-Hillock circuit, and FIG2(b) shows the circuit of this embodiment, which adds a comparator that can set the threshold voltage on the basis of the original Axon-Hillock structure. The structure composed of two MOS tubes M1 and M4 can be regarded as the first-stage inverter in the amplifier, and can also be regarded as half of the differential circuit in the threshold voltage comparator. When M1 and M4 are used as comparators, M 0-4 M0-M4 form a comparator structure with a mirror current source. This structure has a double-end input and a single-end output. The gate of M0 is the positive input and serves as the reference threshold voltage. The gate of M1 is the negative input and serves as the membrane voltage input. When the membrane voltage V mem Above the threshold voltage V thr When , the comparator output voltage Vc is low level, otherwise, it is high level. When M1 and M3 are used as the first stage inverter of the amplifier, they function the same as the first stage inverter in the figure. The output V c The second stage inverter can be effectively controlled. When the membrane voltage V mem Above the threshold voltage, the output of the first stage inverter V c is low level. This low level causes the output of the second-stage inverter (i.e., the output of the neural module) to become high level. Different from the structure in which the amplifier and the comparator are independent of each other in the design in the figure, the present invention combines an amplifier composed of two inverters with a comparator composed of five transistors, which effectively reduces the number of branches in the circuit while maintaining the original functions, thereby reducing the power consumption of the neural module.

[0031] In addition, in order to reduce DC power consumption and the energy required to generate spike signals, the neural unit of this embodiment is simplified based on the structure in the figure. The first step is to remove the membrane capacitance C mem , the parasitic capacitance in the negative half of the comparator (i.e., the first-stage inverter) is used as part of the membrane capacitance. In addition, when the neural circuit is in the initial state, the output voltage V out is 0. At this time, the feedback capacitor Cfb It can be regarded as one end grounded. Therefore, C fb It can also be used as part of the membrane capacitor. The second step is to omit the sodium and potassium ion current sources and the reset current source. Since Vdd (the short horizontal line above M3, M4, M5 and Iin) uses a 0.5V power supply voltage, the output voltage V out The maximum value of and the gate voltage of the reset current switch tube M7 are also 0.5V. By reasonably setting the width-to-length ratio of M7, the width-to-length ratio of M7 is in the range of 1:1 to 100:1. M7 can be regarded as both a switch tube and a device for generating the reset current I r After eliminating multiple branch current sources, the DC power consumption of the neural-like circuit is significantly reduced.

[0032] In the design of the comparator tail current source, relevant processing is also done to save static power consumption. Usually, the tail current source M 2’ The bias voltage has other voltage reference source V b Provide. thr The voltage bias also keeps M0 on. Therefore, even if the input current Iin is 0, M 2’ There is still DC current flowing through the branch M0 and M3. In the resting state, the neural circuit still has a lot of power loss. To solve this problem, the bias voltage of M2 is output V out When there is no input current, V out When the current is input, the bias voltage of M2 is 0.5mV.

[0033] The working process of the neural circuit of the present invention is as follows: when there is no light, the current source I representing the photosensitive diode in The input current I in is 0. At this time, the membrane voltage V mem is 0, which is lower than the threshold voltage V thr , resulting in an output voltage V out The membrane capacitor has no charging current, and M7 is cut off, so no reset current is generated. When there is light, the photodiode generates a constant DC current I in .like Figure 3 As shown, the feedback capacitor C fb I in The charging makes the membrane voltage V mem Then it increases. mem Before reaching the threshold voltage, the output voltage of the neural circuit is always at 0 potential. mem Increases to the threshold voltage V thr When the output of the first stage inverter is V c The output of the second inverter V outRapidly changes from 0 to Vdd. At the same time, through the positive feedback capacitor V fb , V out Make the membrane voltage V mem Pull up to above V out The potential of the comparator and inverter is kept stable. out The reset current source M7 is turned on and generates a reset current I r . Because the reset current I r Greater than the input current I in , membrane voltage V mem Gradually decreases to the threshold voltage V thr . Therefore, the output voltage of the comparator and the brain-like neural circuit is reset to the initial state. The reset current source is turned off again, the feedback capacitor is charged by the input current again, and the neural circuit regenerates the next spike signal. As can be seen from the figure, the resting time T H Controlled by input current, feedback capacitance and threshold voltage. The larger the input current, the smaller its rest time. The larger the feedback capacitance, the longer the rest time. The lower the threshold voltage, the smaller the rest time. The spike width is controlled by input current and reset current. The larger the current difference between the two, the smaller the spike width.

[0034] When the input current is 0, no spike signal is generated in the neural circuit. Since there is no charging current in the feedback capacitor, the membrane voltage V mem is 0. Therefore, the bias voltage of the tail current source M2 is 0. The comparator cannot work because it is not grounded. At this time, except for the weak leakage current of M3 and M7, other MOS tubes in the neural circuit have no static current. Therefore, when there is no input current, the static power consumption of the circuit is the lowest, which is 3pW. When the input current is not 0, the membrane voltage V mem Gradually rising, the tail current source M2 is turned on and provides current to the comparator. At the time point when the membrane voltage is the same as the threshold voltage, the two branches of the comparator are all turned on, and each receives half of the leakage current of M2. At this time, all the neural circuits except M6 and M9 have current passing through them. Therefore, the neural circuit in this state has the highest power consumption.

[0035] The present invention simulates the power consumption of the neuron-like circuit and the energy consumed by each spike signal under different input currents. FIG4 records the variation trend of the total power of the neuron-like circuit and the energy consumed by a spike signal when the input current ranges from 1pA to 150pA.

[0036] Figure 4(a) shows the relationship between circuit power and peak power consumption and input current. When the photodiode generates input current, the power P of the neural circuit is the product of the power supply voltage Vdd and the DC current. E refers to the energy consumed by each spike signal emitted. As the input current I inAs the input current increases, the charging speed of the feedback capacitor increases, and the frequency of state changes in the neuron-like circuit increases. The proportion of time points when the membrane voltage is the same as the threshold voltage increases, so the power of the circuit tends to increase with the increase of input current. The total power is the smallest at 35pW when the input current is 5pA. In contrast to the power, the energy consumed by a spike signal decreases with the increase of input current, tending to 3fJ. This is because the emission frequency of the spike signal increases with the increase of input current. The cycle time occupied by a spike signal decreases. Under the neutralization of the cycle time, even if the circuit power increases, the energy consumed by a spike signal decreases.

[0037] Figure 4(b) shows the relationship between the transmission frequency and the input current. The transmission frequency is positively correlated with the input current. This is because as the input current increases, the charging speed of the feedback capacitor increases, which significantly reduces the charging time t of the membrane voltage. H The membrane voltage quickly reaches the threshold voltage, causing the output voltage to transition and turning on the reset current.

[0038] As shown in Figure 5, different schemes are simulated and compared for the improvement of the tail current source of the comparator. The tail current source formed by M2 is biased by the feedback voltage at the output. The tail current source formed by M2' is biased by a separate voltage source. By comparison, it is found that the use of the M2 tail current source significantly reduces the power of the circuit and the power consumption required for each spike emission.

[0039] To verify the influence of power supply voltage Vdd and ambient temperature on the frequency of the Dharmakaya, the neural circuit is simulated under the conditions of feedback capacitance of 5fF and input current of 40pA. As shown in Figure 6(a), as the power supply voltage Vdd increases, the transmission frequency decreases, and its variation range is 1.5%. The variation of transmission frequency with temperature is shown in Figure 6(b). The higher the temperature, the higher the transmission frequency is. In the range of 27-41℃, the maximum deviation of the transmission frequency is 6%.

[0040] Figure 7 The transient simulation results of neural circuits in Virtuoso are shown. in When there is no current input, the current does not charge the feedback capacitor, so V mem Keep 0 potential. When the current is 3pA, V mem Start charging and discharge under the control of reset current. V out Generates a spike signal with a certain transmission frequency.

[0041] The above shows that the design of the present invention has better performance in terms of low power and energy consumed per spike. The designed neural circuit is used to simulate the frequency information generated by the retinal signal after being illuminated. It also has more important applications in machine learning and brain-like computing.

[0042] The protection scope of the present invention is not limited to the above-mentioned embodiments. Any modifications, equivalent substitutions and improvements that can be made by professionals in the field within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An ultra-low power consumption neural circuit, characterized in that: include: Photoelectric receivers, amplifiers, comparators for mirror current sources; The photoelectric receiver, amplifier, and comparator of the mirror current source are cascaded, and the amplifier and the comparator of the mirror current source have a common part; The amplifier amplifies the input signal of the photoelectric receiver, the photoelectric receiver is used to generate a neural-like signal, and the amplifier is used to amplify the input neural-like signal; The comparator of the mirror current source has a dual-end input and single-end output structure; when the membrane voltage V mem Above the threshold voltage V thr When , the comparator output voltage Vc of the mirror current source is low level, otherwise, it is high level; The comparator of the mirror current source includes four MOS devices M0, M1, M3, and M4; the drain of MOS device M0 is connected to the drain of MOS device M3; the source of MOS device M0 is connected to the source of MOS device M1, the drain of MOS device M1 is connected to the drain of MOS device M4, the gate of MOS device M3 is connected to the gate of MOS device M4, and the gate of MOS device M3 is connected to the drain of MOS device M3; the source of MOS device M3 and the source of MOS device M4 are respectively connected to the power supply voltage, the gate of MOS device M1 is the negative terminal input, and is connected to the membrane voltage V mem The input terminal connection of The amplifier includes four MOS devices M1, M4, M5, and M6; Among them, M1 and M4 are the common parts of the amplifier and the comparator of the mirror current source; the gate of the MOS device M5 is connected to the gate of the MOS device M5; the drains of the MOS devices M1 and M4 are connected to the gates of the MOS devices M5 and M6, and the output between the drains of the MOS devices M1 and M4 is used as the comparator output voltage Vc, and the drains of the MOS devices M5 and M6 are connected to the output voltage V out ; It also includes a tail current source circuit, including a MOS device M2; the sources of the MOS devices M0 and M1 are connected to the drain of the MOS device M2; The branch current source circuit is also included, including a MOS device M7; the drain of the MOS device M7 is connected to the membrane voltage V mem The input terminal is connected to the membrane voltage V mem The input end is provided with an input current terminal Iin, and Iin is connected to the power supply voltage; The gate of the MOS device M7 is connected to the gate of the MOS device M2, and the gate of the MOS device M7 is also connected to the output voltage V out connect; The width-to-length ratio of the MOS device M7 is in the range of 1:1 to 100:

1.

2. The ultra-low power consumption neural circuit according to claim 1, characterized in that: It also includes the feedback capacitor C fb , feedback capacitor C fb One end of the feedback capacitor C is connected to the drain of the MOS device M7. fb The other end is connected to the gate of the MOS device M7.

3. The ultra-low power consumption neural circuit according to claim 2, characterized in that: The bias voltage of MOS device M2 is determined by the output V out Provided; when there is no input current, V out When it is 0, M2 has no static current; when there is current input, the bias voltage of MOS device M2 is 0.5mV.

4. The ultra-low power consumption neural circuit according to claim 3, characterized in that: The gate of MOS device M0 is the positive input. The gate of MOS device M0 is connected to the threshold voltage V thr When the membrane voltage V mem Above the threshold voltage V thr When , the comparator output voltage Vc is low level, otherwise, it is high level.

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