Image sensor and method of operating the same

Abstract

An image sensor and a method of operating the image sensor, the image sensor including an active pixel array, at least one dummy reset array, a dummy read array, and an image processor. The image processor sequentially resets corresponding rows of pixels included in the at least one dummy reset array during a period when pixels of the active pixel array do not perform a reset operation, and sequentially reads corresponding rows of pixels included in the dummy read array during a period when pixels of the active pixel array do not perform a read operation.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0090486, filed on July 25, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] One or more example embodiments relate to an image sensor, and more particularly, to an image sensor including dummy pixels that perform a rolling - shutter operation and a method of operating the image sensor. Background art

[0004] An electronic device having an image - capturing function, such as a digital camera or a smartphone, may include an image sensor. An image sensor, which is a semiconductor device for converting optical information into an electrical signal, may be, for example, a charge - coupled device (CCD) or a complementary metal - oxide - semiconductor (CMOS).

[0005] An image sensor includes a plurality of pixels each including a photoelectric conversion element and a plurality of transistors. A signal on which photoelectric conversion is performed by the photoelectric conversion element is processed and output by the plurality of transistors, and image data may be generated based on signals output from the plurality of pixels. Each of the plurality of pixels may perform photoelectric conversion on light of a specific color or wavelength and may output a signal according to the photoelectric conversion. Summary of the invention

[0006] One or more example embodiments provide an image sensor capable of removing band noise generated by different coupling coefficients in each row of an active pixel array when performing a rolling - shutter operation and capable of improving image quality.

[0007] According to an aspect of an example embodiment of the present disclosure, there is provided an image sensor including an active pixel array, at least one dummy reset array, a dummy read array, and an image processor. The image processor is configured to sequentially reset corresponding rows of pixels included in the at least one dummy reset array during a period when pixels of the active pixel array do not perform a reset operation, and sequentially read corresponding rows of pixels included in the dummy read array during a period when pixels of the active pixel array do not perform a read operation.

[0008] According to an aspect of an example embodiment of the present disclosure, there is provided a method of operating an image sensor including a pixel image including a plurality of shared pixels. The method includes: sequentially resetting corresponding rows of pixels included in at least one dummy reset array during a period when pixels of the active pixel array do not perform a reset operation; and sequentially reading corresponding rows of pixels included in the dummy read array during a period when pixels of the active pixel array do not perform a read operation.

[0009] According to one aspect of an exemplary embodiment of the present disclosure, a method of operating an image sensor is provided, the image sensor including a pixel image including a plurality of shared pixels. The method includes: sequentially performing a reset operation and a read operation in respective rows of an active pixel array; sequentially performing a read operation in respective rows of a dummy read array during a period when the active pixel array does not perform a read operation; and sequentially performing a reset operation in respective rows of at least one dummy reset array during a period when the active pixel array does not perform a reset operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of an image sensor according to an exemplary embodiment of the present disclosure;

[0012] Figure 2A illustrates an example of causing different coupling coefficients between rows of two pixels sharing a floating diffusion (FD) node;

[0013] Figure 2B illustrates another example of causing different coupling coefficients between rows of four pixels sharing an FD node;

[0014] Figure 2C illustrates another example of causing different coupling coefficients between rows of pixels respectively connected to different output lines;

[0015] Figure 3 is a view illustrating a problem that occurs when a dummy pixel array operates in a fixed row;

[0016] Figure 4A illustrates an example of an arrangement of a pixel array including a dummy read array and a dummy reset array according to an exemplary embodiment of the present disclosure;

[0017] Figure 4B illustrates another example of an arrangement of a pixel array including a dummy read array and a dummy reset array according to an exemplary embodiment of the present disclosure;

[0018] Figure 4C illustrates another example of an arrangement of a pixel array including a dummy read array and a dummy reset array according to an exemplary embodiment of the present disclosure;

[0019] Figure 5A illustrates an example of a case of using two dummy reset arrays according to an exemplary embodiment of the present disclosure;

[0020] Figure 5BShows an example of a case where the size of a dummy reset array is changed according to an exemplary embodiment of the present disclosure;

[0021] Figure 6 Shows an example of a case where multiple reset operations are performed according to an exemplary embodiment of the present disclosure;

[0022] Figure 7 Shows a pattern of color filters arranged in a pixel array according to an exemplary embodiment of the present disclosure; and

[0023] Figure 8 Is a block diagram of a computing system including an image sensor according to an exemplary embodiment of the present disclosure. Detailed Description of the Invention

[0024] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 Is a block diagram of an image sensor 10 according to an exemplary embodiment of the present disclosure.

[0026] Referring to Figure 1 , the image sensor 10 may include a pixel array 100 in which a plurality of pixels are arranged in a matrix, a correlated double sampling (CDS) 120, an analog-to-digital converter (ADC) 130, a buffer 140, a row driver 150, a timing generator 160, a control register 170, and a ramp signal generator 180.

[0027] The timing generator 160 may generate one or more control signals for controlling the operations of the CDS 120, ADC 130, row driver 150, and ramp signal generator 180. The control register 170 may generate one or more control signals for controlling the operations of the buffer 140, timing generator 160, and ramp signal generator 180.

[0028] The row driver 150 may drive the pixel array 100 in units of row lines. For example, the row driver 150 may generate a selection signal capable of selecting one row line from among a plurality of row lines. Each of the plurality of pixels may sense incident light and may output an image reset signal and an image signal to the CDS 120 through column lines. The CDS 120 may perform sampling on the received image reset signal and image signal.

[0029] The ADC 130 may output a comparison signal by comparing a ramp signal output from the ramp signal generator 180 with a sampling signal output from the CDS 120. The level transition time of the comparison signal may be counted according to a clock signal provided from the timing generator 160, and the count value may be output to the buffer 140. The ramp signal generator 180 may operate under the control of the timing generator 160.

[0030] Referring to Figure 1 , it shows that the CDS 120 and the ADC 130 receive a column line signal output from the pixel array 100. However, the present disclosure is not limited thereto. In an exemplary embodiment, the image sensor 10 may include two CDSs and two ADCs. In this case, in the pixel array 100, the column line signals of the first region (e.g., the upper pixels of half of the pixel array 100) may be sent to the first CDS and the first ADC. In the pixel array 100, the column line signals of the second region (e.g., the lower pixels of half of the pixel array 100) other than the first region may be sent to the second CDS and the second ADC.

[0031] The buffer 140 may store a plurality of digital signals output from the ADC 130, and may sense, amplify, and output the plurality of digital signals. Therefore, the buffer 140 may include a memory (not shown) and a sense amplifier (not shown). The memory (not shown) is configured to store a count value, and the count value is related to the signals output from a plurality of pixels. The sense amplifier (not shown) may sense and amplify the count value output from the memory (not shown).

[0032] Figure 2A is an exemplary embodiment of a circuit diagram of a shared pixel in which two pixels share a floating diffusion (FD) node, Figure 2B is an exemplary embodiment of a circuit diagram of a shared pixel in which four pixels share an FD node, Figure 2C is an exemplary embodiment of a circuit diagram of a pixel connected to different column output lines.

[0033] According to an exemplary embodiment, Figures 2A to 2C shows an example in which the coupling coefficients are different in each row of the pixel array 100. The coupling coefficient may refer to the parasitic capacitance generated between the transfer transistor and the FD node and / or the column output line of each of the plurality of pixels.

[0034] Referring to Figure 2A , the shared pixel may include two pixels. Specifically, the shared pixel may include a plurality of photosensitive devices PD0 and PD1, a plurality of transfer transistors including a first transfer transistor TG0 and a second transfer transistor TG1, a selection transistor SG, a driving transistor DG, and a reset transistor RG.

[0035] Referring to Figure 2B, the shared pixel may include four pixels. Specifically, the shared pixel may include a plurality of photosensitive devices PD11, PD12, PD13, and PD14, a plurality of transfer transistors including a first transfer transistor TG11, a second transfer transistor TG12, a third transfer transistor TG13, and a fourth transfer transistor TG14, a selection transistor SG, a driving transistor DG, and a reset transistor RG.

[0036] Each photosensitive device may generate photo charges according to the intensity of incident light. For example, each photosensitive device may be a P-N junction diode and may generate charges in proportion to the amount of received light, that is, electrons as negative charges and holes as positive charges. Each photosensitive device may correspond to a photoelectric conversion element, and examples thereof include, but are not limited to, at least one of the following: a phototransistor, a photogate, a pinned photodiode (PPD), and any combination among a phototransistor, a photogate, and a PPD. Each of the transfer transistors TG11, TG12, TG13, and TG14 may be activated and may transfer the photo charges generated by the photosensitive devices to the FD node respectively. The driving transistor DG may correspond to a buffer amplifier. The driving transistor DG may be referred to as a source follower (SF). Since the gate terminal of the driving transistor DG is connected to the FD node, the voltage of the FD node may correspond to the gate voltage of the driving transistor DG. That is, the driving transistor DG may output the pixel signal VOUT by amplifying the gate voltage value changed according to the photo charges transferred to the FD node. The drain terminal of the selection transistor SG is connected to the source terminal of the driving transistor DG. The selection transistor SG may output the pixel signal VOUT to the CDS (e.g., Figure 1 120). The reset transistor RG may be activated in response to a reset signal and may change the voltage of the FD node to a reset voltage in response to the activation of the reset transistor RG.

[0037] According to an exemplary embodiment, the shared pixel may have various parasitic capacitances. Referring to Figure 2A , the shared pixel may be coupled between the FD node and the gate terminals of the first transfer transistor TG0 and the second transfer transistor TG1 connected to the FD node, and may have capacitances C TGFD0 and C TGFD1 . In addition, the shared pixel may be coupled between the gate terminals of the first transfer transistor TG0 and the second transfer transistor TG1 and the column output line, and may have parasitic capacitances C TGVO0 and C TGVO1 . The plurality of mutual capacitances may be different in each row. For example, the parasitic capacitances C TGFD1 and C TGVO1 coupled to the second transfer transistor TG1Significantly affected by the power supply voltage VPIX line or ground GND line (not shown) adjacent to the second transfer transistor TG1, the parasitic capacitance can be different. On the other hand, since the parasitic capacitances C TGFD0 and C TGVO0 coupled to the first transfer transistor TG0 can be positioned farther from the power supply voltage VPIX line or ground GND line (not shown) than the second transfer transistor TG1, the parasitic capacitances C TGFD0 and C TGVO0 may not be significantly affected by the power supply voltage VPLX line or ground GND line. Therefore, in shared pixels sharing the FD node, multiple parasitic capacitances can be different and have different capacitance values.

[0038] According to an example embodiment, referring to Figure 2B , parasitic capacitances C TGFD0 , C TGFD1 , C TGFD2 and C TGFD3 can be provided between the four transfer transistors TG11 to TG14 and the FD node. The first transfer transistor TG11 to the fourth transfer transistor TG14 can form the same column. The first transfer transistor TG11 to the fourth transfer transistor TG14 can respectively correspond to different rows. As described above, the first transfer transistor TG11 to the fourth transfer transistor TG14 corresponding to different rows can have different coupling coefficients. In addition, different parasitic capacitances C TGVO0 , C TGVO1 , C TGVO2 and C TGVO3 can be provided between the first transfer transistor TG11 to the fourth transfer transistor TG14 and the column output line.

[0039] According to an example embodiment, referring to Figure 2C , the first pixel APS0 and the second pixel APS1 can be respectively connected to different column output lines. For example, the first pixel APS0 can output an image signal through the first column output line VOUT0, and the second pixel APS1 can output an image signal through the second column output line VOUT1. In this case, the value of the parasitic capacitance C TGVO0 generated between the transfer transistor TG0 of the first pixel APS0 and the first column output line VOUT0 can be different from the value of the parasitic capacitance C TGVO1 generated between the second transfer transistor TG1 of the second pixel APS1 and the second column output line VOUT1. This is because the first column output line VOUT0 and the second column output line VOUT1 are physically different wirings, so the distance between the transfer transistor TG0 and the first column output line VOUT0 can be different from the distance between the transfer transistor TG1 and the second column output line VOUT1.

[0040] Reference Figure 2A and Figure 2B show that in a shared pixel, two or four pixels share an FD node. However, the present disclosure is not limited thereto, and a plurality of pixels other than two or four pixels may be included in the shared pixel. For example, in the shared pixel, eight or sixteen pixels may share one FD node. Considering the appropriate balance to be maintained among the obtainable area gain, the reduced read speed, and the increased complexity of control signals according to the increase in the number of pixels sharing the FD node, the number of pixels included in the shared pixel may vary according to the exemplary embodiment. In addition, in the above exemplary embodiment, it is shown that the coupling coefficients of the shared pixels sharing the FD node or the pixels connected to different column output lines may be different from each other. However, the present disclosure is not limited thereto. For example, a pixel array according to an exemplary embodiment of the present disclosure may have an asymmetric pixel array structure in which the coupling coefficients are different in each row and / or each column.

[0041] Figure 3 is a view showing problems that occur when the dummy pixel array operates in a fixed row.

[0042] Hereinafter, for convenience of explanation, a period during which the active pixel array sequentially performs only a reset operation without a read operation in a row may be referred to as a read blank period. In addition, a period during which the active pixel array sequentially performs only a read operation without a reset operation in a row may be referred to as a reset blank period. Assume that the active pixel array includes a plurality of rows from the m-th row to the p-th row (m and p are integers greater than 1).

[0043] Reference Figure 3 , in period 310, the active pixel array may sequentially perform a reset operation starting from the m-th row. That is, period 310 may correspond to the read blank period. At the final time point of period 310, the active pixel array may complete the reset operation of the (k - 1)-th row (k is an integer greater than m).

[0044] In period 320, the active pixel array may sequentially perform a reset operation starting from the k-th row, and may sequentially perform a read operation starting from the m-th row in which the reset operation has been completed. The read operation starting from the m-th row and the reset operation starting from the k-th row may be performed simultaneously. That is, in period 320, the active pixel array may simultaneously perform a read operation and a reset operation on different rows. At the final time point of period 320, the active pixel array may complete the reset operation of the p-th row. Since the read operation is performed after period 310, the active pixel array may sequentially complete the read operation of the (l - 1)-th row (l is an integer greater than k).

[0045] During period 330, the active pixel array may perform a read operation sequentially from row l to row p. Since the reset operation was completed on the active pixel array during the previous period, i.e., period 320, period 330 may correspond to a reset blank period.

[0046] According to an exemplary embodiment, during period 320, the same coupling coefficient may be repeated between the row where the read operation is performed and the row where the reset operation is performed. For example, when the second transfer transistor TG1 is activated to read row m at the start time point of period 320, noise based on the second coupling coefficient corresponding to the second transfer transistor TG1 may be caused. When the second transfer transistor TG1 is activated to reset row k at the start time point of period 320, noise based on the second coupling coefficient corresponding to the second transfer transistor TG1 may be caused. Subsequently, during period 320, whenever a reset operation or a read operation is performed, the transfer transistor activated by the reset operation and the transfer transistor activated by the read operation are the same, such that repetition occurs between the first transfer transistor TG0 and the second transfer transistor TG1. Since the activated transfer transistor switches repeatedly between the second transfer transistor TG1 and the first transfer transistor TG0, the coupling coefficient may also repeat between the second coupling coefficient corresponding to the second transfer transistor TG1 and the first coupling coefficient corresponding to the first transfer transistor TG0.

[0047] In another example, at the start time point of period 320, the first transfer transistor TG0 is activated to read row m, and the second transfer transistor TG1 may be activated to reset row k. In this case, the coupling coefficient caused during the read operation may be the first coupling coefficient based on the first transfer transistor TG0, and the coupling coefficient caused during the reset operation may be the second coupling coefficient based on the second transfer transistor TG1. Since the transfer transistors are activated sequentially in each row during period 320, the image quality during period 320 may be uniform. That is, although the read operation and the reset operation are performed sequentially in each row, the coupling coefficient caused by the read operation in the row may correspond to the same coupling coefficient (in this example, the first coupling coefficient), and the coupling coefficient caused by the reset operation in the row may correspond to the same coupling coefficient (in this example, the second coupling coefficient). Therefore, when the image signal output during period 320 may include noise based on a uniform coupling coefficient, an image signal with uniform quality may be output during period 320.

[0048] The image quality in period 310 or 330 may be different from the image quality in period 320. Specifically, assume that at the start time point of period 310, the active pixel array activates the first transfer transistor TG0 and the dummy read array DRD activates the first transfer transistor TG0. When resetting the m-th row, the active pixel array may be affected by the first coupling coefficient based on the first transfer transistor TG0, and the dummy read array may also be affected by the first coupling coefficient based on the first transfer transistor TG0. Subsequently, the active pixel array may activate the second transfer transistor TG1 to reset the (m + 1)-th row as the next row. Therefore, when resetting the (m + 1)-th row, noise is generated in the active pixel array according to the second coupling coefficient based on the second transfer transistor TG1. On the other hand, since the dummy read array toggles the first transfer transistor TG0 in a fixed row, the first transfer transistor TG0 may also be activated at the time point of resetting the (m + 1)-th row. Therefore, in the (m + 1)-th row, noise is generated in the active pixel array according to the second coupling coefficient, and different noise is generated in the dummy read array according to the first coupling coefficient. Therefore, the quality of the entire image deteriorates repeatedly in each row, and thus, the quality of the image signal output in period 310 or 330 may be non-uniform.

[0049] Figure 4A An example of the arrangement of a pixel array including a dummy read array and a dummy reset array according to an exemplary embodiment of the present disclosure is shown. Figure 4B Another example of the arrangement of a pixel array including a dummy read array and a dummy reset array according to an exemplary embodiment of the present disclosure is shown. Figure 4C Another example of the arrangement of a pixel array including a dummy read array and a dummy reset array according to an exemplary embodiment of the present disclosure is shown. Repeated descriptions made previously with reference to Figure 1 will be omitted.

[0050] Referring to Figure 4A , in period 410, the active pixel array may sequentially perform a reset operation starting from the m-th row. It may be assumed that the active pixel array activates the first transfer transistor TG0 in the m-th row. According to the exemplary embodiment, the dummy read array DRD may sequentially perform a read operation starting from the first row. Although Figure 3 the dummy read array of Figure 4AThe dummy read array can perform read operations sequentially from the first row to the nth row. For example, it can be assumed that the dummy read array activates the first transfer transistor TG0 in the first row. Subsequently, both the dummy read array and the active pixel array can sequentially switch the second transfer transistor TG1 and the first transfer transistor TG0. That is, the active pixel array activates the second transfer transistor TG1 in the (m + 1)th row, and the dummy read array can activate the second transfer transistor TG1 in the second row. Next, the active pixel array activates the first transfer transistor TG0 in the (m + 2)th row, and the dummy read array can activate the first transfer transistor TG0 in the third row. Therefore, although the dummy read array and the active pixel array perform read operations and reset operations sequentially in each row respectively, noise based on the same coupling coefficient can be generated. Thus, the image quality does not fluctuate in each row.

[0051] In another example, it can be assumed that the active pixel array activates the first transfer transistor TG0 in the mth row, and the dummy read array activates the second transfer transistor TG1 in the first row. Therefore, in the active pixel array, noise based on the first coupling coefficient of the first transfer transistor TG0 can be generated, and in the dummy read array, noise based on the second coupling coefficient of the second transfer transistor TG1 can be generated. Although the dummy read array and the active pixel array have different second and first coupling coefficients respectively, since the dummy read array and the active pixel array switch the first transfer transistor TG0 and the second transfer transistor TG1 respectively in the next row, noise based on the first coupling coefficient of the first transfer transistor TG0 can be generated in the dummy read array, and noise based on the second coupling coefficient of the second transfer transistor TG1 can be generated in the active pixel array. That is, since the coupling coefficient of the dummy read array and the coupling coefficient of the active pixel array have a consistent difference between the first coupling coefficient and the second coupling coefficient in period 410, image quality fluctuations in each row can be prevented in period 410, and uniform image quality can be provided in period 410.

[0052] In period 420, the active pixel array can perform reset operations sequentially starting from the kth row and can perform read operations sequentially starting from the mth row, which is similar to the operations performed in Figure 3 period 320. Repeated descriptions will be omitted.

[0053] In period 430, the active pixel array may perform a read operation sequentially starting from row l. It can be assumed that the active pixel array activates the first transfer transistor TG0 in row l. The dummy reset array DRS may perform a reset operation sequentially starting from row n. It can be assumed that the dummy reset array activates the first transfer transistor TG0 in row n. Subsequently, both the dummy reset array and the active pixel array may sequentially switch the second transfer transistor TG1 and the first transfer transistor TG0. That is, the active pixel array activates the second transfer transistor TG1 in row l + 1, and the dummy reset array may activate the second transfer transistor TG1 in row n + 1. Next, the active pixel array activates the first transfer transistor TG0 in row l + 2, and the dummy reset array may activate the first transfer transistor TG0 in row n + 2. Therefore, although both the dummy reset array and the active pixel array perform a reset operation and a read operation sequentially in each row, noise based on the same difference in the coupling coefficient can be generated. Therefore, the image quality may not fluctuate in each row.

[0054] In another example, it can be assumed that the active pixel array may perform a read operation sequentially starting from row l, and the dummy reset array activates the second transfer transistor TG1 in row n. Therefore, in the active pixel array, noise based on the first coupling coefficient of the first transfer transistor TG0 can be generated, and in the dummy reset array, noise based on the second coupling coefficient of the second transfer transistor TG1 can be generated. Although the coupling coefficient of the dummy reset array and the coupling coefficient of the active pixel array are different from each other, since the dummy reset array and the active pixel array switch the first transfer transistor TG0 and the second transfer transistor TG1 in the next row respectively, noise based on the first coupling coefficient of the first transfer transistor TG0 can be generated in the dummy reset array, and noise based on the second coupling coefficient of the second transfer transistor TG1 can be generated in the active pixel array. That is, since the coupling coefficient of the dummy reset array and the coupling coefficient of the active pixel array have a consistent difference between the first coupling coefficient and the second coupling coefficient in period 430, image quality fluctuations in each row can be prevented in period 430. Therefore, uniform image quality can be provided in period 430.

[0055] Referring to Figure 4B and Figure 4C , according to the exemplary embodiment, the arrangement of the dummy reset array and the dummy read array may be changed. In Figure 4B the exemplary embodiment, the active pixel array may be arranged at the lower part of the pixel array 100 and operate starting from the first row, and the dummy read array and the dummy reset array may be arranged at the upper part of the pixel array 100. In Figure 4B the operations in periods 440, 450, and 460 in Figure 4AThe operations in time periods 410, 420, and 430 described in

[0056] Referring to Figure 4A and Figure 4B , in time periods 410 and 440 or time periods 430 and 460, the image quality does not deteriorate in each row. The initial image quality may vary based on the physical distance between the activated rows of the active pixel array and the activated rows of the dummy read array or the dummy reset array. For example, at the start time point of time period 410, the m-th row is activated in the active pixel array, and the first row is activated in the dummy read array. Thus, the physical distance between the activated rows in the active pixel array and the activated rows in the dummy read array may correspond to m rows. On the other hand, at the start time point of time period 440, since the first row is activated in the active pixel array and the i-th row is activated in the dummy read array, the physical distance between the activated rows may correspond to i rows. Therefore, the initial image quality may be higher in time period 410 when processing signals between activated rows that are closer to each other than in time period 440 when processing signals between activated rows that are spaced apart from each other.

[0057] In Figure 4C the example embodiment, the dummy read array may be arranged in the lower part of the pixel array 100, and the dummy reset array may be arranged in the upper part of the pixel array 100. Figure 4C The operations in time periods 470, 480, and 490 in Figure 4A may respectively correspond to the operations in time periods 410, 420, and 430 described in

[0058] According to an example embodiment, when, as Figure 4C shown, the dummy reset array is arranged on the upper region of the pixel array 100 and the dummy read array is arranged on the lower region of the pixel array 100, the initial image quality may be higher than Figure 4B and Figure 4C the example embodiments. However, the present disclosure is not limited thereto. The method of arranging the dummy array on the pixel array 100 may vary according to various factors such as the integration time (time difference between the reset operation and the read operation) and the frame length.

[0059] Figure 5A shows an example of a case of using multiple dummy reset arrays according to an example embodiment of the present disclosure.

[0060] According to an example embodiment, in the active pixel array, the integration time in the first frame may be set to be different from the integration time in the second frame. For example, referring to Figure 5A, the integration time in the first frame can correspond to the time period between the time point when the reset operation of the first frame starts and the time point when the read operation of the first frame starts, and the integration time in the second frame can correspond to the time period between the time point when the reset operation of the second frame starts and the time point when the read operation of the second frame starts. The length of the integration time in the first frame can be less than the length of the integration time in the second frame. For example, when the electronic device including the image sensor 10 is in a bright place when processing the first frame and moves to a dark place when processing the second frame, the control register 170 as shown in Figure 1 can generate a control signal that indicates that the integration time is set to be longer in the second frame than in the first frame. Since the time points at which the active pixel array sequentially performs the read operation are fixed, in order to provide a longer integration time in the second frame, the active pixel array can perform the reset operation earlier than the reset operation performed in the first frame based on the control signal.

[0061] Referring to Figure 5A , the dummy array can include a plurality of dummy reset arrays. When the dummy array includes a plurality of dummy reset arrays, the number of dummy reset arrays can correspond to n times the number of rows of the repeated coupling coefficient. For example, when the coupling coefficient is repeated in every two rows in the active pixel array (e.g., the first coupling coefficient of the first transfer transistor TG0 or the second coupling coefficient of the second transfer transistor TG1 in the example embodiment of Figure 2A ), the number of dummy reset arrays can correspond to 2×n = 2n. In another example, when the coupling coefficient is repeated in every four rows in the active pixel array (e.g., any one of the first coupling coefficient of the first transfer transistor TG11 to the fourth coupling coefficient of the fourth transfer transistor TG14 in the example embodiment of Figure 2B ), the number of dummy reset arrays can correspond to 4×n = 4n. Hereinafter, for the sake of convenience of description, an example embodiment will be described based on the case where two coupling coefficients are repeated in every two rows and the dummy array includes two dummy reset arrays DRS1 and DRS2.

[0062] In period 510, the active pixel array can sequentially perform reset operations in each row of the active pixel array. Since the active pixel array performs the reset operation and the read operation simultaneously in period 520, in order to make the image quality in period 510 and the image quality in period 520 uniform, in period 510, the dummy read array can sequentially perform read operations in each row of the dummy read array.

[0063] In period 520, the active pixel array can sequentially perform read operations and reset operations in the corresponding rows, which is similar to the operations performed in period 420 of FIG. 4. Repeated descriptions will be omitted.

[0064] During period 530, the active pixel array may perform read operations sequentially only in each row of the active pixel array. That is, at a time point after the start of period 530, for all rows of the active pixel array, the reset operation for the first frame is completed, but for all rows of the active pixel array, the read operation may not be completed. Since the read operation and the reset operation are performed simultaneously in period 520, in order to generate the same image quality as that in period 520, one of the dummy reset arrays may perform the reset operation sequentially in each row. For example, while the active pixel array performs read operations on the remaining rows of the first frame, the first dummy reset array DRS1 in the dummy reset array may be activated. While the active pixel array performs read operations sequentially in period 530, the first dummy reset array DRS1 performs reset operations sequentially, and thus, the image quality may be the same as that in the adjacent period, i.e., period 520. Fixed rows are not activated in the first dummy reset array and each row is activated sequentially, and thus, the image quality may also be uniform in period 530.

[0065] During period 540, the active pixel array may perform read operations and reset operations simultaneously. When the integration time is set to be longer in the second frame than in the first frame, the time for performing the reset operation for the second frame may be set earlier than in the first frame. Thus, the time interval during which the reset operation for the second frame is performed may overlap with the time interval during which the read operation for the first frame is performed. Since periods 510, 520, and 530 in which the image of the first frame is generated are based on the noise caused by simultaneously performing one reset operation and one read operation, period 540 may also be based on the noise caused by simultaneously performing one read operation and one reset operation. That is, in period 540, since the active pixel array may perform read operations and reset operations simultaneously, the dummy reset array and the dummy read array may not be activated.

[0066] Figure 5B Another example showing a case of using multiple dummy reset arrays according to an exemplary embodiment of the present disclosure is shown. The description made previously with reference to Figure 5A will not be repeated.

[0067] Referring to Figure 5B , in period 550, the active pixel array may perform reset operations sequentially in each row. The reset operation may be performed for the first frame. In order to generate the same image quality as that in period 560, the dummy read array may perform read operations sequentially in each row, which is similar to the operation performed in period 510 of Figure 5A . The repeated description will be omitted.

[0068] According to an exemplary embodiment, in period 550, the second dummy reset array DRS2 may perform a reset operation sequentially in each row. Specifically, in period 550, together with the read operation and the reset operation performed by the active pixel array for the first frame, the second dummy reset array DRS2 may additionally perform a reset operation. When generating an image of the first frame, in the entire pixel array, one read operation and two reset operations may be performed in different rows. One of the two reset operations may be the reset operation performed by the active pixel array for the first frame, and the other of the two reset operations may be the reset operation performed by the second dummy reset array DRS2. The second dummy reset array DRS2 is shown as being set to operate corresponding to the first frame. However, the present disclosure is not limited thereto. According to an exemplary embodiment, the first dummy reset array DRS1 may be set to operate corresponding to the first frame.

[0069] In period 570, the active pixel array may perform only a read operation. That is, period 570 may correspond to a reset blank period, and a read operation may be sequentially performed for the first frame in period 570. In period 570, if the dummy reset array is not activated, the image quality of the first frame generated in period 570 may be different from the image quality corresponding to periods 550 and 560. This is because, while the image quality corresponding to periods 550 and 560 is based on the difference between the coupling coefficients caused by one read operation and two reset operations through the entire pixel array, if the dummy reset array does not operate in period 570, the image quality corresponding to period 570 is determined according to the coupling coefficient caused by one read operation. To prevent this problem and provide a uniform image quality, each row of the dummy reset array may be sequentially activated in period 570, and both the first dummy reset array DRS1 and the second dummy reset array DRS2 may be activated. In this way, both the first dummy reset array and the second dummy reset array perform a reset operation sequentially, and the image quality may be the same as the image quality of period 560.

[0070] In the above exemplary embodiment, the number of dummy reset arrays is shown as two. However, the present disclosure is not limited thereto. As described above, the number of dummy reset arrays may correspond to a multiple of the minimum unit of rows in which the same coupling coefficient is repeated. For example, as Figure 2B shown, when the coupling coefficient is repeated every four rows, the number of dummy reset arrays may be 4, 8, 12,..., or 4n. In addition, when the active pixel array resets multiple rows simultaneously, the number of multiple rows reset simultaneously corresponds to the number of dummy reset arrays that perform a reset operation during the reset blank period.

[0071] Figure 6An example of a situation in which multiple reset operations are performed according to an exemplary embodiment of the present disclosure is shown.

[0072] Referring to Figure 6 , in period 610, the active pixel array may perform a reset operation for the first frame. Since only the reset operation is performed in period 610, the dummy read array may sequentially perform read operations. As described above in Figure 5B , in the entire pixel array, one read operation and two reset operations may be performed. The two reset operations for the first frame may include a reset operation performed in the active pixel array and a reset operation performed in the second dummy reset array.

[0073] In period 620, in the active pixel array, a read operation and a reset operation for the first frame may be performed, which is similar to the operation performed in period 560 of Figure 5B . A repeated description will be omitted.

[0074] In period 630, the active pixel array may perform one read operation and two reset operations at the same time point. According to an exemplary embodiment, when the electronic device including the pixel array 100 moves to a dark environment, the integration time in the second frame processed after the electronic device moves to the dark environment may be increased. Since the time point at which the reset operation for the second frame is performed is advanced according to the increase in the integration time for the second frame, the reset operation for the second frame may be performed before the read operation for the first frame and the reset operation for the first frame may be completed. That is, a read operation and a reset operation for the first frame and a reset operation for the second frame may be performed at the same time point in the active pixel array. In this case, since one read operation and two reset operations are performed in the active pixel array of the pixel array, the dummy array may not operate. If the dummy array operates in period 630, the number of read operations and reset operations performed in period 630 becomes different from the number of read operations and reset operations performed in periods 610, 620, and 640, and thus, the image quality of the first frame may not be uniform.

[0075] Figure 7 A pattern of color filters arranged in a pixel array according to an exemplary embodiment of the present disclosure is shown.

[0076] Referring to Figure 7, which shows a pixel array of a Bayer pattern and a pixel array of a quad Bayer pattern. According to an example embodiment, the pixel array of the Bayer pattern may include R pixels, G1 pixels, G2 pixels, and B pixels. In the pixel array of the quad Bayer pattern, each pixel of the Bayer pattern may be divided into four sub-pixels. For example, the R pixel of the Bayer pattern may be divided into four sub-pixels R1, R2, R3, and R4. According to an example embodiment, in the quad Bayer pattern, pixels of the same color may share an FD node. For example, the photosensitive devices and transfer transistors corresponding to the sub-pixels R1 to R4 may be connected to a common FD node.

[0077] In the above example embodiment, examples of the Bayer pattern and the quad Bayer pattern are shown. However, the present disclosure is not limited thereto, and other patterns of pixel arrays may be used. In another example embodiment, a pixel array of a Bayer pattern divided into nine sub-pixels may be used. For example, the R pixel of the Bayer pattern may be divided into nine pixels R1 to R9.

[0078] Figure 8 is a block diagram showing a computing system 800 including an image sensor according to an example embodiment of the present disclosure.

[0079] Referring to Figure 8 , the computing system 800 may include an image processor 810, a memory device 820, a storage device 830, an image sensor 840, an input and output device 850, and a power supply 860. The image sensor 840 may include a pixel array according to an example embodiment of the present disclosure. Although not shown in Figure 8 , the computing system 800 may further include ports that can communicate with a video card, a sound card, a memory card, a universal serial bus (USB) device, or other electronic devices.

[0080] The image processor 810 may perform specific calculations or tasks. For example, the image processor 810 may include a microprocessor or a central processing unit (CPU). The image processor 810 may communicate with the memory device 820, the storage device 830, and the input and output device 850 through an address bus, a control bus, and a data bus. For example, the image processor 810 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. When receiving a digital zoom instruction from a host, the image processor 810 may output zoom information according to the digital zoom instruction to the image sensor 840 through the bus.

[0081] The memory device 820 may store data required for the operation of the computing system 800. For example, the memory device 820 may include dynamic random access memory (DRAM), mobile DRAM, static RAM (SRAM), or non-volatile access devices. The memory chips may be mounted separately or together using various forms of packaging. For example, the chips may be packaged as packages such as package-on-package (PoP), ball grid array (BGA), chip scale package (CSP), leaded plastic chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP).

[0082] The storage device 830 may include a solid state drive (SSD), a hard disk drive (HDD), and a compact disc read-only memory (CD-ROM). The input and output devices 850 may include an input unit such as a keyboard, a keypad, and a mouse, and an output unit such as a printer and a display. The power supply 860 may supply the operating voltage required for the operation of the computing system 800.

[0083] The image sensor 840 may be connected to the image processor 810 via a bus or another communication link and may perform communication. According to an embodiment of the present disclosure, the image sensor 840 may prevent image quality from deteriorating in each row and may remove band noise that may be caused by a dummy reset array or a dummy read array that performs a rolling shutter operation. The image sensor 840 may be integrated with the image processor 810 on one chip or may be integrated with the image processor 810 on different chips. On the other hand, the computing system 800 should be understood to include all possible computing systems that use the image sensor 840. For example, the computing system 800 may include a digital camera, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, and a tablet personal computer (PC).

[0084] According to an example embodiment, at least one of the components, elements, modules, or units described herein may be embodied as various amounts of hardware, software, and / or firmware structures that perform the corresponding functions described above. For example, at least one of these components, elements, or units may use a direct circuit structure such as a memory, a processor, a logic circuit, a look-up table, etc., which may perform the corresponding functions through the control of one or more microprocessors or other control devices. In addition, at least one of these components, elements, or units may be embodied specifically by a module, a program, or a portion of code that includes one or more executable instructions for performing a specified logical function and that are run by one or more microprocessors or other control devices. In addition, at least one of these components, elements, or units may further include a processor (such as a central processing unit (CPU)), a microprocessor, etc., that perform the corresponding functions, or may be implemented by a processor (such as a central processing unit (CPU)), a microprocessor, etc., that perform the corresponding functions. Two or more of these components, elements, or units may be combined into a single component, element, or unit that performs all of the operations or functions of the two or more combined components, units, or elements. In addition, at least a portion of the functions of at least one of these components, elements, or units may be performed by another of these components, elements, or units. In addition, although a bus is not shown in the block diagram, communication between components, elements, or units may be performed through a bus. The functional aspects of the above example embodiments may be implemented by an algorithm running on one or more processors. In addition, the components, elements, or units represented by the boxes or processing steps may employ any number of related technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0085] Although some example embodiments have been shown and described, those skilled in the art will recognize that changes may be made in the example embodiments without departing from the principles and spirit of the disclosure, the scope of which is defined in the claims and their equivalents.

Claims

1. An image sensor, comprising: Active pixel array; At least one dummy reset array; Dummy read array; And Image processor, wherein the image processor is configured to: During a period when the pixels of the active pixel array do not perform a reset operation, sequentially reset the corresponding rows of the pixels included in the at least one dummy reset array, and During a period when the pixels of the active pixel array do not perform a read operation, sequentially read the corresponding rows of the pixels included in the dummy read array.

2. The image sensor according to claim 1, wherein, During a period when the pixels of the active pixel array perform both a reset operation and a read operation, the corresponding rows of the pixels of the at least one dummy reset array and the corresponding rows of the pixels of the dummy read array are not activated.

3. The image sensor according to claim 1, wherein, The active pixel array includes at least two pixels corresponding to different rows, and wherein the coupling coefficients caused by the activated at least two pixels are different from each other.

4. The image sensor according to claim 3, wherein the number of the at least one dummy reset array corresponds to a multiple of a minimum unit of rows having the same coupling coefficient, and the at least two pixels share a floating diffusion (FD) node or are connected to different column output lines.

5. The image sensor according to claim 1, wherein, The active pixel array is located in the upper region of the entire region of the pixel array, and wherein the dummy read array and the at least one dummy reset array are arranged adjacent to the active pixel array and are in a lower position compared to the active pixel array.

6. The image sensor according to claim 1, wherein the at least one dummy reset array is arranged in an upper region of the entire region of the pixel array, wherein, The dummy read array is arranged in the lower region of the entire region of the pixel array, and wherein the active pixel array is arranged between the at least one dummy reset array and the dummy read array.

7. The image sensor according to claim 1, wherein the number of shared pixels included in the dummy read array is different from the number of shared pixels included in the at least one dummy reset array.

8. The image sensor according to claim 1, wherein the image processor is further configured to set an integration time to increase for a first frame processed after a time point when it is determined that the illumination intensity is less than a certain value; and in response to simultaneously performing a reset operation for the first frame and a second frame adjacent to the first frame, based on the increased integration time, control the operation of the at least one dummy reset array to be bypassed for the second frame.

9. The image sensor according to claim 1, wherein, When the active pixel array simultaneously resets multiple rows, the number of the multiple rows simultaneously reset corresponds to the number of the at least one dummy reset array that performs a reset operation when the active pixel array is in a period when the pixels of the active pixel array do not perform a reset operation.

10. An image sensor, comprising: Active pixel array, including a plurality of active rows, each active row including a plurality of pixels; Dummy pixel array, including a plurality of dummy rows, each dummy row having a plurality of pixels; Row driver, configured to drive the active pixel array and the dummy pixel array; And Timing generator, configured to generate a control signal for controlling the rolling shutter operation of the row driver, wherein each pixel of the plurality of pixels in the active pixel array or the dummy pixel array includes at least two photosensitive devices, at least two transfer transistors, and a floating diffusion node connected to the at least two transfer transistors, wherein the rolling shutter operation includes a first period of sequentially resetting a first part of the plurality of active rows and sequentially reading a first part of the plurality of dummy rows, wherein the rolling shutter operation includes a second period of sequentially resetting a second part and a third part of the plurality of active rows and sequentially reading a first part of the plurality of active rows, and wherein the rolling shutter operation includes a third period of sequentially reading a third part of the plurality of active rows and sequentially resetting a second part of the plurality of dummy rows.

11. The image sensor according to claim 10, wherein, Each frame includes a first period, a second period, and a third period in chronological order.

12. The image sensor according to claim 10, wherein, The first part and the second part of the plurality of dummy rows are different rows.

13. The image sensor according to claim 10, wherein, The first part of the plurality of dummy rows is arranged in the upper region of the active pixel array, and wherein the second part of the plurality of dummy rows is arranged in the lower region of the active pixel array.

14. The image sensor according to claim 10, wherein, The at least two photosensitive devices include a first photosensitive device and a second photosensitive device, Among them, the at least two transfer transistors include a first transfer transistor and a second transfer transistor, and Among them, the reset operation or read operation of the plurality of dummy rows includes sequentially activating the first transfer transistor and the second transfer transistor.

15. The image sensor according to claim 14, wherein, The number of the plurality of dummy rows is 2n, where n is a positive integer.

16. The image sensor according to claim 10, wherein, The at least two photosensitive devices include a first photosensitive device, a second photosensitive device, a third photosensitive device, and a fourth photosensitive device, Among them, the at least two transfer transistors include a first transfer transistor, a second transfer transistor, a third transfer transistor, and a fourth transfer transistor, and Among them, the reset operation or read operation of the plurality of dummy rows includes sequentially activating the first transfer transistor, the second transfer transistor, the third transfer transistor, and the fourth transfer transistor.

17. The image sensor according to claim 16, wherein, The number of the plurality of dummy rows is 4n, where n is a positive integer.

18. The image sensor according to claim 16, wherein, The first photosensitive device, the second photosensitive device, the third photosensitive device, and the fourth photosensitive device correspond to the same color, and Among them, the first photosensitive device, the second photosensitive device, the third photosensitive device, and the fourth photosensitive device form a four-Bayer pattern.

Images