High-resolution attenuator or phase shifter with weighted bits

Abstract

A high-resolution digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architecture is provided. Embodiments use a dithering method to weight bit positions to provide a finer resolution than the lowest set single stage. Bit position weights for a stage are determined to enable selection of a combination of n bit positions that provides a desired total attenuation or phase shift range while allowing utilization of the large number of available states (2n) to generate fractional intermediate step sizes of attenuation or phase shift. The fractional intermediate step sizes have a finer resolution than the lowest set stage. Bit position weights can be determined using a weighting function that includes weights determined according to a linear series, a geometric series, a harmonic series, or alternating variations of these series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the following patent application, which is assigned to the assignee of the present invention, and the contents of which are incorporated herein by reference in their entirety: U.S. patent application serial number 16 / 013,844, filed on June 20, 2018, entitled “High Resolution Attenuator or Phase Shifter with Weighted Bits.” Background Art (1) Technical field

[0004] The present invention relates generally to electronic circuits, and more particularly, the present invention relates to electronic attenuator and / or phase shifting circuits. (2) Background technology

[0006] Digital Step Attenuator

[0007] A digital step attenuator (DSA) is an electronic device that reduces the power of a signal in discrete steps without significantly distorting its waveform. DSAs are often used with radio frequency (RF) systems such as transceivers for broadcast radios, cellular phones, and RF-based digital networks (e.g., Bluetooth, Wi-Fi).

[0008] Typical DSA comprises the switchable two-state attenuator stage of series connection.For example, Fig. 1 is the schematic diagram of the binary weighted DSA100 of prior art.Show four attenuator stages 102a to attenuator stages 102d that are connected in series.Under the control of the selector 104 that the control word provided is decoded into each control line 106, each attenuator stage 102a to attenuator stage 102d can be switched to effective " attenuation " state or " bypass " state (also referred to as " reference state ").Can think that each attenuator stage 102a to attenuator stage 102d has the " position (bit) position " that is associated with a separate control line 106.In this example, the 4-bit control word that is applied to selector 104 can be set with minimum step size 1dB from not adding attenuation (that is, all stages in the bypass state) to 16 kinds of attenuation combinations of 15dB attenuation (that is, all stages in the attenuation state).

[0009] Each attenuator stage 102a to attenuator stage 102d can be implemented using various circuits including bridged-T attenuators, T-type attenuators, pi-type attenuators, and L-pad attenuators. For example, FIG2A is a schematic diagram of a prior art bridged-T attenuator 200. When the bypass switch SwB is set to conduct the signal and the shunt switch SwSh is set to block the signal, the signal applied to the input (In) port is conducted to the output (Out) port, and the bridged-T attenuator 200 is in a reference state. When the bypass switch SwB is set to block the signal and the shunt switch SwSh is set to conduct the signal, the signal applied to the input port is attenuated in a known manner at the output port due to the interaction of the series Rs and shunt Rsh resistors with each other and with the impedance Z0, and the bridged-T attenuator 200 is in an attenuated state. The degree of attenuation is determined by the values of the Rs and Rsh resistors.

[0010] As another example of an attenuator stage, FIG2B is a schematic diagram of a prior art pi-type attenuator 210. As shown in FIG2A , when the bypass switch SwB is set to conduct the signal and the paired shunt switch SwSh is set to block the signal, the signal applied to the input port is conducted to the output port, and the pi-type attenuator 210 is in a reference state. When the bypass switch SwB is set to block the signal and the shunt switch SwSh is set to conduct the signal, the signal applied to the input port is attenuated in a known manner at the output port due to the interaction of the series resistor Rs and the shunt resistor Rsh, and the pi-type attenuator 210 is in an attenuated state. Again, the degree of attenuation is determined by the values of the resistors Rs and Rsh.

[0011] The DSA may also include a transmission line having multiple shunt attenuator stages. For example, FIG2C is a schematic diagram of a prior art shuntable transmission line digital step attenuator 220. A transmission line 222 (e.g., a microstrip, coplanar waveguide, or equivalent structure or circuit) is coupled to one or more shunt attenuator stages 224, each of which includes at least a shunt resistor Rsh and a shunt switch SwSh. Although the shunt attenuator stages 224 are not actually connected in series with each other in terms of signal conduction, each shunt attenuator stage 224 is connected to a limited portion of the transmission line 222, and the combined structure is then connected in series with other similar structures to form the entire transmission line 222, thereby achieving attenuation behavior similar to the series configuration of FIG1. By switching one or more shunt switches SwSh to an on state, a signal applied at the input port is attenuated at the output port, thereby shunting a portion of the signal energy to ground and thereby attenuating the applied signal. One constraint on the transmission line attenuator 220 is that the attenuation per stage is typically limited to approximately 1 dB or 2 dB.

[0012] As another example, a DSA can be fabricated in a known manner using a hybrid coupler and one or more resistive reflective termination circuits coupled to the direct and coupled ports of the hybrid coupler. An example of such a DSA is described in U.S. patent application Ser. No. 15 / 212,046, filed on July 15, 2016, entitled “Hybrid Coupler with Phase and Attenuation Control” (which also describes a hybrid coupler-based digital phase shifter), which is assigned to the assignee of the present invention and is hereby incorporated by reference herein.

[0013] It should be understood that the specific circuitry of the attenuator stages shown in Figures 2A to 2C can vary for specific applications. In addition, the attenuator stages of a DSA do not have to be of the same type. For example, some attenuator stages can be pi-type attenuators, while other attenuator stages can be bridged-T attenuators. An example of such a DSA configuration is described in U.S. patent application serial number 14 / 996,078, entitled "Digital Step Attenuator," filed on January 14, 2016, which is assigned to the assignee of the present invention and is hereby incorporated by reference. In addition, some or all stages of a DSA can provide more than one attenuation level, in which case a corresponding number of bit positions will be assigned to such stages. An example of a multi-state attenuator stage is described in U.S. Patent No. 9,531,359, entitled "Improved Multi-State Attenuator," published on December 27, 2016, which is assigned to the assignee of the present invention and is hereby incorporated by reference.

[0014] Digital Step Phase Shifter

[0015] Electronic phase shifter circuits are used to change the transmission phase angle of a signal and are commonly used to shift the phase of RF signals. RF phase shifter circuits can be used in applications such as in-phase discriminators, beamforming networks, power dividers, linearization of power amplifiers, and phased array antennas.

[0016] A digital phase shifter (DPS) circuit is a digitally controlled collection of multiple phase shifter stages connected in series that provide a discrete set of phase states similar to those selected by a control word, either directly or after decoding, in the DSA 100. For example, FIG3 is a schematic diagram of a prior art binary-weighted DPS 300. Four phase shifter stages 302a through 302d connected in series are shown. Each phase shifter stage 302a through 302d can be switched to an active "phase shifted" state or a "bypassed" state (also referred to as a "reference state") under the control of a selector 304 that decodes a provided control word into a respective control line 306. Thus, each phase shifter stage 302a through 302d can be considered to have a "bit position" associated with a separate control line 306. In this example, a 4-bit control word applied to selector 304 can set 16 phase shift combinations from no added phase shift (ie, all stages in the bypass state) to 15° phase shift (ie, all stages in the phase shift state) with a minimum step size of 1°.

[0017] Phase shifters 302a through 302d can be implemented using various circuits. For example, FIG4A is a schematic diagram of a prior art inductor-based phase shifter 400. When switches Sw1 and Sw2 are connected to the bypass path, a signal applied to the input port is conducted to the output port, and phase shifter 400 is in a reference state. When switches Sw1 and Sw2 are connected to inductor L, a signal applied to the input port is conducted to the output port through inductor L, and phase shifter 400 is in a phase-shifted state. The degree of phase shifting is determined by the value of inductor L.

[0018] As another example, FIG4B is a schematic diagram of a prior art capacitor-based phase shifter 410. When switches Sw1 and Sw2 are connected to the bypass path, a signal applied to the input port is conducted to the output port, and phase shifter 410 is in a reference state. When switches Sw1 and Sw2 are connected to capacitor C, a signal applied to the input port is conducted to the output port through the capacitor, and phase shifter 400 is in a phase-shifted state. The degree of phase shift is determined by the value of capacitor C.

[0019] A DPS can also include a transmission line with multiple shunt phase shifting elements. For example, FIG4C is a schematic diagram of a prior art shunt transmission line phase shifter 420. A transmission line 422 (e.g., a microstrip, coplanar waveguide, or equivalent structure or circuit) is coupled to one or more shunt phase shifter stages 424. In this example, each shunt phase shifter stage 424 includes at least a shunt capacitor Csh and a shunt switch SwSh. Although the shunt phase shifter stages 424 are not actually connected in series with each other in terms of signal conduction, each shunt phase shifter stage 424 is connected to a limited portion of the transmission line 422, and the combined structure is then connected in series with other similar structures to form the entire transmission line 422, thereby achieving phase shifter behavior similar to the series configuration of FIG3. By switching one or more shunt switches SwSh to an on state, a signal applied to an input port is phase shifted at an output port, thereby causing the applied signal to be phase shifted.

[0020] As another example, a DPS can be fabricated in a known manner using a hybrid coupler and a plurality of capacitive or inductive reflection termination circuits coupled to the direct and coupled ports of the hybrid coupler. An example of such a DPS is described in U.S. patent application Ser. No. 14 / 988 / 463, filed on Jan. 5, 2016, entitled “Reflection-Based RF Phase Shifter” (a hybrid coupler-based DSA is similar, except that the capacitive reflection termination circuits shown are replaced with resistive reflection termination circuits), which is assigned to the assignee of the present invention and is hereby incorporated by reference herein.

[0021] As will be appreciated, the specific circuitry of the phase shifter stages shown in FIG. 4A through FIG. 4C may vary for specific applications. Furthermore, the phase shifter stages of a DPS need not be of a uniform type. Furthermore, some or all stages of a DPS may provide more than one level of phase shifting, in which case a corresponding number of bit positions would be assigned to such stages. Examples of multi-state phase shifter stages are described in U.S. Patent Application No. 15 / 017,433, filed February 5, 2016, entitled “Low Loss Multi-State Phase Shifter,” which is assigned to the assignee of the present invention and is hereby incorporated by reference herein.

[0022] Level bit position weight

[0023] In DSAs and DPSs such as those described above, each attenuator stage or phase shifter stage is typically described as being assigned a bit position corresponding to one of the control lines 106, 306 from the associated selector 104, 304. For example, in FIG1 , attenuator stage 102 d can be considered to be associated with the most significant bit (MSB) of a 4-bit binary-weighted control word, while attenuator stage 102 a can be considered to be associated with the least significant bit (LSB) of the 4-bit binary-weighted control word. A binary-weighted control word of "1001" sets attenuator stages 102 d and 102 a to an active attenuation state (a total of 9 dB in the example shown), while setting attenuator stages 102 b and 102 c to a bypass (reference) state.

[0024] While the above examples of DSA and DPS use binary-weighted control words, other commonly used bit position weighting schemes are thermometer weighting (i.e., with each unit change in state, the attenuation or phase shift value changes incrementally or incrementally) and hybrid thermometer / binary weighting. Further description of such conventional weighting can be found in U.S. Patent No. 9,397,635, entitled “Segmented Attenuator with Glitch Reduction,” issued on July 19, 2016, which is assigned to the assignee of the present invention and is hereby incorporated by reference herein.

[0025] The problem with such conventional weighting is that the resolution is limited to the LSB value (i.e., the minimum attenuator stage value or the minimum phase shifter stage value). Thus, for example, the binary-weighted DSA 100 of FIG. 1 has a resolution of 1 dB; similarly, the binary-weighted DPS 300 of FIG. 3 has a resolution of 1°. As another example, in a transmission line DSA 220 such as that shown in FIG. 2C , it is typically desirable to have attenuator stages 224 repeated along the transmission line 222 at quarter-wavelength (λ / 4) intervals, with the attenuator stages 224 having similar fixed-value shunt resistors Rsh. To avoid transmission line loading, thermometer coding must be used for similar fixed-value shunt resistors. Therefore, to achieve a reasonable maximum attenuation range, the number of attenuator stages and therefore control lines required, as well as the associated IC area, will be very large. For example, a transmission line DSA 220 for an application requiring an attenuation range of 21 dB and a resolution of 1 dB would require 21 shunt attenuator stages 224 spaced at λ / 4 intervals and 21 control lines, thereby increasing cost. Similar issues apply to DPS, but especially for RF applications, it is often preferable to have higher resolution to improve accuracy.

[0026] Therefore, there is a need for a DSA and DPS circuit architecture that provides high resolution at relatively low cost. The present invention satisfies this need and provides additional benefits. Summary of the Invention

[0027] Embodiments of the present invention use a dithering method to weight bits to provide higher resolution in digital step attenuators (DSAs) and digital phase shifters (DPSs), particularly in transmission line DSAs and transmission line DPSs. Several dithering methods are disclosed, but each provides higher resolution than prior art methods, and in many cases, significantly higher resolution without additional cost. Thus, embodiments of the present invention provide a means of separating range from resolution to allow greater design flexibility. Such flexibility is exploited to implement transmission line architectures and enables implementations with less than about 2 dB of attenuation per bit position.

[0028] More specifically, the bit position weights of the stages in a DSA or DPS are determined to enable selection of various combinations of N bit positions that provide a desired total attenuation or phase shift range, while also allowing utilization of the large number of states available (2 N ) to produce fractional intermediate steps of attenuation or phase shift that are finer in resolution than thermometer, binary, or mixed thermometer / binary bit position weighting available in the prior art. Indeed, for the same number of bit positions, embodiments of the present invention can achieve a higher range to resolution ratio for a reduced MSB to LSB ratio and exhibit a better Figure of Merit (FOM) metric than conventional designs. Such bit position weights can be determined using a variety of methods, but a method that follows a mathematical expression is convenient.

[0029] Embodiments include DSAs and DPSs having stage weights assigned to bit positions, the stage weights being determined by applying a bit position weighting function that produces fractional intermediate step sizes of signal change (i.e., attenuation or phase shift). The fractional intermediate step sizes of signal change have a finer resolution than the signal change value of the lowest-valued stage. The bit position weighting function can be one of a linear series function, an alternating linear series function, a geometric series function, an alternating geometric series function, a harmonic series function, or an alternating harmonic series function. Furthermore, the signal change value of at least one stage can be set to a fixed value that is not determined by the bit position weighting function.

[0030] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic diagram of a binary-weighted DSA according to the prior art.

[0032] FIG. 2A is a schematic diagram of a prior art bridge-T attenuator.

[0033] FIG. 2B is a schematic diagram of a prior art pi-type attenuator.

[0034] FIG. 2C is a schematic diagram of a conventional splittable transmission line digital step attenuator.

[0035] FIG3 is a schematic diagram of a binary weighted DPS in the prior art.

[0036] FIG. 4A is a schematic diagram of a prior art inductor-based phase shifter.

[0037] FIG. 4B is a schematic diagram of a prior art capacitor-based phase shifter.

[0038] FIG. 4C is a schematic diagram of a prior art splittable transmission line phase shifter.

[0039] 5A is a graph of decay weights by bit position for a 9-bit DSA using uniform bit position weighting.

[0040] 5B is a graph illustrating possible attenuation levels that may be set for the bit position weights shown in FIG. 5A according to various combinations of bit position states.

[0041] Figure 6A is a graph of the attenuation weights by bit position for 9-bit DSA using linear progression bit position weighting.

[0042] Figure 6B It shows that it can be targeted Figure 6A A graph showing possible attenuation levels for various combinations of bit position states according to which the bit position weights are set.

[0043] Figure 6C is a graph of the attenuation weights per bit position for different values of A0 and K for 9-bit DSA using linear progression bit position weighting.

[0044] Figure 6D It shows that it can be targeted Figure 6C A graph showing possible attenuation levels for various combinations of bit position states according to which the bit position weights are set.

[0045] Figure 7A is a graph of the attenuation weights per bit position for different values of A0 and K for 9-bit DSA using alternating linear progression bit position weighting.

[0046] Figure 7B It shows that it can be targeted Figure 7AA graph showing possible attenuation levels for various combinations of bit position states according to which the bit position weights are set.

[0047] Figure 8A is a graph of the attenuation weights per bit position for different values of A0 and K for 9-bit DSA using geometric bit position weighting.

[0048] Figure 8B It shows that it can be targeted Figure 8A A graph showing possible attenuation levels for various combinations of bit position states according to which the bit position weights are set.

[0049] Figure 9A is a graph of the attenuation weights per bit position for different values of A0 and K for 9-bit DSA using alternating geometric progression bit position weighting.

[0050] Figure 9B It shows that it can be targeted Figure 9A A graph showing possible attenuation levels for various combinations of bit position states according to which the bit position weights are set.

[0051] Figure 10A is a graph of the attenuation weights per bit position for different values of A0 and K for 9-bit DSA using harmonic series bit position weighting.

[0052] Figure 10B It shows that it can be targeted Figure 10A A graph showing possible attenuation levels for various combinations of bit position states according to which the bit position weights are set.

[0053] Figure 11A is a graph of the attenuation weights per bit position for different values of A0 and K for 9-bit DSA using alternating harmonic series bit position weighting.

[0054] Figure 11B It shows that it can be targeted Figure 11A A graph showing possible attenuation levels for various combinations of bit position states according to which the bit position weights are set.

[0055] Figure 12A is a graph of attenuation weights by bit position for a 9-bit DSA using alternating harmonic series bit position weightings for bit positions 1 through 8 for selected values of A0 and K, where bit position 9 is assigned a fixed value (0.25 dB in this example).

[0056] Figure 12B It shows that it can be targeted Figure 12A A graph showing possible attenuation levels for various combinations of bit position states according to which the bit position weights are set.

[0057] Figure 13is a graph of the decay weights by bit position for a 9-bit DSA using harmonic series bit position weighting and alternating harmonic series bit position weighting.

[0058] Figure 14 is a process flow diagram of a first method of setting bit position weights for multiple signal change stages.

[0059] Throughout the drawings, like reference numbers and designations indicate like elements. DETAILED DESCRIPTION

[0060] The present invention encompasses DSA and DPS circuit architectures that provide high resolution at a relatively low cost, along with additional benefits. Generally, embodiments of the present invention use dithering to weight bits to provide higher resolution in digital step attenuators (DSAs) and digital phase shifters (DPSs), particularly in transmission line DSAs and transmission line DPSs. An important aspect of such embodiments is that they achieve finer resolution than the lowest-valued individual attenuation or phase shifter stages.

[0061] Uniform position weighting

[0062] To better understand various aspects of the invention, it is useful to consider conventional uniform (thermometer) weighting.For purposes of illustration, a DSA example will be used, but the concepts apply to both DSA and DPS.

[0063] FIG5A is a graph 500 of the attenuation weights by bit position for a 9-bit DSA using uniform bit position weighting. Uniform bit position weighting is commonly used with transmission line DSAs. In the example shown, each of the nine bit positions has an attenuation value of 1 dB when switched to the attenuation state (i.e., each bit position can attenuate the input signal by -1 dB). Mathematically, the nth bit value = A0, where A0 is a constant (-1 dB in this example), and n = bit position ≥ 1.

[0064] In normal use, higher attenuation levels will be achieved by incrementally activating additional attenuator stages until a maximum attenuation level of -9 dB is reached. However, because the attenuator stages can be individually switched between a non-attenuated reference state and an active attenuation state, there are in effect 512 (2 9 ) possible combinations, but the large number of states only provides 9 possible attenuation levels. For example, activating only bit positions 1 and 9 achieves the same attenuation level as activating only bit positions 2 and 8.

[0065] FIG5B is a graph illustrating possible attenuation levels that can be set according to various combinations of bit position states for the bit position weights shown in FIG5 A. As shown in graph curve 522, because the minimum resolution available between different attenuation levels is 1 dB, the attenuation levels from 0 dB to -9 dB are coarse step functions.

[0066] Binary position weighting will also exhibit a minimum resolution of 1 dB (but the range of attenuation will be greater if 9 steps are used; however, to cover 9 attenuation levels, only 4 binary weighting steps are needed). To illustrate the limitations of binary position weighting, it is helpful to consider the mathematical definitions of the least significant bit (LSB) and most significant bit (MSB) in the context of an attenuator:

[0067] LSB=Total_Attenuation_Range / (2 N -1), where N is the number of bits. [Formula 1]

[0068] Therefore, the LSB can be made considerably smaller by increasing the number of bits N. However,

[0069] MSB=LSB*2 (N-1) =Total_Attenuation_Range*2 (N-1) / (2 N -1). [Formula 2]

[0070] For binary position weighting, if we assume 2 N is much greater than 1, then the denominator in formula 2 is simplified to 2 N and the MSB is close to (Total_Attenuation_Range / 2) (as mentioned above, it should also be noted that the value of the MSB quickly reaches the maximum attenuation per bit imposed by practical constraints on the transmission line DSA architecture, typically a maximum of about 2dB per bit).

[0071] Table 1 shows the MSB problem associated with binary bit position weighting for several specific implementations of varying the number of attenuator bit positions. As the number of bits N increases, the MSB approaches an approximately constant value around 4.5 dB (although this value will be further constrained by the practical constraints on the transmission line DSA architecture mentioned above).

[0072] Range (dB) N-bit LSB(dB) MSB(dB) 9 9 0.018 4.51 9 8 0.035 4.52 9 7 0.071 4.54 9 6 0.140 4.57 9 5 0.290 4.65 9 4 0.600 4.80 9 3 1.300 5.14

[0073] Table 1

[0074] Dithering of bit position weights

[0075] Embodiments of the present invention use dithering methods to weight bits to provide higher resolution in DSA and DPS, particularly in transmission line DSA and transmission line DPS. Several dithering methods are disclosed below, but each provides higher resolution than prior art methods without additional cost, and in many cases significantly higher resolution. The dithering methods can be used in conjunction with DSA and DPS circuits of the type shown in Figures 1, 2C, 3, and / or 4C, but with the novel bit weighting described below.

[0076] More particularly, the bit position weights of the stages in a DSA or DPS are determined to enable selection of various combinations of N bit positions that provide a desired total attenuation or phase shift range, while also allowing utilization of the large number of states (2 N ) to produce fractional intermediate steps of attenuation or phase shift that are much finer in resolution than can be achieved using prior art thermometers, binary, or hybrid thermometer / binary bit position weighting. Indeed, for the same number of bit positions, embodiments of the present invention can achieve a higher range to resolution ratio for a reduced MSB to LSB ratio and exhibit a better Figure of Merit (FOM) metric than conventional designs. Several methods can be used to determine such bit position weights using a bit position weighting function that produces fractional intermediate steps of signal change (i.e., attenuation or phase shift), but it is convenient to use methods that obey mathematical expressions, several of which are described below.

[0077] Linear Progression Bit Position Weighting: In a first embodiment, the weights assigned to bit positions in DSA or DPS are determined by applying a linear progression of bit position weighting. Mathematically, nth bit value = A0 + ((n-1) x K), where A0 is a constant, n = bit position ≥ 1, and K is a non-zero scaling constant. An alternative form that provides slightly different results is: nth bit value = A0 - ((n-1) x K).

[0078] For illustration purposes, the DSA example is used again (but the concepts apply equally to DPS). Figure 6Ais a graph 600 of the attenuation weights by bit position for a 9-bit DSA using linear progression bit position weighting. As shown in graph 600, each bit position (representing an attenuator step) is set to an attenuation level in the range from about 0.6 dB to about 1.5 dB. In the example shown, the average attenuation level for each bit position is about 1 dB, but the difference in attenuation levels between adjacent bit positions is about 0.11 dB. Such bit position weighting will be particularly useful for transmission line DSAs (and transmission line DPSs) because the variance from the average of all bit positions is not particularly large and the maximum bit attenuation level remains within the 1 dB to 2 dB range, which is typically suitable for shunt values on transmission lines.

[0079] In the example shown, combinations of bit positions can be selectively activated to provide total attenuation ranging from 0 dB to approximately -9 dB. However, by utilizing the large number of available states (512 in this example), various combinations of bit positions can produce intermediate steps of attenuation resolution that are much finer than the prior art examples of Figures 5A and 5B. For example, Figure 6B It shows that it can be targeted Figure 6A Graph 620 of possible attenuation levels for various combinations of bit position state settings is shown. Graph curve 522 shows the coarse step size function from FIG. 5B resulting from the 1 dB minimum resolution available between different attenuation levels. In contrast, graph curve 622 shows the coarse step size function from FIG. Figure 6A A much finer step size function to achieve approximately the same overall attenuation range is shown in FIG, weighted by the bit positions shown in FIG, resulting from the finer minimum resolution available between different attenuation levels (approximately 0.11 dB).

[0080] As a specific example, if bit position 8 has a weight of 1.5 dB and bit position 1 has a weight of 0.6 dB, then activating both bits provides an attenuation of 2.1 dB - a value not achievable with the uniform bit position weighting shown in FIG. 5A .

[0081] It should be understood that A0 and K in the above mathematical expressions may vary for specific applications. For example, Figure 6C is a graph 640 of the attenuation weights by bit position for different values of A0 and K for 9-bit DSA using linear progression bit position weighting, and Figure 6D It shows that it can be targeted Figure 6C Graph 660 of possible attenuation levels for bit position weightings set according to various combinations of bit position states is shown. For comparison, graph curve 642a represents the uniform bit position weighting of FIG. 5A, and graph curve 642b represents the corresponding possible attenuation levels.

[0082] Graph curve 644a represents a bit position weighting where A0 is approximately 1.1 dB and K is approximately 0.1; graph curve 644b represents the corresponding possible attenuation level. Graph curve 646a represents a bit position weighting where A0 is approximately 1.2 dB and K is approximately 0.18; graph curve 644b represents the corresponding possible attenuation level. Curve 648a represents a bit position weighting where A0 is approximately 1.3 dB and K is approximately 0.3; graph curve 644b represents the corresponding possible attenuation level. Note that, as an example, graph curves 644a and 644b indicate that the maximum attenuation per bit is maintained, the range is increased, and the resolution is significantly improved compared to graph curves 642a and 642b (taken from Figures 5A and 5B, respectively). As shown in FIG. Figure 6D As shown, larger K values produce a larger total attenuation range, but slightly lower resolution.

[0083] It will be appreciated that the actual assignment of the bit position weights to the physical DSA or DPS levels can be ordered in different ways without changing the result - only the mapping of states to physical levels will change. Thus, for example, the weights assigned to bit positions 1 and 2 can be reversed, and any other physical ordering of the bit position weight values can be assigned to the levels. Thus, it will be appreciated that 6A to 6D The non-uniformly weighted graph shown in is a convenient way to calculate bit position weights that can be assigned to a sequentially ordered set of DSA or DPS levels, without the limitations associated with requiring the calculated bit position weights to be strictly assigned to physically sequential levels.

[0084] Alternating Linear Progression Bit Position Weighting: In a second embodiment, the weights assigned to bit positions in DSA or DPS are determined by applying alternating linear progression bit position weighting. Mathematically, the nth bit value = A0 + (-1) n ×((n-1)×K), where A0 is a constant, n=bit position ≥ 1, and K is a non-zero proportionality constant. Using this expression, the first bit position will be equal to A0, and the second bit position will have a more positive value relative to A0. The alternative form provides a more negative value relative to A0 for the second bit position, and thus gives a slightly different result: nth bit value = A0 + (-1) (n-1) ×((n-1)×K).

[0085] Figure 7A is a graph 700 of the attenuation weights by bit position for different values of A0 and K for a 9-bit DSA using alternating linear progression bit position weighting, and Figure 7B It shows that it can be targeted Figure 7AGraph 720 shows possible attenuation levels for bit position weightings set according to various combinations of bit position states. For comparison, graph curve 642a represents the uniform bit position weighting of FIG. 5A, and graph curve 642b represents the corresponding possible attenuation levels.

[0086] Graph curve 702a shows that each bit position is set to an attenuation level within a range of up to about 0.4 dB above or below 1 dB based on a particular choice of A0 and K; graph curve 702b represents the corresponding possible attenuation levels. Graph curve 704a shows that each bit position is set to an attenuation level within a range of up to about 0.9 dB above or below 1 dB based on another particular choice of K (A0 is the same as graph curve 702a); graph curve 704b represents the corresponding possible attenuation levels. In both cases, the resolution of the bit position weighting according to the alternating linear progression is much finer than that of the conventional uniform weighting. As described above, the actual assignment of the bit position weights to the physical DSA or DPS levels can be ordered in different ways without changing the result—only the mapping of weights to levels will change.

[0087] Geometric bit position weighting: In a third embodiment, the weights assigned to bit positions in a DSA or DPS are determined by applying geometric bit position weighting. Mathematically, the nth bit value = A0 + K / 2 (n-1) , where A0 is a constant, n = bit position ≥ 1, and K is a non-zero proportionality constant. Using this expression, the first bit position will be positive relative to A0 (i.e., A0 + K), and the second bit position will have a more negative value relative to the first position (i.e., A0 + K / 2). An alternative form provides a first bit position that is negative relative to A0 (i.e., A0 - K), and a more positive value relative to the first position (i.e., A0 - K / 2) for the second bit position, and thus gives a slightly different result: nth bit value = A0 - K / 2 (n-1) .

[0088] Figure 8A is a graph 800 of the decay weights by bit position for different values of A0 and K for 9-bit DSA using geometric bit position weighting, and Figure 8B It shows that it can be targeted Figure 8A Graph 820 shows possible attenuation levels for bit position weightings set according to various combinations of bit position states. For comparison, graph curve 642a represents the uniform bit position weighting of FIG. 5A, and graph curve 642b represents the corresponding possible attenuation levels.

[0089] Graph curve 802a shows that based on a particular selection of A0 and K, each bit position is set to start at approximately 1.25 dB and decrease, thereby asymptotically approaching an attenuation level of approximately 1 dB; graph curve 802b represents the corresponding possible attenuation level. Graph curve 804a shows that based on another particular selection of A0 and K, each bit position is set to start at approximately 1.75 dB and decrease, thereby asymptotically approaching an attenuation level of approximately 1 dB; graph curve 804b represents the corresponding possible attenuation level. Graph curve 806a shows that based on yet another particular selection of A0 and K, each bit position is set to start at approximately 3 dB and decrease, thereby asymptotically approaching an attenuation level of approximately 1 dB; graph curve 862b represents the corresponding possible attenuation level.

[0090] In all cases, the resolution of bit position weighting according to the geometric level is finer, and in some cases much finer, than the resolution of conventional uniform weighting. As mentioned above, the actual assignment of bit position weights to physical DSA or DPS levels can be ordered differently without changing the result - only the mapping of weights to levels will change.

[0091] Alternating Geometric Progression Bit Position Weighting: In a fourth embodiment, the weights assigned to bit positions in a DSA or DPS are determined by applying alternating geometric progression bit position weighting. Mathematically, the nth bit value = A0 + (-1) (n-1) ×K / 2 (n -1) , where A0 is a constant, n = bit position ≥ 1, and K is a non-zero proportional constant. Using this expression, the first bit position will be positive relative to A0, and the second bit position will have a more negative value relative to the first position. An alternative form provides a first bit position that is negative relative to A0, and a more positive value for the second bit position relative to the first position, and thus gives a slightly different result: nth bit value = A0 + (-1) n ×K / 2 (n-1) .

[0092] Figure 9A is a graph 900 of the attenuation weights by bit position for different values of A0 and K for 9-bit DSA using alternating geometric progression bit position weighting, and Figure 9B It shows that it can be targeted Figure 9A Graph 920 shows possible attenuation levels for bit position weightings set according to various combinations of bit position states. For comparison, graph curve 642a represents the uniform bit position weighting of FIG. 5A, and graph curve 642b represents the corresponding possible attenuation levels.

[0093] Graph curve 902a shows that based on a particular selection of A0 and K, each bit position is set to start at approximately 1.25 dB and alternately decrease in value below and above 1 dB, thereby asymptotically approaching an attenuation level of approximately 1 dB; graph curve 902b shows the corresponding possible attenuation level. Graph curve 904a shows that based on another particular selection of A0 and K, each bit position is set to start at approximately 1.75 dB and alternately decrease in value below and above 1 dB, thereby asymptotically approaching an attenuation level of approximately 1 dB; graph curve 904b shows the corresponding possible attenuation level. Graph curve 906a shows that based on yet another particular selection of A0 and K, each bit position is set to start at approximately 2.75 dB and alternately decrease in value below and above 1 dB, thereby asymptotically approaching an attenuation level of approximately 1 dB; graph curve 902b shows the corresponding possible attenuation level.

[0094] In all cases, the resolution of bit position weighting according to alternating geometric levels is finer, and in some cases much finer, than the resolution of conventional uniform weighting. As mentioned above, the actual assignment of bit position weights to physical DSA or DPS levels can be ordered differently without changing the result - only the mapping of weights to levels will change.

[0095] Harmonic Series Bit Position Weighting: In a fifth embodiment, the weights assigned to bit positions in a DSA or DPS are determined by applying harmonic series bit position weighting. Mathematically, nth bit value = A0 + K / n, where A0 is a constant, n = bit position ≥ 1, and K is a non-zero proportionality constant. Using this expression, the first bit position will be positive relative to A0, and the second bit position will have a more negative value relative to the first position. An alternative form provides a first bit position that is negative relative to A0, and a more positive value for the second bit position relative to the first position, and thus gives a slightly different result: nth bit value = A0 - K / n.

[0096] Figure 10A is a graph 1000 of the attenuation weights by bit position for different values of A0 and K for 9-bit DSA using harmonic stage bit position weighting, and Figure 10B It shows that it can be targeted Figure 10A Graph 1020 shows possible attenuation levels for bit position weightings set according to various combinations of bit position states. For comparison, graph curve 642a represents the uniform bit position weighting of FIG. 5, and graph curve 642b represents the corresponding possible attenuation levels.

[0097] Graph curve 1002a shows an attenuation level that, based on a particular selection of A0 and K, starts at approximately 1.95 dB and decreases with an offset to a value close to 1 dB; graph curve 1002b represents the corresponding possible attenuation level. Graph curve 1004a shows an attenuation level that, based on another particular selection of A0 and K, starts at approximately 1.65 dB and decreases with an offset to a value close to 1 dB; graph curve 1004b represents the corresponding possible attenuation level. Graph curve 1006a shows an attenuation level that, based on another particular selection of A0 and K, starts at approximately 1 dB and increases with an offset to a value close to 1.65 dB; graph curve 1006b represents the corresponding possible attenuation level. Graph curve 1008a shows that each bit position is set to an attenuation level starting at about 0.7 dB and increasing with an offset to a value close to about 1.6 dB based on another specific choice of A0 and K; graph curve 1008b represents the corresponding possible attenuation levels. In all cases, the first bit position is positive relative to A0.

[0098] In all cases, the resolution of the bit position weights according to the harmonic level is finer, and in some cases much finer, than the resolution of conventional uniform weighting. As mentioned above, the actual assignment of the bit position weights to the physical DSA or DPS levels can be ordered differently without changing the result - only the mapping of weights to levels will change.

[0099] Alternating Harmonic Stage Bit Position Weighting: In the sixth embodiment, the weights assigned to bit positions in DSA or DPS are determined by applying alternating harmonic stage bit position weighting. Mathematically, the nth bit value = A0 + (-1) n × K / n, where A0 is a constant, n=bit position ≥ 1, and K is a non-zero proportionality constant. Using this expression, the first bit position will be negative relative to A0, and the second bit position will have a more positive value relative to the first position. An alternative form provides a first bit position that is positive relative to A0, and a more negative value relative to the first position for the second bit position, and thus gives a slightly different result: nth bit value = A0 + (-1) (n-1) ×K / n.

[0100] Figure 11A is a graph 1100 of the attenuation weights by bit position for different values of A0 and K for 9-bit DSA using alternating harmonic stage bit position weighting, and Figure 11B It shows that it can be targeted Figure 11AGraph 1120 shows possible attenuation levels for bit position weightings set according to various combinations of bit position states. For comparison, graph curve 642a represents the uniform bit position weighting of FIG. 5, and graph curve 642b represents the corresponding possible attenuation levels.

[0101] Graph curve 1102a illustrates the attenuation level for a particular selection of A0 and K, where each bit position is set to begin at approximately 1.75 dB and alternate between 1 dB below and above, with an offset approaching approximately 1 dB below and above. Graph curve 1102b represents the corresponding possible attenuation level. Similarly, graph curve 1104a illustrates the attenuation level for another particular selection of A0 and K, where each bit position is set to begin at approximately 1.5 dB and alternate between 1 dB below and above, with an offset approaching approximately 1 dB below and above. Graph curve 1104b represents the corresponding possible attenuation level. In both cases, the first bit position is positive relative to A0.

[0102] Graph curves 1102a and 1104a begin with weighting values above 1 dB. Conversely, graph curve 1106a illustrates an attenuation level where, based on a particular selection of A0 and K, each bit position is set to begin at approximately 0.25 dB and alternate between 1 dB above and below, with an offset approaching levels approximately 1 dB above and below; curve 1106b represents the corresponding possible attenuation level. Similarly, graph curve 1108a illustrates an attenuation level where, based on another particular selection of A0 and K, each bit position is set to begin at approximately 0.5 dB and alternate between 1 dB above and below, with an offset approaching levels approximately 1 dB above and below; graph curve 1108b represents the corresponding possible attenuation level. In both cases, the first bit position is negative relative to A0.

[0103] In all cases, the resolution of the bit position weights according to the alternating modulation and level numbers is finer, and in some cases much finer, than the resolution of the conventional uniform weights. As mentioned above, the actual assignment of the bit position weights to the physical DSA or DPS levels can be ordered differently without changing the result - only the mapping of weights to levels will change.

[0104] General mathematical progression with added fixed bits: In a seventh embodiment, the weights assigned to bit positions in a DSA or DPS are determined by applying a general mathematical progression of one of the types described above (e.g., alternating harmonic progression bit position weights), but constraining one or more bit positions to have relatively small fixed values (e.g., 0.1 dB and / or 0.25 dB) of "add-on" attenuation that is not determined by the general mathematical progression.

[0105] Thus, as just one example, the n bit positions may have a value consisting of an alternating harmonic progression (e.g., A0+(-1) n ×K / n or A0+(-1) (n-1) × K / n, where A0 = 1 dB), and the n+1 bit position may be set to 0.25 dB (as an example only), while optionally the n+2 bit position may be set to 0.1 dB (as an example only). The choice of "additional" bit weights may depend on the application; for example, the resolution density may be distributed in certain areas by one or more fixed "additional" bit weights. More generally, a DSA or DPS may include a portion of bit positions in which weights are determined by applying a general mathematical series of one of the types described above, and a portion of bit positions with conventional bit position weights (e.g., thermometer weighting and / or binary weighting).

[0106] Figure 12A is a graph 1200 of attenuation weights by bit position for a 9-bit DSA using alternating harmonic series bit position weightings for bit positions 1 through 8 for selected values of A0 and K, with bit position 9 being assigned a fixed value (0.25 dB in this example). Figure 12B It shows that it can be targeted Figure 12A Graph 1220 shows possible attenuation levels for bit position weightings set according to various combinations of bit position states. For comparison, graph curve 642a represents the uniform bit position weighting of FIG. 5, and graph curve 642b represents the corresponding possible attenuation levels.

[0107] Graph curve 1202a shows the attenuation level based on a particular choice of A0 and K, with each bit position set to start at approximately 0.5 dB and alternately dropping values above and below 1 dB, approaching levels approximately 1 dB above and below with offsets; curve 1202b represents the corresponding possible attenuation level. In the illustrated embodiment, graph curve 1202a is shown extrapolated to the ninth bit position. However, since bit position 9 is instead assigned a fixed value, the actual "tail" of graph curve 1202a will look like graph curve 1204a, essentially a blend of graph curve 1202a with an extended "tail" down to approximately 0.25 dB. Graph curve 1204b represents the corresponding possible attenuation level for graph curve 1204a. Generally, setting one or more bit positions to a small fixed value shifts graph curve 1202b upward; by choosing appropriate values for A0, K, and the fixed value, a downward shift is also possible.

[0108] It should be clear that one or more additional fixed-value bit positions can be used with the other level-based bit position weightings described above. In all cases, the resolution of such hybrid bit position weightings is finer, and in some cases much finer, than that of conventional uniform weightings. As described above, the actual assignment of bit position weights to physical DSA or DPS levels can be ordered differently without changing the results—only the mapping of weights to levels will change.

[0109] Bit position weighted quality factor

[0110] The selection of a particular bit position weighting from those disclosed above in connection with embodiments of the invention will depend on the particular application. However, it may be useful to assign a figure of merit (FOM) to the candidate bit position weightings to assist in the selection. For example, one FOM may be defined as the total range (the total range of attenuation or phase shift, as the case may be) divided by the resolution (i.e., maximum step size) of the particular bit position weighting: FOM = range / resolution. Applying this definition to the attenuation value pair state graph curves in the above example (e.g., selecting the best FOM with respect to several graph curves) gives the values listed in Table 2 below. In general, for a fixed range, a smaller maximum step size (i.e., lower resolution) will produce a higher FOM, and so a higher FOM is better.

[0111] picture type FOM 5B Uniform [Regular] ～9 6B Linear series ～85 7B Alternating Linear Series ～74 8B Geometric series ～97 9B Alternating geometric series ～184 10B Harmonic series ～72 11B Alternating harmonic series ～208 12B Alternating harmonic series + minimum fixed position ～107

[0112] Table 2

[0113] As indicated in Table 2, the bit position weights resulting from the alternating harmonic series provide an unusually high FOM (~208), especially compared to the FOM of the conventional uniformly weighted design (~9), because the maximum step size of the uniform bit position weighting is very coarse compared to the very fine step sizes achievable using the alternating harmonic series implementation of the present invention.

[0114] In looking at embodiments of the present invention in a different way, in its simplest form, the "range" of a DSA or DPS can be thought of as being controlled by the average bit weight A0 multiplied by the number of bits N (essentially, the thermometer-coded bit strings each have an A0 value). The "resolution" is then mathematically superimposed on this set of bits, for example by applying the mathematical series described above. The above FOM definition only considers range and resolution (i.e., maximum step size). An alternative FOM definition that can be used is: (range / resolution)*(LSB / MSB). This metric can be expressed equivalently as:

[0115] (Range*LSB) / (Resolution*MSB) [Equation 3]

[0116] This second FOM2 metric will clearly show the benefits of the architecture of the present invention compared to even a purely binary weighted architecture (the best resolution possible for conventional implementations). For example, Table 3 compares a conventional binary weighted implementation with two different implementations of the present invention based on alternating harmonic series bit position weighting using the formula listed in Table 4 and values for A0 and K. All cases in Table 3 use 9 bits (i.e., N=9) and target a total attenuation range of 9 dB; higher values of the FOM 2 metric are better.

[0117]

[0118] Table 3

[0119] Weighted A0 K Mode Alternating harmonic series 1 0.959 0.5 <![CDATA[A0+(-1) (n-1) ×K / n]]> Alternating harmonic series 2 1.041 0.5 <![CDATA[A0+(-1) n ×K / n]]>

[0120] Table 4

[0121] The alternating nature of the bit shifting in the alternating harmonic series implementation results in an improved FOM2 result by significantly reducing the MSB to LSB ratio. The primary reason for this improvement is that the relative attenuation step size from bit to bit is always centered around the A0 value. The reduction in the MSB to LSB ratio benefits from improved manufacturing yield, where the range of the individual circuit elements (whether resistance or impedance) used to produce each bit of attenuation or phase shift is more tightly constrained, and thus uniformity between elements is more easily maintained.

[0122] The examples in Tables 3 and 4 help illustrate some of the advantages of using alternating series (particularly alternating harmonic series) over non-alternating series. In general, the value of A0 in the above mathematical expressions for embodiments of the present invention can be thought of as an offset, while the second term in each mathematical expression can be thought of as a weighting factor as a function of n: Aw(n). Thus, for example, the weighting factor Aw(n) for an alternating harmonic series might be (-1) n ×K / n or (-1) (n-1) The above alternative form of the stage position weighting includes a factor (-1) as part of the weighting factor Aw(n) n or (-1) (n-1) , which changes the sign of the weighting factor Aw(n) for each increment of n. Alternating the sign of the weighting factor Aw(n) about the offset A0, particularly for the two or three most significant bits, maximizes the range of individual bit attenuation levels while maintaining comparable bit position weightings.

[0123] For example, Figure 13Graph 1300 shows the ranked attenuation weights from maximum to minimum attenuation for a 9-bit DSA using harmonic series bit position weights 1302 and alternating harmonic series bit position weights 1304. (Sorting the bit position weights for the alternating harmonic series makes it easier to compare these weights with the harmonic series bit position weights.) As shown in graphs 1302 and 1304, the range of bit level attenuation for harmonic series bit position weights 1302 is approximately 0.44 dB, while the range of bit level attenuation for alternating harmonic series bit position weights 1304 is approximately 0.75 dB. This difference is a result of the sign of the weighting factor Aw(n) alternating as a function of n about the offset A0.

[0124] In general, the use of a bit position weighting series including an alternating weighting factor Aw(n) provides more optimized resolution when one or both of the following constraints are met: (1) the maximum bit position attenuation level is constrained ("MSB" constraint), and / or (2) the minimum bit position attenuation is constrained ("LSB" constraint). In particular, the use of alternating geometric series bit position weighting or alternating harmonic series bit position weighting provides very fine resolution in the center of the attenuation range because nearly every state provides a unique attenuation value. The attenuation offset A0 in applying the weighting factor Aw(n) provides an increased degree of freedom, such that the relative bit attenuation level with respect to A0 can be made smaller and larger than with conventional weighting when one or both of the above-mentioned MSB and LSB constraints exist. That is, by using a nominal attenuation offset A0, larger relative attenuation levels can be achieved by utilizing both sides of the offset.

[0125] Broad implementation method

[0126] It should be understood that although specific mathematical expressions have been disclosed that generate bit position weights that provide fractional intermediate steps of attenuation or phase shift with a finer resolution than the value of the signal change at the lowest set level, other mathematical functions may provide alternative bit position weights that also exhibit fractional intermediate steps of attenuation or phase shift with a finer resolution than the value of the signal change at the lowest set level. Furthermore, the term "function" as used herein includes weighting methods that may not technically be "functions" in pure mathematical terms, but that similarly generate bit position weights that exhibit fractional intermediate steps of attenuation or phase shift and with a finer resolution than the value of the signal change at the lowest set level.

[0127] Most generally, embodiments of the present invention comprise an electronic circuit comprising a plurality of stages, each stage being configured to selectively change the attenuation or phase of an applied signal, each stage being assigned a bit position and digitally selectable by an associated control line to be in a reference state or in an active signal change state, wherein each stage is configured to provide an associated signal change (i.e., attenuation or phase shift, as the case may be) value, and wherein the associated signal change value for each stage is a function of a corresponding bit position weight determined by applying a bit position weighting function that produces fractional intermediate step sizes of signal change. The fractional intermediate step sizes of signal change have a finer resolution than the signal change value of the lowest-valued stage. The bit position weighting function can be one of: a linear series function, an alternating linear series function, a geometric series function, an alternating geometric series function, a harmonic series function, or an alternating harmonic series function. Furthermore, the signal change value of at least one stage can be set to a fixed value that is not determined by the bit position weighting function.

[0128] application

[0129] Embodiments of the present invention can be used in a variety of applications, such as DSAs and DPSs used in broadcast radio, cellular telephones, and RF-based digital networks (e.g., WiFi, Bluetooth), as well as in phase discriminators, beamforming networks, power dividers, linearization of power amplifiers, and phased array antennas. In some applications, one or more DSAs and one or more DPSs can be coupled in parallel or series to vary the attenuation and / or phase of an applied input signal. As described above, the dithering method described above can be used in conjunction with DSA and DPS circuits of the type shown in Figures 1, 2C, 3, and / or 4C, but with the novel bit weighting described above.

[0130] It should be noted that two or more different types of bit position weighting described above for embodiments of the present invention may be combined. For example, in a 12-bit DSA, linear bit position weighting may be used for the first 8 LSBs of the DSA, while geometric or harmonic bit position weighting may be used for the 4 MSBs of the DSA.

[0131] For use with transmission line DSAs, it is particularly useful to select bit position weights that maintain a shunt resistance greater than about 2*Z0 (where Z0 is the characteristic impedance of the transmission line) and an attenuation per bit less than about 2 dB.

[0132] The specific values of the components of each stage of the DSA or DPS can be determined based on the relative bit position weightings indicated by the expressions described above for embodiments of the present invention. For example, if A0 is set to 1 dB, K is set to 0.1 dB, and linear bit position weighting is used, the first stage of the DSA can be configured to provide 1 dB of attenuation, the second stage can be configured to provide 1.1 dB of attenuation, the third stage can be configured to provide 1.2 dB of attenuation, and so on, to as many stages as required for a particular application. Once a specific weight (i.e., value) is selected for the attenuator or phase shifter stage, then selecting the components and component values to achieve that weight is a conventional design problem.

[0133] method

[0134] Another aspect of the present invention includes a method for setting bit position weights for multiple stages of a DSA or DSP. For example, Figure 14 1400 is a process flow diagram of a first method for setting bit position weights for a plurality of signal change stages. The method includes providing an electronic circuit comprising a plurality of stages, each stage configured to selectively change the attenuation or phase of an applied signal, each stage being assigned a bit position and digitally selectable by an associated control line to be in a reference state or in an active signal change state (step 1402); configuring each stage to provide an associated signal change value (step 1404); and setting the associated signal change value for each stage to be a function of a corresponding bit position weight determined by applying a bit position weighting function that produces a fractional intermediate step size of the signal change (step 1406).

[0135] Other aspects of the above method include: the fractional intermediate step size of the signal change has a finer resolution than the signal change value of the lowest fixed level; the bit position weighting function can be one of the following: a linear series function, an alternating linear series function, a geometric series function, an alternating geometric series function, a harmonic series function or an alternating harmonic series function; and the method also includes providing at least one level having a signal change value set to a fixed value, which fixed value is not determined by the bit position weighting function.

[0136] Another method for setting bit position weights includes providing an electronic digital step attenuator circuit comprising a plurality of serially connected attenuator stages, each stage being assigned a bit position and digitally selectable by an associated control line to be in a reference state or in an attenuation state; configuring each stage with components to provide an associated signal attenuation value; and setting the associated signal attenuation value of each stage as a function of a corresponding bit position weight determined by applying an alternating harmonic stage bit position weighting function. Another aspect of the method includes providing at least one stage having a signal attenuation value set to a fixed value that is not determined by the alternating harmonic stage bit position weighting function.

[0137] Yet another method for setting bit position weights includes providing an electronic transmission line digital step attenuator circuit comprising a plurality of shunt attenuator stages, each stage being assigned a bit position and digitally selectable by an associated control line to be in a reference state or in an attenuation state; configuring each stage with components to provide an associated signal attenuation value; and setting the associated signal attenuation value for each stage as a function of a corresponding bit position weight determined by applying an alternating harmonic stage digital bit position weighting function.

[0138] Yet another method for setting bit position weights includes providing an electronic transmission line digital phase shifter circuit comprising a plurality of shunt phase shifter stages, each stage being assigned a bit position and digitally selectable by an associated control line to be in a reference state or in a phase-shifted state; configuring each stage with components to provide an associated signal phase shift value; and setting the associated signal phase shift value for each stage as a function of a corresponding bit position weight determined by applying an alternating harmonic stage digital bit position weighting function.

[0139] Manufacturing Techniques and Options

[0140] The term "MOSFET" as used in this disclosure means any field effect transistor (FET) having an insulated gate and comprising a metal or metalloid, an insulator, and a semiconductor structure. The term "metal" or "metalloid" includes at least one conductive material (e.g., aluminum, copper, or other metals, or highly doped polysilicon, graphene, or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric materials), and "semiconductor" includes at least one semiconductor material.

[0141] As should be apparent to one of ordinary skill in the art, various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise noted above, the selection of appropriate component values is a matter of design choice, and various embodiments of the present invention can be implemented in any suitable IC technology (including, but not limited to, MOSFET structures) or in hybrid or discrete circuit form. Integrated circuit embodiments can be manufactured using any suitable substrate and process, including, but not limited to, standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, the present invention can be implemented in other transistor technologies (e.g., bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies). However, the above-described inventive concepts are particularly useful for DSAs and DPSs fabricated using SOI-based fabrication processes (including SOS), as well as for fabrication processes with similar characteristics. Fabrication using CMOS processes on SOI or SOS enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., up to and exceeding 50 GHz radio frequencies). Monolithic IC implementations are particularly useful because parasitic capacitances can usually be kept low (or at a minimum, uniform across all cells, allowing them to be compensated for) by careful design.

[0142] Voltage levels can be adjusted and / or voltage and / or logic signal polarity can be inverted depending on the particular specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices). Component voltage, current, and power handling capabilities can be adjusted as needed, for example, by adjusting device dimensions, "stacking" components (particularly FETs) in series to withstand higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuits and / or provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0143] in conclusion

[0144] Several embodiments of the present invention have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the steps described above may not be order-dependent and, therefore, may be performed in an order different from that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the methods described above may be performed in a repetitive, serial, or parallel manner.

[0145] It should be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the appended claims and that other implementations are within the scope of the claims. (Note that parenthetical markers used for claim elements are provided for ease of reference to such elements and do not, by themselves, indicate a particular required order or listing of the elements; furthermore, such markers may be repeated in dependent claims as references to additional elements and should not be construed as starting a conflicting sequence of markers.)

Claims

1. An electronic circuit comprising: (a) a plurality of stages, each stage configured to selectively change the attenuation or phase of an applied signal, each stage being assigned a respective one of N bit positions, where N is a positive integer, each stage being digitally selectable by an associated control line to be in a reference state or in a valid signal-changing state; (b) wherein each stage is configured to provide an associated signal change value; (c) wherein the associated signal change value of each stage is a function of a corresponding bit position weight determined by applying a bit position weighting function; and (d) a selector coupled to the control line of each of the plurality of stages and configured to decode a provided control word into the control line; (e) wherein the control word provided has a range of values that enables the selector to select a combination of the N bit positions assigned to the stages to select the corresponding stages to provide a total range of signal changes, the total range of signal changes having a minimum signal change and a maximum signal change, and enabling the selector to provide a plurality of signal changes within the total range of signal changes between the minimum signal change and the maximum signal change, wherein the bit position weighting function enables selection of the combination of the stages to provide intermediate steps of signal changes between the plurality of signal changes with a resolution less than the signal change value of any one of the plurality of stages.

2. The electronic circuit according to claim 1, wherein The bit position weighting function is a linear series function, wherein the nth bit weight value of the N bit positions is equal to A0+((n-1)×K) or equal to A0-–((n-1)×K), where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportional constant.

3. The electronic circuit according to claim 1, wherein The bit position weighting function is an alternating linear series function, wherein the n-th bit weight value of the N bit positions is equal to A0+(-1) n ×((n-1)×K) or equal to A0+(-1) (n-1) ×((n-1)×K), where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportional constant.

4. The electronic circuit according to claim 1, wherein The bit position weighting function is a geometric series function, wherein the n-th bit weight value of the N bit positions is equal to A0+K / 2 (n-1) Or A0–K / 2 (n-1) , where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportionality constant.

5. The electronic circuit according to claim 1, wherein The bit position weighting function is an alternating geometric series function, wherein the n-th bit weight value of the N bit positions is equal to A0+(-1) (n-1) ×K / 2 (n-1) Or equal to A0+(-1) n ×K / 2 (n-1) , where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportionality constant.

6. The electronic circuit according to claim 1, wherein The bit position weighting function is a harmonic series function, wherein the nth bit weight value of the N bit positions is equal to A0+K / n or equal to A0–K / n, where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportional constant.

7. The electronic circuit according to claim 1, wherein The bit position weighting function is an alternating harmonic series function, wherein the n-th bit weight value of the N bit positions is equal to A0+(-1) n ×K / n or equal to A0+(-1) (n-1) ×K / n, where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportionality constant.

8. The electronic circuit of claim 1 , further comprising at least one stage coupled to the plurality of stages, and the at least one stage having a signal change value set to a fixed value that is not determined by the bit position weighting function.

9. The electronic circuit of claim 1 , wherein the electronic circuit is an electronic digital step attenuator circuit, wherein the plurality of stages are a plurality of serially connected attenuator stages, wherein the active signal change state of each attenuator stage provides a signal attenuation value.

10. The electronic circuit of claim 9 , further comprising at least one serially connected attenuator stage coupled to the plurality of serially connected attenuator stages and having a signal attenuation value set to a fixed value that is not determined by the bit position weighting function.

11. The electronic circuit of claim 1 , wherein the electronic circuit is an electronic transmission line digital step attenuator circuit, wherein: The plurality of stages is a plurality of shunt attenuator stages coupled to the transmission line, wherein the active signal change state of each shunt attenuator stage provides a signal attenuation value.

12. The electronic circuit of claim 1 , wherein the electronic circuit is an electronic transmission line digital phase shifter circuit, wherein the plurality of stages are a plurality of shunt phase shifter stages coupled to a transmission line, wherein, The active signal at each shunt phase shifter stage changes state to provide a phase shift value.

13. A method for setting a signal change value for each of a plurality of stages of an electronic circuit and selecting a signal change within a total range of signal changes achieved by the plurality of stages, each stage being configured to selectively change the attenuation or phase of an applied signal, each stage being assigned a respective one of N bit positions, wherein N is a positive integer, each stage being digitally selectable by an associated control line to be in a reference state or in a valid signal change state, the method comprising: (a) configuring each stage to provide an associated signal change value; (b) setting the associated signal change value of each stage to a weight set by applying a weighting function; (c) selecting combinations of N bit positions assigned to the stages so as to select corresponding stages to provide the signal change within a total range of the signal change, the total range of the signal change having a minimum signal change and a maximum signal change level, and providing a plurality of signal change levels between the minimum signal change level and the maximum signal change level within the total range of the signal change, wherein the bit position weighting function enables selection of combinations of the stages to provide intermediate steps of signal change between the plurality of signal change levels with a resolution less than the signal change value of any one of the plurality of stages.

14. The method according to claim 13, wherein The bit position weighting function is a linear series function, wherein the nth bit weight value of the N bit positions is equal to A0+((n-1)×K) or equal to A0-–((n-1)×K), where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportional constant.

15. The method according to claim 13, wherein The bit position weighting function is an alternating linear series function, wherein the n-th bit weight value of the N bit positions is equal to A0+(-1) n ×((n-1)×K) or equal to A0+(-1) (n-1) ×((n-1)×K), where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportional constant.

16. The method according to claim 13, wherein: The bit position weighting function is a geometric series function, wherein the n-th bit weight value of the N bit positions is equal to A0+K / 2 (n-1) Or it is equal to A0-–K / 2 (n-1) , where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportionality constant.

17. The method according to claim 13, wherein: The bit position weighting function is an alternating geometric series function, wherein the n-th bit weight value of the N bit positions is equal to A0+(-1) (n-1) ×K / 2 (n-1) Or equal to A0+(-1) n ×K / 2 (n -1) , where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportionality constant.

18. The method according to claim 13, wherein The bit position weighting function is a harmonic series function, wherein the nth bit weight value of the N bit positions is equal to A0+K / n or equal to A0--K / n, where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportional constant.

19. The method according to claim 13, wherein The bit position weighting function is an alternating harmonic series function, wherein the n-th bit weight value of the N bit positions is equal to A0+(-1) n ×K / n or equal to A0+(-1) (n-1) ×K / n, where A0 is a constant, n is the bit position of the stage and is a positive integer, and K is a non-zero proportionality constant.

20. The method of claim 13, further comprising providing at least one stage coupled to the plurality of stages, and the at least one stage having a signal change value set to a fixed value that is not determined by the bit position weighting function.

21. The method of claim 13, wherein the electronic circuit is an electronic digital step attenuator circuit comprising a plurality of attenuator stages connected in series, wherein the active signal change state of each attenuator stage provides a signal attenuation value.

22. The method of claim 21 further comprising providing at least one series-connected attenuator stage coupled to the series-connected attenuator stage and having a signal attenuation value set to a fixed value that is not determined by the bit position weighting function.

23. The method of claim 13, wherein the electronic circuit is an electronic transmission line digital step attenuator circuit, wherein the plurality of stages are a plurality of shunt attenuator stages coupled to a transmission line, wherein the active signal change state of each shunt attenuator stage provides a signal attenuation value.

24. The method of claim 13, wherein the electronic circuit is an electronic transmission line digital phase shifter circuit, wherein the plurality of stages are a plurality of shunt phase shifter stages coupled to a transmission line, wherein the active signal change state of each shunt phase shifter stage provides a phase shift value.

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