Chip-to-chip flip-chip packaging method and product

Abstract

The present application relates to a chip-attached flip-chip packaging method and product. Specifically, the present application provides a flip-chip packaging method, comprising: cutting a wafer to form a plurality of chip units, wherein each of the plurality of chip units comprises a plurality of chips; flip-chip bonding the plurality of chip units to a substrate via chip solder balls; and plastic-sealing the plurality of chip units and the substrate and cutting them to form a flip-chip packaged finished product.

Description

Technical Field

[0001] The present application generally relates to flip chip packaging technology, and more specifically to chip-attached flip chip packaging methods and products. Background Art

[0002] In the semiconductor industry, flip chip packaging technology is an innovation in the packaging field and is increasingly being used in the packaging field. Compared with general packaging technology, the main difference of flip chip packaging technology is that it integrates the two processes or stations of die bonding and wire bonding, thereby simplifying the production process of the packaging front-end and effectively improving the packaging efficiency and finished product yield.

[0003] As chip sizes become thinner and smaller, flip chip packaging technology is facing increasingly severe technical challenges. For example, the chip size has been reduced to 0.5×0.5mm. 2 The following (this small chip size can also be called a die), resulting in the chip can only accommodate at most two solder balls (for example, tin balls) under the chip. However, the existing flip chip packaging technology has an insurmountable threshold due to its own process, that is, the chip area must be larger than 0.5×0.5mm 2 Once the area is smaller than this, the chip is very likely to tilt during the existing flip-chip packaging process due to the small number of solder balls underneath.

[0004] In view of this, there is an urgent need in the art to provide improved solutions to solve the above problems. Summary of the invention

[0005] The embodiments of the present application attempt to solve at least one problem existing in the related field to at least some extent by providing a chip-attached flip-chip packaging method, and accordingly provide a flip-chip packaging product prepared using the chip-attached flip-chip packaging method.

[0006] In one embodiment, the present application provides a flip-chip packaging method, comprising: cutting a wafer to form a plurality of chip units, wherein each of the plurality of chip units comprises a plurality of chips; flip-chip bonding the plurality of chip units to a substrate via chip solder balls; and plastic-sealing and cutting the plurality of chip units and the substrate to form a flip-chip packaging product.

[0007] According to an embodiment of the present application, the number of chips included in the plurality of chip units is an even number.

[0008] According to an embodiment of the present application, the number of chips included in the multiple chip units is the same.

[0009] According to an embodiment of the present application, the chips in the plurality of chip units have different arrangements and / or chip sizes.

[0010] According to an embodiment of the present application, when the number of the chip solder balls is 1, the number of chips included in each of the plurality of chip units is at least four.

[0011] According to an embodiment of the present application, when the number of the chip solder balls is 2, the number of chips included in each of the plurality of chip units is at least two.

[0012] According to an embodiment of the present application, the cutting includes using a product cutting blade to cut along the gaps between the plurality of chip units, and using a wafer cutting blade to cut along the gaps between the chips within the plurality of chip units.

[0013] According to an embodiment of the present application, it further includes first using the wafer cutting knife to cut, and then using the finished product cutting knife to cut.

[0014] According to an embodiment of the present application, it further comprises first using the finished product cutting knife for cutting, and then using the wafer cutting knife for cutting.

[0015] According to an embodiment of the present application, the chip area of ​​the chip is less than or equal to 0.5×0.5 mm 2 .

[0016] According to an embodiment of the present application, the solder ball is a tin ball.

[0017] In one embodiment, the present application provides a flip-chip packaging product, which includes: a substrate; a chip flip-chip bonded to the substrate via chip solder balls; and a plastic encapsulating compound encapsulating the chip and exposing at least one side surface of the chip.

[0018] Additional aspects and advantages of the embodiments of the present application will be described, shown, or explained in part in the subsequent description through implementation of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The following will briefly describe the drawings necessary for describing the embodiments of the present application or the prior art to facilitate the description of the embodiments of the present application. Obviously, the drawings described below are only some of the embodiments in the present application. For those skilled in the art, without the need for creative work, drawings of other embodiments can still be obtained based on the structures illustrated in these drawings.

[0020] Figure 1 A cross-sectional view showing a finished product of a flip-chip packaged chip in the prior art.

[0021] Figure 2A schematic diagram of a single solder ball package in the prior art is shown.

[0022] Figure 3 A schematic diagram of a double solder ball package in the prior art is shown.

[0023] Figure 4 A schematic flow chart showing the existing flip chip packaging technology.

[0024] Figure 5 A schematic flow chart showing the conjoined flip chip packaging technology according to an embodiment of the present application is shown.

[0025] Figure 6 A partially enlarged schematic diagram of a dual-ball conjoined flip-chip package according to an embodiment of the present application is shown.

[0026] Figure 7 A partial schematic diagram of single solder ball flip chip bonding according to an embodiment of the present application is shown.

[0027] Figure 8 A partial schematic diagram of double-ball flip-chip bonding according to an embodiment of the present application is shown.

[0028] Fig. 9 A schematic diagram of a flip chip packaging product using an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] In order to better understand the spirit of the present application, it is further described below in conjunction with some preferred embodiments of the present application. In the full text of the present application specification, the same or similar components and components with the same or similar functions are represented by similar figure marks. The embodiments of the accompanying drawings described herein are illustrative and graphical and are used to provide a basic understanding of the present application. The embodiments of the present application should not be interpreted as limiting the present application.

[0030] In the present application, unless otherwise specified or limited, when a first feature is located "above" or "below" a second feature in a structure, the structure may include an embodiment in which the first feature is in direct contact with the second feature, and the structure may also include another embodiment in which the first feature is not in direct contact with the second feature, but is in contact with the second feature through an additional feature formed therebetween. In addition, when a first feature is located "above", "above" or "at the top of" a second feature, it may include an embodiment in which the first feature is directly or obliquely located "above", "above" or "at the top of" the second feature, or simply represents that the height of the first feature is higher than the height of the second feature; and when a first feature is located "below", "below" or "at the bottom of" a second feature, it may include an embodiment in which the first feature is directly or obliquely located "below", "below" or "at the bottom of" the second feature, or simply represents that the height of the first feature is lower than the height of the second feature. Directional terms mentioned in this application, such as top, bottom, left, right, front, back, side, horizontal, lateral, vertical, etc., are only used to refer to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand this application, but not to limit this application.

[0031] Various embodiments of the present application are discussed in detail below. Although specific implementations are discussed, it should be understood that these embodiments are only for illustrative purposes. Those skilled in the relevant art will recognize that other components and configurations may be used without departing from the spirit and scope of the present application.

[0032] Figure 1 The finished cross-sectional view of the flip chip packaged in the prior art is shown. Figure 1 As shown, a single chip 100 cut from a wafer is flip-chip bonded to a substrate 102 via a plurality of solder balls 101 after flip-chip mounting, and a plastic sealant 103 covers the chip 100, the plurality of solder balls 101 and the substrate 102, thereby forming a flip-chip package product. It should be understood that the plurality of solder balls 101 are not limited to Figure 1 The four shown in the figure can be any number; the substrate 102 is not limited to Figure 1 The structure shown in the figure can be any continuous or discrete structure. It should still be understood that the plastic encapsulation 103 can only cover the chip 100 and the plurality of solder balls 101 , but not the substrate 102 . Figure 1 The conventional flip chip package shown is usually larger in size and can accommodate more solder balls under the chip. Therefore, the chip 100 can remain parallel to the substrate 102 and the chip 100 will not tilt or even fall on the substrate 102.

[0033] However, as the chip size is reduced to 0.5×0.5mm 2 Below this point, the number of solder balls that can be accommodated under the chip will be less than 3. At this point, due to the limitation of the flip chip packaging machine capacity, the finished package will encounter difficult problems to overcome, which will be discussed in detail below. Figure 2 and Figure 3 Be elaborated in detail.

[0034] Figure 2 The schematic diagram of single solder ball packaging in the prior art is shown. A single chip 200 cut from a wafer is flip-chip bonded to a substrate 202 via only one solder ball 201 after flip-chip mounting. Since only one solder ball provides support, the chip 200 is very likely to tilt after flip-chip bonding, making it difficult for the chip 200 to remain parallel to the substrate 202 or even fall on the substrate 202, thereby reducing the packaging efficiency and the yield rate of finished products.

[0035] Similarly, Figure 3 The schematic diagram of the double solder ball package in the prior art is shown. A single chip 300 cut from a wafer is flip-chip bonded to a substrate 302 via only two solder balls 301 after flip-chip mounting. Figure 2 In terms of Figure 3 The illustrated embodiment includes two solder balls 301 to provide better support, but Figure 3 The two solder balls 301 can only provide fragile linear support at most, so the chip 300 is still very likely to tilt after flip chip bonding, making it difficult for the chip 300 to remain parallel to the substrate 302 or even fall on the substrate 302, thereby reducing the packaging efficiency and the yield rate of the finished product.

[0036] Figure 4 A schematic flow chart showing the current flip chip packaging technology. Figure 4 As shown, a plurality of identical chips with circuits formed thereon are included on the wafer 401. In the prior art, the chips on the wafer 401 are cut into pieces for subsequent packaging steps. Figure 4 The right side of the middle wafer 401 shows a partial enlarged view consisting of multiple chips 402 that have been cut separately by a wafer cutting knife, and each chip 402 contains a single solder ball 403. Next, the cut multiple chips 402 are flip-chip bonded to the substrate 404 via their respective single solder balls 403, and there are approximately equal gaps between the multiple chips 402 that have completed flip-chip bonding. Furthermore, in a subsequent step, a plastic encapsulating glue 405 (or any packaging material) is used to plastic-encapsulate the multiple chips 402 that have completed flip-chip bonding. In the final finished product cutting step, a finished product cutting knife is used to cut the multiple plastic-encapsulated chips 402 along the horizontal and vertical cutting lanes 406 to obtain a flip-chip packaged finished product. It should be understood that Figure 4The eight chips 402 shown in the figure are only examples, and the processes such as flip chip bonding, flip chip packaging and finished product cutting can be implemented for any number of chips.

[0037] exist Figure 4 In the conventional flip chip packaging technology, each chip 402 containing only a single solder ball 403 is cut into pieces and then flip-chip bonded to a substrate 404, which causes the chip 402 to easily tilt or even fall on the substrate during the flip chip packaging process due to the lack of effective support from the solder ball below (e.g. Figure 2 The defects shown in the figure) will reduce the packaging efficiency and product yield. It should be understood that if the chip containing double solder balls is used Figure 4 In the conventional flip chip packaging technology shown in the figure, the chip will also be easily tilted or even fall on the substrate during the flip chip packaging process due to the lack of effective support from the solder balls below (for example Figure 3 The defects shown) will also reduce the packaging efficiency and product yield.

[0038] Figure 5 A schematic flow chart showing the conjoined flip chip packaging technology according to an embodiment of the present application. Figure 5 As shown, the wafer 501 contains a number of identical chips with circuits formed thereon. Different from the split cutting method of the prior art, Figure 5 The chips on the wafer 501 in the embodiment are cut into a plurality of chip units for subsequent packaging steps, and each of the plurality of chip units includes an even number of chips of the same number. Figure 5 In the figure, a partial enlarged view of two chip units 502 cut by a wafer cutting knife is shown on the right side of the wafer 501, wherein each chip unit 502 is composed of four conjoined chips 503, and each chip 503 may include a single solder ball 503'.

[0039] It should be understandable that Figure 5 In the illustrated embodiment and all the embodiments described below, the number of chips included in each chip unit may be different from each other and is not limited to an even number. Figure 5 In the illustrated embodiment, the chip unit 502 located at the lower right side of the wafer 501 may include five chips 503 instead of the four chips 503 shown in the figure, so that it has a different number of chips from the chip unit 502 including four chips 503 above it and has an odd number of chips. Figure 5 In the illustrated embodiment and all the embodiments described below, the chips included in each chip unit may also have different arrangements and / or chip sizes. For example (but not limited to), Figure 5In the illustrated embodiment, each chip unit 502 may also be composed of only two chips 503 in a conjoined manner, wherein the two chips 503 in one chip unit 502 are arranged in a 1×2 manner, and the two chips 503 in another chip unit 502 are arranged in a 2×1 manner. Furthermore, the chip area of ​​one or more chips 503 may be less than or equal to 0.5×0.5 mm. 2 .

[0040] Next, the cut multiple chip units 502 are flip-chip bonded to the substrate 504 via single solder balls 503', and there is a certain gap between the multiple chip units 502 that have completed flip-chip bonding. In this way, each chip unit 502 can be stably supported by a total of four single solder balls 503'. Further, in the subsequent steps, the multiple chip units 502 that have completed flip-chip bonding are plastic-sealed using plastic sealant 505 (or any packaging material). It is worth noting that the substrate design needs to be designed in units of 2 or multiples of 2 products to maximize the use of substrate space and reduce costs.

[0041] Still see Figure 5 In the final finished product cutting step, since the gap 507 between the two chip units 502 is large and basically does not contain wafer material, it is only necessary to use the finished product cutting knife to cut along the gap 507 between the two chip units 502. However, inside the chip unit 502, since the gaps between the chips 503 are small and contain wafer material, a wafer cutting knife (or other cutting tools with wafer cutting capabilities) must be used to cut along the gaps 506 between the chips 503. It should be understood that it is possible to use a wafer cutting knife first and then a finished product cutting knife, or it is possible to use the reverse order of first using a finished product cutting knife and then a wafer cutting knife, as long as all the chips 503 after flip chip packaging are cut off.

[0042] exist Figure 5 In the illustrated embodiment, although each of the chips 503 includes only a single solder ball 503', thanks to the adoption of the conjoined flip-chip packaging technology, each chip unit 502 as a whole can include up to four solder balls 503', and the four chips 503 can provide additional support to each other with the help of the conjoined structure, so that each chip 503 in the chip unit 502 will not tilt in any form during the flip-chip packaging process and will not fall on the substrate 504, thereby effectively avoiding the following problems: Figure 2 and Figure 3 The defects displayed significantly improve packaging efficiency and product yield.

[0043] Figure 5The chip-attached flip-chip package used in the illustrated embodiment can increase the total chip area during flip-chip bonding by multiples, thereby breaking through the limitation of chip area on the flip-chip machine capability, and increasing the flip-chip machine capability in terms of chip bonding area by multiples. At the same time, during a single flip-chip bonding, since the number of chips bonded by the chip-attached flip-chip package is several times that of the traditional flip-chip package, the efficiency of flip-chip bonding can also be effectively improved.

[0044] It should be understandable. Figure 5 Each chip in the embodiment shown may also include double solder balls or any other number of solder balls. Figure 6 The enlarged schematic diagram of a partial double-bump conjoined flip chip package according to an embodiment of the present application is shown. After being conjoined and cut, multiple chips on a wafer are flip-chip bonded to a substrate 601 to form a chip array 602. A partial chip array 603 can be shown by enlarging a part of the chip array 602. Figure 6 It can be seen that the local chip array 603 includes four chip units, each chip unit includes four chips, and each chip includes two chip solder balls. After completing the flip chip packaging of the chip array 602, the finished product cutting knife 604 can be used to cut along the gaps between the chip units, and then the wafer cutting knife can be used to cut along the gaps between the chips. It should be understood that the above cutting order can be reversed without affecting the finished package.

[0045] The chip-on-chip flip-chip packaging technology of the present invention may have the following design constraints on the quantity relationship between the chip solder balls and the chip:

[0046] 1. When the number of chip solder balls under the chip is 1, the number of chips contained in each of the plurality of chip units should be at least four.

[0047] 2. When the number of chip solder balls under the chip is 2, the number of chips contained in each of the plurality of chip units should be at least two.

[0048] Figure 7 A partial schematic diagram of single solder ball flip chip bonding according to an embodiment of the present application is shown. According to the above rule 1, when the number of chip solder balls 703 under each chip 702 is 1, each of the plurality of chip units 701 should include at least four chips 702 to ensure reliable solder joint support.

[0049] Figure 8 A partial schematic diagram of double solder ball flip chip bonding according to an embodiment of the present application is shown. According to the above rule 2, when the number of chip solder balls 803 under each chip 802 is 2, each of the plurality of chip units 801 should include at least two chips 802 to ensure reliable solder joint support.

[0050] As a special embodiment, when the chip aspect ratio is greater than or equal to 3 (the aspect ratio may be equal to the number of chips that are simultaneously flip-chip packaged), then in the width direction, only more than 3 chips need to be conjoined for flip-chip packaging to effectively solve the common chip warping problem during flip-chip packaging.

[0051] Fig. 9 A schematic diagram of a flip chip package product using an embodiment of the present application is shown. The flip chip package product 900 may include a chip 901, chip solder balls 902, a substrate 903, and a plastic encapsulant 904. The chip 901 is flip-chip bonded to the substrate 903 via the chip solder balls 902, and the plastic encapsulant 904 encapsulates the upper surface of the chip 901 and fills the space between the chip 901 and the substrate 903 except for the chip solder balls 902. Among them, any side surface or even all side surfaces of the chip 901 may be exposed to the outside without being encapsulated by the plastic encapsulant 904. As an embodiment, Fig. 9 The flip chip package product 900 shown may also include only one chip solder ball 902. As another embodiment, Fig. 9 The chip area of ​​the middle chip 901 can be less than or equal to 0.5×0.5mm 2 .

[0052] Fig. 9 The flip chip package product 900 shown can be prepared by the conjoined flip chip packaging technology described in each embodiment of the present application. The conjoined flip chip packaging method of each embodiment of the present application can be used to obtain a product in a more efficient and robust manner. Fig. 9 The flip chip package product 900 is shown, and in the whole process flow, the chip 901 always remains parallel to the substrate 903 without tilting, so as to improve the efficiency and the finished product yield while obtaining a special chip package product including at least one exposed side surface.

[0053] The chip-attached flip-chip packaging technology of the present invention breaks through the limitation that the number of chip solder balls must be greater than 2 in traditional flip-chip packaging, improves the process capability, and breaks through the limitation of chip area on flip-chip machine capability by doubling the total chip area during flip-chip bonding, so that the flip-chip machine's capability in bonding chip area is increased exponentially, and the efficiency of flip-chip bonding is effectively improved. At the same time, the chip-attached flip-chip packaging technology of the present invention can effectively prevent the chip from tilting during the flip-chip packaging process, thereby improving efficiency and finished product yield.

[0054] References to "embodiments", "partial embodiments", "one embodiment", "another example", "example", "specific example" or "partial example" throughout the specification mean that at least one embodiment or example in the present application includes the specific features, structures, materials or characteristics described in the embodiment or example. Therefore, descriptions appearing in various places throughout the specification, such as "in some embodiments", "in an embodiment", "in one embodiment", "in another example", "in an example", "in a specific example" or "example", do not necessarily refer to the same embodiment or example in the present application.

[0055] The technical content and technical features of the present application have been described by the above-mentioned relevant embodiments, but the above-mentioned embodiments are only examples for implementing the present application. Those skilled in the art may still make various substitutions and modifications based on the teachings and disclosures of the present application without departing from the spirit of the present application. Therefore, the embodiments disclosed in the present application do not limit the scope of the present application. On the contrary, modifications and equivalent settings contained in the spirit and scope of the claims are all included in the scope of the present application.

Claims

1. A flip chip packaging method, comprising: cutting the wafer to form a plurality of chip units, wherein each of the plurality of chip units comprises a plurality of chips; Flip-die bonding each of the plurality of chips to a substrate via one or two chip solder balls; and The plurality of chip units and the substrate are plastic-encapsulated and cut to form a flip chip package product. 2 . The flip chip packaging method according to claim 1 , wherein the number of chips included in the plurality of chip units is an even number. 3 . The flip chip packaging method according to claim 1 , wherein the number of chips included in the plurality of chip units is the same. 4 . The flip chip packaging method according to claim 1 , wherein the chips in the plurality of chip units have different arrangements and / or chip sizes. 5 . 5 . The flip chip packaging method according to claim 1 , wherein when the number of the chip solder balls is 1, the number of chips included in each of the plurality of chip units is at least four. 6 . The flip chip packaging method according to claim 1 , wherein when the number of the chip solder balls is 2, the number of chips included in each of the plurality of chip units is at least two. 7 . The flip chip packaging method according to claim 1 , wherein the cutting comprises using a product cutting blade to cut along the gaps between the plurality of chip units, and using a wafer cutting blade to cut along the gaps between the chips within the plurality of chip units. 8 . The flip chip packaging method according to claim 7 , further comprising first cutting with the wafer cutting knife and then cutting with the finished product cutting knife. 9 . The flip chip packaging method according to claim 7 , further comprising first cutting with the product cutting knife and then cutting with the wafer cutting knife.

10. The flip chip packaging method according to claim 1, wherein the chip area of ​​the chip is less than or equal to 0.5×0.5 mm 2 . The flip chip packaging method according to claim 1 , wherein the chip solder balls are solder balls.

12. A flip chip packaging product prepared by the flip chip packaging method according to claim 1, comprising: substrate; The chip is flip-chip bonded to the substrate via chip solder balls; A plastic encapsulation sealant encapsulates the chip and exposes at least one side surface of the chip.

13. The flip chip package product according to claim 12, wherein the chip area of ​​the chip is less than or equal to 0.5×0.5 mm 2 . The flip chip package product according to claim 12 , wherein the chip solder balls are solder balls.

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