SRAM Circuit

Abstract

An SRAM circuit, the SRAM circuit includes: a read unit and a write unit, wherein: the read unit is connected to the write unit, includes at least one negative capacitance transistor, suitable for reading data; the write unit is connected to the read unit, includes at least one negative capacitance transistor, suitable for writing data; wherein the at least one negative capacitance transistor of the read unit and the at least one negative capacitance transistor of the write unit are asymmetrically arranged in the SRAM circuit. The above scheme can improve the read and write capabilities of the SRAM.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a SRAM circuit. Background Art

[0002] Static Random-Access Memory (SRAM) is a type of random access memory. SRAM can save the data stored inside it without refreshing the circuit. Dynamic Random Access Memory (DRAM) needs to be refreshed and charged every once in a while, otherwise the internal data will disappear. Therefore, SRAM has higher performance, but the same capacity of DRAM memory can be designed to be smaller, but SRAM requires a large volume. At the same time, the read and write capabilities of SRAM affect each other and increase and decrease at the same time.

[0003] In the prior art, in order to improve the read and write capabilities of the SRAM, complex read circuits and write circuits are usually designed, which further increases the size and cost of the SRAM. Summary of the invention

[0004] The embodiment of the present invention solves the technical problem that the read and write capabilities of SRAM are relatively poor.

[0005] To solve the above technical problems, an embodiment of the present invention provides an SRAM circuit, comprising: a read unit and a write unit, wherein: the read unit is connected to the write unit, comprises at least one negative capacitance transistor, and is suitable for reading data; the write unit is connected to the read unit, comprises at least one negative capacitance transistor, and is suitable for writing data; wherein the at least one negative capacitance transistor of the read unit and the at least one negative capacitance transistor of the write unit are asymmetrically arranged in the SRAM circuit.

[0006] Optionally, at least one negative capacitance transistor in the read unit is suitable for pulling down the first bit line voltage.

[0007] Optionally, the read unit includes a negative capacitance transistor.

[0008] Optionally, at least one negative capacitance transistor in the write unit is suitable for controlling conduction or disconnection between the second bit line and the write unit.

[0009] Optionally, the write unit includes a negative capacitance transistor.

[0010] Optionally, the read unit includes a first negative capacitance transistor and a first NMOS transistor, wherein: the first NMOS transistor has a source connected to the first bit line, a gate connected to the word line, and a drain connected to the source of the first negative capacitance transistor and the write unit; the first negative capacitance transistor has a gate connected to the write unit and a drain connected to ground.

[0011] Optionally, the write unit includes a second negative capacitance transistor and a first PMOS tube, wherein: the first PMOS tube has a source connected to the power supply voltage, a gate connected to the read unit, and a drain connected to the source of the second negative capacitance transistor; the second negative capacitance transistor has a gate connected to the word line, and a drain connected to the second bit line.

[0012] Optionally, the SRAM circuit also includes: a second PMOS tube and a second NMOS tube, wherein: the second PMOS tube has a source connected to the power supply voltage and the write unit, a gate connected to the read unit, the write unit and the source of the second NMOS tube, and a drain connected to the write unit, the read unit and the gate of the second NMOS tube; the second NMOS tube has a drain connected to ground.

[0013] Optionally, the SRAM circuit is a 6T SRAM circuit.

[0014] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0015] At least one negative capacitance transistor of the read unit and at least one negative capacitance transistor of the write unit are asymmetrically arranged in the SRAM circuit. At least two negative capacitance transistors are used to form an asymmetric structure, which not only strengthens the read and write currents through the negative capacitance transistors, but also uses an asymmetric structure to ensure that each pair of negative capacitance transistors will not affect each other, thereby avoiding the situation where the read and write capabilities of one side are enhanced and the other side is weakened. Therefore, the above scheme can effectively improve the read and write capabilities of the SRAM circuit without increasing the complexity of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 4 is a circuit diagram of an SRAM circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In the prior art, in order to improve the read and write capabilities of the SRAM, complex read circuits and write circuits are usually designed, which further increases the size and cost of the SRAM.

[0018] In an embodiment of the present invention, at least one negative capacitance transistor (Negative Capacitance Fin Field-Effect Transistor, NC-FINFET) of the read unit and at least one negative capacitance transistor of the write unit are asymmetrically arranged in the SRAM circuit. At least two negative capacitance transistors are used to form an asymmetric structure, which not only strengthens the read and write currents through the negative capacitance transistors, but also uses an asymmetric structure to ensure that each pair of negative capacitance transistors will not affect each other, thereby avoiding the situation where the read and write capabilities of one side are enhanced and the other side is weakened. Without increasing the complexity of the circuit, the read and write capabilities of the SRAM circuit are effectively improved.

[0019] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0020] Reference Figure 1 , an embodiment of the present invention provides an SRAM circuit, including: a read unit 101 and a write unit 102, wherein:

[0021] The read unit 101 is connected to the write unit 102 and includes at least one negative capacitance transistor NC-FINFET1, which is suitable for reading data;

[0022] The write unit 102 is connected to the read unit 101 and includes at least one negative capacitance transistor NC-FINFET2 suitable for writing data.

[0023] Capacitance, or the amount of charge stored, is generally positive. However, if ferroelectric material is added to the gate of a transistor, a negative capacitance value will be generated. This is because, at a certain critical voltage, the polarization direction of the ferroelectric will reverse, which will cause a huge accumulation of bound charge on the surface of the material to instantly exceed the electrode supply of the power supply. At this time, if a resistor is placed between the electrode and the external power supply, it can be seen that the voltage is decreasing, but the charge is still increasing, resulting in a negative capacitance phenomenon.

[0024] Negative capacitance transistors are transistors that use the negative capacitance principle and use ferroelectric materials in the transistor gate. When the voltage is constant, compared with the case where the current of an ordinary transistor is a certain value under a certain process, the negative capacitance transistor can accumulate a huge amount of charge, carry more current, and thus have the effect of increasing the current. Therefore, the current control ability of the negative capacitance transistor is strong, and its current is also significantly increased. In addition, the power consumption generated by controlling the transistor using negative capacitance is very low, which reduces the power consumption of the circuit using the negative capacitance transistor, and has broad prospects in the semiconductor field.

[0025] In the embodiment of the present invention, the read unit 101 and the write unit 102 each include at least one negative capacitance transistor (Negative Capacitance Fin Field-Effect Transistor, NC-FINFET).

[0026] In an embodiment of the present invention, the read unit 101 and the write unit 102 may each include at least one negative capacitance transistor. Specifically, the number of negative capacitance transistors NC-FINFET1 in the read unit 101 may be the same as the number of negative capacitance transistors NC-FINFET2 in the write unit 102. For example, the number of negative capacitance transistors NC-FINFET1 in the read unit 101 is 1, and the number of negative capacitance transistors NC-FINFET2 in the write unit 102 is 1. The number of negative capacitance transistors NC-FINFET1 in the read unit 101 may be different from the number of negative capacitance transistors NC-FINFET2 in the write unit 102.

[0027] In a specific implementation, at least one negative capacitance transistor NC-FINFET1 of the read unit 101 and at least one negative capacitance transistor NC-FINFET2 of the write unit 102 may be asymmetrically arranged in the SRAM circuit.

[0028] If the read unit 101 includes only one negative capacitance transistor NC-FINFET1 and the write unit 102 includes only one negative capacitance transistor NC-FINFET2, the position of the negative capacitance transistor NC-FINFET1 in the SRAM circuit is asymmetrical to the position of the negative capacitance transistor NC-FINFET2 in the SRAM circuit.

[0029] If the number of negative capacitance transistors NC-FINFET1 included in the read unit 101 is multiple, and the number of negative capacitance transistors NC-FINFET2 included in the write unit 102 is also multiple, then there is at least one negative capacitance transistor NC-FINFET1 in the read unit 101, and its setting position is asymmetrical to the position of the corresponding negative capacitance transistor NC-FINFET2 in the write unit 102.

[0030] In a conventional SRAM circuit, a common transistor in a read unit and a common transistor in a write unit are usually arranged symmetrically. However, the symmetrically arranged transistors may cause the read and write capabilities of the SRAM circuit to affect each other.

[0031] In practical applications, for an SRAM circuit, the symmetrical arrangement of the transistors of the read unit and the transistors of the write unit may mean that the connection relationships between the gates, sources and drains of the two and other components or input signals are the same or similar.

[0032] For example, Figure 1 In the embodiment of the present invention, the negative capacitance transistor NC-FINFET1 in the read unit 101 substantially corresponds to the negative capacitance transistor NC-FINFET2 in the write unit 102. Figure 1 It can be seen that the position of the negative capacitance transistor NC-FINFET1 in the read unit 101 and the position of the negative capacitance transistor NC-FINFET2 in the write unit 102 are set asymmetrically.

[0033] Compared to a conventional SRAM circuit, or a case where all ordinary transistors in an SRAM circuit are replaced with negative capacitance transistors, in an embodiment of the present invention, the negative capacitance transistors of the read unit 101 and the write unit 102 are asymmetrically arranged, so that when the negative capacitance transistors improve the current control capability and enhance the current, the mutual influence of the read and write capabilities caused by the symmetrical arrangement can be avoided.

[0034] In a specific implementation, at least one negative capacitance transistor NC-FINFET1 in the read unit 101 is adapted to pull down the voltage of the first bit line BL. Figure 1 It can be seen that the negative capacitance transistor NC-FINFET1 is used as a pull-down tube in the read unit 101. Since the read capability of the SRAM circuit depends on the ratio of the current of the pull-down tube to the current of the switch tube (positive correlation), therefore, using the negative capacitance transistor NC-FINFET1 to replace the original ordinary transistor as the pull-down tube can effectively increase the current of the pull-down tube, making the read current Iread stronger, and the ratio of the current of the pull-down tube to the current of the switch tube in the read unit 101 is also higher, thereby improving the read capability of the SRAM circuit.

[0035] In a specific implementation, the read unit 101 includes a negative capacitance transistor NC-FINFET1. At the same time, the negative capacitance transistor NC-FINFET1 of the read unit 101 and at least one negative capacitance transistor NC-FINFET2 of the write unit 102 are asymmetrically arranged in the SRAM circuit. It can be understood that, under the premise that at least one negative capacitance transistor NC-FINFET1 of the read unit 101 and at least one negative capacitance transistor NC-FINFET2 of the write unit 102 are asymmetrically arranged in the SRAM circuit, multiple negative capacitance transistors can be respectively arranged in the read unit 101 and the write unit 102, and the present invention is not limited here.

[0036] In a specific implementation, at least one negative capacitance transistor NC-FINFET2 in the write unit 102 is adapted to control the conduction or disconnection between the second bit line BLB and the write unit 102. Meanwhile, the negative capacitance transistor NC-FINFET1 of the read unit 101 and at least one negative capacitance transistor NC-FINFET2 of the write unit 102 are asymmetrically arranged in the SRAM circuit.

[0037] Depend on Figure 1 It can be seen that the negative capacitance transistor NC-FINFET2 is used as a switch tube in the write unit 102. Since the write capability of the SRAM circuit depends on the ratio of the current of the switch tube to the current of the pull-up tube (positive correlation), therefore, using the negative capacitance transistor NC-FINFET2 to replace the original ordinary transistor as the switch tube can effectively increase the current of the switch tube, making the write current Iwrite stronger, and the ratio of the current of the switch tube to the current of the pull-up tube in the write unit 102 is also higher, thereby improving the write capability of the SRAM circuit.

[0038] In a specific implementation, the write unit 102 includes a negative capacitance transistor NC-FINFET2. At the same time, the negative capacitance transistor NC-FINFET1 of the read unit 101 and at least one negative capacitance transistor NC-FINFET2 of the write unit 102 are asymmetrically arranged in the SRAM circuit. It can be understood that, under the premise that at least one negative capacitance transistor NC-FINFET1 of the read unit 101 and at least one negative capacitance transistor NC-FINFET2 of the write unit 102 are asymmetrically arranged in the SRAM circuit, multiple negative capacitance transistors can be respectively arranged in the read unit 101 and the write unit 102, and the present invention is not limited here.

[0039] In a specific implementation, the read unit 101 may include a first negative capacitance transistor NC-FINFET1 and a first NMOS transistor N1, wherein:

[0040] The first NMOS transistor N1 has a source connected to the first bit line BL, a gate connected to the word line WL, and a drain connected to the source of the first negative capacitance transistor NC-FINFET1 and the write unit 102;

[0041] The first negative capacitance transistor NC-FINFET1 has a gate connected to the write unit 102 and a drain connected to the ground.

[0042] exist Figure 1 In the read unit 101, the first negative capacitance transistor NC-FINFET1 is a pull-down transistor, and the first NMOS transistor N1 is a switch transistor. Since the negative capacitance transistor NC-FINFET1 is set as a pull-down transistor in the read unit 101, the read current Iread is enhanced.

[0043] In a specific implementation, the write unit 102 may include a second negative capacitance transistor NC-FINFET2 and a first PMOS transistor P1, wherein:

[0044] The first PMOS transistor P1 has a source connected to the power supply voltage, a gate connected to the read unit 101, and a drain connected to the source of the second negative capacitance transistor NC-FINFET2;

[0045] The second negative capacitance transistor NC-FINFET2 has a gate connected to the word line WL and a drain connected to the second bit line BLB.

[0046] exist Figure 1 In the write unit 102, the second negative capacitance transistor NC-FINFET2 is a switch tube, and the first PMOS tube P1 is a pull-up tube. Since the negative capacitance transistor NC-FINFET2 is set as a switch tube in the write unit 102, the write current Iwrite is enhanced, and the current ratio of the switch tube to the pull-up tube in the write unit 102 is increased, which effectively improves the write capability of the SRAM circuit.

[0047] In addition, since the negative capacitance transistor NC-FINFET1 of the read unit 101 and the negative capacitance transistor NC-FINFET2 of the write unit 102 are asymmetrically arranged in the SRAM circuit, the read unit 101 and the write unit 102 not only improve the reading and writing capabilities respectively, but also do not affect each other or increase or decrease each other, thereby effectively improving the overall reading and writing capabilities of the SRAM circuit.

[0048] In a specific implementation, the SRAM circuit may further include: a second PMOS transistor P2 and a second NMOS transistor N2, wherein:

[0049] The second PMOS transistor P2 is a pull-up transistor, the source of which is connected to the power supply voltage and the write unit 102, the gate of which is connected to the read unit 101, the write unit 102 and the source of the second NMOS transistor N2, and the drain of which is connected to the write unit 102, the read unit 101 and the gate of the second NMOS transistor N2;

[0050] The second NMOS tube N2 is a pull-down tube, and the drain is grounded.

[0051] In a specific implementation, the SRAM circuit may be a 6T SRAM circuit, that is, a SRAM circuit including 6 transistors. It is understandable that the above solution may be used for a variety of SRAM circuits, such as 6T SRAM, 8T SRAM, 10T SRAM, etc., and the present invention is not limited thereto.

[0052] In summary, at least one negative capacitance transistor of the read unit and at least one negative capacitance transistor of the write unit are asymmetrically arranged in the SRAM circuit. At least two negative capacitance transistors are used to form an asymmetric structure, which not only strengthens the read and write currents through the negative capacitance transistors, but also uses an asymmetric structure to ensure that each pair of negative capacitance transistors will not affect each other, thereby avoiding the situation where the read and write capabilities of one side are enhanced and the other side is weakened. Without increasing the complexity of the circuit, the read and write capabilities of the SRAM circuit are effectively improved.

[0053] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A SRAM circuit, characterized in that: include: A read unit and a write unit, where: The read unit is connected to the write unit, includes at least one negative capacitance transistor, and is suitable for reading data; The write unit is connected to the read unit, includes at least one negative capacitance transistor, and is suitable for writing data; Wherein, at least one negative capacitance transistor of the read unit and at least one negative capacitance transistor of the write unit are asymmetrically arranged in the SRAM circuit; The read unit includes a first negative capacitance transistor and a first NMOS tube; the write unit includes a second negative capacitance transistor and a first PMOS tube; the SRAM circuit also includes: a second PMOS tube and a second NMOS tube; The first NMOS tube has a source connected to the first bit line, a gate connected to the word line, and a drain connected to the drain of the second PMOS tube; the first negative capacitance transistor has a gate connected to the gate of the second PMOS tube, the drain of the first PMOS tube and the source of the second NMOS tube, and the drain is grounded; the gate of the second negative capacitance transistor is connected to the word line, and the drain is connected to the second bit line; the first PMOS tube has a source connected to the power supply voltage, and a gate connected to the gate of the second NMOS tube, the drain of the second PMOS tube and the source of the first negative capacitance transistor; the second NMOS tube has a drain connected to the ground.

2. The SRAM circuit according to claim 1, wherein: At least one negative capacitance transistor in the read unit is adapted to pull down a first bit line voltage.

3. The SRAM circuit according to claim 1, wherein: At least one negative capacitance transistor in the write unit is adapted to control conduction or disconnection between the second bit line and the write unit.

4. The SRAM circuit according to claim 1, wherein: The SRAM circuit is a 6T SRAM circuit.

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