Methods and devices related to radio frequency devices

Abstract

Embodiments of the present disclosure relate to methods and devices related to radio frequency devices. Methods and devices related to RF devices are discussed. To manufacture the device, the RF device is formed on a first side of a semiconductor substrate, and the second side is thinned and subsequently processed.

Description

Technical Field

[0001] The present application relates to a method for manufacturing a device comprising one or more radio frequency devices and to a corresponding device. Background Art

[0002] Radio frequency devices are used, for example, in communication circuits. An example of a radio frequency device is a transistor-based radio frequency switch, which in some embodiments can be formed by coupling multiple transistors in series. As used herein, radio frequency can refer to frequencies above 100 kHz, particularly in the megahertz range or gigahertz range. For example, for the upcoming 5G (fifth generation) mobile communication standard, frequencies up to 300 GHz will be used.

[0003] For such RF devices, regulatory requirements are becoming increasingly stringent. For example, reduced insertion loss and improved linearity may be required. Summary of the Invention

[0004] There is provided a method according to claim 1 and an apparatus according to claim 15. The dependent claims define further embodiments.

[0005] According to an embodiment, a method is provided, comprising:

[0006] providing a semiconductor substrate having a first side and a second side opposite to the first side,

[0007] forming at least one radio frequency device at the first side, for example on and / or in the first side,

[0008] thinning the semiconductor substrate from the second side, and

[0009] The second side of the thinned semiconductor substrate is processed to reduce leakage current or improve radio frequency linearity of at least one radio frequency device.

[0010] According to another embodiment, there is provided an apparatus comprising:

[0011] A semiconductor substrate having a first side and a second side opposite to the first side, wherein the thickness of the semiconductor substrate is 70 μm or less,

[0012] at least one radio frequency device formed on a first side of the semiconductor substrate; and

[0013] a processed region at the second side of the semiconductor substrate, wherein the processed region comprises one or more of:

[0014] - ion implantation layer;

[0015] - defect-rich layer;

[0016] - a doped layer having a doping concentration that is higher than the doping concentration in a region adjacent to the doped layer;

[0017] - an aluminum oxide layer; and

[0018] - Etched area.

[0019] The above summary is intended merely to give a brief overview of some embodiments and should not be construed as limiting in any way, as other embodiments may include other features besides those explicitly mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a flow chart illustrating a method according to an embodiment.

[0021] Figures 2A to 2F are cross-sectional views of an apparatus at various stages of processing according to an embodiment.

[0022] Figure 3 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figures 6A to 6C are cross-sectional views of apparatus at various stages of processing according to further embodiments.

[0023] Figures 7 to 9 are diagrams for explaining effects of some embodiments.

[0024] Figures 10 and 11 A comparison of properties of a device according to an embodiment with a conventional device is shown. DETAILED DESCRIPTION

[0025] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. It should be understood that these embodiments are given for illustrative purposes and should not be construed as limiting in any way. For example, although an embodiment may be described as including multiple features, elements, process steps, etc., in other embodiments, some of these features, elements, or process steps may be omitted or replaced by alternative features, elements, or process steps. In addition to the features, elements, or process steps explicitly shown and described, other features, elements, or process steps may be provided, for example, features, elements, or process steps used in conventional radio frequency devices and their manufacture.

[0026] Figure 1 A method for manufacturing a device according to some embodiments is shown. Figures 2A to 2F To describe Figure 1 The method, which shows the Figure 1 The various processing stages of the device in the example implementation of the method, reference Figure 3 To Figure 6 (Figure 5 includes Figure 5A and Figure 5B , and Figure 6 includes Figures 6A to 6C ) is used to explain the variations and optional parts of the method, and to refer to Figures 7 to 9 , which is used to explain various effects that can be obtained in some embodiments. However, it should be noted that Figure 1 The method and the devices shown in FIG. 2 to FIG. 6 can also be implemented independently of each other, and the joint description is only used to provide a better understanding.

[0027] At 10, Figure 1 The method includes providing a semiconductor substrate. For example, the substrate can be a complete semiconductor wafer. As an example, Figure 2A A silicon wafer 20 is provided as a substrate. In other embodiments, other semiconductor wafers may be used, for example wafers based on III-V semiconductors (eg gallium arsenide).

[0028] The semiconductor substrate has a first side and a second side opposite to the first side. Figure 2A The middle silicon wafer 20 has a first side 20A and a second side 20B.

[0029] At 11, the method includes forming a radio frequency (RF) device at a first side of a substrate. "At" the first side means that the RF device can be formed in the first side of the substrate by depositing one or more layers on the substrate and processing these layers, or by both of the aforementioned processes. Any conventional technique such as ion implantation, photolithography, etching, metal deposition, oxide deposition, semiconductor layer deposition can be used to form the RF device. In the sense used in this document, "RF device" can refer to one or more devices, or can refer to a device that includes multiple different components. For example, an RF switch can be formed as a series connection of multiple RF transistors. As an example, in Figure 2, an active RF device 22 is formed in the first side 20A of the silicon wafer 20 and in the device layer 21 on the first side 20A. At Figure 2A In the example shown, device 22 is a field effect transistor. In other embodiments, other devices, both active and passive, may be formed.

[0030] To facilitate subsequent processing, the silicon wafer can then be mounted on a handling carrier at a first side. For example, a glass carrier can be used to which the silicon wafer is mounted using, for example, an adhesive. Figure 2B An example is shown in FIG, wherein a silicon wafer 20 (together with devices 22 and layer 21 ) is mounted at its first side to a handling carrier 23 .

[0031] Next, in Figure 1At 12, the method includes thinning the substrate from the second side of the substrate. To thin the substrate, any suitable technique may be used, such as mechanical grinding or chemical mechanical polishing (CMP). The thickness of the substrate after thinning may be between 5 μm and 70 μm, for example, about 25 μm. Figure 2C An example is shown in FIG, wherein the substrate 20 is moved from the second side to 20B (see Figure 2A ) thinning, that is, thinning from the side opposite to the side where the active device 22 is formed.

[0032] In some embodiments, thinning the substrate generates defects at the second side of the silicon substrate that may adversely affect the operation of the RF devices formed at the first side, for example due to leakage currents, free carriers, or increased conductivity. Figure 1 In an embodiment, to mitigate this adverse effect, the second side of the thinned substrate is processed at 13 to form a processed region at the second side. In an embodiment, the processed region may extend substantially over the entire second side, such as over at least 80% or at least 90% of the second side.

[0033] exist Figure 2D , ion implantation is performed as indicated by arrow 25 to form a processed region 24. In general, a processed region may be formed in the silicon substrate 20 by modifying a region of the silicon substrate 20 on the second side (e.g., by ion implantation as described above), or may be formed by depositing one or more additional layers on the second side of the substrate 20.

[0034] There are various possibilities for such treatment at 13. In some embodiments, the treatment forms (deep) defects at the second side. This can be achieved, for example, by ion implantation with appropriate dose and energy or by some kind of etching process like reactive ion etching (e.g. Bosch etching). In particular, in this way deep defects can be formed in the semiconductor material (in Figure 2D In the example of silicon, the Fermi level is formed in the middle or near the middle of the band gap of the substrate, which fixes the Fermi level in the middle or near the middle of the band gap. In other embodiments, the generated defect levels can also be distributed almost continuously across the band gap, so that the Fermi level is approximately in the middle of the band gap. This sets the shallow defects formed by thinning (i.e., defects with energy levels close to the band gap) to a defined state and mitigates the adverse effects of these shallow defects. In some embodiments, this can lead to a reduction in charge carriers and, therefore, high-ohmic behavior of the substrate at the second side.

[0035] In other embodiments, the treated region may be a doped region for generating charge carriers, such as an n-doped region or a p-doped region. For example, the doped region may be formed by ion implantation (e.g., by implanting phosphorus or arsenic into silicon for n-type doping or boron for p-type doping) or by depositing a doped layer. In other embodiments, a layer such as an aluminum oxide layer may be deposited on the second side. Reference will now be made to Figures 7 to 9 To explain in some embodiments Figure 1 The effect of 12 thinning points and Figure 1 The effect of the 13 treatments.

[0036] In some embodiments, the treated region may be used to reduce the electric field at or near the second side.

[0037] Figure 7 A field effect transistor 70 is shown as an example of an RF device to be explained below. Figure 7 , a field effect transistor 70 is shown as including a drain region 72 formed in a substrate (e.g., a silicon wafer 20), a source region 73 formed in the substrate, and a gate electrode 71. The gate electrode 71 is coupled to a gate resistor 74. As is known in the art, the transistor 70 is controlled by applying a gate-source voltage. To form an RF switch as described above, a plurality of such transistors can be coupled in series. A plurality of transistors is also referred to as a transistor stack hereinafter. For example, approximately 30 transistors can be coupled in series. In operation, an RF signal 75 is then applied to the transistors. Typical source-drain voltages in this application can be in the range of 1V to 3V per transistor, or in other words, the amplitude of the RF signal 75 applied to each transistor can be on the order of 1V to 3V, which substantially corresponds to the total voltage applied to the transistors in series divided by the number of transistors.

[0038] When the implementation is as Figure 7 The transistor 70 shown in FIG. 1 forms various parasitic capacitances according to the embodiment. As an example, Figure 7 The drain-gate capacitance 76, gate-source capacitance 77, drain-substrate capacitance 78, and source-substrate capacitance 79 are shown. These capacitances can cause an uneven distribution of the total voltage across the transistors, resulting in a higher voltage drop across the last transistor of the transistor stack. This last transistor has a specific breakdown voltage. When the voltage drop across the last transistor exceeds its breakdown voltage, applying a higher voltage will cause first a breakdown of this last transistor, and subsequently a breakdown of the entire transistor stack. Ultimately, the transistor stack can maintain a lower total maximum RF voltage amplitude than the ideal voltage distribution. This is in Figure 8 Shown in.

[0039] Figure 8The voltage drop U across a plurality of transistors n of a transistor stack is shown. In an ideal case, as shown by curve 80, the RF voltage across the stacked transistors is uniformly distributed, i.e., with each "added" transistor, the voltage drop U increases by the same amount ΔU. In practice, by Figure 7 The capacitances shown or other effects, in particular substrate capacitances 78, 79, introduce an uneven voltage distribution, as shown by curve 81. On the other hand, such an uneven voltage distribution requires the transistors to be constructed to tolerate a higher voltage, since a higher voltage drop occurs across some transistors than in the uniform case.

[0040] By thinning the substrate, the uneven voltage distribution can be reduced. The uneven voltage distribution is at least partially caused by the substrate capacitance 78, substrate capacitance 79. Figure 9 A transistor 90A and a substrate contact 90B are shown formed on a thinned substrate 91. The transistor 90A may be formed as shown for Figure 7 Transistor 90A may be implemented as explained for transistor 70. Transistor 90A may be part of a series connection of a larger number of transistors, such as a transistor stack (eg, about 30 transistors), as explained above.

[0041] In operation, field lines 92 are present, which for a thinned substrate appear to a large extent outside the substrate, thereby reducing capacitance 78, capacitance 79. Semiconductor materials such as silicon have a relatively high dielectric constant, for example the dielectric constant of silicon is about 12. By thinning the substrate, or by replacing the substrate with a carrier substrate having a lower dielectric constant, as will be explained further below, capacitance 78, capacitance 79 can be reduced and thus in some embodiments the uneven voltage distribution can be reduced. However, as mentioned, the leakage current is increased by thinning, for example due to defects caused by thinning. Such defects at the second side of the substrate may lead to increased leakage current, which leads to an undesirably higher current consumption of the entire chip. Defects may also lead to a higher nonlinear behavior. By Figure 1 2 , these leakage currents can be significantly reduced in some embodiments, thereby improving device performance and mitigating the adverse effects of thinning.

[0042] Return to Figure 1At 14, the method optionally includes forming a heat sink layer on the second side. The heat sink layer is a layer having a thermal conductivity sufficient to disperse the heat generated by the RF device in operation. The thickness of the heat sink layer can be between 1 μm and 10 μm, but is not limited thereto. Suitable materials include aluminum nitride (AlN), aluminum oxide (Al2O3), sapphire, silicon carbide (SiC), carbon or a diamond-like layer, such as a diamond-like coating or diamond-like carbon. In some embodiments, the heat sink layer, in addition to its heat dissipation function, can also prevent unwanted ions from diffusing from outside the device to the active area, especially in a specific area where the RF device is formed. As an example, in Figure 3 A heat spreader layer 30 provided on the processed area 24 is shown in FIG.

[0043] Optionally, at 15, Figure 1 The method may include further processing of the second side. It should be noted that, if provided, the heat spreader layer at 14 may also be formed after this further processing. Such further processing may include ion implantation and / or etching between the different devices.

[0044] Examples of such selective ion implantation are given by Figure 5A Indicated by arrows 51 in FIG. Here, two RF devices 22 are shown. A photoresist 50 is provided and structured to form a mask for ion implantation so that an implantation region 52 is formed only between the devices 22. The implantation region 52 can extend through the entire substrate 20 and reach the layers of the devices 22. The ions used for ion implantation can include helium (He) ions, hydrogen (H) ions, or argon (Ar) ions. Through such ion implantation, the charge carrier lifetime in the implantation region 52 can be reduced, which increases the DC (direct current) isolation between the devices 22 and / or can enhance the RF performance of passive devices such as coils or couplers.

[0045] Additionally or alternatively, further processing at 15 may include thinning the oxide between devices. Figure 6A 5 , on the one hand, the ion implantation indicated by arrow 61, as already explained, is performed, here using photoresist 60 and forming implanted regions 62 which substantially correspond to regions 52 of FIG5 . Additionally, etching of the silicon is performed so that the silicon of silicon wafer 20 is thinned between devices 22. In some embodiments, reactive ion etching (RIE) can be used for this thinning.

[0046] Return to Figure 1 At 16, the method may include further processing of the substrate. In an embodiment, the further processing may include mounting a support substrate to the semiconductor substrate. Figure 2F An example is shown in FIG, wherein a support substrate 26 is mounted to the substrate. The support substrate may be made of a material having a lower dielectric constant than silicon (see above for Figure 9 ). In an embodiment, a material with good thermal conductivity, such as aluminum nitride, aluminum oxide, sapphire or silicon carbide, can be selected for the support substrate, for example in an embodiment where a heat dissipation layer is not provided. In other embodiments, a glass substrate can be used. In some embodiments, the dielectric constant of the support substrate can be below 8, for example, about 4 in the case of glass. In addition, at 16, the disposal carrier 23 (if provided) is removed in an embodiment. The support substrate can be mounted to the substrate using an adhesive bonding technique (e.g., a BCB layer and / or a SU-8 layer) or using a glue layer.

[0047] For example, in the embodiment where additional etching is performed at 15, glue may be used to fill the space created when the support substrate is mounted to the semiconductor substrate. Figure 6B An example is shown in FIG, where the holes are filled with glue 63. The glue may also extend in the layer to provide a bond between the substrate 20 and the support substrate 25, as for Figure 6C As shown in the glue layer 64 in.

[0048] Other processing at 16 may include conventional semiconductor device processing, such as testing, dicing, or packaging, which are also used in conventional device manufacturing processes and will not be described in further detail here.

[0049] In the above examples, especially Figures 2A to 2F In the device shown in , a simple semiconductor wafer such as a simple silicon wafer is used as the semiconductor substrate. In other embodiments, a substrate with a buried insulating layer can be used as the semiconductor substrate, in particular a silicon-on-insulator (SOI) wafer. The processing of such a substrate is essentially as explained above. To give an example, Figure 4 A device according to one embodiment is shown, which substantially corresponds to Figure 2F , wherein a silicon-on-insulator wafer 40 is used instead of the silicon wafer 20, the silicon wafer 40 including a top silicon layer 40B at a first side 40A where the device 22 is formed, a bottom silicon layer 40D at a second side 40E, and a buried oxide layer 40C between the silicon layers 40B and 40D. Figure 1 The thinning at 12 is performed by thinning the bottom silicon layer 40D. Unlike some conventional methods in which the silicon layer 40D is completely removed, in an embodiment, the silicon layer 40D maintains a certain thickness, for example, a thickness between 5 μm and 70 μm.

[0050] The processed region 24 is then formed at the bottom silicon layer 40D. In some embodiments, the silicon layer 40D then serves as a heat spreader layer, but an additional heat spreader layer as described above may also be provided (see Figure 1 Otherwise, when a semiconductor substrate having a buried isolation layer such as an SOI substrate is used, the following steps may be performed as described in reference to Figure 1 The processing explained includes the variations described above.

[0051] For example, additional ion implantations between devices may be performed, which may extend through the buried oxide. Figure 5B An example is shown where, in addition to implantation layers 52 being formed between devices 22, devices 22 may be formed in SOI wafer 40 extending through the buried oxide, corresponding to Figure 5A Likewise, additional removal of material, for example by reference to Figure 6A The explained etching can also be performed with such a wafer. Combinations of the variations are also possible.

[0052] To illustrate the effects of some embodiments, in particular Figure 1 The 13 treatments in Figure 10 as well as Figure 11 Best performance results for some wafers are shown. Figure 10 The second harmonic H2 in dBm is shown relative to the power pin (Pin), also in dBm. Curve 100 shows the result of a thinned silicon wafer (thinned at 12) without treatment at 13. Curve 101 shows the result of treatment at 13 by boron implantation, curve 102 shows the result for argon implantation, and curve 103 shows the result for Bosch etching of the second side. It can be seen that second harmonic generation is reduced by various treatments, thereby increasing linearity.

[0053] exist Figure 11 In FIG. 1 , the substrate current I_substrate in amperes (A) is plotted against the power pins. The substrate current essentially corresponds to an undesirable increase in the total current consumption of the chip. Curve 110 shows the result of thinning without treatment (thinning at 12 without Figure 1 Curve 111 shows the result of the treatment by boron implantation to the second side, curve 112 shows the result of the treatment by argon implantation, and curve 113 shows the result of the treatment by Bosch etching at 13. It can be seen that the current is significantly reduced by various treatments. It should be noted that Figure 10 and Figure 11 The curves in are merely examples for a particular implementation, and the curves and results may vary depending on the equipment, processes, and materials used.

[0054] Various embodiments are defined by the following embodiments:

[0055] Example 1. A method comprising:

[0056] providing a semiconductor substrate having a first side and a second side opposite to the first side,

[0057] forming at least one radio frequency device on the first side;

[0058] thinning the semiconductor substrate from the second side; and

[0059] The second side of the thinned semiconductor substrate is processed to reduce leakage current or improve radio frequency linearity of at least one radio frequency device.

[0060] Example 2. The method of Example 1, wherein processing the second side of the thinned semiconductor substrate to reduce leakage current or improve radio frequency linearity comprises reducing a density of free charge carriers at the second side of the thinned semiconductor substrate.

[0061] Example 3. The method of example 1 or 2, wherein processing the second side of the thinned semiconductor substrate to reduce leakage current or improve radio frequency linearity comprises providing charge carriers at the second side of the thinned semiconductor substrate.

[0062] Example 4. The method of Example 3, wherein providing the charge carriers comprises introducing a dopant into the second side of the thinned semiconductor substrate.

[0063] Example 5. The method of example 3 or 4, wherein providing the carrier includes forming a doping layer on the second side of the thinned semiconductor substrate.

[0064] Example 6. The method of any one of Examples 1 to 5, wherein processing the second side of the thinned semiconductor substrate to reduce leakage current or improve radio frequency linearity comprises introducing defects at the second side of the semiconductor substrate.

[0065] Example 7. The method of any of Examples 1 to 6, wherein processing the second side of the thinned semiconductor substrate to reduce leakage current or improve radio frequency linearity comprises implanting ions into the second side of the thinned semiconductor substrate.

[0066] Example 8. The method of Example 7, wherein the ions include at least one ion selected from the group consisting of argon ions and boron ions.

[0067] Example 9. The method of any of Examples 1 to 8, wherein processing the second side of the thinned semiconductor substrate to reduce leakage current or improve radio frequency linearity additionally provides ion gettering at the second side of the thinned semiconductor substrate.

[0068] Example 10. The method of any of Examples 1 to 9, wherein processing the second side of the thinned semiconductor substrate to reduce leakage current or improve radio frequency linearity comprises performing a Bosch etch.

[0069] Example 11. The method of any one of Examples 1 to 10, wherein processing the second side of the thinned semiconductor substrate to reduce leakage current or improve radio frequency linearity comprises forming an aluminum oxide layer on the second side of the thinned semiconductor substrate.

[0070] Example 12. The method of any one of Examples 1 to 11, further comprising forming a heat dissipation layer on the second side of the thinned semiconductor substrate.

[0071] Example 13. The method of any one of Examples 1 to 12, wherein forming at least one radio frequency device comprises forming at least two radio frequency devices, wherein the method further comprises:

[0072] At least one of ion implantation or etching is performed from the second side of the thinned semiconductor substrate, the ion implantation or etching being confined to a region between the at least two radio frequency devices.

[0073] Example 14. The method of Example 13, wherein the ion implantation extends into the device layer on the first side of the thinned semiconductor substrate.

[0074] Example 15. The method of any of Examples 1 to 14, wherein thinning the semiconductor substrate from the second side includes thinning the semiconductor substrate to a thickness between 5 μm and 75 μm.

[0075] Example 16. The method of any one of Examples 1 to 15, wherein the semiconductor substrate includes a first semiconductor layer on a first side, a second semiconductor layer on a second side, and an insulating layer between the first semiconductor layer and the second semiconductor layer, wherein processing the thinned second side of the semiconductor substrate to improve radio frequency linearity includes processing the thinned second semiconductor layer.

[0076] Example 17. The method of Example 16, wherein the thinned second semiconductor layer has a thickness between 5 μm and 70 μm.

[0077] Example 18. The method according to any one of embodiments 1 to 17, further comprising mounting a support substrate at the second side.

[0078] Example 19. A device comprising:

[0079] A semiconductor substrate having a first side and a second side opposite to the first side, wherein the thickness of the semiconductor substrate is 70 μm or less,

[0080] at least one radio frequency device formed at a first side of the semiconductor substrate; and

[0081] a processed region at the second side of the semiconductor substrate, wherein the processed region comprises one or more of:

[0082] - ion implantation layer;

[0083] - defect-rich layer;

[0084] - a doped layer having a doping concentration that is higher than the doping concentration in regions of adjacent doped layers;

[0085] - an aluminum oxide layer; and

[0086] - Reactive ion etched areas.

[0087] Example 20. The apparatus of embodiment 19, wherein the processed region is configured to additionally provide ion gettering at the second side of the semiconductor substrate.

[0088] Example 21. The apparatus of Example 19 or 20, further comprising a heat dissipation layer on the second side of the semiconductor substrate.

[0089] Example 22. The device of any one of Examples 19 to 21, wherein the at least one radio frequency device includes at least two radio frequency devices, wherein the device further comprises:

[0090] At least one of the ion implantation region or the etching region on the second side of the semiconductor substrate is limited to a region between at least two radio frequency devices.

[0091] Example 23. The device of Example 22, wherein the ion implantation region extends into the device layer on the first side of the semiconductor substrate.

[0092] Example 24. The device of any of Embodiments 19 to 23, wherein the semiconductor substrate comprises a first semiconductor layer on the first side, a second semiconductor layer on the second side, and an insulating layer between the first and second semiconductor layers, wherein the second semiconductor layer has a thickness between 5 μm and 70 μm.

[0093] Example 25. The apparatus of any one of embodiments 19 to 24, further comprising a support substrate mounted at the second side.

[0094] Example 26. The apparatus of any of Examples 19 to 25, wherein the processed region is adapted to pin the Fermi level at or near the middle of a bandgap of the semiconductor substrate, for example, within 0.1 eV or 0.2 eV of the middle of the bandgap.

[0095] Example 27. The apparatus of any one of Examples 19 to 26, wherein the reactive ion etch region is an etch region.

[0096] Example 28. The apparatus of any of Examples 19 to 27, wherein the processed region extends over substantially the entire second side of the semiconductor substrate (eg, over at least 80% or at least 90% of the second side).

[0097] Example 29. The apparatus of any of Examples 19 to 28, wherein the treatment layer is configured to reduce a density of free charge carriers at the second side of the thinned semiconductor substrate.

[0098] Example 30. The device of any one of Examples 19 to 29, manufactured by the method of any one of Examples 1 to 18.

[0099] Although specific embodiments have been shown and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A method comprising: Providing a semiconductor substrate (20; 40), the semiconductor substrate (20; 40) having a first side (20A; 40A) and a second side (20B; 40E)， forming at least one radio frequency device (22) at the first side (20A; 40A); From the second side (20B; 40B) thinning the semiconductor substrate (20; 40); and processing the second side (20B; 40) of the thinned semiconductor substrate (20; 40); 40B) to reduce leakage current or improve radio frequency linearity of the at least one radio frequency device (22), Wherein processing the second side (20B; 40B) of the thinned semiconductor substrate (20; 40) to reduce leakage current or improve radio frequency linearity comprises performing a Bosch etch.

2. The method of claim 1 , wherein processing the second side ( 20B; 40B) of the thinned semiconductor substrate to reduce leakage current or improve radio frequency linearity comprises reducing a density of free charge carriers at the second side ( 20B; 40B) of the thinned semiconductor substrate.

3. The method of claim 1 or 2, wherein processing the second side (20B; 40B) of the thinned semiconductor substrate to reduce leakage current or improve radio frequency linearity comprises providing charge carriers at the second side (20B; 40B) of the thinned semiconductor substrate (20; 40).

4. The method of claim 3, wherein providing charge carriers comprises introducing dopants in the second side (20B; 40B) of the thinned semiconductor substrate (20; 40).

5. The method according to claim 3 or 4, wherein providing charge carriers comprises forming a doping layer on the second side (20B; 40B) of the thinned semiconductor substrate (20; 40).

6. The method according to any one of claims 1 to 5, wherein processing the second side (20B; 40B) of the thinned semiconductor substrate (20; 40) to reduce leakage current or improve radio frequency linearity comprises introducing defects at the second side (20B; 40B) of the semiconductor substrate.

7. The method according to any one of claims 1 to 6, wherein processing the second side (20B; 40B) of the thinned semiconductor substrate (20; 40) to reduce leakage current or improve radio frequency linearity additionally provides ion removal at the second side (20B; 40B) of the thinned semiconductor substrate (20; 40).

8. The method according to any one of claims 1 to 7, further comprising forming a heat dissipation layer (30) on the second side (20B; 40B) of the thinned semiconductor substrate (20; 40).

9. A method comprising: Providing a semiconductor substrate (20; 40), the semiconductor substrate (20; 40) having a first side (20A; 40A) and a second side (20B; 40E)， forming at least one radio frequency device (22) at the first side (20A; 40A); From the second side (20B; 40B) thinning the semiconductor substrate (20; 40); and processing the thinned semiconductor substrate (20; 40) of the second side (20B; 40B) to reduce leakage current or improve radio frequency linearity of the at least one radio frequency device (22), comprising performing ion implantation or Bosch etching; as well as An aluminum oxide layer is formed on the second side (20B; 40B) of the thinned semiconductor substrate (20; 40).

10. A method comprising: Providing a semiconductor substrate (20; 40), the semiconductor substrate (20; 40) having a first side (20A; 40A) and a second side (20B; 40E)， forming at least two radio frequency devices (22) at the first side (20A; 40A); From the second side (20B; 40B) thinning the semiconductor substrate (20; 40); and processing the second side (20B; 40) of the thinned semiconductor substrate (20; 40); 40B), to reduce leakage current or improve radio frequency linearity of the at least two radio frequency devices (22), comprising: thinning the second side (20B; 40B) performing at least one of ion implantation (51; 61) or etching, said ion implantation or said etching being confined to a region between said at least two radio frequency devices (22).

11. The method of claim 10, wherein the ion implantation (51) extends into a device layer (21) on the first side (20A; 40A) of the thinned semiconductor substrate (20; 40).

12. A method comprising: Providing a semiconductor substrate (20; 40), the semiconductor substrate (20; 40) having a first side (20A; 40A) and a second side (20B; 40E)， forming at least one radio frequency device (22) at the first side (20A; 40A); From the second side (20B; 40B) thinning the semiconductor substrate (20; 40); and processing the second side (20B; 40B) of the thinned semiconductor substrate (20; 40) to reduce leakage current or improve radio frequency linearity of the at least one radio frequency device (22), The semiconductor substrate (40) includes a first semiconductor layer (40B) on the first side (40A), a second semiconductor layer (40D) on the second side (40E), and an insulating layer (40C) between the first semiconductor layer (40B) and the second semiconductor layer (40D), wherein processing the thinned second side (20B; 40B) of the semiconductor substrate (20; 40) to reduce leakage current or improve radio frequency linearity includes processing the thinned second semiconductor layer (40D) using ion implantation or Bosch etching.

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