Semiconductor module device

Abstract

The present invention discloses a semiconductor module device comprising: a housing; a first semiconductor substrate disposed within the housing; a second semiconductor substrate disposed within the housing; a first plurality of controllable semiconductor elements; and a second plurality of controllable semiconductor elements. During operation of the semiconductor module device, each of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, wherein the switching losses are greater than the conduction losses. Furthermore, during operation of the semiconductor module device, each of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, wherein the conduction losses are greater than the switching losses. At least a first subset of the first plurality of controllable semiconductor elements is disposed on the first semiconductor substrate, and at least a first subset of the second plurality of controllable semiconductor elements is disposed on the second semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor module arrangement comprising controllable semiconductor elements. Background Art

[0002] Semiconductor devices (e.g., power semiconductor modules) are widely used in automotive, industrial, and consumer electronics applications to drive loads, convert power, and the like. For example, such semiconductor devices may include an ANPC (Active Neutral Point Clamped) topology. The ANPC topology includes several controllable semiconductor elements, each of which has a control electrode (e.g., a gate electrode or a base electrode) and a load path formed between a first load electrode (e.g., a source electrode or an emitter electrode) and a second load electrode (e.g., a drain electrode or a collector electrode).

[0003] There is often a need for semiconductor module arrangements having highly symmetrical, low-inductance commutation paths. Summary of the Invention

[0004] A semiconductor module arrangement includes: a housing; a first semiconductor substrate disposed within the housing; a second semiconductor substrate disposed within the housing; a first plurality of controllable semiconductor elements; and a second plurality of controllable semiconductor elements. During operation of the semiconductor module arrangement, each of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, wherein the switching losses are greater than the conduction losses. During operation of the semiconductor module arrangement, each of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, wherein the conduction losses are greater than the switching losses. At least a first subset of the first plurality of controllable semiconductor elements is disposed on the first semiconductor substrate, and at least a first subset of the second plurality of controllable semiconductor elements is disposed on the second semiconductor substrate.

[0005] Another semiconductor module arrangement includes: a housing; a first semiconductor substrate disposed within the housing; a second semiconductor substrate disposed within the housing; a first plurality of controllable semiconductor elements; and a second plurality of controllable semiconductor elements. Each controllable semiconductor element in the first plurality of controllable semiconductor elements has a maximum allowable temperature, wherein during operation of the semiconductor module arrangement, each controllable semiconductor element in the first plurality of controllable semiconductor elements reaches its maximum allowable temperature. Each controllable semiconductor element in the second plurality of controllable semiconductor elements has a maximum allowable temperature, wherein during operation of the semiconductor module arrangement, each controllable semiconductor element in the second plurality of controllable semiconductor elements does not reach its maximum allowable temperature. At least a first subset of the first plurality of controllable semiconductor elements is disposed on the first semiconductor substrate, and at least a first subset of the second plurality of controllable semiconductor elements is disposed on the second semiconductor substrate.

[0006] The present invention may be better understood with reference to the following drawings and description. The components in the drawings are not necessarily to scale, but emphasis is placed on illustrating the principles of the present invention. In the drawings, like reference numerals designate corresponding parts throughout the different views. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic cross-sectional view of a semiconductor module arrangement is shown.

[0008] Figure 2 is a circuit diagram of an exemplary semiconductor device.

[0009] Figure 3 is a circuit diagram of another exemplary semiconductor device.

[0010] Figure 4 is a circuit diagram of another exemplary semiconductor device.

[0011] Figure 5 is a top view of an exemplary semiconductor module arrangement.

[0012] Figure 6 is a top view of another exemplary semiconductor module arrangement. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings illustrate specific examples in which the present invention may be practiced. It should be understood that the features and principles described with respect to the various examples may be combined with one another unless otherwise specifically noted. In the specification and in the claims, designations of certain elements as "first element," "second element," "third element," etc., should not be understood as enumerations. Rather, such designations are merely used to refer to different "elements." That is, for example, the presence of a "third element" does not require the presence of a "first element" and a "second element." As described herein, an electrical wire may be a single conductive element or comprise at least two individual conductive elements connected in series and / or parallel. The electrical wire may comprise metal and / or semiconductor material and may be permanently conductive (i.e., non-switchable). The electrical wire may have a resistivity that is independent of the direction of current flowing through the wire. The semiconductor body described herein may be made of (doped) semiconductor material and may be a semiconductor chip or included in a semiconductor chip. The semiconductor body has electrical connection pads and includes at least one semiconductor element having an electrode. The pads are electrically connected to the electrodes, which includes the pad being the electrode, and vice versa.

[0014] refer to Figure 1, schematically shows a cross-sectional view of a power semiconductor module arrangement 100. The power semiconductor module arrangement 100 includes a housing 17 and a semiconductor substrate 10. The semiconductor substrate 10 includes a dielectric insulating layer 11, a (structured) first metallization layer 111 attached to the dielectric insulating layer 11, and a (structured) second metallization layer 112 attached to the dielectric insulating layer 11. The dielectric insulating layer 11 is disposed between the first and second metallization layers 111, 112.

[0015] Each of the first and second metallization layers 111 , 112 may be composed of or include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; or any other metal or alloy that remains solid during operation of the power semiconductor module device. The semiconductor substrate 10 may be a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 11 is a ceramic (e.g., a thin ceramic layer). The ceramic may be composed of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 may be composed of or include one of the following materials: Al 2 O 3 , AlN, SiC, BeO, or Si 3 N 4 . For example, the substrate 10 may be a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. Furthermore, the substrate 10 may be an insulated metal substrate (IMS). For example, an insulated metal substrate typically includes a dielectric insulating layer 11 comprising a (filler) material (e.g., epoxy or polyimide). For example, the material of dielectric insulating layer 11 may be filled with ceramic particles. Such particles may include, for example, SiO, AlO, AlN, or BN, and may have a diameter between about 1 μm and about 50 μm. Substrate 10 may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulating layer 11. For example, non-ceramic dielectric insulating layer 11 may be composed of or include a cured resin.

[0016] The semiconductor substrate 10 is arranged in a housing 17. Figure 1 In the example shown in , the semiconductor substrate 10 is arranged on a base plate 12 forming the ground surface of the housing 17, while the housing 17 itself only includes side walls and a top cover. However, this is only an example. The housing 17 may also include a ground surface, and the semiconductor substrate 10 and the (optional) base plate 12 are arranged inside the housing 17. In some power semiconductor module devices 100, more than one semiconductor substrate 10 is arranged on a single base plate 12 or on the ground surface of the housing 17. The semiconductor substrate 10 itself may also form the ground surface of the housing 17. In such a case, the housing only includes side walls and a top cover, without a ground surface, and the base plate 12 can be omitted.

[0017] One or more semiconductor bodies 120 may be arranged on at least one semiconductor substrate 10. Each of the semiconductor bodies 120 arranged on the at least one semiconductor substrate 10 may include a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor), and / or any other suitable semiconductor element.

[0018] One or more semiconductor bodies 120 may form a semiconductor device on at least one semiconductor substrate 10. Figure 1 In FIG. 1 , only two semiconductor bodies 120 are shown by way of example. Figure 1 The second metallization layer 112 of the semiconductor substrate 10 is a continuous layer. Figure 1 In the example shown in , the first metallization layer 111 is a structured layer. "Structured layer" means that the first metallization layer 111 is not a continuous layer, but includes recesses between different sections of the layer. Figure 1 Such a recess is schematically shown in . In this example, the first metallization layer 111 comprises three different segments. However, this is only an example. Any other number of segments is possible. Different semiconductor bodies 120 can be mounted on the same segment or different segments of the first metallization layer 111. The different segments of the first metallization layer 111 may not have electrical connections or may be electrically connected to one or more other segments using, for example, bonding wires 13. For example, the electrical connection 13 may also include a connecting plate or a conductor track, to name just a few examples. One or more semiconductor bodies 120 may be electrically and mechanically connected to the semiconductor substrate 10 via a conductive connection layer 130. For example, such a conductive connection layer may be a solder layer, a conductive adhesive layer, or a sintered metal powder (e.g., sintered silver powder) layer.

[0019] According to other examples, the second metallization layer 112 may also be a structured layer. It is also possible to completely omit the second metallization layer 112. For example, the first metallization layer 111 may also generally be a continuous layer.

[0020] Figure 1The power semiconductor module device 100 shown in further includes a terminal element 14. The terminal element 14 is electrically connected to the first metallization layer 111 and provides an electrical connection between the interior and the exterior of the housing 17. The terminal element 14 may be electrically connected to the first metallization layer 111 with a first end, while a second end 141 of each of the terminal elements 14 protrudes out of the housing 17. The terminal elements 14 may be electrically contacted from the outside at their respective second ends 141. A first portion of the terminal element 14 may extend through the interior of the housing 17 in a vertical direction y. The vertical direction y is a direction perpendicular to the top surface of the semiconductor substrate 10, wherein the top surface of the semiconductor substrate 10 is the surface on which at least one semiconductor body 120 is mounted. However, Figure 1 The terminal elements 14 shown in FIG are merely examples. The terminal elements 14 may be implemented in any other manner and may be arranged anywhere within the housing 17. For example, one or more terminal elements 14 may be arranged close to or adjacent to a side wall of the housing 17. The terminal elements 14 may also protrude through the side wall of the housing 17 instead of protruding through the top cover.

[0021] The semiconductor bodies 120 may each include chip pad metallization (not specifically shown), for example, source, drain, emitter, collector, anode, cathode, or gate metallization. The chip pad metallization typically provides a contact surface for electrically connecting the semiconductor body 120. For example, the chip pad metallization may electrically contact the connection layer 130, the terminal element 14, or the electrical connection 13. For example, the chip pad metallization may be composed of or include a metal such as aluminum, copper, gold, or silver. For example, the electrical connection 13 and the terminal element 14 may also be composed of or include a metal such as copper, aluminum, gold, or silver.

[0022] The power semiconductor module arrangement 100 typically also includes a casting compound 15. For example, the casting compound 15 may consist of or include silicone gel, or may be a rigid molding compound. The casting compound 15 may at least partially fill the interior of the housing 17, thereby covering the components and electrical connections arranged on the semiconductor substrate 10. The terminal element 14 may be partially embedded in the casting compound 15. However, at least the second end 141 of the terminal element 14 is not covered by the casting compound 15 and protrudes from the casting compound 15 through the housing 17 to the outside of the housing 17. The casting compound 15 is configured to protect the components and electrical connections inside the power semiconductor module 100 (in particular inside the housing 17) from certain environmental conditions and mechanical damage.

[0023] As described above, two or more semiconductor bodies 120 may form a semiconductor device on at least one semiconductor substrate 10. Arranging the two or more semiconductor bodies 210 in a half-bridge arrangement is merely an example. For example, the semiconductor device may also include an ANPC (Active Neutral Point Clamped) topology. The ANPC topology includes several controllable semiconductor elements, each of which has a control electrode (e.g., a gate electrode or a base electrode) and a load path formed between a first load electrode (e.g., a source electrode or an emitter electrode) and a second load electrode (e.g., a drain electrode or a collector electrode).

[0024] Now refer to Figure 2 , schematically illustrating an exemplary semiconductor device. Figure 2 The semiconductor device may include an ANPC (Active Neutral Point Clamped) topology and may operate in the ANPC (Active Neutral Point Clamped) topology. Figure 2 The semiconductor device in the embodiment includes a first power supply node DC+ configured to be operably connected to a first potential. The semiconductor device also includes a second power supply node NP configured to be operably connected to a second potential. A third power supply node DC- is configured to be operably connected to a third potential. The first potential is positive relative to the second potential, and the third potential is negative relative to the second potential. The device also includes a first controllable semiconductor element T1 and a second controllable semiconductor element T2. Each of the first controllable semiconductor element T1 and the second controllable semiconductor element T2 includes a control electrode G1, G2 and a controllable load path between a first load electrode and a second load electrode. The load paths of the first controllable semiconductor element T1 and the second controllable semiconductor element T2 are coupled in series and are coupled between the first power supply node DC+ and the second power supply node NP.

[0025] The apparatus further includes a third controllable semiconductor element T3 and a fourth controllable semiconductor element T4. Each of the third controllable semiconductor element T3 and the fourth controllable semiconductor element T4 includes a control electrode G3, G4 and a controllable load path between a first load electrode and a second load electrode. The load paths of the third controllable semiconductor element T3 and the fourth controllable semiconductor element T4 are coupled in series and are coupled between a second power supply node NP and a third power supply node DC-.

[0026] The first controllable semiconductor element T1 and the second controllable semiconductor element T2 are connected to each other via a first common node P, and the third controllable semiconductor element T3 and the fourth controllable semiconductor element T4 are connected to each other via a second common node N.

[0027] The device also includes: a fifth controllable semiconductor element T5, which has a control electrode G5 and a controllable load path between two load electrodes, and the load path is operably connected between the first common node P and the output node OUT; and a sixth controllable semiconductor element T6, which has a control electrode G6 and a controllable load path between two load electrodes, and the load path is operably connected between the output node OUT and the second common node N.

[0028] Each of the controllable semiconductor elements T1, T2, T3, T4, T5, T6 may include one or more switching elements, each switching element having a control electrode and a controllable load path between a first load electrode and a second load electrode, the load paths of the switching elements of the controllable semiconductor elements being operably connected in parallel between nodes between which the corresponding controllable semiconductor elements are connected.

[0029] As above for Figure 1 As already described, each of the individual switching elements can be implemented as a separate semiconductor body 120. Figure 2 Each of the controllable semiconductor elements T1-T6 in the device can include at least one inherent freewheeling element F1, F2, F3, F4, F5, F6 (e.g., a body diode), which is electrically connected between the first load electrode and the second load electrode of the corresponding controllable semiconductor element T1-T6. If the controllable semiconductor elements T1-T6 include more than one individual switching element coupled in parallel, each of the individual switching elements can include an inherent freewheeling element. However, it is also possible for an external diode element to be coupled in parallel to each of the controllable semiconductor elements T1-T6. For example, each of such external diode elements can be implemented as a separate semiconductor body 120.

[0030] For example, if the topology is operated in a so-called ANPC1 topology (fifth controllable semiconductor element T5 is permanently on, output current and output voltage are both positive), then Figure 2 The current commutation path of the semiconductor arrangement generally extends through the first controllable semiconductor element T1 and the second freewheeling element F2. For example, if the topology is operated in a so-called ANPC1 topology (the sixth controllable semiconductor element T6 is permanently on, the output current and the output voltage are both negative), then Figure 2 Another current commutation path of the semiconductor arrangement typically extends through the fourth controllable semiconductor element T4 and the third freewheeling element F3.

[0031] For example, if the topology is operated in a so-called ANPC2 topology (the first controllable semiconductor element T1 is permanently on, the output current and the output voltage are both positive), then Figure 2The current commutation path of the semiconductor device generally extends through the fifth controllable semiconductor element T5, the third controllable semiconductor element T3 and the sixth freewheeling element F6. For example, if the topology is operated in a so-called ANPC2 topology (the fourth controllable semiconductor element T4 is permanently turned on, the output current and the output voltage are both negative), then Figure 2 Another current commutation path of the semiconductor arrangement typically extends through the sixth controllable semiconductor element T6, the second controllable semiconductor element T2 and the fifth freewheeling element F5.

[0032] Now refer to Figure 3 , schematically illustrating another exemplary semiconductor device. Figure 3 The semiconductor device may include an NPC1 (Neutral Point Clamped 1) topology and may be operated in an NPC1 (Neutral Point Clamped 1) topology. Figure 3 The semiconductor device in the embodiment includes a first power supply node DC+ configured to be operably connected to a first potential. The semiconductor device also includes a second power supply node NP configured to be operably connected to a second potential. A third power supply node DC- is configured to be operably connected to a third potential. The first potential is positive relative to the second potential, and the third potential is negative relative to the second potential. The device also includes a first controllable semiconductor element T1 and a second controllable semiconductor element T2. Each of the first controllable semiconductor element T1 and the second controllable semiconductor element T2 includes a control electrode G1, G2 and a controllable load path between a first load electrode and a second load electrode. The load paths of the first controllable semiconductor element T1 and the second controllable semiconductor element T2 are coupled in series and are coupled between the first power supply node DC+ and the output node OUT.

[0033] The apparatus further includes a third controllable semiconductor element T3 and a fourth controllable semiconductor element T4. Each of the third controllable semiconductor element T3 and the fourth controllable semiconductor element T4 includes a control electrode G3, G4 and a controllable load path between a first load electrode and a second load electrode. The load paths of the third controllable semiconductor element T3 and the fourth controllable semiconductor element T4 are coupled in series and are coupled between the output node OUT and a third power supply node DC-.

[0034] The first controllable semiconductor element T1 and the second controllable semiconductor element T2 are connected to each other via a first common node P, and the third controllable semiconductor element T3 and the fourth controllable semiconductor element T4 are connected to each other via a second common node N.

[0035] Each of the controllable semiconductor elements T1, T2, T3, T4 may include one or more switching elements, each switching element having a control electrode and a controllable load path between a first load electrode and a second load electrode, the load paths of the switching elements of the controllable semiconductor elements being operably connected in parallel between nodes between which the corresponding controllable semiconductor elements are connected.

[0036] As above for Figure 1 It has been described that each of the individual switching elements can be implemented as a separate semiconductor body 120 . Figure 3 Each of the controllable semiconductor elements T1-T4 in the device can include at least one inherent freewheeling element F1, F2, F3, F4 (e.g., a body diode), which is electrically connected between the first load electrode and the second load electrode of the corresponding controllable semiconductor element T1-T4. If the controllable semiconductor elements T1-T4 include more than one individual switching element coupled in parallel, each of the individual switching elements can include an inherent freewheeling element. However, it is also possible for an external diode element to be coupled in parallel to each of the controllable semiconductor elements T1-T4. Each of such external diode elements can be implemented as a separate semiconductor body 120.

[0037] The apparatus further includes a fifth diode element D5 operatively connected between the second power supply node NP and the first common node P, and a sixth diode element D6 operatively connected between the second common node N and the second power supply node NP.

[0038] exist Figure 3 In the device, a first current commutation path can extend from the first power supply node DC+ through the first controllable semiconductor element T1 and further through the fifth diode element D5 to the second power supply node NP, while the second controllable semiconductor element T2 is turned on (the output voltage and output current are both positive). A second current commutation path can extend from the third power supply node DC- through the fourth controllable semiconductor element T4 and the sixth diode element D6 to the second power supply node NP, while the third controllable semiconductor element T3 is turned on (the output voltage and output current are both negative).

[0039] Now refer to Figure 4 , schematically illustrating another exemplary semiconductor device. Figure 4 The semiconductor device may include an NPC2 (Neutral Point Clamped 2) topology and may be operated in an NPC2 (Neutral Point Clamped 2) topology. In particular, Figure 4 is a circuit diagram of an exemplary three-level NPC2 topology. Figure 4The NPC2 topology includes a half-bridge module 200 and a common collector module 220. For example, a typical NPC topology includes four controllable semiconductor elements T11, T12, T13, and T14 (e.g., IGBTs (insulated gate bipolar transistors), MOSFETs (metal oxide semiconductor field effect transistors), JFETs (junction field effect transistors), or HEMTs (high electron mobility transistors)), and four diode elements D11, D12, D13, and D14.

[0040] The half-bridge module 200 is configured to convert a DC voltage provided at the inputs DC+ and DC- of the half-bridge module 200 into an AC voltage provided at the output node OUT of the half-bridge module 200. The AC voltage can be provided to a load (not shown), for example, coupled to the output node OUT of the half-bridge module 200. The half-bridge module 200 is coupled between a first power supply node DC+, which is configured to be operatively coupled to a first potential, and a second power supply node DC-, which is configured to be operatively coupled to a second potential. The first potential can be a positive potential, and the second potential can be a negative potential, so that a DC voltage is provided via the first and second power supply nodes DC+ and DC-. The first and second power supply nodes DC+ and DC- form the inputs of the half-bridge module 200.

[0041] The half-bridge module 200 may include a high-side switch T11 (also referred to as a first controllable semiconductor element or a first switch) and a low-side switch T12 (also referred to as a second controllable semiconductor element or a second switch) coupled in series with each other and coupled between a first power supply node DC+ and a second power supply node DC-. The half-bridge module 200 may be configured to drive a load (not specifically shown) at its output node OUT. For example, the load may be an inductive load. The output node OUT is electrically connected to a common node between the high-side switch T11 and the low-side switch T12.

[0042] exist Figure 4 In the circuit arrangement of FIG. 1 , each controllable semiconductor element T11, T12 of the half-bridge module 200 is implemented as an IGBT (insulated gate bipolar transistor). Each of the controllable semiconductor elements T11, T12 may include an external freewheeling diode element D11, D12 coupled in parallel to the corresponding controllable semiconductor element T11, T12. According to another example, each of the controllable semiconductor elements T11, T12 includes two or more separate switching elements (not specifically shown) electrically coupled in parallel to each other.

[0043] Each of the first and second controllable semiconductor elements T11 and T12 includes a control electrode G11, G12 and a controllable load path between a first load electrode (e.g., an emitter electrode) and a second load electrode (e.g., a collector electrode). The load paths of the first and second controllable semiconductor elements T11 and T12 are coupled in series and are coupled between a first power supply node DC+ and a second power supply node DC-.

[0044] The common collector module 220 includes a third controllable semiconductor element T13, a fourth controllable semiconductor element T14, a third diode D13, and a fourth diode D14. Each of the third controllable semiconductor element T13 and the fourth controllable semiconductor element T14 includes a control electrode G13, G14 and a controllable load path between a first load electrode (e.g., an emitter electrode) and a second load electrode (e.g., a collector electrode). The load paths of the third controllable semiconductor element T13 and the fourth controllable semiconductor element T14 are coupled in series between a fourth neutral node M and an output node OUT. In this series connection of the third controllable semiconductor element T13 and the fourth controllable semiconductor element T14, the second load electrode (e.g., the collector electrode) of the third controllable semiconductor element T13 is coupled to the second load electrode (e.g., the collector electrode) of the fourth controllable semiconductor element T14. The first load electrode (e.g., the emitter electrode) of the third controllable semiconductor element T13 is coupled to the output node OUT, and the first load electrode (e.g., the emitter electrode) of the fourth controllable semiconductor element T14 is coupled to the fourth neutral node M. A third diode element D13 is coupled in parallel to the third controllable semiconductor element T13 between the output node OUT and the fourth controllable semiconductor element T14, wherein an anode of the third diode element D13 is coupled to the output node OUT and a cathode of the third diode element D13 is coupled to the second load electrode of the fourth controllable semiconductor element T14. A fourth diode element D14 is coupled in parallel to the fourth controllable semiconductor element T14 between the fourth neutral node M and the second load electrode of the third controllable semiconductor element T13, wherein an anode of the fourth diode element D14 is coupled to the fourth neutral node M and a cathode of the fourth diode element D14 is coupled to the second load electrode of the third controllable semiconductor element T13.

[0045] According to one example, each of the controllable semiconductor elements T13 , T14 of the common collector module 220 includes two or more separate switching elements (not specifically shown) electrically coupled in parallel to each other.

[0046] Figure 4The current commutation path of the semiconductor devices generally extends through both the half-bridge module 200 and the common collector module 220. Specifically, the commutation path can extend from the first power supply node DC+ through the first controllable semiconductor element T11, and further through the third controllable semiconductor element T13 and the fourth diode element D14 to the fourth neutral node M (the third controllable semiconductor element T13 is permanently on, and the output voltage and output current are both positive). The commutation path can also extend from the second power supply node DC- through the second controllable semiconductor element T12, and further through the third diode element D13 and the fourth controllable semiconductor element T14 to the fourth neutral node M (the fourth controllable semiconductor element T14 is permanently on, and the output voltage and output current are both negative).

[0047] In the above Figure 2 、 Figure 3 and Figure 4 In each of the semiconductor devices described above, each of the controllable semiconductor elements T1, T2, T3, T4, T5, T6, T11, T12, T13, and T14 can be a fast switching element or a slow switching element. A fast switching element is generally a switching element that can perform a switching operation (e.g., from an on state to an off state, or vice versa) at a certain speed. A threshold speed can be defined in this regard. If the switching speed of a switching element is faster than the threshold speed, it can be defined as a fast switching element. If the switching speed of a switching element is slower than the threshold speed, it can be defined as a slow switching element. For example, a switching element with a turn-on time of <100 ns (nanoseconds) and a turn-off time of <100 ns can be considered a fast switching device, and a switching element with a turn-on time of ≥100 ns (nanoseconds) and a turn-off time of ≥100 ns can be considered a slow switching device. Fast switching devices are generally more expensive than slow switching devices. However, the use of different types of controllable semiconductor elements (fast switching elements and slow switching elements) is merely an example. It is also possible to use the same type of controllable semiconductor elements for all controllable semiconductor elements T1, T2, T3, T4, T5, T6, T11, T12, T13, and T14, and it is also possible to use different types of control circuits for different controllable semiconductor elements T1, T2, T3, T4, T5, T6, T11, T12, T13, and T14. Depending on the corresponding control circuit, the controllable semiconductor elements exhibit different switching characteristics. That is, some controllable semiconductor elements can perform fast switching operations, while other controllable semiconductor elements can perform slow switching operations. The different switching characteristics of the controllable semiconductor elements can also be supported by means of different electromagnetic compatibility (EMC) filtering. Such EMC filtering can be implemented in the semiconductor substrate 10 or in the electrical connections (e.g., bond wires).

[0048] Generally, in the semiconductor devices described above and in other semiconductor devices, it is not necessary to implement all switching devices as fast switching devices. In many semiconductor devices, it is sufficient to implement only some of the switching devices as fast switching devices. By implementing at least some of the switching devices as slow switching devices, the overall cost of the power semiconductor module device can be reduced.

[0049] Typically, during operation, each switching device generates switching losses and conduction losses. According to one example, a switching element that generates more switching losses than conduction losses during operation can be implemented as a fast switching device. For example, any other switching device that generates more conduction losses than switching losses during operation can be implemented as a slow switching device.

[0050] For example, in Figure 2 In a semiconductor device of the type shown in FIG. 1 , in a so-called ANPC1 topology, the switching elements T1 , T2 , T3 and T4 can be implemented as fast switching elements, while the switching elements T5 and T6 can be implemented as slow switching elements. For example, if Figure 2 If the fifth switching element T5 of the semiconductor device is permanently turned on, then if the first switching element T1 and the second diode element D2 are conducting (the first diode element D1 and the second switching element T2 are not conducting), a positive output voltage and a positive output current can be provided at the output node OUT. If the sixth switching element T6 is permanently turned on, then if the fourth switching element T4 and the third diode element D3 are conducting (the fourth diode element D4 and the third switching element T3 are not conducting), a negative output voltage and a negative output current can be provided at the output node OUT. Since the fifth switching element T5 and the sixth switching element T6 are both permanently turned on for a long period of time, it is not necessary to implement them as fast switching elements.

[0051] According to another example (e.g., an ANPC2 topology), it is also possible to implement switching elements T1, T2, T3, and T4 as slow switching elements, and switching elements T5 and T6 as fast switching elements. If the first switching element T1 is permanently on, then if the fifth switching element T5, the third switching element T3, and the sixth diode element D6 are conductive, a positive voltage and a positive current are provided at the output node OUT. If the fourth switching element T4 is permanently on, then if the sixth switching element T6, the second switching element T2, and the fifth diode element D5 are conductive, a negative voltage and a negative current can be provided at the output node OUT. Since the first switching element T1 and the fourth switching element T4 are both permanently on for a certain period of time, it is not necessary to implement them as fast switching elements.

[0052] Each semiconductor device or topology typically includes a very unique implementation that can result in an optimized balance between switching and conduction losses. However, the semiconductor substrate on which the semiconductor body is mounted can also have an impact on the thermal and electrical properties of the respective semiconductor body. Therefore, the type of substrate selected can depend on the type of semiconductor body mounted on the substrate. However, as mentioned above, different semiconductor bodies in the same semiconductor device may have different requirements for the type of semiconductor substrate used.

[0053] Therefore, in Figure 5 In the example shown in FIG, a semiconductor module includes two different semiconductor substrates 101 and 102. Each of the first semiconductor substrate 101 and the second semiconductor substrate 102 may have a dielectric insulating layer 11 and a first metallization layer 111 mounted thereon, as described above for Figure 1 As already described. The first metallization layer 111 of the first semiconductor substrate 101 may be a structured metallization layer comprising two or more different individual segments. The same applies to the first metallization layer 111 of the second semiconductor substrate 102, which may also be a structured layer comprising two or more individual segments. The first semiconductor substrate 101 and the second semiconductor substrate 102 may have different thermal and / or electrical properties (thermal design and / or electrical design). The dielectric insulating layer 11 of the first substrate 101 may include a different material than the dielectric insulating layer 11 of the second substrate 102, resulting in different thermal properties. For example, the dielectric insulating layer 11 of the first substrate 101 may include only one material or a compound of two or more materials. The dielectric insulating layer 11 of the second substrate 102 may also include only one material or a compound of two or more materials. However, at least one of the materials in the second substrate 102 may be different from that in the first substrate 101. That is, the first substrate 101 does not include at least one material included in the second substrate 102. For example, one of the first substrate 101 and the second substrate 102 may include a filler, while the other substrate may not include any filler. According to another example, both substrates 101 and 102 include a filler, but the filler of the first substrate 101 has a different material than the filler of the second substrate 102.

[0054] The thermal properties (thermal design) of a substrate generally affect the temperature of controllable semiconductor elements mounted thereon. For example, if a substrate has a high thermal conductivity, heat generated by the controllable semiconductor elements mounted thereon can be conducted away more efficiently than if the substrate has a lower thermal conductivity. Thus, even if the same number of switching operations are performed by all controllable semiconductor elements, during operation, controllable semiconductor elements mounted on a substrate with a higher thermal conductivity can have a lower temperature than other controllable semiconductor elements mounted on a substrate with a lower thermal conductivity. The electrical properties (electrical design) of a substrate can affect the switching characteristics of the controllable semiconductor elements mounted thereon. That is, for example, the material of the metallization layer of the substrate and the thickness of the metallization layer can affect the switching characteristics of the controllable semiconductor elements mounted thereon.

[0055] The semiconductor device may include a first plurality of switching elements 121 and a second plurality of switching elements 122. The first plurality of switching elements 121 includes a first subset 1211 and a second subset 1212. The first subset 1211 includes a first number A of switching elements, where A ≥ 1. The second subset 1212 includes a second number B of switching elements, where B ≥ 0 and A > B. The first subset 1211 of the first plurality of switching elements 121 is disposed on a first substrate 101. The second subset 1212 of the first plurality of switching elements 121 may be disposed on either the first substrate 101 or the second substrate 102. That is, more than 50% of the switching elements in the first plurality of switching elements 121 may be disposed on the first substrate 101. For example, more than 60%, more than 75%, more than 90%, or 100% of the switching elements in the first plurality of switching elements 121 may be disposed on the first substrate 101. A significantly smaller percentage of the switching elements in the first plurality of switching elements 121, or none of the switching elements, may be disposed on the second substrate 102. The first substrate 101 may include one or more materials that improve or support the thermal and / or electrical performance of the first plurality of switching elements 121. Even if a small percentage of the switching elements in the first plurality of switching elements 121 are disposed on the second substrate 102, this may not improve or support the thermal and / or electrical performance of the first plurality of switching elements 121, and the overall performance of the semiconductor device may only be slightly negatively affected.

[0056] The second plurality of switching elements 122 includes a third subset 1221 and a fourth subset 1222. The third subset 1221 includes a third number C of switching elements, where C ≥ 1. The fourth subset 1222 includes a fourth number D of switching elements, where D ≥ 0 and C > D. The third subset 1221 of the second plurality of switching elements 122 is arranged on the second substrate 102. The fourth subset 1222 of the second plurality of switching elements 122 can be arranged on the second substrate 102 or on the first substrate 101. That is, more than 50% of the switching elements in the second plurality of switching elements 122 are arranged on the second substrate 102. For example, more than 60%, more than 75%, more than 90%, or 100% of the switching elements in the second plurality of switching elements 122 can be arranged on the second substrate 102. A significantly smaller percentage of the switching elements in the second plurality of switching elements 122, or none of the switching elements, can be arranged on the first substrate 101. The second substrate 102 may include one or more materials that improve or support the thermal and / or electrical performance of the second plurality of switching elements 122. Even if a small percentage of the switching elements in the second plurality of switching elements 122 are disposed on the first substrate 101, this may not improve or support the thermal and / or electrical performance of the second plurality of switching elements 122, and the overall performance of the semiconductor device may only be slightly negatively affected.

[0057] The first substrate 101 and the second substrate 102 are arranged within the same package 17. If the semiconductor module device includes a base plate 12, the first substrate 101 and the second substrate 102 are mounted on the same base plate 12, and the base plate 12 with the base plates 101 and 102 mounted thereon may be arranged in the package 17, or the base plate 12 with the base plates 101 and 102 mounted thereon may form the bottom of the package 17. The first substrate 101 may be electrically coupled to the second substrate 102, for example, by bonding wires, bonding ribbons, connecting pads, or conductor rails. During operation of the power semiconductor module, a commutation path may pass through both the first substrate 101 and the second substrate 102.

[0058] The switching elements in the first plurality of switching elements 121 may have common thermal and electrical characteristics, and the switching elements in the second plurality of switching elements 122 may have common thermal and electrical characteristics that are different from the thermal and electrical characteristics of the switching elements in the first plurality 121 .

[0059] According to one example, the switching elements in the first plurality of switching elements 121 are fast switching elements that perform switching operations (e.g., from an on state to an off state, or vice versa) at a speed higher than a threshold speed. For example, the switching elements in the first plurality of switching elements 121 may have an on-time of <100 ns (nanoseconds) and an off-time of <100 ns. The switching elements in the second plurality of switching elements 122 may be implemented as slow switching elements that perform switching operations at a speed lower than a threshold speed. For example, the switching elements in the second plurality of switching elements 122 may have an on-time of ≥100 ns (nanoseconds) and an off-time of ≥100 ns.

[0060] According to another example, during operation, the switching elements in the first plurality of switching elements 121 generate switching losses and conduction losses, wherein the conduction losses are greater than the switching losses. In this example, the switching elements in the second plurality of switching elements 122 may also generate switching losses and conduction losses, wherein the switching losses are greater than the conduction losses.

[0061] Electrical terminals configured to electrically couple the substrates 101 , 102 and semiconductor bodies mounted thereon to respective potentials may be arranged on the first substrate 101 or on the second substrate 102 .

[0062] The separation of semiconductor bodies having different thermal and electrical properties on separate substrates 101, 102 results in improved overall thermal and electrical performance of the power semiconductor device. Substrates with improved thermal properties (increased thermal conductivity) are generally more expensive than substrates with lower thermal properties (low thermal conductivity). For example, during operation of the power semiconductor module device, fast switching elements can generate more heat than slow switching elements. Arranging both fast switching elements and slow switching elements on a single substrate with high thermal properties (high thermal conductivity) can increase the overall cost of the power semiconductor module because the surface area of the single substrate needs to be considerable to accommodate both the switching elements of the first plurality of switching elements 121 and the switching elements of the second plurality of switching elements 122. Therefore, using separate substrates 101, 102 with different thermal and / or electrical properties can significantly reduce the cost of the power semiconductor module. The surface area of the more expensive substrate with high thermal and / or electrical properties can be reduced, and the remaining surface area can be provided on the less expensive substrate with reduced thermal and / or electrical properties.

[0063] According to one example, the first substrate 101 may be composed of or include AlN, wherein a first subset 1211 of the switching elements in the first plurality of switching elements 121 is arranged on the first substrate 101. For example, the second substrate 102 may be composed of or include Al2O3, wherein a third subset 1221 of the switching elements in the second plurality of switching elements 122 is arranged on the second substrate 102. However, the above materials are merely examples. The first substrate 101 and the second substrate 102 may be composed of or include any other suitable materials, wherein at least one of the materials may be different for different substrates 101, 102.

[0064] The terminal element 14 for electrically contacting the first substrate 101 can have the same thermal and electrical properties as, or can have different thermal and electrical properties than, the terminal element 14 for electrically contacting the second substrate 102. For example, the terminal element 14 for electrically contacting the first substrate 101 can have a higher power loop resistance than the terminal element 14 for electrically contacting the second semiconductor substrate 102, or vice versa, depending on the electrical and thermal properties of the respective substrates 101, 102 and the electrical and thermal properties of the semiconductor bodies mounted thereon. For example, if the first plurality of switching elements 121 includes fast switching elements and the second plurality of switching elements 122 includes slow switching elements, the power loop resistance of the terminal element 14 electrically contacting the first substrate 101 can be higher than the power loop resistance of the terminal element 14 electrically contacting the second substrate 102. This also applies to any other structures and connection elements of the respective substrates 101, 102, such as the conductive connection layer 130, the metallization layers 111, 112, or the electrical connection 13.

[0065] To improve the electromagnetic compatibility of substrates 101 and 102, additional shielding elements may be provided for at least one of substrates 101 and 102. For example, if first plurality of switching elements 121 includes fast switching elements and second plurality of switching elements 122 includes slow switching elements, or if switching elements in first plurality of switching elements 121 generate higher conduction losses than switching losses and switching elements in second plurality of switching elements 122 generate higher switching losses than conduction losses, it may be sufficient to provide additional shielding elements only for first substrate 101 and not for second substrate 102. For example, first substrate 101 may be an insulated metal substrate (IMS) with additional conductive shielding. Second substrate 102 may be a conventional substrate without additional shielding other than an IMS.

[0066] According to another example, in addition to the switching elements of the first plurality of switching elements 121 (and optionally the second plurality of switching elements 122), a plurality of capacitive elements may be mounted on the first substrate 101. For example, such capacitive elements may be symmetrically arranged on the first substrate 101 to prevent asymmetric switching characteristics of the semiconductor device. Additional structuring of the second metallization layer 112 of the first substrate 101 may further contribute to the symmetrical switching characteristics of the semiconductor device. For a second substrate 102 on which slow switching elements (or alternatively, on which elements generating higher switching losses than conduction losses are mounted) are mounted, it may not be necessary to structure the second metallization layer 122. Furthermore, if any capacitive elements are mounted on the second substrate 102, it may not be necessary to arrange the capacitive elements symmetrically on the second substrate 102.

[0067] exist Figure 2 In the device, an additional capacitive element ( Figure 2 10). For example, such an additional capacitive element may be implemented as an additional semiconductor body 120. The additional semiconductor body 120 may be mounted on the first substrate 101 or the second substrate 102, or may be mounted on an external printed circuit board (PCB) that is arranged to be separated from the substrates 101, 102 (e.g., outside the housing 17) but electrically coupled to the substrates 101, 102.

[0068] exist Figure 6 The embodiment of the invention on two separate substrates 101, 102 is shown by way of example. Figure 2 semiconductor devices. Figure 6 In the example of FIG. 1 , the first substrate 101 and the second substrate 102 are arranged on the substrate 12. The substrate 12 may be arranged in the housing 17 or may form the bottom of the housing 17 (the housing is Figure 6 (not specifically shown in the figure). However, according to another example, the base plate 12 can be omitted. It is also possible to arrange the first and second substrates 101, 102 in a frame and to arrange the housing 17 so that the frame with the substrates 101, 102 forms the bottom of the housing 17. The first substrate 101 comprises a first metallization layer 1111, as described above for Figure 1 Described. Figure 6 In the example shown in FIG. 1 , the first metallization layer 1111 includes five different individual segments. Figure 2 The first controllable semiconductor element T1 of the ANPC topology shown in FIG. 1 may be arranged in the first section 111 of the first metallization layer 1111. 11For example, the drain electrode or collector electrode of the first controllable semiconductor element T1 may be electrically coupled to the first section 111 11 . First section 111 11 The first freewheeling element F1 may also be arranged in the first section 111. 11 In particular, the cathode electrode of the first freewheeling element F1 may be electrically coupled to the first segment 111. 11 The second controllable semiconductor element T2 and the second freewheeling element F2 may be arranged in the second section 111 of the first metallization layer 1111. 12 For example, the drain electrode or collector electrode of the second controllable semiconductor element T2 and the cathode electrode of the second freewheeling element F2 may be coupled to the second section 111. 12 For example, the emitter electrode or source electrode of the first controllable semiconductor element T1 and the anode electrode of the first freewheeling element F1 may be electrically coupled to the second section 111 (eg by means of bonding wires). 12 The third controllable semiconductor element T3 and the third freewheeling element F3 may be arranged in the third section 111 of the first metallization layer 1111. 13 For example, the drain electrode or collector electrode of the third controllable semiconductor element T3 and the cathode electrode of the third freewheeling element F3 may be coupled to the third section 111. 13 The emitter electrode or source electrode of the second controllable semiconductor element T2 and the anode electrode of the second freewheeling element F2 may be electrically coupled to the third section 111 (eg by means of bonding wires). 13 The fourth controllable semiconductor element T4 and the fourth freewheeling element F4 may be mounted in the fourth section 111 of the first metallization layer 1111. 14 For example, the drain electrode or collector electrode of the fourth controllable semiconductor element T4 and the cathode electrode of the fourth freewheeling element F4 may be electrically coupled to the fourth section 111. 14 The emitter electrode or source electrode of the third controllable semiconductor element T3 and the anode electrode of the third freewheeling element F3 may be electrically coupled to the fourth section 111 (eg by means of bonding wires). 14 The fifth section 111 of the first metallization layer 1111 15 The emitter electrode or source electrode of the fourth controllable semiconductor element T4 and the anode electrode of the fourth freewheeling element F4 may be electrically coupled to the fifth section 111. 15 .

[0069] exist Figure 6 In the example of FIG. 1 , the second substrate 102 includes a first metallization layer 1112 having three different sections. The fifth controllable semiconductor element T5 and the fifth freewheeling element F5 can be mounted in the first section 111 of the first metallization layer 1112. 21In particular, the drain electrode or collector electrode of the fifth controllable semiconductor element T5 and the cathode electrode of the fifth freewheeling element F5 may be electrically coupled to the first section 111. 21 The sixth controllable semiconductor element T6 and the sixth freewheeling element F6 are arranged in the second section 111 of the first metallization layer 1112 of the second substrate 102. 22 In particular, the drain electrode or collector electrode of the sixth controllable semiconductor element T6 and the cathode electrode of the sixth freewheeling element F6 may be electrically coupled to the second section 111. 22 The emitter electrode or source electrode of the fifth controllable semiconductor element T5 and the anode electrode of the fifth freewheeling element F5 may be electrically coupled (eg by means of bonding wires) to the second section 111 of the first metallization layer 1112. 22 The emitter electrode or source electrode of the sixth controllable semiconductor element T6 and the anode electrode of the sixth freewheeling element F6 may be electrically coupled (eg by means of bonding wires) to the third section 111 of the first metallization layer 1112. 23 . Second section 111 22 may be electrically coupled to or form an output node OUT of the device.

[0070] Similar to what has been described above for controllable semiconductor elements, the semiconductor device may include a first plurality of freewheeling elements (e.g., diodes). Each freewheeling element of the first plurality of freewheeling elements may be coupled in parallel to one of the controllable semiconductor elements of the first plurality of controllable semiconductor elements. In particular, the first plurality of freewheeling elements may include at least a first subset, wherein each freewheeling element of the first subset is coupled in parallel to one of the controllable semiconductor elements of the first subset of the first plurality of controllable semiconductor elements. The semiconductor device may also include a second plurality of freewheeling elements (e.g., diodes). Each freewheeling element of the second plurality of freewheeling elements may be coupled in parallel to one of the controllable semiconductor elements of the second plurality of controllable semiconductor elements. In particular, the second plurality of freewheeling elements may include at least a first subset, wherein each freewheeling element of the first subset is coupled in parallel to one of the controllable semiconductor elements of the first subset of the second plurality of controllable semiconductor elements.

[0071] The first section 111 of the first metallization layer 1112 of the second substrate 102 21 The second section 111 of the first metallization layer 1111 of the first substrate 101 may be electrically coupled (eg, by means of a bonding wire) to the second section 111 of the first metallization layer 1111 of the first substrate 101. 12 , and the third section 111 of the first metallization layer 1112 of the second substrate 102 23 The fourth section 111 may be electrically coupled (eg, by means of a bonding wire) to the first metallization layer 1111 of the first substrate 101. 14 .

[0072] As described above, the additional capacitive element C1 may be arranged on the second substrate 102. Figure 6 According to an example, the additional capacitive element C1 may be arranged in the third section 111 of the first metallization layer 1112 of the second substrate 102. 23 and can be electrically coupled to the first section 111 of the first metallization layer 1112 of the second substrate 102 21 The additional capacitive element C1 can operate as a snubber element and suppress or reduce voltage transients. The additional capacitive element C1 can also reduce the stray inductance of the semiconductor device and, therefore, reduce any overvoltage that may occur in the semiconductor device and potentially damage the semiconductor body. This allows for faster switching of the switching element.

[0073] The additional capacitive element C1 can also reduce the steepness of the edges of the voltage appearing in the semiconductor arrangement during the switching process. Less steep slopes during switching operations generally improve the electromagnetic compatibility of the semiconductor arrangement.

[0074] Furthermore, the additional capacitive element C1 is used to connect the first section 111 to the 21 Coupled to the third section 111 23 The inherent inductance of the electrical connection elements (e.g., bonding wires) can form a low-pass filter (as seen from the phase output OUT toward the input voltage (DC+, DC-)). In this way, any overvoltage peaks that occur during the switching operation of the semiconductor device can be filtered and not passed toward the input side (e.g., toward the first common node P and the second common node N). This allows the first, second, third, and fourth controllable switching elements T1, T2, T3, T4 to have a lower maximum blocking voltage than the fifth and sixth controllable switching elements T5, T6. This is because the LC filter short-circuits short-term overvoltages. Generally, a lower blocking voltage results in lower forward losses, thereby optimizing the loss rate within the semiconductor device.

[0075] Figure 5 and Figure 6 The example in FIG is shown with the aid of a power semiconductor module comprising two individual substrates 101 , 102 . Figure 5 and Figure 6 The general principles described can also be applied to power semiconductor modules comprising more than two individual substrates. That is, the overall performance can be further optimized by using more than two different substrates, each of which is optimized for the semiconductor devices mounted thereon and their specific functions, as well as their electrical and thermal properties.

[0076] Typically, in order to reduce the stray inductance of the power semiconductor module, the terminal elements can be placed as close to each other as possible within the power semiconductor module. This reduces or limits any parasitic effects, such as overvoltage shutdown or forward recovery effects. In addition, it is desirable to optimize the commutation path on the substrate of the power semiconductor module. The commutation path can be optimized, for example, by reducing the length of the path through which the current must flow and also by reducing the number of bonded connections within the power semiconductor module. This helps to avoid any added parasitic stray inductance in addition to the stray inductance of the input terminals (DC+, DC-). Any suboptimal commutation path may lead to unwanted resonant circuits (e.g., stray inductance together with the capacitance of the semiconductor body or substrate), which may also cause additional oscillations that may have a negative impact on the electromagnetic compatibility of the power semiconductor module.

[0077] During operation of the power semiconductor module arrangement, any semiconductor devices that are subject to greater stress than other semiconductor devices may be spatially separated from those semiconductor devices that are subject to less stress.

[0078] In the examples described above with respect to the accompanying drawings, the controllable semiconductor elements of the first plurality of controllable semiconductor elements have been described as fast switching elements, while the controllable semiconductor elements of the second plurality of controllable semiconductor elements have been described as slow switching elements. That is, the thermal properties and / or electrical properties of the substrate have been described as being optimized for fast switching elements or slow switching elements. However, this is merely an example. It is also possible to optimize different substrates for other properties of the controllable semiconductor elements mounted on the substrate. For example, each of the controllable semiconductor elements may have a maximum allowable temperature. The maximum allowable temperature is typically a maximum operating temperature, up to which a particular controllable semiconductor element can safely operate. Exceeding the maximum allowable temperature may cause thermal damage to the corresponding controllable semiconductor element. The maximum operating temperature of the controllable semiconductor element is typically defined in a corresponding data sheet of the controllable semiconductor element, wherein the data sheet is published by the manufacturer of the controllable semiconductor element.

[0079] According to one example, each controllable semiconductor element of the first plurality of controllable semiconductor elements has a maximum permissible temperature, wherein during operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements reaches its maximum permissible temperature. On the other hand, each controllable semiconductor element of the second plurality of controllable semiconductor elements may have a maximum permissible temperature, wherein during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements does not reach its maximum permissible temperature.

[0080] At least a first subset of a first plurality of controllable semiconductor elements (the first subset comprising >50%, >60%, >75%, >90%, or = 100% of the total number of controllable semiconductor elements in the first plurality of controllable semiconductor elements) can be mounted on a first substrate. At least a first subset of a second plurality of controllable semiconductor elements (the first subset comprising >50%, >60%, >75%, >90%, or = 100% of the total number of controllable semiconductor elements in the second plurality of controllable semiconductor elements) can be mounted on a second substrate. The first substrate can have, for example, optimized thermal properties compared to the thermal properties of the second substrate. That is, the thermal conductivity of the first substrate can be higher than the thermal conductivity of the second substrate. In this way, heat can be dissipated more efficiently from at least the first subset of the first plurality of controllable semiconductor elements, which can generate more heat during operation than the controllable semiconductor elements in the second plurality of controllable semiconductor elements. On the other hand, the controllable semiconductor elements in the second plurality of controllable semiconductor elements can be mounted on a substrate having inferior thermal properties compared to the first substrate. It may be sufficient for the controllable semiconductor elements of the second plurality of controllable semiconductor elements to generate less heat during operation of the semiconductor module arrangement (compared to the controllable semiconductor elements of the first plurality of controllable semiconductor elements).

[0081] Substrates with better thermal properties are often more expensive than substrates with poorer thermal properties. Therefore, portions of the substrate area can be provided by a lower-cost substrate. As mentioned above, in this example, it is also possible to provide more than two substrates within the same package to further optimize the overall semiconductor module arrangement.

[0082] In the examples described above, different semiconductor substrates of the semiconductor module device may include different materials, for example, to provide different electrical and / or thermal properties for different types of controllable semiconductor components. However, this is merely an example. Alternatively or additionally, for example, the different substrates may have different thicknesses in the vertical direction y. According to one example, the dielectric insulating layer 111 of the first semiconductor substrate 101 has a first thickness in the vertical direction y that is different from the second thickness of the dielectric insulating layer 112 of the second semiconductor substrate 102. The vertical direction y is perpendicular to the rear surface of the first semiconductor substrate 101 and perpendicular to the rear surface of the second semiconductor substrate 102. The rear surface of a semiconductor substrate is a surface parallel to the top surface of the respective semiconductor substrate, where the top surface is the surface on which at least one controllable semiconductor component is mounted. Alternatively or additionally, the second metallization layer 1121 of the first semiconductor substrate 101 is a structured layer including recesses between different sections of the layer. The different sections of the second metallization layer 1121 of the first semiconductor substrate 101 are arranged in a first pattern. The second metallization layer 1122 of the second semiconductor substrate 102 is also a structured layer including recesses between different sections of the layer, wherein the different sections of the second metallization layer 1122 of the second semiconductor substrate 102 are arranged in a second pattern that is different from the first pattern. According to another example, the second metallization layer 1121 of the first semiconductor substrate 101 is a structured layer, while the second metallization layer 1122 of the second semiconductor substrate 102 is a continuous layer.

Claims

1. A semiconductor module device, comprising: case; a first semiconductor substrate disposed inside the housing; a second semiconductor substrate disposed inside the housing; a first plurality of controllable semiconductor elements; as well as a second plurality of controllable semiconductor elements, wherein During operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, wherein the switching losses are greater than the conduction losses, During operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, wherein the conduction losses are greater than the switching losses, At least a first subset of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate, and At least a first subset of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.

2. The semiconductor module device according to claim 1, wherein the first subset of the first plurality of controllable semiconductor elements includes more than 50%, more than 60%, more than 75%, or more than 90% of the controllable semiconductor elements in the first plurality of controllable semiconductor elements; and The first subset of the second plurality of controllable semiconductor elements includes more than 50%, more than 60%, more than 75%, or more than 90% of the controllable semiconductor elements of the second plurality of controllable semiconductor elements.

3. The semiconductor module device according to claim 1 or 2, wherein: The first plurality of controllable semiconductor elements is electrically coupled to the second plurality of controllable semiconductor elements.

4. The semiconductor module device according to claim 1 or 2, wherein: During operation of the semiconductor module arrangement, at least one commutation path passes through both the first semiconductor substrate and the second semiconductor substrate.

5. The semiconductor module device according to claim 1 or 2, wherein: The first semiconductor substrate includes a dielectric insulating layer comprising at least a first material, and The second semiconductor substrate includes a dielectric insulating layer including at least a second material, which is not included in the dielectric insulating layer of the first substrate.

6. The semiconductor module device according to claim 1 or 2, wherein: The first semiconductor substrate includes a dielectric insulating layer and a second metallization layer arranged on a rear surface of the dielectric insulating layer, and the second semiconductor substrate includes a dielectric insulating layer and a second metallization layer arranged on a rear surface of the dielectric insulating layer, wherein The dielectric insulating layer of the first semiconductor substrate has a first thickness in a vertical direction that is different from a second thickness of the dielectric insulating layer of the second semiconductor substrate, wherein the vertical direction is perpendicular to the back surface of the first semiconductor substrate and the back surface of the second semiconductor substrate, Alternatively, the second metallization layer of the first semiconductor substrate is a structured layer comprising recesses between different sections of the layer, wherein the different sections of the second metallization layer of the first semiconductor substrate are arranged in a first pattern, and the second metallization layer of the second semiconductor substrate is a structured layer comprising recesses between different sections of the layer, wherein the different sections of the second metallization layer of the second semiconductor substrate are arranged in a second pattern different from the first pattern, or both.

7. The semiconductor module arrangement according to claim 5, further comprising at least one electrical connection element, wherein The first semiconductor substrate includes a first metallization layer disposed on a first surface of its corresponding dielectric insulating layer; The second semiconductor substrate includes a first metallization layer disposed on a first surface of its corresponding dielectric insulating layer; and Each of the at least one electrical connection element is configured to: electrically coupling the first metallization layer of the first semiconductor substrate to the first metallization layer of the second semiconductor substrate, electrically coupling one of the controllable semiconductor elements of the first plurality of controllable semiconductor elements to one of the controllable semiconductor elements of the second plurality of controllable semiconductor elements, electrically coupling one of the controllable semiconductor elements of the first plurality of controllable semiconductor elements to the first metallization layer of the second semiconductor substrate, or One of the controllable semiconductor elements of the second plurality of controllable semiconductor elements is electrically coupled to the first metallization layer of the first semiconductor substrate.

8. The semiconductor module arrangement according to claim 7, wherein: Each of the at least one electrical connection element comprises a bonding wire, a bonding ribbon, a connection pad, or a conductor track.

9. The semiconductor module arrangement according to claim 1 or 2, further comprising: a first plurality of diode elements; as well as a second plurality of diode elements, wherein At least a first subset of the first plurality of diode elements is arranged on the first semiconductor substrate, and At least a first subset of the second plurality of diode elements is arranged on the second semiconductor substrate.

10. The semiconductor module arrangement according to claim 9, wherein Each diode element of the first subset of the first plurality of diode elements is coupled in parallel to a different one of the controllable semiconductor elements of the first subset of the first plurality of controllable semiconductor elements, and Each diode element of the first subset of the second plurality of diode elements is coupled in parallel to a different one of the controllable semiconductor elements of the first subset of the second plurality of controllable semiconductor elements.

11. The semiconductor module device according to claim 1 or 2, wherein: Meet at least one of the following: The first semiconductor substrate has a thermal design that is different from the thermal design of the second semiconductor substrate, wherein the thermal design of the semiconductor substrate affects the temperature of the controllable semiconductor element mounted thereon, and The first semiconductor substrate has an electrical design that differs from an electrical design of the second semiconductor substrate, wherein the electrical design of the semiconductor substrate influences the switching characteristics of the controllable semiconductor element mounted thereon.

12. The semiconductor module arrangement according to claim 1 or 2, wherein: The first plurality of controllable semiconductor elements and the second plurality of controllable semiconductor elements are arranged in a neutral point clamped topology or an active neutral point clamped topology.

13. The semiconductor module device according to claim 1 or 2, wherein: At least one of the first semiconductor substrate and the second semiconductor substrate includes an additional conductive shielding element configured to improve the electromagnetic compatibility of the respective semiconductor substrate.

14. The semiconductor module arrangement according to claim 1 or 2, further comprising at least one capacitive element arranged on the second semiconductor substrate, wherein The capacitive element is configured to suppress or reduce voltage transients occurring in the semiconductor module arrangement.

15. The semiconductor module arrangement according to claim 1 or 2, further comprising at least one of the following: a plurality of electrical connection elements configured to electrically couple elements disposed on the first semiconductor substrate and the second semiconductor substrate to each other; a plurality of conductive connection layers configured to electrically couple the controllable semiconductor elements of the first plurality of controllable semiconductor elements and the second plurality of controllable semiconductor elements to the corresponding first semiconductor substrate or the second semiconductor substrate, a first metallization layer, the first metallization layer being arranged on the first surface of the first semiconductor substrate, another first metallization layer, the another first metallization layer being arranged on the first surface of the second semiconductor substrate, and a plurality of terminal elements configured to electrically contact the first semiconductor substrate and the second semiconductor substrate from outside the housing, wherein The connection elements, conductive connection layers, first metallization layers and / or terminal elements arranged on the second semiconductor substrate have a power circulation resistance different from the power circulation resistance of the connection elements, conductive connection layers, first metallization layers and / or terminal elements arranged on the first semiconductor substrate.

16. The semiconductor module arrangement according to claim 15, wherein The connecting elements, conductive connecting layer, first metallization layer and / or terminal elements arranged on the second semiconductor substrate have a higher power circulation resistance than the power circulation resistance of the connecting elements, conductive connecting layer, first metallization layer and / or terminal elements arranged on the first semiconductor substrate.

17. The semiconductor module arrangement according to claim 1 or 2, wherein: Each of the controllable semiconductor elements in the first plurality of controllable semiconductor elements comprises at least one of an IGBT, a MOSFET, a JFET, or a HEMT, and Each of the controllable semiconductor elements in the second plurality of controllable semiconductor elements includes at least one of an IGBT, a MOSFET, a JFET, or a HEMT.

18. A semiconductor module device comprising: case; a first semiconductor substrate disposed inside the housing; a second semiconductor substrate disposed inside the housing; a first plurality of controllable semiconductor elements; as well as a second plurality of controllable semiconductor elements, wherein each controllable semiconductor element of the first plurality of controllable semiconductor elements has a maximum permissible temperature, wherein during operation of the semiconductor module arrangement each controllable semiconductor element of the first plurality of controllable semiconductor elements reaches its maximum permissible temperature, each controllable semiconductor element of the second plurality of controllable semiconductor elements has a maximum permissible temperature, wherein, during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements does not reach its maximum permissible temperature, At least a first subset of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate, and At least a first subset of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.

19. The semiconductor module arrangement according to claim 18, wherein The maximum permissible temperature of a controllable semiconductor element is a maximum operating temperature defined in a data sheet of the controllable semiconductor element, up to which the controllable semiconductor element can be safely operated, and wherein exceeding the maximum permissible temperature can cause thermal destruction of the respective controllable semiconductor element.

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