protective device

Abstract

Embodiments of the present disclosure provide a protective device. The present disclosure provides an electronic device including a substrate. The substrate includes a well and a peripheral insulating wall laterally surrounding the well. At least one lateral bipolar transistor is formed in the well, and at least one transistor has a base region extending below parallel collector and emitter regions. The peripheral insulating wall is widened in a first direction parallel to the collector and emitter regions, such that the base region penetrates the peripheral insulating wall.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to electronic devices protected against electrostatic discharge. Background Art

[0002] Electrostatic discharge (ESD) in unprotected integrated circuits can have undesirable effects on the integrated circuit, often leading to degradation of components forming part of the circuit. This degradation often results in severe failures that can render the circuit partially or even completely inoperable.

[0003] To avoid potential damage caused by electrostatic discharge, existing integrated circuits typically include protection against the effects of such electrostatic discharge. To be effective, such protection should ideally have:

[0004] a trigger voltage that is sufficiently low to properly protect the circuit in the event of an electrostatic discharge and relatively high to avoid any untimely triggering during normal operation of the circuit;

[0005] a holding voltage that, after protection is activated, is low enough to allow the circuit to be exposed to the lowest possible voltage while ensuring good dissipation of the current from the electrostatic discharge; and

[0006] A dynamic resistance, which is as low as possible, results in a clamping voltage or limit voltage that is as low as possible, which corresponds to the maximum voltage that can be reached in the event of an electrostatic discharge.

[0007] Existing devices for protecting against electrostatic discharge cannot reconcile all of the above characteristics, which affects the performance of these devices. Summary of the Invention

[0008] There is a need to improve the performance of existing devices for protecting against electrostatic discharge.

[0009] The embodiments overcome all or part of the disadvantages of known devices for protecting against electrostatic discharge.

[0010] An embodiment provides an electronic device including a substrate, the substrate including:

[0011] trap;

[0012] a peripheral insulating wall laterally surrounding the well; and

[0013] at least one lateral bipolar transistor formed in the well, the at least one lateral bipolar transistor having a base region extending below parallel collector and emitter regions;

[0014] The wall is widened in a first direction parallel to the collector region and the emitter region such that the base region penetrates into the wall.

[0015] According to one embodiment, the base region stops before the wall in a second direction perpendicular to the first direction.

[0016] According to one embodiment:

[0017] The substrate has a first conductivity type;

[0018] The wall has a first conductivity type;

[0019] The base region has a first conductivity type;

[0020] The well has a second conductivity type different from the first conductivity type; and

[0021] The collector region and the emitter region have the second conductivity type.

[0022] According to one embodiment, the base region penetrates into the wall at a distance in the range of approximately 20% to approximately 50% of the length of the base region in the first direction, preferably, the base region penetrates into the wall at a distance in the range of 20% to 50% of the length of the base region in the first direction.

[0023] According to one embodiment, the base region continues into the wall over a distance of approximately 30% of the length of the base region in the first direction, preferably the base region continues into the wall over a distance of 30% of the length of the base region in the first direction.

[0024] According to one embodiment, the first conductivity type is p-type and the second conductivity type is n-type.

[0025] According to one embodiment, the first conductivity type is n-type and the second conductivity type is p-type.

[0026] According to one embodiment:

[0027] The first contact trace is vertically aligned with the collector region; and

[0028] The second contact trace is vertically aligned with the emitter region.

[0029] One embodiment provides an apparatus for protecting against electrostatic discharge, the apparatus comprising at least one electronic device of this type.

[0030] According to one embodiment, the device has a holding voltage greater than 5V and a clamping voltage less than 7V.

[0031] According to one embodiment, the device is suitable for applications having a protection limit voltage between approximately 0V and approximately 5V, preferably between 0V and 5V. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments with reference to the accompanying drawings, in which:

[0033] Figure 1 schematically illustrates a top view of an embodiment of an electronic device;

[0034] Figure 2 Schematically shows the Figure 1 A cross-sectional perspective view of plane AA;

[0035] Figure 3 Schematically shows the Figure 1 A cross-sectional perspective view of plane BB;

[0036] Figure 4 Shown with reference Figures 1 to 3 an electrical circuit equivalent to the embodiment of the apparatus in question; and

[0037] Figure 5 The current-voltage characteristics of an embodiment of the device for protecting against electrostatic discharge are shown. DETAILED DESCRIPTION

[0038] In different drawings, the same elements are designated by the same reference numerals. In particular, structural elements and / or functional elements common to different embodiments may be designated by the same reference numerals and may have the same structural features, dimensional features, and material features.

[0039] For the sake of clarity, only the steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, components or integrated circuits to be protected against electrostatic discharge are not described, which are compatible with components or circuits protected against electrostatic discharge in a conventional manner.

[0040] Throughout this disclosure, the term electrically “connected” is used to designate a direct electrical connection between circuit elements with no intervening elements other than conductors, while the term “coupled” is used to designate an electrical connection between circuit elements that may be direct or may be via one or more intervening elements.

[0041] In the following description, when referring to terms that define absolute positions (such as terms "front", "back", "top", "bottom", "left", "right", etc.), terms that define relative positions (such as terms "above", "below", "up", "down", etc.), or terms that define orientations (such as terms "horizontal", "vertical", etc.), reference is made to the orientation of the accompanying drawings unless otherwise specified.

[0042] The terms "substantially," "substantially," and "approximately" are used herein to designate a tolerance of plus or minus 10%, preferably plus or minus 5%, of the value in question.

[0043] Figure 1 A top view of an embodiment of an electronic device 100 is schematically shown.

[0044] The device 100 integrates one or more parallel lateral transistors in a substrate 300 . Figure 1 is a top view illustrating the distribution of conductive contact traces for the collector and emitter regions of a transistor.

[0045] According to this embodiment, the device 100 is formed in all or part of a substrate 300. The substrate 300 is, for example, a silicon wafer. Figure 1 Only a rectangular portion of the silicon wafer is shown in FIG. The substrate 300 (or a portion of the substrate 300 ) comprises an interdigitated structure at its upper surface 302 .

[0046] exist Figure 1 In the example, the interdigitated structure is formed by the following terms:

[0047] The substantially parallel first fingers 310, 312 and 314 are formed from a first side of the substrate 300 (at Figure 1 The right-hand side in FIG) extends along the first direction X at the upper surface 302 of the substrate 300; and

[0048] Substantially parallel second fingers 320 and 322 extend from a second side of the substrate 300 (at Figure 1 The second side (left-hand side in FIG) extends at the upper surface 302 of the substrate 300 along the first direction X. In this example, the second side is the side opposite to the first side, so that the first fingers 310, 312 and 314 and the second fingers 320 and 322 are substantially parallel to each other.

[0049] The first fingers 310, 312, and 314 form contact traces for a first region (eg, a collector region of a transistor).The second fingers form contact traces for a second region (eg, an emitter region of a transistor).

[0050] In other words, here, the interdigitated structure is formed by two interlaced "combs," one comb formed by first fingers 310, 312, and 314, and the other comb formed by second fingers 320 and 322. Thus, the interdigitated structure includes alternating first fingers and second fingers along a second direction Y perpendicular to the first direction X. In other words, two adjacent first fingers and two adjacent second fingers are separated by a second finger and a first finger, respectively.

[0051] The first fingers 310, 312, and 314 are spaced apart from the second fingers 320 and 322. In other words, the fingers 310, 312, 314, 320, and 322 are discontinuous.

[0052] For simplicity, Figure 1 In the example of FIG, only five fingers are shown (three first fingers 310, 312, 314 and two second fingers 320, 322). Figure 1 In the example of FIG. 3 , the substrate 300 may further include a plurality of other first fingers and second fingers, which are inserted between the first finger 312 and the second finger 322 .

[0053] Therefore, the substrate 300 may include any number of first fingers and any number of second fingers. The number of first fingers may be different from the number of second fingers. The substrate 300 may, for example, include eight first fingers and seven second fingers.

[0054] The substrate 300 preferably includes at least two first fingers and at least one second finger. Figure 1 The substrate 300 is shown as including an odd number of first fingers and an even number of second fingers. However, in practice, the substrate 300 may also include an even number or an odd number of first fingers or second fingers.

[0055] Figure 2 Schematically shows the Figure 1 The cross-sectional perspective view of the plane AA of FIG. The cross-sectional view AA is perpendicular to the direction X of the first fingers 310 , 312 , and 314 and the second fingers 320 and 322 (ie, parallel to the direction Y).

[0056] exist Figure 2 In FIG, substrate 300 includes a well 330 below its upper surface 302. Well 330 is laterally bounded by peripheral insulating walls 340. Figure 2 In the cross-sectional view of , only the walls of the insulating wall 340 parallel to the axis X are visible. In this example, the insulating wall 340 comprises a first zone 3400 (bottom Iso) and a second zone 3402 (top Iso) stacked in a third vertical direction (Z).

[0057] Substrate 300 is made of a material of a first conductivity type (e.g., p-type doped single-crystal silicon). Peripheral insulating wall 340 has the same conductivity type as substrate 300, in this case, p-type. Also in this example, first region 3400 is formed of a p-type buried layer. Second region 3402 is formed of another layer also of p-type.

[0058] Alternatively, the thickness of the well 330 is substantially equal to the thickness of the second region 3402 , and the wall 340 then comprises only this second region 3402 .

[0059] Preferably, the well 330 is formed by epitaxy (by epitaxial growth) of a doped material of a second conductivity type, which is different from the first conductivity type. The well 330 is made of, for example, n-type silicon. Thus, the conductivity type of the well 330 is different from:

[0060] the conductivity type of substrate 300; and

[0061] The conductivity type of the wall 340 .

[0062] exist Figure 2 In the example, the substrate 300 is passivated at its surface, and therefore, the substrate 300 includes a surface passivation layer 350. Therefore, in this example, the upper surface 302 of the substrate 300 corresponds to the upper surface of the passivation layer 350 of the substrate 300.

[0063] exist Figure 2 , a third region 360 is formed at the interface between the lower surface of the well 330 and the substrate 300. The third region 360 extends in the direction Y and stops before the peripheral insulating wall 340. In this example, the region 360 is formed of an n-type buried layer.

[0064] The first regions 370, 372 and 374 and the second regions 380 and 382 are formed under the passivation layer 350 of the substrate 300. The first regions 370, 372 and 374 and the second regions 380 and 382 are parallel and discontinuous, and the first regions and the second regions extend along the first direction X. Figure 2 In the example:

[0065] First regions 370, 372, and 374 are vertically aligned with first fingers 310, 312, and 314, respectively; and

[0066] The second regions 380 and 382 are vertically aligned with the second fingers 320 and 322 , respectively.

[0067] First fingers 310, 312, and 314 penetrate through passivation layer 350 of substrate 300 to contact first regions 370, 372, and 374, respectively. Similarly, second fingers 320 and 322 penetrate through passivation layer 350 of substrate 300 to contact second regions 380 and 382, ​​respectively.

[0068] exist Figure 2 In the embodiment, the third region 390 extends from the passivation layer 350 of the substrate 300 below the first regions 370, 372, and 374 and the second regions 380 and 382. In the second direction Y, the third region 390 stops before the peripheral insulating wall 340.

[0069] The first regions 370, 372, and 374 and the second regions 380 and 382 have the same conductivity type as the well 330, which is n-type in this example. The third region 390 has the same conductivity type as the substrate 300, which is p-type in this example.

[0070] Therefore, the third region 390 forms a pn junction with the first regions 370, 372, and 374 and the second regions 380 and 382. Figure 2 In the embodiment, the first regions 370 and 372, the second region 380 and the third region 390 are combined to form a lateral transistor 500, which is an NPN type transistor, also referred to as an NPN lateral transistor 500. In this example:

[0071] The first regions 370 and 372 form the collector region of the transistor 500;

[0072] The second region 380 forms the emitter region of the transistor 500;

[0073] The third region 390 forms the base region of the transistor 500; and

[0074] The first region 374 and the second region 382 form the collector region and the emitter region, respectively, of another NPN lateral transistor that is similar to the transistor 500 and is Figure 2 is partially shown.

[0075] Thus, first fingers 310 and 312 are connected to collector regions 370 and 372, respectively, to form collector contacts of lateral NPN transistor 500. Second finger 320 is connected to emitter region 380 to form an emitter contact of lateral NPN transistor 500. Base region 390 is not connected to the contact traces and is referred to as the "floating base" of transistor 500.

[0076] Figure 3 Schematically shows the Figure 1 The cross-sectional perspective view of the plane BB of FIG. The cross-sectional view BB is parallel to the direction X (ie, perpendicular to the direction Y) of the first fingers 310, 312 and 314 and the second fingers 320 and 322. Figure 3 In FIG, only the first finger 310, the second finger 320 and a portion of the first finger 312 are shown, and plane BB ( Figure 1 ) passes through the substrate 300 approximately in the middle of the first finger 312.

[0077] exist Figure 3 In FIG, the well 300 is also laterally bounded by a peripheral insulating wall 340. Figure 3In the cross-sectional view of FIG, only the walls of the insulating wall 340 parallel to the axis X are visible. In this example, the insulating wall 340 likewise comprises a first region 3400 (bottom Iso) and a second region 3402 (top Iso) of the stack.

[0078] The third region 360 extends in the direction X and stops before the peripheral insulating wall 340 .

[0079] According to this embodiment, the wall 340 is widened in a first direction X parallel to the collector regions 370, 372 and 374 and the emitter regions 380 and 382 (at Figure 3 Only the collector region 372 can be seen in the cross-sectional view of FIG, such that the base region 390 penetrates into the wall 340.

[0080] exist Figure 3 , the base region 390 penetrates into the wall 340 over a distance designated by D in the range of approximately 20% to approximately 50% of the length (designated by L) of the base region 390 in the first direction X, preferably, the distance D is in the range of 20% to 50% of the length L of the region 390 in the first direction X. More preferably, the base region 390 penetrates into the wall 340 over a distance D of approximately 30% of the length L of the base region 390 in the first direction X, and even more preferably, the distance D is equal to 30% of the length L of the region 390 in the first direction X.

[0081] Alternatively, the base region 390 penetrates only into the second region 3402 of the wall 340. Where appropriate, the width of the first region 3400 can be smaller than the width of the second region 3402, these widths being both evaluated in the first direction X.

[0082] Device 100, including one or more transistors similar to lateral NPN transistor 500, can be used to protect at least one integrated circuit and / or a discrete electronic component from electrostatic discharge. For example, device 100 can protect input / output circuits from electrostatic discharge that can occur across the input / output circuits.

[0083] In order to protect one or more input / output circuits, each input / output circuit includes a terminal (identified by GND) set to a reference potential (e.g., ground), and another terminal (identified by IO) set to a non-zero potential, for example:

[0084] coupling or connecting the collector contacts 310, 312 of the transistor 500 to the terminal set to the potential 10; and

[0085] The emitter contact 320 of the transistor 500 is coupled or connected to a terminal which is provided as ground GND.

[0086] Figure 4 Shown with reference Figures 1 to 3 An equivalent circuit to the embodiment of the apparatus 100 discussed.

[0087] If combined Figure 2 and 3 For simplicity of discussion, the device 100 is considered hereinafter to include a single lateral NPN transistor 500. Figure 4 In the equivalent circuit, the transistor 500 of the device 100 includes:

[0088] Collector terminal 502 (C);

[0089] floating base 504 (B); and

[0090] Emitter terminal 506 (E).

[0091] According to the reference Figure 2 and Figure 3 Examples discussed:

[0092] For example, the collector terminal 502 of the transistor 500 is formed by the contact traces 310 and 312 connected to the first collector regions 370 and 372 ;

[0093] For example, the floating base 504 of the transistor 500 is formed by the base region 390; and

[0094] For example, the emitter terminal 506 of the transistor 500 is formed by the contact trace 320 connected to the second emitter region 380 .

[0095] As in Figure 4 As shown in FIG, the transistor 500 of the device 100 further includes:

[0096] a first Zener diode 510 having an anode connected to the floating base 504 of the transistor 500 and having a cathode connected to the collector terminal 502 of the transistor 500; and

[0097] A second Zener diode 512 has an anode connected to the floating base 504 of the transistor 500 and has a cathode connected to the emitter terminal 506 of the transistor 500 .

[0098] In an example of an apparatus 100 capable of protecting one or more input / output circuits from electrostatic discharge:

[0099] The collector terminal 502 of the transistor 500 is connected to the input / output terminal (IO) of the circuit(s) to be protected; and

[0100] The emitter terminal 506 of the transistor 500 is connected to the ground GND.

[0101] Figure 5 1 shows the current-voltage characteristics of an embodiment of a device for protecting against electrostatic discharge (eg, a device 100 including at least one lateral NPN transistor 500). Figure 5 The current-voltage characteristics correspond to the reference Figure 4 The equivalent circuit in question.

[0102] exist Figure 5 In FIG, curve 700 reflects the variation in the intensity of the forward current (denoted by IF) or the reverse current (denoted by IR) flowing through the NPN lateral transistor 500. Such intensity is a function of the forward bias voltage (denoted by VF) or the reverse bias voltage (denoted by VR).

[0103] Therefore, in Figure 5 , curve 700 is divided into two parts:

[0104] A portion 700F (at Figure 5 the right-hand side of the ); and

[0105] The portion 700R (at Figure 5 on the left-hand side of the diagram).

[0106] Portions 700F and 700R of curve 700 are substantially identical in their signs. For simplicity, only portion 700F is described below, and transposing such description to portion 700R of curve 700 is within the capabilities of those skilled in the art based on the indications below.

[0107] In normal operation, the forward bias voltage VF of the device 100 can take values ​​ranging from 0V to a limit voltage (identified by VRM). The limit voltage VRM corresponds to the maximum voltage value provided for a given application. Depending on the application under consideration, the limit voltage VRM is, for example, approximately 3V or approximately 5V. When the transistor 500 is biased at the limit voltage VRM, a leakage current (identified by IRM) flows through the transistor 500.

[0108] In the event of an overvoltage, for example due to electrostatic discharge, the bias voltage VF may temporarily exceed a threshold voltage (identified by VTRIG). The threshold voltage VTRIG corresponds to the voltage for triggering the protection. In order to avoid any risk of untimely triggering of the protection, it is ensured that the threshold voltage VTRIG is greater than the limit voltage VRM provided in the application under consideration.

[0109] Once the threshold voltage VTRIG is exceeded (i.e., once the protection is triggered), a snap-back effect occurs. This snap-back phenomenon causes the bias voltage across transistor 500 to drop significantly. After the snap-back, the bias voltage VF can therefore be reduced to a minimum voltage value (identified by VHOLD) called the "holding value." In other words, the holding voltage VHOLD corresponds to the minimum voltage that can be reached after the protection is triggered.

[0110] The snapback phenomenon enables transistor 500 to discharge a current much greater than the current it would conduct (the current it would conduct at the same voltage value before the snapback). In other words, the snapback phenomenon enables transistor 500 to carry a large current while limiting the voltage rise (temporary overvoltage) caused by the electrostatic discharge. By limiting the voltage rise in this way, the risk of degradation of one or more circuits and / or components protected by transistor 500 is reduced.

[0111] However, even after the protection is triggered, the electrostatic discharge is still sufficient to keep the forward bias voltage VF of transistor 500 elevated. This increase in voltage VF is accompanied by an increase in current IF across transistor 500. Current IF across transistor 500 is then substantially proportional to the forward bias voltage VF according to a relationship of the type IF=VF / RDYN, where RDYN is referred to as the "dynamic resistance" of the protection.

[0112] As in Figure 5 As shown in FIG, the value of the forward bias voltage VF can then be raised to a value called the clamping voltage (denoted by VCL). The clamping voltage VCL corresponds to the maximum intensity (peak pulse current) acceptable by the protection, denoted by IPP.

[0113] For some applications, it is desirable to obtain a holding voltage VHOLD that is greater than the limit voltage VRM. The inventors have observed that the value of the holding voltage VHOLD can be modified by adjusting the doping levels of the base and emitter regions of transistor 500. In particular, the inventors have observed that an increase in the doping levels of the base and emitter regions of transistor 500 results in a decrease in the holding voltage VHOLD.

[0114] For the transistor 500 ( Figure 3), the inventors have further observed that the trigger voltage VTRIG can be reduced without degrading the quality of the protection. A reduction in the trigger voltage VTRIG means that the protection is faster and more sensitive. A reduction in the trigger voltage VTRIG can further reduce the residual clamping voltage VCL seen by the application before the full activation of the structure. In other words, the inventors have observed that a more sensitive protection can be obtained by improving the value of the dynamic resistance RDYN, due to the presence of the two Zener diodes 510 and 512 in parallel ( Figure 4 ), so the device 100 has an improved series resistance.

[0115] As reference Figure 3 As discussed, the base region 390 extending inside the wall 340 by approximately 30% of the length L of the base region 390 in the first direction X enables a reduction of approximately 8.5% in the clamping voltage VCL for the same current IF. In other words, at the same voltage VF, the transistor 500 can deliver a larger current IF than a transistor having the base region 390 that does not penetrate into the peripheral insulating wall 340.

[0116] In particular, a device for preventing electrostatic discharge makes it possible to obtain a holding voltage VHOLD greater than 5V while maintaining a blocking voltage VCL less than 7V, the device for preventing electrostatic discharge comprising the device as described above with reference to Figures 1 to 3 At least one device 100 is described. Thus, this protection device is compatible with applications where the limit voltage VRM is between approximately 0V and approximately 5V, preferably between 0V and 5V. Figure 4 ) exists, the desired holding voltage VHOLD value is obtained.

[0117] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, the previously described Figures 1 to 5 The description is based on an embodiment of the device 100 including at least one lateral NPN transistor 500. However, the conductivity type (doping) used as an example in this disclosure can be reversed. In particular, based on the instructions provided above, it is within the capabilities of a person skilled in the art to adapt such an embodiment to a device 100 including at least one lateral PNP transistor.

[0118] Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, based on the indications above, the connection of the contact traces of the transistor 500 included in the device 100 across the circuit(s) and / or discrete components to be protected is within the capabilities of a person skilled in the art.

[0119] The various embodiments described above can be combined to provide additional embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to encompass all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. An electronic device comprising a substrate, the substrate comprising: trap; a peripheral insulating wall laterally surrounding the well; as well as at least one lateral bipolar transistor formed in the well, the at least one lateral bipolar transistor having a base region extending below parallel collector and emitter regions; The peripheral insulating wall is widened in a first direction parallel to the collector region and the emitter region so that the base region penetrates into the peripheral insulating wall, wherein: The substrate has a first conductivity type; The peripheral insulating wall has the first conductivity type; The base region has the first conductivity type; The well has a second conductivity type different from the first conductivity type; and The collector region and the emitter region have the second conductivity type. 2 . The device of claim 1 , wherein the base region is spaced apart from the peripheral insulating wall in a second direction perpendicular to the first direction. 3 . The device according to claim 1 , wherein the base region penetrates into the peripheral insulating wall by a distance in the range of 20% to 50% of the length of the base region in the first direction. 4 . The device according to claim 1 , wherein the base region penetrates into the peripheral insulating wall by a distance of 30% of a length of the base region in the first direction. The device of claim 1 , wherein the first conductivity type is p-type, and the second conductivity type is n-type. The device of claim 1 , wherein the first conductivity type is n-type, and the second conductivity type is p-type.

7. The apparatus according to claim 1, further comprising: a first contact trace vertically aligned with the collector region; as well as A second contact trace is vertically aligned with the emitter region.

8. An electrostatic discharge protection device, comprising: At least one electronic device comprising: substrate; a well in the substrate; a peripheral insulating wall laterally surrounding the well; and at least one lateral bipolar transistor in the well, the at least one lateral bipolar transistor having a collector region, an emitter region, and a base region, the collector region and the emitter region extending in a first direction and laterally spaced apart from each other in a second direction perpendicular to the first direction, the base region extending under the collector region and the emitter region, wherein the base region has a width extending into the peripheral insulating wall along the first direction, wherein: The substrate has a first conductivity type; The peripheral insulating wall has the first conductivity type; The base region has the first conductivity type; The well has a second conductivity type different from the first conductivity type; and The collector region and the emitter region have the second conductivity type. 9 . The device of claim 8 , wherein the ESD protection device has a holding voltage greater than 5V and a clamping voltage less than 7V.

10. The apparatus according to claim 8, configured to protect applications with a limit voltage between 0V and 5V.

11. The apparatus according to claim 8, further comprising: an input / output (IO) terminal electrically coupled to the collector region of the at least one lateral bipolar transistor, Wherein the emitter region of the at least one lateral bipolar transistor is electrically coupled to electrical ground.

12. The apparatus according to claim 11, further comprising: a first Zener diode having an anode electrically connected to the base region of the at least one lateral bipolar transistor, the first Zener diode having a cathode electrically connected to the collector region of the at least one lateral bipolar transistor; as well as A second Zener diode has an anode electrically connected to the base region of the at least one lateral bipolar transistor, and a cathode electrically connected to the collector region of the at least one lateral bipolar transistor.

13. An electronic device comprising: substrate; a well in the substrate; a peripheral insulating wall laterally surrounding the well; as well as a lateral bipolar transistor in the well, the lateral bipolar transistor having a collector region, an emitter region, and a base region, the collector region and the emitter region extending in a first direction and laterally spaced apart from each other in a second direction perpendicular to the first direction, the base region extending under the collector region and the emitter region, wherein the base region has a width extending into the peripheral insulating wall along the first direction, wherein: The substrate has a first conductivity type; The peripheral insulating wall has the first conductivity type; The base region has the first conductivity type; The well has a second conductivity type different from the first conductivity type; and The collector region and the emitter region have the second conductivity type. 14 . The device of claim 13 , wherein a width of the peripheral insulating wall along the first direction is greater than a width of the well along the first direction. 15 . The device according to claim 13 , wherein the base region penetrates into the peripheral insulating wall by a distance in the range of 20% to 50% of a length of the base region in the first direction. 16 . The device according to claim 13 , wherein the base region penetrates into the peripheral insulating wall by a distance of 30% of a length of the base region in the first direction.

17. The apparatus according to claim 13, further comprising: a first contact trace extending along the first direction and covering the collector region; as well as A second contact trace extends along the first direction and covers the emitter region, the second contact trace being laterally spaced apart from the first contact trace along the second direction.

18. The apparatus according to claim 17, further comprising: A passivation layer is provided on the substrate, each of the first contact trace and the second contact trace at least partially contacting the passivation layer.

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