Semiconductor device including a barrier layer

Abstract

The present invention discloses a semiconductor device including a barrier layer, the semiconductor device including a plurality of magnetic tunnel junction (MTJ) structures in an interlayer insulating layer on a substrate. The barrier layer is on the interlayer insulating layer and the plurality of MTJ structures. The upper insulating layer is on the barrier layer. The upper interconnect is on the upper insulating layer. The upper plug is connected to a corresponding one of the plurality of MTJ structures and the upper interconnect and extends into the upper insulating layer and the barrier layer. The barrier layer includes a material having a higher absorption constant than the upper insulating layer.

Description

Technical Field

[0001] Devices and methods consistent with example embodiments relate to a semiconductor device including a barrier layer and a method of forming the semiconductor device. Background Art

[0002] A semiconductor device including an upper insulating layer and an upper interconnection on a magnetic tunnel junction (MTJ) structure has been studied. A process of forming the upper interconnection may include multiple plasma etching processes. In the process of forming the upper interconnection, the MTJ structure may be damaged. Summary of the invention

[0003] Example embodiments of the inventive concepts are directed to providing a semiconductor device that is advantageous in improving mass production efficiency and has excellent electrical performance, and a method of forming the semiconductor device.

[0004] According to an example embodiment, a semiconductor device is provided, the semiconductor device including a plurality of magnetic tunnel junction (MTJ) structures in an interlayer insulating layer on a substrate. A barrier layer is on the interlayer insulating layer and the plurality of MTJ structures. An upper insulating layer is on the barrier layer, the barrier layer including a material having a higher absorption constant than the upper insulating layer. An upper interconnect is on the upper insulating layer; an upper plug is connected to the upper interconnect and the MTJ of the plurality of MTJ structures and extends into the upper insulating layer and the barrier layer.

[0005] According to an example embodiment, a semiconductor device is provided, which includes a logic circuit area on a substrate. A variable resistance area is on the logic circuit area, and the variable resistance area includes a plurality of variable resistance elements in an interlayer insulating layer. An interconnection area is on the variable resistance area. The interconnection area includes a first upper insulating layer on a first barrier layer and a first barrier layer on a first etch stop layer. The first barrier layer includes a material having an absorption constant higher than that of the first upper insulating layer and the first etch stop layer. A first upper interconnection is on the first upper insulating layer, and a first upper plug is connected to a corresponding one of the plurality of variable resistance elements and the first upper interconnection and extends into the first upper insulating layer, the first barrier layer, and the first etch stop layer.

[0006] According to an example embodiment, a semiconductor device is provided, the semiconductor device including a plurality of MTJ structures in an interlayer insulating layer on a substrate. An etch stop layer is on the interlayer insulating layer and the plurality of MTJ structures. At least one barrier layer is on the etch stop layer and includes a non-magnetic metal layer. A first upper insulating layer is on the at least one barrier layer. An upper interconnect is on the first upper insulating layer. An upper plug is connected to a corresponding one of the plurality of MTJ structures and the upper interconnect and extends into the first upper insulating layer, the at least one barrier layer, and the etch stop layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 8is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0008] Figures 9 to 16 is a cross-sectional view illustrating a method of forming a semiconductor device according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0009] Although the terms "first", "second", "third", etc. may be used herein to describe various elements, components and / or layers, these elements, components and / or layers should not be limited by these terms. These terms are only used to distinguish one element, component and / or layer from another element, component and / or layer. Therefore, without departing from the scope of the present disclosure, the first element, component or layer discussed below may be referred to as a second element, component or layer.

[0010] Similarly, for ease of description, spatial relational terms such as "below", "above", etc. may be used herein to describe the relationship of an element or feature to other element(s) or feature(s) as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, the spatial relational terms are also intended to cover other different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relational descriptors used herein are interpreted accordingly. In addition, when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may be one or more other intervening elements.

[0011] Figures 1 to 8 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0012] When the term "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a tolerance of ±10% around the numerical value. When a range is specified, the range includes all values ​​therebetween in increments such as 0.1%.

[0013] Reference Figure 1 , a semiconductor device according to an embodiment of the inventive concept may include a logic circuit region LC on a substrate 21. The logic circuit region LC may include various logic circuits such as a switching element, a memory controller, an application processor, a microprocessor, or a combination thereof.

[0014] In one embodiment, the logic circuit region LC may include a plurality of active regions 23, a device isolation layer 25, a plurality of source / drain regions 27, a gate dielectric layer 28, a plurality of gate electrodes 29, a plurality of gate spacers 31, a plurality of gate capping layers 32, a first lower insulating layer 33, a source plug 34, a source line 35, a second lower insulating layer 37, a plurality of lower plugs 38, and a plurality of lower interconnections 39. The plurality of source / drain regions 27, the gate dielectric layer 28, and the gate electrode 29 may constitute a plurality of transistors 30. Each of the plurality of transistors 30 may include a fin field effect transistor (finFET), a multi-bridge channel (MBC) transistor, a nanowire transistor, a vertical transistor, a recessed channel transistor, a three-dimensional (3D) transistor, a planar transistor, or a combination thereof.

[0015] The substrate 21 may include a semiconductor substrate such as a silicon wafer or a silicon on insulator (SOI) wafer. The plurality of transistors 30 may be in and / or on the substrate 21. For example, some of the plurality of transistors 30 may be in the substrate 21 and the rest of the transistors may be on the substrate 21, all of the plurality of transistors 30 may be on the substrate 21, or all of the plurality of transistors 30 may be in the substrate 21. Some of the plurality of transistors 30 may be used as switching elements. The active region 23 may be defined in the substrate 21 by a device isolation layer 25. The plurality of gate electrodes 29 may be on the active region 23. The gate dielectric layer 28 may be between the plurality of gate electrodes 29 and the active region 23. The plurality of source / drain regions 27 may be formed in the active region 23 on both sides of each of the plurality of gate electrodes 29. The plurality of gate spacers 31 may be on the sidewalls of the plurality of gate electrodes 29. The plurality of gate capping layers 32 may be on the plurality of gate electrodes 29.

[0016] A first lower insulating layer 33 may be on the plurality of source / drain regions 27 and the device isolation layer 25. A source line 35 may be on the first lower insulating layer 33. A source plug 34 may be in the first lower insulating layer 33. The source plug 34 may pass through the first lower insulating layer 33 and contact a corresponding one of the plurality of source / drain regions 27. A second lower insulating layer 37 may be on the first lower insulating layer 33. The plurality of lower plugs 38 and the plurality of lower interconnections 39 may be in the first lower insulating layer 33 and the second lower insulating layer 37. Some of the plurality of lower plugs 38 and the plurality of lower interconnections 39 may be electrically connected to a corresponding one of the plurality of source / drain regions 27.

[0017] Each of the plurality of gate electrodes 29, the source plugs 34, the source lines 35, the plurality of lower plugs 38, and the plurality of lower interconnections 39 may be formed of a conductive material, and the conductive material may be: a metal, such as aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), silver (Ag), platinum (Pt), ruthenium (Ru), tungsten (W), tantalum (Ta), and / or titanium (Ti); a conductive ceramic (e.g., a metal nitride, such as titanium nitride (TiN), zirconium nitride (ZrN), hafnium nitride (HfN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), MoN, and / or tungsten nitride (WN)); a metal oxide, such as zirconium oxide (ZnO), indium oxide (InO), or both. 2 O 3 ), fluorine-doped tin oxide (FTO), indium tin oxide (ITO) and / or aluminum-doped zinc oxide (AZO); and / or metal silicides, such as nickel silicide (NiSi), magnesium silicide (Mg 2 Si), molybdenum disilicide (MoSi 2 ) and / or tungsten disilicide (WSi 2 ); polysilicon; conductive carbon; or a combination thereof. The gate dielectric layer 28 may be an insulator. For example, the gate dielectric layer 28 may be silicon oxide, silicon nitride, silicon oxynitride, such as hafnium silicate (HfSiO 4 ), zirconium silicate (ZrSiO 4 ), hafnium oxide (HfO 2 ) and / or zirconium oxide (ZrO 2 ), or a combination thereof. The plurality of gate spacers 31 may be an insulator, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The plurality of gate cap layers 32 may include silicon nitride. Each of the device isolation layer 25, the first lower insulating layer 33, and the second lower insulating layer 37 may be an insulator, and may be silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof.

[0018] The variable resistance region VR may be on the logic circuit region LC. The variable resistance region VR may include a plurality of variable resistance elements 45 and 55 in the plurality of interlayer insulating layers 48 and 58. The plurality of variable resistance elements 45 and 55 may include a magnetoresistive random access memory (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FeRAM) or a combination thereof. In one embodiment, the variable resistance region VR may include a plurality of first lower electrodes 41, a plurality of first variable resistance elements 45, a plurality of first upper electrodes 46, a first storage spacer 47, a first interlayer insulating layer 48, a first intermediate interconnect 49, a plurality of second lower electrodes 51, a plurality of second variable resistance elements 55, a plurality of second upper electrodes 56, a second storage spacer 57, a second interlayer insulating layer 58, a plurality of second intermediate interconnects 59 and a third interlayer insulating layer 60.

[0019] The semiconductor device may include a nonvolatile memory device such as an MRAM or a cross-point (X-point) memory. The semiconductor device may include an embedded MRAM (eMRAM). In one embodiment, each of the plurality of first variable resistance elements 45 and the plurality of second variable resistance elements 55 may include a magnetic tunnel junction (MTJ) structure. Each of the plurality of first variable resistance elements 45 and the plurality of second variable resistance elements 55 may include an in-plane MTJ (iMTJ) or a perpendicular MTJ (pMTJ). For example, each of the plurality of first variable resistance elements 45 may include a first reference layer 42, a first tunnel layer 43, and a first storage layer 44. Each of the plurality of second variable resistance elements 55 may include a second reference layer 52, a second tunnel layer 53, and a second storage layer 54.

[0020] The plurality of first lower electrodes 41, the plurality of first variable resistance elements 45, the plurality of first upper electrodes 46, and the first storage spacer 47 may be in the first interlayer insulating layer 48. The plurality of first variable resistance elements 45 may be between the plurality of first lower electrodes 41 and the plurality of first upper electrodes 46. The first storage spacer 47 may be on side surfaces of the plurality of first lower electrodes 41, the plurality of first variable resistance elements 45, and the plurality of first upper electrodes 46.

[0021] Each of the plurality of first lower electrodes 41 may be connected to the plurality of source / drain regions 27 via the plurality of lower plugs 38 and / or the plurality of lower interconnections 39. Each of the plurality of first variable resistance elements 45 may be connected to the plurality of transistors 30 via the plurality of first lower electrodes 41, the plurality of lower plugs 38, and / or the plurality of lower interconnections 39. Each of the plurality of first variable resistance elements 45 may include a first reference layer 42, a first memory layer 44 on the first reference layer 42, and a first tunnel layer 43 between the first reference layer 42 and the first memory layer 44.

[0022] The first intermediate interconnection 49 may be on the first interlayer insulating layer 48 and connected to the plurality of first upper electrodes 46. The second interlayer insulating layer 58 may cover the first interlayer insulating layer 48 and the first intermediate interconnection 49.

[0023] The plurality of second lower electrodes 51, the plurality of second variable resistance elements 55, the plurality of second upper electrodes 56, and the second storage spacer 57 may be in the second interlayer insulating layer 58. The plurality of second variable resistance elements 55 may be between the plurality of second lower electrodes 51 and the plurality of second upper electrodes 56. The second storage spacer 57 may be on the side surfaces of the plurality of second lower electrodes 51, the plurality of second variable resistance elements 55, and the plurality of second upper electrodes 56. The plurality of second lower electrodes 51 may be connected to the first intermediate interconnection 49. Each of the plurality of second variable resistance elements 55 may include a second reference layer 52, a second storage layer 54 on the second reference layer 52, and a second tunnel layer 53 between the second reference layer 52 and the second storage layer 54.

[0024] The third interlayer insulating layer 60 may be on the second interlayer insulating layer 58. The plurality of second intermediate interconnections 59 may be in the third interlayer insulating layer 60 and connected to the plurality of second upper electrodes 56.

[0025] Each of the plurality of first lower electrodes 41, the plurality of first upper electrodes 46, the first intermediate interconnection 49, the plurality of second lower electrodes 51, the plurality of second upper electrodes 56, and the plurality of second intermediate interconnections 59 may include a conductive material such as metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof. The conductive material of the plurality of first lower electrodes 41, the plurality of first upper electrodes 46, the first intermediate interconnection 49, the plurality of second lower electrodes 51, the plurality of second upper electrodes 56, and the plurality of second intermediate interconnections 59 may be the same or different material as the lower interconnection 39. Each of the first reference layer 42 and the second reference layer 52 may include a pinned layer, a fixed layer, or a combination thereof. Each of the first reference layer 42 and the second reference layer 52 may include a ferromagnetic material. Each of the first reference layer 42 and the second reference layer 52 may include a synthetic antiferromagnetic (SAF) structure. The SAF structure may include two magnetic layers and a spacer layer interposed between the two magnetic layers. For example, the SAF structure may include a cobalt / iron / boron (CoFeB) layer, a ruthenium (Ru) layer, and a cobalt iron (CoFe) layer stacked sequentially.

[0026] Each of the first storage layer 44 and the second storage layer 54 may include a free layer. Each of the first storage layer 44 and the second storage layer 54 may include CoFe, CoFeB, or a combination thereof. Each of the first storage layer 44 and the second storage layer 54 may include a SAF structure. Each of the first tunnel layer 43 and the second tunnel layer 53 may correspond to a tunnel barrier layer. Each of the first tunnel layer 43 and the second tunnel layer 53 may include a metal oxide, such as magnesium oxide (MgO), ruthenium oxide (RuO), vanadium oxide (VO), tungsten oxide (WO), tantalum oxide (TaO), hafnium oxide (HfO), molybdenum oxide (MoO), or a combination thereof. For example, each of the first tunnel layer 43 and the second tunnel layer 53 may be a MgO layer.

[0027] Each of the first storage spacer 47 and the second storage spacer 57 may include a material having a higher absorption constant K than the first interlayer insulating layer 48, the second interlayer insulating layer 58, and the third interlayer insulating layer 60. The absorption constant K may be a thermal conductivity of the material. The absorption constant K may also be an optical absorption coefficient of the material for a wavelength of light such as ultraviolet (UV).

[0028] Each of the first interlayer insulating layer 48 , the second interlayer insulating layer 58 , and the third interlayer insulating layer 60 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof.

[0029] The interconnection region BE may be on the variable resistance region VR. In one embodiment, the interconnection region BE may include a first etch stop layer 71, a first barrier layer 72, a first upper insulating layer 73, a second barrier layer 74, a second upper insulating layer 75, a third barrier layer 76, a first upper plug 77, a first upper interconnection 79, a second etch stop layer 81, a fourth barrier layer 82, a third upper insulating layer 83, a fourth upper insulating layer 85, a second upper plug 87, a second upper interconnection 89, a third etch stop layer 91, a fifth barrier layer 92, a fifth upper insulating layer 93, a sixth upper insulating layer 95, and a third upper plug 97.

[0030] The first etch stop layer 71 may cover the third interlayer insulating layer 60 and the plurality of second intermediate interconnections 59. The first barrier layer 72, the first upper insulating layer 73, the second barrier layer 74, the second upper insulating layer 75, and the third barrier layer 76 may be sequentially stacked on the first etch stop layer 71. The first upper plug 77 may be in the first etch stop layer 71, the first barrier layer 72, the first upper insulating layer 73, the second barrier layer 74, the second upper insulating layer 75, and the third barrier layer 76. The first upper interconnection 79 may be on the third barrier layer 76. The first upper plug 77 may pass through the first etch stop layer 71, the first barrier layer 72, the first upper insulating layer 73, the second barrier layer 74, the second upper insulating layer 75, and the third barrier layer 76, and contact a corresponding one of the plurality of second intermediate interconnections 59 and the first upper interconnection 79.

[0031] Each of the first upper plug 77 and the first upper interconnect 79 may include a conductive material such as a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof. Each of the first upper insulating layer 73 and the second upper insulating layer 75 may include an insulator such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof. In one embodiment, the first upper insulating layer 73 may include a silicon oxide layer formed using tetraethyl orthosilicate (TEOS). The second upper insulating layer 75 may include a material layer that is relatively more flowable than the first upper insulating layer 73. The second upper insulating layer 75 may include a silicon oxide layer formed using flowable TEOS (FTEOS).

[0032] The first etch stop layer 71 may include a material having an etch selectivity with respect to the first upper insulating layer 73, the second upper insulating layer 75, the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76. In an implementation, the first etch stop layer 71 may include silicon carbon nitride (SiCN).

[0033] Each of the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76 may include a material having a higher absorption constant K than the first etch stop layer 71, the first upper insulating layer 73, and the second upper insulating layer 75. Each of the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76 may include silicon oxynitride (SiON). Each of the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76 may include a silicon oxynitride layer formed at a process temperature of 250° C. to 350° C. Each of the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76 may be thicker than the first etch stop layer 71. Each of the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76 may have a thickness of 10 nm to 100 nm.

[0034] In an implementation, each of the first storage spacer 47 and the second storage spacer 57 may include a material having a higher absorption constant K than the first etch stop layer 71, the first upper insulating layer 73, and the second upper insulating layer 75. Each of the first storage spacer 47 and the second storage spacer 57 may include silicon oxynitride.

[0035] The second etch stop layer 81, the fourth barrier layer 82, the third upper insulating layer 83, and the fourth upper insulating layer 85 may be sequentially stacked on the third barrier layer 76 and the first upper interconnection 79. The second upper plug 87 may be in the second etch stop layer 81, the fourth barrier layer 82, the third upper insulating layer 83, and the fourth upper insulating layer 85. The second upper interconnection 89 may be on the fourth upper insulating layer 85. The second upper plug 87 may pass through the second etch stop layer 81, the fourth barrier layer 82, the third upper insulating layer 83, and the fourth upper insulating layer 85, and contact the first upper interconnection 79 and the second upper interconnection 89.

[0036] The third etch stop layer 91, the fifth barrier layer 92, the fifth upper insulating layer 93, and the sixth upper insulating layer 95 may be sequentially stacked on the fourth upper insulating layer 85 and the second upper interconnection 89. The third upper plug 97 may be in the third etch stop layer 91, the fifth barrier layer 92, the fifth upper insulating layer 93, and the sixth upper insulating layer 95. The third upper plug 97 may pass through the third etch stop layer 91, the fifth barrier layer 92, the fifth upper insulating layer 93, and the sixth upper insulating layer 95 and contact the second upper interconnection 89.

[0037] Each of the second upper plug 87, the second upper interconnection 89, and the third upper plug 97 may be formed of a conductor such as metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof. Each of the third upper insulating layer 83 and the fifth upper insulating layer 93 may include a configuration similar to that of the first upper insulating layer 73. Each of the third upper insulating layer 83 and the fifth upper insulating layer 93 may include a silicon oxide layer formed using TEOS.

[0038] Each of the fourth upper insulating layer 85 and the sixth upper insulating layer 95 may include a configuration similar to that of the second upper insulating layer 75. For example, each of the fourth upper insulating layer 85 and the sixth upper insulating layer 95 may include a silicon oxide layer formed using FTEOS.

[0039] Each of the second etch stop layer 81 and the third etch stop layer 91 may include a configuration similar to that of the first etch stop layer 71. For example, each of the second etch stop layer 81 and the third etch stop layer 91 may include silicon carbon nitride. Each of the fourth barrier layer 82 and the fifth barrier layer 92 may include a configuration similar to that of the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76. For example, each of the fourth barrier layer 82 and the fifth barrier layer 92 may include a material having an absorption constant K higher than that of the second etch stop layer 81, the third upper insulating layer 83, the fourth upper insulating layer 85, the third etch stop layer 91, the fifth upper insulating layer 93, and the sixth upper insulating layer 95. Each of the fourth barrier layer 82 and the fifth barrier layer 92 may include silicon oxynitride.

[0040] The first passivation layer 113, the input / output (I / O) terminal 115, the second passivation layer 117, the opening 119W, and the bump 129 may be above the interconnection area BE. The bump 129 may include a pillar structure 125 and a solder 127 on the pillar structure 125. The pillar structure 125 may include a barrier layer 121, a seed layer 122, and a pillar 123. The I / O terminal 115 may include a bump, a bonding pad, or a bonding finger.

[0041] The first passivation layer 113 may cover the sixth upper insulating layer 95. The first passivation layer 113 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof. The first passivation layer 113 may include a silicon oxide layer formed using TEOS.

[0042] The I / O terminal 115 may be in the first passivation layer 113. The I / O terminal 115 may contact the third upper plug 97. The I / O terminal 115 may be connected to a corresponding one of the plurality of second intermediate interconnects 59 via the third upper plug 97, the second upper interconnect 89, the second upper plug 87, the first upper interconnect 79, and the first upper plug 77. The I / O terminal 115 may be electrically connected to at least one of the plurality of first variable resistance elements 45 and the plurality of second variable resistance elements 55. The I / O terminal 115 may be a conductor, such as a metal, a metal nitride, a metal silicide, a metal oxide, a conductive carbon, or a combination thereof. For example, the I / O terminal 115 may include aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), silver (Ag), platinum (Pt), ruthenium (Ru), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0043] The second passivation layer 117 may cover the I / O terminal 115 and the first passivation layer 113. The second passivation layer 117 may be an insulator such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, photosensitive polyimide (PSPI), or a combination thereof. The opening 119W may pass through the second passivation layer 117. The bump 129 may be on the second passivation layer 117. The bump 129 may extend through the opening 119W into the second passivation layer 117 and contact the upper surface of the I / O terminal 115.

[0044] The barrier layer 121 may include Ti, TiN, Ta, TaN, or a combination thereof. The seed layer 122 may include copper (Cu). The pillar 123 may include a conductive material such as nickel (Ni), copper (Cu), aluminum (Al), silver (Ag), platinum (Pt), ruthenium (Ru), tin (Sn), gold (Au), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The solder 127 may include Sn, Ag, Cu, Ni, Au, or a combination thereof. For example, the solder 127 may be a layer of a eutectic alloy such as Sn-Ag-Cu.

[0045] The formation of the first upper plug 77, the first upper interconnect 79, the second upper plug 87, the second upper interconnect 89, the third upper plug 97 and the I / O terminal 115 may include a plurality of patterning processes. The plurality of patterning processes may include an etching process using plasma. The first barrier layer 72, the second barrier layer 74, the third barrier layer 76, the fourth barrier layer 82 and the fifth barrier layer 92 may prevent damage to the plurality of first variable resistance elements 45 and the plurality of second variable resistance elements 55 during the plurality of patterning processes.

[0046] Reference Figure 2, a semiconductor device according to an embodiment of the present inventive concept may include a substrate 21, an active region 23, a device isolation layer 25, a plurality of source / drain regions 27, a gate dielectric layer 28, a plurality of gate electrodes 29, a plurality of gate spacers 31, a plurality of gate capping layers 32, a first lower insulating layer 33, a source plug 34, a source line 35, a second lower insulating layer 37, a plurality of lower plugs 38, a plurality of first lower electrodes 41, a plurality of first variable resistance elements 45, a plurality of first upper electrodes 46, a first storage spacer 47, a first Interlayer insulating layer 48, a plurality of second intermediate interconnections 59, a third interlayer insulating layer 60, a first etch stop layer 71, a first barrier layer 72, a first upper insulating layer 73, a second barrier layer 74, a second upper insulating layer 75, a third barrier layer 76, a first upper plug 77, a first upper interconnection 79, a third etch stop layer 91, a fifth barrier layer 92, a fifth upper insulating layer 93, a sixth upper insulating layer 95, a third upper plug 97, a first passivation layer 113, an I / O terminal 115, a second passivation layer 117, and an opening 119W. The same reference numerals denote the same elements, and a detailed description thereof will not be repeated.

[0047] The plurality of first variable resistance elements 45 may be connected to the plurality of transistors 30 via the plurality of first lower electrodes 41 and the plurality of lower plugs 38. Each of the plurality of transistors 30 may function as a switching element. An opening 119W may pass through the second passivation layer 117. An upper surface of the I / O terminal 115 may be partially exposed within the opening 119W.

[0048] A lateral width of a portion of the first upper plug 77 adjacent to the first barrier layer 72 may be greater than a lateral width of a portion of the first upper plug 77 adjacent to the first upper insulating layer 73. A lateral width of a portion of the first upper plug 77 adjacent to the first etch stop layer 71 may be greater than a lateral width of a portion of the first upper plug 77 adjacent to the first barrier layer 72. A lateral width of a portion of the first upper plug 77 adjacent to the second barrier layer 74 may be greater than a lateral width of a portion of the first upper plug 77 adjacent to the second upper insulating layer 75. A lateral width of a portion of the first upper plug 77 adjacent to the third barrier layer 76 may be greater than a lateral width of a portion of the first upper plug 77 adjacent to the second upper insulating layer 75.

[0049] Reference Figure 3, a lateral width of a portion of the first upper plug 77A adjacent to the first barrier layer 72 may be substantially equal to a lateral width of a portion of the first upper plug 77A adjacent to the first upper insulating layer 73. A lateral width of a portion of the first upper plug 77A adjacent to the first etch stop layer 71 may be greater than a lateral width of a portion of the first upper plug 77A adjacent to the first barrier layer 72. A lateral width of a portion of the first upper plug 77A adjacent to the second barrier layer 74 may be substantially equal to a lateral width of a portion of the first upper plug 77A adjacent to the second upper insulating layer 75. A lateral width of a portion of the first upper plug 77A adjacent to the third barrier layer 76 may be substantially equal to a lateral width of a portion of the first upper plug 77A adjacent to the second upper insulating layer 75.

[0050] In addition, a lateral width of a portion of the third upper plug 97A adjacent to the fifth barrier layer 92 may be substantially equal to a lateral width of a portion of the third upper plug 97A adjacent to the fifth upper insulating layer 93, and may be substantially equal to a lateral width of a portion of the third upper plug 97A adjacent to the sixth upper insulating layer 95. A lateral width of a portion of the third upper plug 97A adjacent to the third etch stop layer 91 may be greater than a lateral width of a portion of the third upper plug 97A adjacent to the fifth barrier layer 92.

[0051] Reference Figure 4 , the first barrier layer 72, the first upper insulating layer 73, and the second upper insulating layer 75 may be sequentially stacked on the first etch stop layer 71. The first upper interconnection 79 may be on the second upper insulating layer 75. The first upper plug 77B may pass through the first etch stop layer 71, the first barrier layer 72, the first upper insulating layer 73, and the second upper insulating layer 75. The lateral width of a portion of the first upper plug 77B adjacent to the first etch stop layer 71 may be greater than the lateral width of a portion of the first upper plug 77B adjacent to the first barrier layer 72 and the lateral width of a portion of the first upper plug 77B adjacent to the second upper insulating layer 75. The lateral width of a portion of the first upper plug 77B adjacent to the first barrier layer 72 may also be greater than the lateral width of a portion of the first upper plug 77B adjacent to the first upper insulating layer 73 and the second upper insulating layer 75.

[0052] Reference Figure 5, the first barrier layer 72, the first upper insulating layer 73, the second barrier layer 74, and the second upper insulating layer 75 may be sequentially stacked on the first etch stop layer 71. The first upper interconnection 79 may be on the second upper insulating layer 75. The first upper plug 77C may pass through the first etch stop layer 71, the first barrier layer 72, the first upper insulating layer 73, the second barrier layer 74, and the second upper insulating layer 75. The lateral width of a portion of the first upper plug 77C adjacent to the first etch stop layer 71 may be greater than the lateral width of a portion of the first upper plug 77C adjacent to the first barrier layer 72 and the lateral width of a portion of the first upper plug 77C adjacent to the second upper insulating layer 75. The lateral width of the portion of the first upper plug 77C adjacent to the first barrier layer 72 may also be greater than the lateral width of the portion of the first upper plug 77C adjacent to the first upper insulating layer 73 and the second upper insulating layer 75, and the lateral width of the portion of the first upper plug 77C adjacent to the second barrier layer 74 may also be greater than the lateral width of the portion of the first upper plug 77C adjacent to the first upper insulating layer 73 and the second upper insulating layer 75.

[0053] Reference Figure 6 , the first barrier layer 72, the first upper insulating layer 73, the second upper insulating layer 75, and the third barrier layer 76 may be sequentially stacked on the first etch stop layer 71. The first upper interconnection 79 may be on the third barrier layer 76. The first upper plug 77D may pass through the first etch stop layer 71, the first barrier layer 72, the first upper insulating layer 73, the second upper insulating layer 75, and the third barrier layer 76. The lateral width of a portion of the first upper plug 77D adjacent to the first etch stop layer 71 may be greater than the lateral width of a portion of the first upper plug 77D adjacent to the first barrier layer 72 and the lateral width of a portion of the first upper plug 77D adjacent to the second upper insulating layer 75. The lateral width of the portion of the first upper plug 77D adjacent to the first barrier layer 72 may also be greater than the lateral width of the portion of the first upper plug 77D adjacent to the first upper insulating layer 73 and the second upper insulating layer 75, and the lateral width of the portion of the first upper plug 77D adjacent to the third barrier layer 76 may also be greater than the lateral width of the portion of the first upper plug 77D adjacent to the first upper insulating layer 73 and the second upper insulating layer 75.

[0054] Reference Figure 7 , a first barrier layer 72, a first upper insulating layer 73, and a second upper insulating layer 75 may be sequentially stacked on the first etch stop layer 71. A first upper interconnection 79 may be on the second upper insulating layer 75. A first upper plug 77B may pass through the first etch stop layer 71, the first barrier layer 72, the first upper insulating layer 73, and the second upper insulating layer 75. A third etch stop layer 91, a fifth upper insulating layer 93, and a sixth upper insulating layer 95 may be sequentially stacked on the second upper insulating layer 75 and the first upper interconnection 79.

[0055] The third upper plug 97A may be in the third etch stop layer 91, the fifth upper insulating layer 93, and the sixth upper insulating layer 95. The third upper plug 97A may pass through the third etch stop layer 91, the fifth upper insulating layer 93, and the sixth upper insulating layer 95 and contact the first upper plug 77B.

[0056] Reference Figure 8 , a first barrier layer 72, a first upper insulating layer 73, a second barrier layer 74A, and a second upper insulating layer 75 may be sequentially stacked on the first etch stop layer 71. A first upper interconnection 79 may be on the second upper insulating layer 75. A first upper plug 77C may pass through the first etch stop layer 71, the first barrier layer 72, the first upper insulating layer 73, the second barrier layer 74A, and the second upper insulating layer 75. A contact spacer 277 may surround a side surface of the first upper plug 77C.

[0057] The second barrier layer 74A may include a non-magnetic metal layer. The contact spacer 277 may be interposed between the first upper plug 77C and the second barrier layer 74A, between the first upper plug 77C and the first barrier layer 72, and between the first upper plug 77C and the first etch stop layer 71. The spacer 277 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0058] Figures 9 to 16 is a cross-sectional view illustrating a method of forming a semiconductor device according to an example embodiment of the inventive concept.

[0059] Reference Fig. 9 An active region 23, a device isolation layer 25, a plurality of source / drain regions 27, a gate dielectric layer 28, a plurality of gate electrodes 29, a plurality of gate spacers 31, a plurality of gate capping layers 32, a first lower insulating layer 33, a source plug 34, a source line 35, a second lower insulating layer 37 and a plurality of lower plugs 38 may be formed on a substrate 21 in a logic circuit region LC.

[0060] Reference Fig.10 , a plurality of first lower electrodes 41, a plurality of first variable resistance elements 45, and a plurality of first upper electrodes 46 may be formed in the variable resistance region VR on the logic circuit region LC. Each of the plurality of first variable resistance elements 45 may include the first reference layer 42, the first tunnel layer 43, and the first memory layer 44 as discussed above.

[0061] Reference Fig.11, a first storage spacer 47 may be formed on side surfaces of the plurality of first lower electrodes 41, the plurality of first variable resistance elements 45, and the plurality of first upper electrodes 46. A first interlayer insulating layer 48 may be formed to cover the second lower insulating layer 37. An upper surface of the first interlayer insulating layer 48 and an upper surface of the plurality of first upper electrodes 46 may be substantially coplanar. A plurality of second intermediate interconnects 59 and a third interlayer insulating layer 60 may be formed on the first interlayer insulating layer 48. Each of the plurality of second intermediate interconnects 59 may be connected to a corresponding one of the plurality of first upper electrodes 46.

[0062] Reference Fig.12 A first etch stop layer 71, a first barrier layer 72, a first upper insulating layer 73, a second barrier layer 74, a second upper insulating layer 75, and a third barrier layer 76 may be sequentially stacked in the interconnection region BE on the variable resistance region VR. A mask pattern 298 may be formed on the third barrier layer 76.

[0063] Each of the first upper insulating layer 73 and the second upper insulating layer 75 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric or a combination thereof. In one embodiment, the first upper insulating layer 73 may include a silicon oxide layer formed using TEOS. The second upper insulating layer 75 may include a material layer that is relatively more flowable than the first upper insulating layer 73. The second upper insulating layer 75 may include a silicon oxide layer formed using FTEOS. The first upper insulating layer 73 and the second upper insulating layer 75 may be formed, for example, by the decomposition of TEOS and FTEOS. TEOS and FTEOS may be deposited on the first barrier layer 72 and the second barrier layer 74, respectively, via a chemical vapor deposition (CVD) process.

[0064] The first etch stop layer 71 may include a material having an etch selectivity with respect to the first upper insulating layer 73, the second upper insulating layer 75, the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76. In an implementation, the first etch stop layer 71 may include silicon carbon nitride.

[0065] Each of the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76 may include a material having a higher absorption constant K than the first etch stop layer 71, the first upper insulating layer 73, and the second upper insulating layer 75. Each of the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76 may include silicon oxynitride. Each of the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76 may include a silicon oxynitride layer formed using a low temperature deposition process performed at a process temperature of 250° C. to 350° C. Each of the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76 may be thicker than the first etch stop layer 71. Each of the first barrier layer 72, the second barrier layer 74, and the third barrier layer 76 may have a thickness of 10 nm to 100 nm.

[0066] Reference Fig.13 The mask pattern 298 may be used as an etching mask to form a contact hole 77H through the third barrier layer 76, the second upper insulating layer 75, the second barrier layer 74, the first upper insulating layer 73, and the first barrier layer 72. The first etch stop layer 71 may be exposed at the bottom of the contact hole 77H.

[0067] Reference Fig.14 , the contact hole 77H may be enlarged by etching the first etch stop layer 71. The plurality of second intermediate interconnects 59 may be exposed at the bottom of the contact hole 77H. The first to fourth undercut regions UC1, UC2, UC3, and UC4 may be formed during the etching of the first etch stop layer 71. The first undercut region UC1 may be formed adjacent to the first etch stop layer 71. The second undercut region UC2 may be formed adjacent to the first barrier layer 72. The third undercut region UC3 may be formed adjacent to the second barrier layer 74. The fourth undercut region UC4 may be formed adjacent to the third barrier layer 76. The mask pattern 298 may be removed to expose the upper surface of the third barrier layer 76. For example, the mask pattern 298 may be removed due to the etching of the first etch stop layer 71, or the mask pattern 298 may be removed in a separate process after the etching.

[0068] Reference Fig.15 , a first upper plug 77 may be formed inside the contact hole 77H. A first upper interconnection 79 may be formed on the third barrier layer 76 and contact the first upper plug 77 .

[0069] The formation of the first upper plug 77 and the first upper interconnect 79 may include a plurality of patterning processes. The plurality of patterning processes may include an etching process using plasma. The first barrier layer 72, the second barrier layer 74, and the third barrier layer 76 may prevent or reduce damage to the plurality of first variable resistance elements 45 during the plurality of patterning processes.

[0070] Reference Fig.16, a third etch stop layer 91, a fifth barrier layer 92, a fifth upper insulating layer 93, and a sixth upper insulating layer 95 may be sequentially stacked on the third barrier layer 76 and the first upper interconnection 79. A third upper plug 97 may be formed to pass through the sixth upper insulating layer 95, the fifth upper insulating layer 93, the fifth barrier layer 92, and the third etch stop layer 91 and contact the first upper interconnection 79.

[0071] The formation of the third upper plug 97 may include a patterning process. The patterning process may include an etching process using plasma. The first barrier layer 72, the second barrier layer 74, the third barrier layer 76, and the fifth barrier layer 92 may prevent damage to the plurality of first variable resistance elements 45 during the patterning process.

[0072] According to an example embodiment of the inventive concept, a semiconductor device can be provided, which includes a plurality of variable resistance elements, at least one barrier layer, an upper insulating layer, a plurality of upper plugs, and a plurality of upper interconnects. The at least one barrier layer may include a material having a higher absorption constant K than the upper insulating layer. The at least one barrier layer may prevent damage to the plurality of variable resistance elements during a process of forming the plurality of upper plugs and the plurality of upper interconnects. A semiconductor device that is conducive to improving mass production efficiency and has excellent electrical properties can be realized.

[0073] Although the embodiments of the present invention have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the present invention and without changing its essential features. Therefore, the above embodiments should be considered in a descriptive sense only, not for limiting purposes.

[0074] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0097396 filed on August 9, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a plurality of magnetic tunnel junction structures in an interlayer insulating layer on a substrate; a barrier layer on the interlayer insulating layer and the plurality of magnetic tunnel junction structures; an etch stop layer between the interlayer insulating layer and the barrier layer; an upper insulating layer on the barrier layer, the barrier layer comprising a material having a higher absorption constant than the upper insulating layer; an upper interconnect on the upper insulating layer; as well as An upper plug is connected to the upper interconnect and a magnetic tunnel junction structure among the plurality of magnetic tunnel junction structures and extends into the upper insulating layer, the barrier layer, and the etch stop layer.

2. The semiconductor device according to claim 1, wherein The barrier layer includes silicon oxynitride.

3. The semiconductor device according to claim 1, wherein The barrier layer has a thickness of 10 nm to 100 nm.

4. The semiconductor device according to claim 1, wherein: Each of the plurality of magnetic tunnel junction structures comprises: Reference layer; a storage layer on the reference layer; and A tunnel layer is provided between the reference layer and the storage layer. 5 . The semiconductor device according to claim 4 , further comprising a storage spacer on a side surface of each of the plurality of magnetic tunnel junction structures.

6. The semiconductor device according to claim 5, wherein: The storage spacer includes a material having a higher absorption constant than the upper insulating layer.

7. The semiconductor device according to claim 1, wherein The barrier layer includes a material having a higher absorption constant than the etch stop layer.

8. The semiconductor device according to claim 7, wherein: The barrier layer is thicker than the etch stop layer.

9. The semiconductor device according to claim 7, wherein: The etch stop layer includes silicon carbon nitride, and the barrier layer includes silicon oxynitride.

10. A semiconductor device comprising: a logic circuit region on the substrate; a variable resistance region on the logic circuit region, the variable resistance region including a plurality of variable resistance elements in an interlayer insulating layer; an interconnection region on the variable resistance region, the interconnection region comprising a first barrier layer on the first etch stop layer and a first upper insulating layer on the first barrier layer, the first barrier layer comprising a material having a higher absorption constant than the first upper insulating layer and the first etch stop layer; a first upper interconnect on the first upper insulating layer; as well as A first upper plug is connected to a corresponding one of the plurality of variable resistance elements and the first upper interconnection and extends into the first upper insulating layer, the first barrier layer, and the first etch stop layer.

11. The semiconductor device according to claim 10, wherein: The plurality of variable resistance elements include a magnetoresistive random access memory, a resistive random access memory, a ferroelectric random access memory, or a combination thereof.

12. The semiconductor device according to claim 10, wherein: The logic circuit area includes a plurality of transistors connected to the plurality of variable resistance elements.

13. The semiconductor device according to claim 10, further comprising: a second barrier layer between the first upper insulating layer and the first upper interconnect, The second barrier layer includes a material having a higher absorption constant than the first upper insulating layer and the first etch stop layer.

14. The semiconductor device according to claim 13, further comprising: a second upper insulating layer between the first upper insulating layer and the first upper interconnect; as well as a third barrier layer between the second upper insulating layer and the first upper interconnection, The third barrier layer includes a material having a higher absorption constant than the second upper insulating layer, the first upper insulating layer, and the first etch stop layer.

15. The semiconductor device according to claim 10, further comprising: a second upper insulating layer between the first upper insulating layer and the first upper interconnect; a second etch stop layer on the first upper interconnect; a fourth barrier layer on the second etch stop layer; a third upper insulating layer on the fourth barrier layer; a second upper interconnect on the third upper insulating layer; as well as a second upper plug connected to the first upper interconnect and the second upper interconnect and extending into the third upper insulating layer, the fourth barrier layer, and the second etch stop layer, The fourth barrier layer includes a material having a higher absorption constant than the third upper insulating layer and the second etch stop layer.

16. The semiconductor device according to claim 10, further comprising: input / output terminals above the interconnection region, Wherein, the input / output terminal includes a bump pad, a bonding pad or a bonding finger.

17. A semiconductor device comprising: a plurality of magnetic tunnel junction structures in an interlayer insulating layer on a substrate; an etch stop layer on the interlayer insulating layer and the plurality of magnetic tunnel junction structures; at least one barrier layer on the etch stop layer, the at least one barrier layer comprising a non-magnetic metal layer; a first upper insulating layer on the at least one barrier layer; an upper interconnect on the first upper insulating layer; as well as An upper plug connected to a corresponding one of the plurality of magnetic tunnel junction structures and the upper interconnect and extending into the first upper insulating layer, the at least one barrier layer, and the etch stop layer. 18 . The semiconductor device according to claim 17 , further comprising a contact spacer between the at least one barrier layer and the upper plug.

19. The semiconductor device according to claim 17, further comprising: a second upper insulating layer between the etch stop layer and the first upper insulating layer, wherein the at least one barrier layer comprises a first barrier layer between the etch stop layer and the second upper insulating layer and a second barrier layer between the second upper insulating layer and the first upper insulating layer, and The first barrier layer includes a material having a higher absorption constant than that of the second upper insulating layer, and the second barrier layer includes the non-magnetic metal layer.

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