DC-DC converter regulation circuit and method

Abstract

Embodiments of the present disclosure relate to DC-DC converter regulation circuits and methods. Embodiment DC-DC converter circuits include a DC-DC converter and a regulation circuit. The regulation circuit includes a comparator configured to detect an overshoot period during a discharge phase of the DC-DC converter, during which the output voltage of the DC-DC converter exceeds a target voltage, and a timer configured to measure the duration of the overshoot period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Application No. 1908993, filed on August 6, 2019, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of voltage converters, and in particular to a regulation circuit and method for regulating the output voltage of a DC-DC converter. Background Art

[0004] The operation of a direct current (DC) to DC converter typically involves generating an inductor current through an inductor during a charging phase of the converter, and then supplying the inductor current to the output of the DC-DC converter during a discharging phase of the converter. This operation causes the output voltage of the converter to drop during the charging phase and rise during at least a portion of the discharging phase.

[0005] In the case of boost and buck-boost converters, the difficulty is that the charging phase does not result in any voltage change at the converter's output, as the inductor does not supply current to the output during this phase. In the case of buck converters, the difficulty is that the charging phase is not solely responsible for the resulting voltage change. Therefore, in a buck, boost, or buck-boost converter, it is generally not possible to directly control the characteristics of the charging phase based on the level of the output voltage during the charging phase.

[0006] Therefore, there is a need in the art for an improved regulation circuit and method for regulating the output voltage of a DC-DC converter. Summary of the Invention

[0007] According to one aspect, a DC-DC conversion circuit is provided, comprising: a DC-DC converter; and a regulation circuit comprising: a comparator configured to detect an overshoot period during a discharge phase of the DC-DC converter, during which an output voltage of the DC-DC converter exceeds a target voltage; and a timer configured to measure a duration of the overshoot period.

[0008] According to one embodiment, the DC-DC converter comprises an inductor; and during a discharge phase of the DC-DC converter, the inductor current is supplied by the inductor to the output of the DC-DC converter.

[0009] According to one embodiment, the regulation circuit includes a controller configured to adjust a duration of an inductor charging phase and / or an inductor discharging phase of the DC-DC converter based on a duration of the overshoot period.

[0010] According to one embodiment, the regulation circuit further comprises a first further comparator configured to detect a rising voltage condition when the duration of the overshoot period exceeds a threshold level, and the controller is configured to adjust the duration of the inductor charging phase and / or the inductor discharging phase of the DC-DC converter in response to the detection of the rising voltage condition.

[0011] According to one embodiment, the regulating circuit further comprises a low-pass filter configured to generate the threshold level based on a plurality of previous values of the measured duration of the overshoot period.

[0012] According to one embodiment, the regulation circuit further comprises a second further comparator configured to detect a falling voltage condition when the duration of the overshoot period is below a threshold level, and the controller is further configured to adjust the duration of the inductor charging phase and / or the inductor discharging phase of the DC-DC converter in response to the detection of the falling voltage condition.

[0013] According to one embodiment, the timer comprises a counter configured to increment or decrement a count value during the overshoot period.

[0014] According to another aspect, an electronic device is provided, including: a DC power supply supplying a first voltage level; and the above-mentioned DC-DC conversion circuit, the DC-DC conversion circuit being configured to convert the first voltage level into an output voltage.

[0015] According to yet another aspect, a method of DC-DC conversion is provided, comprising: detecting an overshoot period during a discharge phase of the DC-DC converter, during which an output voltage of the DC-DC converter exceeds a target voltage period; and measuring a duration of the overshoot period.

[0016] According to one embodiment, during the discharge phase, an inductor current through the inductor of the DC-DC converter is supplied to the output of the DC-DC converter.

[0017] According to one embodiment, the method further comprises adjusting a duty cycle of the DC-DC converter based on the duration of the overshoot period.

[0018] According to one embodiment, the method further comprises detecting a rising voltage condition when the duration of the overshoot period exceeds a threshold level; and reducing the duration of the charging phase of the DC-DC converter in response to detecting the rising voltage condition.

[0019] According to one embodiment, the method further comprises generating the threshold level by applying a low pass filter to a plurality of previous values of the measured duration of the overshoot period.

[0020] According to one embodiment, the method further comprises detecting a falling voltage condition when the duration of the overshoot period is below a threshold level; and increasing the duration of the charging phase of the DC-DC converter in response to the detection of the falling voltage condition.

[0021] According to one embodiment, measuring the duration of the overshoot period includes incrementing or decrementing a count value during the overshoot period. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments, which are given by way of illustration only and not limitation, with reference to the accompanying drawings, in which:

[0023] Figure 1 is a circuit diagram of a DC-DC converter according to an example;

[0024] Figure 2 It shows Figure 1 A timing diagram of an example of signals in a circuit;

[0025] Figure 3 A DC-DC conversion circuit is schematically shown according to an example embodiment of the present disclosure;

[0026] Figure 4 According to an exemplary embodiment of the present disclosure, Figure 3 Overshoot detection circuit;

[0027] Figure 5 It shows Figure 4 A timing diagram of an example of signals in a circuit;

[0028] Figure 6 Another exemplary embodiment according to the present disclosure shows in more detail Figure 3 overshoot detection circuit; and

[0029] Figure 7 Yes Figure 3 Timing diagram of the measured signals in the circuit. DETAILED DESCRIPTION

[0030] In the various drawings, similar features have been indicated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0031] For the sake of clarity, only those operations and elements that are useful for understanding the embodiments described herein are described in detail and described. In particular, in the following, examples are described with respect to a boost converter, and specific circuit implementations of buck or buck-boost direct current (DC)-DC converters are not described in detail, as these circuits are well known to those skilled in the art. Furthermore, it will be apparent to those skilled in the art how to apply the described principles to buck converters and buck-boost converters.

[0032] Unless otherwise specified, when two elements are referred to as being connected together, this means a direct connection without any intermediate elements other than conductors, and when two elements are referred to as being linked or coupled together, this means the two elements may be connected or they may be linked or coupled via one or more other elements.

[0033] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean within ±10%, preferably within ±5%.

[0034] Figure 1 is a circuit diagram showing an example of a DC-DC converter 100 , which is a boost converter in this example.

[0035] The DC-DC converter 100 includes an inductor 102 coupled in series with a transistor 104 between an input power supply voltage rail VIN and a ground voltage rail. For example, the transistor 104 is an n-channel metal oxide semiconductor (NMOS) transistor, with its source connected to the ground voltage rail and its drain connected to the inductor 102. The transistor 104 is controlled by a phase signal φ. An intermediate node 106 between the inductor 102 and the transistor 104 is coupled to an output 108 of the converter 100, for example, via a diode 110. A capacitor 112 is coupled, for example, between the output node 108 and the ground voltage rail.

[0036] exist Figure 1 In FIG. 1 , the current flowing through the inductor 102 is labeled I_COIL, and the voltage at the output 108 is labeled VOUT.

[0037] Now refer to Figure 2 Describe in more detail Figure 1 Operation of the DC-DC converter 100.

[0038] Figure 2 It is shown in Figure 1 1 is a timing diagram of an example of the phase signal φ, the current I_COIL, and the output voltage VOUT (solid line curve) in the circuit of .

[0039] During the charging phase (CHARGE) of the converter 100, for example, the phase signal φ is asserted, causing the transistor 104 to turn on. The inductor current I_COIL flowing through the inductor 102 increases during this charging phase, for example, in a relatively linear manner. During this phase, the inductor current I_COIL mostly passes through the transistor 104, and thus a relatively small current flows to the output node 108. As a result, the voltage across the capacitor 112 is discharged, causing the output node 108 to be 100V. Figure 2 The output voltage VOUT represented by the solid line curve in , for example, decreases in a relatively linear manner, depending on the type of load.

[0040] During the discharge phase (DISCHARGE), the phase signal φ is, for example, low, so that the transistor 104 is no longer conductive. The inductor current I_COIL flowing through the inductor 102 is then directed to the output node 108, and thus, the voltage VOUT rises, for example, during at least some of each discharge phase. The inductor current I_COIL decreases, for example, in a relatively linear manner during the discharge phase. Figure 2 In the example of FIG. 5 , the output voltage VOUT rises during each discharge phase above the target level TARGET and then falls again towards the end of each discharge phase.

[0041] As explained in the background section above, since the output of the converter 100 is not supplied by the inductor 102 during the charging phase, it becomes difficult to regulate the output voltage VOUT of the converter 100, and therefore, during the charging phase, any modification to the parameters of the charging phase (such as its duration) will have no effect on the output voltage VOUT, making closed-loop regulation difficult.

[0042] One way to solve this problem is to regulate the voltage conversion based on the sum of the output voltage VOUT and a voltage ramp applied during the charging phase. Such a voltage ramp is given by Figure 2 The dashed curve RAMP in FIG. 1 is shown in FIG. 2 . Such a voltage ramp is chosen to represent the effect that the energy stored in the inductor will have at the output of the converter. Figure 2 The dashed curve in FIG represents an example of the sum of the output voltage VOUT and the voltage ramp RAMP. Assuming the voltage ramp is selected correctly, the resulting sum of the ramp signal and the output voltage VOUT can be used to determine when the charging phase should end, for example when the sum exceeds the target level TARGET.

[0043] However, a disadvantage of this voltage ramp-based approach is the need for a ramp generator to generate the voltage ramp and a fast adder to add the voltage ramp to the output voltage signal VOUT. These circuits increase cost and complexity. Furthermore, if the voltage ramp does not accurately represent the energy stored in the inductor, the result will be that the average voltage applied to the load will not be correctly regulated. A particular difficulty is that when the voltages VIN and VOUT are variable, the static ramp curve will not correctly represent the stored energy. Furthermore, depending on the conversion mode (buck, boost, buck-boost), the charging phase will have different effects on the output voltage. Therefore, the converter required to cover two or three of these modes cannot rely on a static ramp, and using a variable ramp generator would add even greater cost and complexity.

[0044] Figure 3 A DC-DC conversion circuit 300 is schematically shown according to an example embodiment of the present disclosure.

[0045] The DC-DC converter circuit 300 includes, for example, a DC-DC converter (DC-DC CONVERTER) 302 having an input line 304 coupled to an input voltage VIN and an output 306 providing an output voltage VOUT. The DC-DC converter 302 is, for example, Figure 1 Alternatively, the converter 302 may be another type of converter, such as a buck converter or a buck-boost converter.

[0046] The DC-DC converter 302 also receives a phase signal φ generated by a feedback path including an overshoot detection circuit (OVERSHOOT DETECTION) 308 and a pulse width modulation controller (PWM CONTROLLER) 310 .

[0047] For example, the phase signal φ indicates the start and end of the alternating charging and discharging phases of the converter 302. Figure 1 In the case of boost converter 100, the converter alternates directly between charging and discharging phases under the control of a single binary phase signal φ. In other types of DC-DC converters, more than one phase signal φ may be present, such as a first phase signal φ_CHARGE for controlling the start and end of the charging phase and a second phase signal φ_DISCHARGE for controlling the start and end of the discharging phase. Furthermore, there may be time gaps between each charging phase and the subsequent discharging phase and / or between each discharging phase and the subsequent charging phase.

[0048] Overshoot detection circuit 308, for example, receives output voltage VOUT from output 306 of converter 302 and generates an overshoot metric OS_METRIC based on the output voltage. PWM controller 310, for example, receives overshoot metric OS_METRIC and generates phase signal φ based on the metric. In particular, PWM controller 310, for example, adjusts the duty cycle of phase signal φ and / or the duration of the charging phase of converter 302 based on the overshoot metric OS_METRIC.

[0049] Figure 4 According to an example embodiment, the Figure 3 The overshoot detection circuit 308 of the DC-DC converter 302 is shown. The circuit 308 includes, for example, a comparator (CMP) 402, which is configured to compare the output voltage VOUT of the converter 302 with the target level TARGET. For example, the positive input of the comparator 402 is coupled to the output 306 of the converter 302, and the negative input of the comparator 402 receives the target level TARGET, which represents the target voltage to be supplied at the output 306 of the DC-DC converter 302. The comparator 402 generates an overshoot signal OS' at its output 404, which indicates the overshoot period when the output voltage VOUT exceeds the target level TARGET.

[0050] Output 404 of comparator 402 is coupled to one input of an AND gate 406, for example, whose other input receives a signal φ_DISCHARGE indicating when converter 302 is in a discharge phase. For example, in one embodiment, signal φ_DISCHARGE corresponds to the inversion of phase signal φ.

[0051] The output signal OS at the output 408 of the AND gate 406 represents the overshoot period that occurs during the discharge phase.

[0052] The output 408 of the AND gate 406 is provided, for example, to a timer 410, which measures the duration of the overshoot period. Figure 4 In the example of FIG4 , the timer is implemented by a counter (COUNTER) that is clocked by a clock signal CLK. The counter 410 generates an output count value that forms an overshoot metric OS_METRIC, for example, at the end of each discharge phase. In some embodiments, the counter 410 is reset at the end of each discharge phase by applying the inverse of the signal φ_DISCHARGE generated, for example, by the inverter 413 to the reset input R of the counter. Another type of device can be used to evaluate the overshoot duration instead of a counter. For example, the overshoot duration can be based on the time it takes for the capacitor to discharge. However, an advantage of a digital solution (such as a counter-based solution) is that it allows the complexity of the analog circuit system to be reduced.

[0053] In some embodiments, overshoot detection circuit 308 further includes means for detecting whether a voltage overshoot is still present at the end of each discharge phase. For example, flip-flop 414 is configured to sample signal OS at the end of a discharge phase. For example, flip-flop 414 has its data input coupled to output 408 of AND gate 406, and its clock input receives signal φ_DISCHARGE, inverted by inverter 413. Flip-flop 414, for example, provides signal OS_END at its output 416, which is asserted when signal OS is asserted at the end of a discharge phase.

[0054] Now refer to Figure 5 Describe in more detail Figure 4 The operation of the overshoot detection circuit 308.

[0055] Figure 5 It shows Figure 4 1 is a timing diagram of an example of the inductor current I_COIL, the output voltage VOUT, the overshoot signal OS, the clock signal CLK, and the overshoot metric OS_METRIC in the circuit of FIG.

[0056] The inductor current I_COIL and the output voltage VOUT are similar to Figure 2 , and will not be described in detail.

[0057] As in Figure 2 In the example, Figure 5 The example shows two cycles of charge / discharge phase. Figure 5 In the example of FIG. 1 , during the period when the output voltage VOUT exceeds the target voltage TARGET, the overshoot signal OS is, for example, Figure 5 is asserted during each discharge phase, and these overshoot periods are Figure 5 The durations t_OS1 and t_OS2 in the example of FIG.

[0058] The clock signal CLK has, for example, a frequency between 10 and 1000 times the frequency of the converter, in other words, a clock period between 10 and 1000 times smaller than the period of the charge / discharge phase.

[0059] The counter 410 is configured, for example, to output an updated count value at the end of each discharge period. Figure 5At the end of the first discharge period, a count value COUNT1 is output, for example, and represents the duration t_OS1 of the overshoot period during the first discharge phase. This count value COUNT1 is used, for example, to regulate voltage conversion. For example, PWM controller 310 is configured to adjust the duration of the subsequent charge phase and / or the duration of the subsequent discharge phase based on this count value. In some embodiments, the duration of the charge phase is adjusted based only on the count value COUNT1.

[0060] For example, if the overshoot period is equal to or substantially equal to the duration of the discharge phase, e.g., equal to more than 90% of the duration of the discharge phase, the PWM controller 310 is configured to adjust the phase signal φ, or the plurality of phase signals if more than one phase signal is present, to reduce the output voltage VOUT. Additionally or alternatively, the PWM controller 310 receives the signal OS_END from the flip-flop 414 and is further configured to reduce the output voltage, e.g., if the overshoot still exists at the end of the discharge phase, as indicated by the signal OS_END.

[0061] PWM controller 310 is, for example, configured to adjust phase signal φ or multiple phase signals if more than one phase signal is present so as to increase output voltage VOUT if the overshoot period is equal to 0, in other words if the output of comparator 402 is never asserted during the discharge phase.

[0062] For example, to decrease the output voltage VOUT, the PWM controller 310 decreases the duration of the charging phase, and to increase the voltage VOUT, the PWM controller 310 increases the duration of the charging phase.

[0063] In other embodiments, the PWM controller 310 is configured to adjust the duration of the charging phase to obtain a given range of overshoot durations, equal to, for example, a range between 20% and 80% of the duration of the discharging phase or a range between 10% and 90% of the duration of the discharging phase.

[0064] Figure 6 Another exemplary embodiment according to the present disclosure is shown in more detail. Figure 3 The overshoot detection circuit 308 is configured to detect the overshoot of the circuit. Figure 6 A part of the circuit with Figure 4 The circuits are identical and those features that are common have been labeled with like reference numerals and will not be described again in detail.

[0065] exist Figure 6In the example shown in FIG. 4 , the counter 408 provides an output signal OS_METRIC′ to another metric evaluation circuit 600 , which generates an overshoot metric signal OS_METRIC that is provided to the PWM controller 310 .

[0066] Circuit 600, for example, includes a comparator (CMP) 602 having a positive input coupled to output line 412 of counter 408 and a negative input coupled to node 604 providing a threshold level THRD. Comparator 602 is configured to compare the value of the overshoot metric OS_METRIC' to the threshold level THRD and assert an output signal METRIC RISING when the threshold is exceeded. This signal METRIC RISING indicates a rising voltage state of the converter, in other words, that the average output voltage is rising.

[0067] The threshold level THRD is generated, for example, based on one or more previous values of the signal OS_METRIC′ by a low pass filter (LPF) 606. For example, the low pass filter generates an average of N previous count values, where N is equal to between 2 and 20, for example.

[0068] In some embodiments, circuit 600 further includes another comparator 608 having a positive input coupled to node 604 and a negative input coupled to output line 412 of counter 408. Comparator 608 is configured, for example, to compare the count value of overshoot metric OS_METRIC′ with a threshold level THRD and assert an output signal METRIC FALLING when the overshoot metric OS_METRIC′ is below the threshold level THRD. Signal METRIC FALLING indicates a falling voltage state of the converter, in other words, a falling average output voltage.

[0069] For example, the overshoot metrics METRIC RISING and METRIC FALLING allow PWM controller 310 to adjust phase signal φ so that the overshoot metric remains relatively stable. For example, if the overshoot metric indicates that the overshoot duration is zero, or if the signal METRIC FALLING is asserted, PWM controller 310 increases average output voltage VOUT, for example, by increasing the duration of the charging phase. However, if the overshoot metric indicates that the overshoot duration is substantially equal to the duration of the discharging phase, or if the signal METRIC RISING is asserted, PWM controller 310 decreases average output voltage VOUT, for example, by decreasing the duration of the charging phase. In this manner, after a number of convergence cycles, the charging phase duration will converge to a static value that results in a stable overshoot duration, for example.

[0070] Figure 7is a circuit diagram based on a DC-DC converter 302 operating in a buck-boost mode. Figure 3 Timing diagram of the measured signals in the circuit. Figure 3 Specifically, the QR (quasi-resonant) steady-state operation, also known as transition mode, is shown. Operating in QR mode means that the current in the inductor drops to zero at the end of the discharge phase, and a new charging phase immediately follows the discharge phase. In other words, QR mode exists right between DCM (discontinuous conduction mode) and CCM (continuous conduction mode).

[0071] Figure 7 The charge phase signal φ_CHARGE and the discharge phase signal φ_DISCHARGE, the output voltage VOUT, and the overshoot signal OS' are shown. Figure 7 The measurement signal is based on a converter frequency of 259.7 kHz, an input voltage VIN of 12 V, and a target voltage of 18 V. The measured average output voltage is 18.017 V, with a relatively low amplitude of 294 mV.

[0072] An advantage of the embodiments described herein is that the output voltage of the DC-DC converter can be regulated in a simple manner by a relatively low-cost and low-complexity circuit. In fact, the solution involves, for example, only a few relatively low-cost comparators and counters.

[0073] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily envision other variations. In particular, it will be apparent to those skilled in the art that the embodiments described herein may be applied to any type of DC-DC converter.

Claims

1. A DC-DC conversion circuit, comprising: a DC-DC converter, the DC-DC converter comprising an inductor; as well as Regulation circuit, including: a first comparator configured to detect an overshoot period during a discharge phase of the DC-DC converter, during which an output voltage of the DC-DC converter exceeds a target voltage, wherein during the discharge phase of the DC-DC converter, an inductor current is supplied by the inductor to an output of the DC-DC converter; a timer configured to measure a duration of the overshoot period; a low-pass filter configured to generate a threshold level based on a plurality of previous values of the measured duration of the overshoot period; a second comparator configured to detect a rising voltage state when the duration of the overshoot period exceeds the threshold level; a third comparator configured to detect a falling voltage state when the duration of the overshoot period is below the threshold level; and A controller configured to adjust a duration of an inductor charging phase of the DC-DC converter and / or a duration of an inductor discharging phase of the DC-DC converter in response to the detection of the rising voltage state and the detection of the falling voltage state. 2 . The DC-DC conversion circuit of claim 1 , wherein the low-pass filter is configured to generate the threshold level based on between 2 and 20 previous values of the measured duration of the overshoot period. 3 . The DC-DC conversion circuit according to claim 1 , wherein the timer comprises a counter configured to increment or decrement a count value during the overshoot period.

4. An electronic device comprising: A direct current (DC) power supply, supplying a first voltage level; as well as A DC-DC conversion circuit is configured to convert the first voltage level into an output voltage, the DC-DC conversion circuit comprising: a DC-DC converter including an inductor; and Regulation circuit, including: a first comparator configured to detect an overshoot period during a discharge phase of the DC-DC converter, during which the output voltage of the DC-DC converter exceeds a target voltage, wherein during the discharge phase of the DC-DC converter, an inductor current is supplied by the inductor to the output of the DC-DC converter; a timer configured to measure a duration of the overshoot period; a low-pass filter configured to generate a threshold level based on a plurality of previous values of the measured duration of the overshoot period; a second comparator configured to detect a rising voltage state when the duration of the overshoot period exceeds the threshold level; a third comparator configured to detect a falling voltage state when the duration of the overshoot period is below the threshold level; and A controller configured to adjust a duration of an inductor charging phase of the DC-DC converter and / or a duration of an inductor discharging phase of the DC-DC converter in response to the detection of the rising voltage state and the detection of the falling voltage state. 5 . The electronic device of claim 4 , wherein the regulating circuit further comprises a low-pass filter configured to generate the threshold level based on a plurality of previous values of the measured duration of the overshoot period. 6 . The electronic device of claim 4 , wherein the timer comprises a counter configured to increment or decrement a count value during the overshoot period.

7. A method for direct current (DC)-DC conversion, comprising: detecting an overshoot period during a discharge phase of a DC-DC converter during which an output voltage of the DC-DC converter exceeds a target voltage, wherein during the discharge phase of the DC-DC converter, an inductor current through an inductor of the DC-DC converter is supplied to an output of the DC-DC converter; measuring the duration of the overshoot period; generating a threshold level by applying a low pass filter to a plurality of previous values of the measured duration of the overshoot period; detecting a rising voltage state in response to the duration of the overshoot period exceeding the threshold level; In response to the detection of the rising voltage state, adjusting a duty cycle of an inductor charging phase of the DC-DC converter and / or a duty cycle of an inductor discharging phase of the DC-DC converter; detecting a falling voltage condition in response to the duration of the overshoot period being below the threshold level; In response to the detection of the falling voltage condition, a duty cycle of the inductor charging phase of the DC-DC converter and / or a duty cycle of the inductor discharging phase of the DC-DC converter are adjusted.

8. The method according to claim 7, further comprising: In response to the detection of the rising voltage condition, a duration of a charging phase of the DC-DC converter is reduced.

9. The method of claim 8, wherein generating the threshold level comprises: The threshold level is generated by applying a low pass filter to between 2 and 20 previous values of the measured duration of the overshoot period.

10. The method according to claim 8, further comprising: In response to the detection of the reduced voltage condition, the duration of the charging phase of the DC-DC converter is increased.

11. The method of claim 7, wherein measuring the duration of the overshoot period comprises: A count value is incremented or decremented during the overshoot period.

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