A packaging structure for stacked wafers and a packaging method thereof

Abstract

The present invention relates to a stacked wafer structure and its packaging method, belonging to the technical field of semiconductor chip packaging. It includes a wafer stack C2, a carrier wafer A1, and an electrical connection layer (150). The wafer stack C2 is disposed above the carrier wafer A1 and connected through the electrical connection layer (150). The wafer stack C1 includes several functional wafers. From bottom to top, the wafer size gradually decreases, and stepped sidewalls are formed around it. Above the carrier wafer A1, a dielectric layer III (300) is coated on the front surface and the stepped sidewalls of the wafer stack C2, and a dielectric layer III opening (301) is formed. A metal seed layer (310) and metal bumps (360) are disposed in the dielectric layer III opening (301). The metal bumps (360) are connected to the metal interconnect layer (120) of an adjacent wafer through the metal seed layer (310). The present invention provides a multi-layer stacked wafer structure and its manufacturing method.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a packaging method for stacked wafers, belonging to the technical field of semiconductor chip packaging. Background Art

[0002] With the development of the semiconductor industry, the performance of electronic products needs to be continuously improved. As the manufacturing cost of chips has risen sharply, the way to improve product performance has shifted from the miniaturization of chip circuit nodes to the packaging field.

[0003] In order to reduce the packaging area and power consumption, and at the same time meet the development trend of low cost and full integration of integrated circuits, packaging more requires stacking chips instead of the traditional flat layout, that is, making the chips "stand up" instead of "spreading out". The stacking of chips can integrate various types of chips such as logic chips, memory chips, and RF chips to form heterogeneous chiplets, thereby significantly reducing power consumption, saving space, and shortening the signal exchange time, which conforms to the development trend of future packaging. A typical example is the Fiji GPU display core chip of Advanced Micro Devices (AMD) in the United States. After the high-bandwidth memory (HBM) and the logic chip are stacked, they are then subjected to 2.5D packaging with the GPU chip. However, there is already a clear roadmap in the industry to stack all these chips to form a true 3D packaging.

[0004] Wafer-level packaging (WLP) is a typical low-cost and high-efficiency packaging method. For areas with relatively high metal bumps 360 or a relatively dense layout of metal bumps 360, there is a relatively high risk of debonding failure, and there are more heterogeneous integration layers. Once a failure occurs, it may cause a large loss in yield.

[0005] Therefore, being able to use a traditional wafer-level bump production line to achieve the growth of stacked wafer pins is a low-cost way that can ensure the yield output. However, the morphology of the edge part of the multi-layer stacked wafers changes greatly, which makes it difficult to manufacture using a traditional WLP production line and the feasibility is insufficient. Summary of the Invention

[0006] Based on this, it is necessary to provide a packaging structure and a packaging method for stacked wafers, which can constrain the edge and thickness of the stacked wafers during the manufacturing process to form a specific morphology, ensuring that the edge morphology will not affect the bump manufacturing process during the bump manufacturing process.

[0007] The object of the present invention is achieved as follows: A stacked wafer structure of the present invention includes a wafer stack C2, a carrier wafer A1, and an electrical connection layer. The wafer stack C2 is disposed above the carrier wafer A1 and connected through the electrical connection layer. The wafer stack C1 includes several functional wafers.

[0008] The wafer includes a silicon substrate, through-silicon vias, dielectric layer I, and a metal interconnect layer. The through-silicon vias penetrate the silicon substrate vertically. The dielectric layer I is disposed above the silicon substrate and exposes the metal interconnect layer through an opening in the dielectric layer I.

[0009] From bottom to top, the size of the wafer decreases layer by layer, and stepped sidewalls are formed around it. Above the carrier wafer A1, a dielectric layer III is coated on the front surface of the wafer stack C2 and a dielectric layer III opening is formed. The dielectric layer III is coated downward on the stepped sidewalls of the wafer stack C2. A metal seed layer and metal bumps are disposed inside the dielectric layer III opening. The metal bumps are connected to the metal interconnect layer of an adjacent wafer through the metal seed layer.

[0010] Further, the difference in the outer diameter size Δ1 between the wafer B1 and the wafer A1 is not greater than 2.5 mm, and the minimum difference in the outer diameter size Δ1 between the wafer B1 and the wafer A1 should ensure effective electrical interconnection of the metal contacts 401 of the electroplating fixture.

[0011] Further, the ratio of the difference in the outer diameter size Δ2 between the wafer B2 and the wafer B1 to the thickness t2 of the wafer B2 itself is not less than 2:1.

[0012] Further, the ratio of the difference in the outer diameter size Δ3 between the wafer B3 and the wafer B2 to the thickness t3 of the wafer B3 itself is not less than 2:1.

[0013] Further, the ratio of the difference in the outer diameter size Δ4 between the wafer B4 and the wafer B3 to the thickness t4 of the wafer B4 itself is not less than 2:1.

[0014] A packaging method for a stacked wafer packaging structure according to the present invention has the following process steps:

[0015] Step 1: Provide the wafer A1 and wafers B1, B2, B3, and B4. Through-silicon vias, dielectric layer I, and a metal interconnect layer are completed on the silicon substrates of the wafers B1, B2, B3, and B4. Metal is deposited inside the through-silicon vias and connected to the metal interconnect layer. The top layer of the metal interconnect layer exposes the dielectric layer I. The wafer B1 is the bottommost wafer for packaging and will be interconnected with other wafers in the future. The wafer B4 is the wafer for finally growing metal bumps.

[0016] Step 2: Trim the edges of wafers B1, B2, B3, and B4. After trimming, the length of wafer B1 > wafer B2 > wafer B3 > wafer B4. The thickness of each wafer includes the top layer thickness of its metal interconnect layer. Define: The outer ring size spacing difference between wafer B1 and wafer A1 is △1, the outer ring size spacing difference between wafer B2 and wafer B1 is △2, the outer ring size spacing difference between wafer B3 and wafer B2 is △3, and the outer ring size spacing difference between wafer B4 and wafer B3 is △4. Define the trimming length: The outer ring size spacing difference △1 between wafer B1 and wafer A1 shall not be greater than 2.5 mm and the outer ring size spacing difference △1 between wafer B1 and wafer A1 shall ensure effective electrical interconnection of the metal contacts of the electroplating fixture at the minimum. The ratio of the outer ring size spacing difference △1 between wafer B1 and wafer A1 to the thickness t1 of wafer B1 itself shall not be less than 2:1;

[0017] The ratio of the outer ring size spacing difference △2 between wafer B2 and wafer B1 to the thickness t2 of wafer B2 itself shall not be less than 2:1. Correspondingly, the ratio of the outer ring size spacing difference △3 between wafer B3 and wafer B2 to the thickness t3 of wafer B3 itself shall not be less than 2:1, and the ratio of the outer ring size spacing difference △4 between wafer B4 and wafer B3 to the thickness t4 of wafer B4 itself shall not be less than 2:1;

[0018] Step 3: Provide a carrier plate and bond the upper surface of wafer B1 to the carrier plate through an adhesive;

[0019] Step 4: Thin the silicon substrate of wafer B1 through a thinning process such as mechanical grinding or chemical etching to expose the upper surface of the silicon through holes;

[0020] Step 5: On wafer B1, form a dielectric layer on the silicon through holes through a coating or chemical deposition process and form a dielectric layer opening, and the dielectric layer opening exposes the upper surface of the silicon through holes;

[0021] Step 6: Form a conductive layer in the dielectric layer opening through one process or a combination of several processes among evaporation plating, electroplating, or electroless plating, and the conductive layer is connected to the silicon through holes;

[0022] Step 7: Interconnect wafer B1 and wafer B2, and connect the top layer of the metal interconnect layer of wafer B2 to the conductive layer of wafer B1; Repeat the above steps, stack wafer B3 on wafer B2, and stack wafer B4 on wafer B3 to complete layer-by-layer interconnection, form a wafer stack C1 and form a stepped sidewall around it. Wafer B2, wafer B3, and wafer B4 are subjected to the same thinning process, then form their respective dielectric layers through a coating or chemical deposition process, and finally form their respective conductive layers;

[0023] Step 8: After the required number of stacked layers is satisfied, debond and remove the carrier plate;

[0024] Step Nine: Then, bond the wafer B1 of the wafer stack C1 face-to-face with the bottom wafer A1, that is, interconnect the top layer of the protruding metal interconnect layer of wafer B1 with the pads of the bottom wafer A1 to form a wafer stack C2. Since the wafer A1 > wafer B1 > wafer B2 > wafer B3 > wafer B4 after trimming the length, stepped sidewalls are formed around the wafer stack C2; because the thickness of the wafer stack C2 may exceed the actual production capacity of the wafer packaging production line, the back side of the wafer A1 will also be ground and thinned to meet the thickness limit of the machine operation;

[0025] Step Ten: Coat a dielectric layer III on the front side of the wafer stack C2 and its stepped sidewalls around. The dielectric layer III covers the front side of wafer B4 and the stepped sidewalls of the wafer stack C2, and the dielectric layer opening exposes the top layer of the metal interconnect layer of wafer B4;

[0026] Step Eleven: Use magnetron sputtering or evaporation methods to form a metal seed layer covering on the front side of the wafer stack C2 and its stepped sidewalls around. The metal seed layer also covers the top layer of the metal interconnect layer of B4 at the same time;

[0027] Step Twelve: Then continue to coat photoresist on the metal seed layer. The thickness T of the photoresist layer needs to be not less than 50% of the thickness of the thickest wafer among wafers B1, B2, B3, and B4, that is, T ≥ 0.5 * max{wafer B1, wafer B2, wafer B3, wafer B4};

[0028] Expose a photoresist layer opening in the photoresist layer on the front side of wafer B4;

[0029] Step Thirteen: Use electroplating process to form metal bumps, remove the useless photoresist, and etch away the useless metal seed layer to complete the production of metal bumps. The materials for forming the metal bumps include but are not limited to conductive materials such as gold, tin, silver, copper, nickel, etc. that can be achieved by electroplating.

[0030] Further, in Step Two, trim the edges of wafers B1, B2, B3, and B4. Cut the silicon base from top to bottom only until it is flush with the bottom of the silicon vias; in Step Four, thin the remaining silicon base of wafer B1 through thinning processes such as mechanical grinding or chemical etching until the upper surface of the silicon vias is exposed to complete the trimming of the edges of wafers B1, B2, B3, and B4.

[0031] Further, in Step Seven, when wafers B1, B2, B3, and B4 are stacked in sequence and connected to each other, the gaps between the top layers of the metal interconnect layers are filled with an organic resin, and the thickness of the organic resin is equal to the thickness of the top layer of the metal interconnect layer.

[0032] Further, the organic resin includes epoxy resin or phenolic resin.

[0033] Furthermore, the treatment method for the edge of the photoresist layer includes: first, forming an anti-seepage ring at the edge of wafer B4 through a light-shielding or exposure method, and then developing the photoresist at the edge through an exposure or light-shielding method.

[0034] Beneficial effects

[0035] 1. During the manufacturing process, define the position difference between the upper and lower wafers and the ratio of the thickness of a single wafer to the thickness of the photoresist to ensure the coverage of the photoresist.

[0036] 2. Define the diameter difference between the upper and lower wafers on the premise that the centers of the second-layer wafer and the bottom-layer wafer coincide, forming a position difference at the edge to ensure the sealing and effectiveness of the electrical interconnection of the electroplating fixture contacts. Description of the drawings

[0037] Figure 1 It is a schematic cross-sectional view of a stacked wafer package structure of the present invention;

[0038] Figure 2 is Figure 1 a partially enlarged schematic cross-sectional view;

[0039] Figures 3A to 3R It is a schematic cross-sectional view of the packaging method of the stacked wafer package structure of the present invention;

[0040] In the figure:

[0041] Through-silicon via 101

[0042] Dielectric layer I 110

[0043] Metal interconnection layer 120

[0044] Electrical connection layer 150

[0045] Bonding pad 151

[0046] Carrier plate 200

[0047] Bonding layer 201

[0048] Wafer A1

[0049] Wafer B1

[0050] Wafer B2

[0051] Wafer B3

[0052] Wafer B4

[0053] Dielectric layer III 300

[0054] Dielectric layer III opening 301

[0055] Metal seed layer 310

[0056] Photoresist layer 320

[0057] Photoresist layer opening 323

[0058] Anti-seepage ring 304

[0059] Metal bump 360

[0060] Electroplating fixture metal contact 401

[0061] Electroplating fixture sealing layer 402. Detailed implementation manners

[0062] The following combines the accompanying drawings to elaborate on the detailed implementation manners of the present invention.

[0063] A packaging structure for stacked wafers according to the present invention, as Figure 1 and Figure 2 shown, includes a wafer stack C2, a wafer A1, and an electrical connection layer 150. A pad 151 is provided in the electrical connection layer 150. The wafer A1 bears the wafer stack C2.

[0064] The wafer stack C2 is disposed above the bearing wafer A1 and is connected through the electrical connection layer 150. The wafer stack C1 includes several functional wafers, as Figure 1 shown, and is exemplified by wafers B1, B2, B3, and B4.

[0065] Each functional wafer includes a silicon substrate 100, a silicon through-hole 101, a dielectric layer I 110, and a metal interconnection layer 120. The silicon through-hole 101 penetrates the silicon substrate 100 up and down. The dielectric layer I 110 is disposed above the silicon substrate 100 and exposes the top layer 121 of the metal interconnection layer 120 through a dielectric layer I opening;

[0066] From bottom to top, the wafer size of the wafer stack C2 gradually decreases, and its four sides form stepped sidewalls. Above the bearing wafer A1, a dielectric layer III 300 is coated on the front side of the wafer stack C2 and a dielectric layer III opening 301 is formed. The dielectric layer III 300 is coated downward on the stepped sidewalls of the wafer stack C2, as Figure 1 shown. A metal seed layer 310 and a metal bump 360 are disposed in the dielectric layer III opening 301. The metal bump 360 is connected to the metal interconnection layer 120 of an adjacent wafer through the metal seed layer 310.

[0067] Specifically, the outer diameter size spacing difference Δ1 between the wafer B1 and the wafer A1 is not greater than 2.5 mm, and the minimum of the outer diameter size spacing difference Δ1 between the wafer B1 and the wafer A1 should ensure effective electrical interconnection of the metal contacts 401 of the electroplating fixture. The ratio of the outer diameter size spacing difference Δ2 between the wafer B2 and the wafer B1 to the thickness t2 of the wafer B2 itself is not less than 2:1. The ratio of the outer diameter size spacing difference Δ3 between the wafer B3 and the wafer B2 to the thickness t3 of the wafer B3 itself is not less than 2:1. The ratio of the outer diameter size spacing difference Δ4 between the wafer B4 and the wafer B3 to the thickness t4 of the wafer B4 itself is not less than 2:1.

[0068] Particularly, the ratio of the sum of the lengths of the edges of the wafer B1, wafer B2, wafer B3, and wafer B4 after trimming to the edge of the wafer A1 to the total thickness of the wafer B1, wafer B2, wafer B3, and wafer B4 is not less than 2:1. The lengths of the edges of the wafer B1, wafer B2, wafer B3, and wafer B4 after trimming are not greater than 2.5 mm, and the minimum should ensure effective electrical interconnection of the metal contacts 401 of the electroplating fixture.

[0069] The packaging method of a stacked wafer packaging structure of the present invention Figures 3A to 3R is a schematic diagram of a wafer packaging method, shown schematically with five layers of wafers A1, B1, B2, B3, and B4. The process steps are as follows:

[0070] Step 1: Refer to Figure 3A , provide the wafers A1, B1, B2, B3, and B4. Through-silicon vias 101, dielectric layer I 110, and metal interconnection layer 120 are completed on the silicon substrate 100 of the wafers B1, B2, B3, and B4. Metal is deposited inside the through-silicon vias 101 and connected to the metal interconnection layer 120. The top layer 121 of the metal interconnection layer 120 exposes the dielectric layer I 110. Among them, the wafer B1 is the bottommost wafer for packaging and will be interconnected with other wafers in the future, and the wafer B4 is the wafer for finally growing the metal bumps 360.

[0071] Step 2: Refer to Figure 3B and Figure 3C , trim the edges of the wafers B1, B2, B3, and B4. After trimming, the length of the wafer B1 > wafer B2 > wafer B3 > wafer B4 (the thickness of each wafer includes the thickness of the top layer of its metal interconnection layer), as shown in Figure 3BAs shown in the figure, the following definitions are made: the difference in the outer - ring size spacing between wafer B1 and wafer A1 is Δ1, the difference in the outer - ring size spacing between wafer B2 and wafer B1 is Δ2, the difference in the outer - ring size spacing between wafer B3 and wafer B2 is Δ3, and the difference in the outer - ring size spacing between wafer B4 and wafer B3 is Δ4. The trimming length is defined as follows: the difference in the outer - ring size spacing Δ1 between wafer B1 and wafer A1 should not be greater than 2.5 mm, and the minimum value of the difference in the outer - ring size spacing Δ1 between wafer B1 and wafer A1 should ensure the effective electrical interconnection of the metal contacts 401 of the electroplating fixture. The ratio of the difference in the outer - ring size spacing Δ1 between wafer B1 and wafer A1 to the thickness t1 of wafer B1 itself should not be lower than 2:1. The metal contacts 401 of the electroplating fixture are pressed on the metal seed layer 310 to conduct electricity, and the electroplating - fixture sealing layer 402 abuts against the sealing ring to prevent the electroplating solution from seeping in.

[0072] As Figure 3C shown, the ratio of the difference in the outer - ring size spacing Δ2 between wafer B2 and wafer B1 to the thickness t2 of wafer B2 itself should not be lower than 2:1. Correspondingly, the ratio of the difference in the outer - ring size spacing Δ3 between wafer B3 and wafer B2 to the thickness t3 of wafer B3 itself should not be lower than 2:1, and the ratio of the difference in the outer - ring size spacing Δ4 between wafer B4 and wafer B3 to the thickness t4 of wafer B4 itself should not be lower than 2:1.

[0073] Step three: Refer to Figure 3D and provide a carrier plate 200. Bond the upper surface of wafer B1 to the carrier plate 200 through an adhesive 201.

[0074] Step four: Refer to Figure 3E and thin the silicon substrate 100 of wafer B1 through a thinning process such as mechanical grinding or chemical etching to expose the upper surface of the silicon vias 101. Due to the trimming process in step one, the edge of the thinned wafer B1 becomes a complete wafer with a reduced diameter.

[0075] Step five: Refer to Figure 3F and form a dielectric layer 130 on the silicon vias 101 of wafer B1 through a coating or chemical deposition process, and form a dielectric - layer opening 131. The dielectric - layer opening 131 exposes the upper surface of the silicon vias 101. The dielectric layer I 110 includes organic materials such as polyimide and phenolic resin, but it is also possible to use inorganic materials such as silicon oxide and silicon nitride.

[0076] Step six: Refer to Figure 3G and form a conductive layer in the dielectric - layer opening 131 through one or a combination of processes such as evaporation plating, electroplating, or chemical plating. The conductive layer is connected to the silicon vias 101. The conductive layer includes common metals such as aluminum, copper, tin, nickel, or noble metals to facilitate subsequent interconnection with wafer B2.

[0077] Step seven: Refer to Figure 3H, the wafers B1 and B2 are interconnected, and the top layer of the metal interconnect layer of wafer B2 is connected to the conductive layer of wafer B1; see Figure 3I , repeat the steps, stack wafer B3 on wafer B2, stack wafer B4 on wafer B3, complete layer-by-layer interconnection, form a wafer stack C1 and form a stepped sidewall around it. The same thinning process is performed on wafers B2, B3, and B4, and then their respective dielectric layers are formed through coating or chemical deposition processes, and finally their respective conductive layers are formed;

[0078] Step eight, see Figure 3J , after the required number of stacked layers is satisfied, debond and remove the carrier plate 200;

[0079] Step nine, see Figure 3K , then bond the wafer B1 of the wafer stack C1 face-to-face with the bottom wafer A1, that is, the top layer 121 of the protruding metal interconnect layer 120 of wafer B1 is interconnected with the pad 151 (pad) of the bottom wafer A1 to form a wafer stack C2. Since the length is trimmed, wafer A1 > wafer B1 > wafer B2 > wafer B3 > wafer B4, a stepped sidewall is formed around the wafer stack C2; because the thickness of the wafer stack C2 may exceed the actual production capacity of the wafer packaging production line, the back side of wafer A1 will also be ground and thinned to meet the thickness limit of the machine operation;

[0080] Step ten, see Figure 3L , coat a dielectric layer III 300 on the front surface of the wafer stack C2 and its stepped sidewalls around it. The dielectric layer III 300 covers the front surface of wafer B4 and the stepped sidewalls of the wafer stack C2, and its dielectric layer III opening 301 exposes the top layer of the metal interconnect layer of wafer B4. Because the adhesive layer of the dielectric layer III 300 is very thin, it is difficult to completely cover the stepped sidewalls during actual operation.

[0081] Step eleven, see Figure 3M , use magnetron sputtering or evaporation to form a metal seed layer 310 to cover the front surface of the wafer stack C2 and its stepped sidewalls around it. The metal seed layer 310 also covers the top layer of the metal interconnect layer of B4;

[0082] Step twelve, see Figure 3N , then continue to coat photoresist on the metal seed layer 310. The setting of the thickness T of the photoresist layer 320 is a key factor. Generally, the thickness T of the photoresist layer 320 needs to be not less than 50% of the thickness of the thickest wafer among wafers B1, B2, B3, and B4, that is, T≥0.5*max{wafers B1, B2, B3, B4};

[0083] See Figure 3N, during this process, a photoresist layer opening 323 is exposed in the photoresist layer 320 on the front side of the wafer B4. The treatment method for the edge includes: first, an anti-seepage ring 321 is completed at the edge of the wafer B4 by means of light shielding or exposure, and then the photoresist at the edge is developed by means of exposure or light shielding. Whether to use light shielding or exposure for the treatment depends on whether the photoresist material is a positive photoresist material or a negative photoresist material. If the photoresist material is a positive photoresist material, the light shielding method is adopted; if the photoresist material is a negative photoresist material, the exposure method is adopted. However, for laminated photoresists, this method can also be realized by methods such as laser ablation;

[0084] Step Thirteen, refer to Figure 3O and 3P , a metal bump 360 is formed by using an electroplating process, the useless photoresist is removed, and the useless metal seed layer 310 is etched away to complete the production of the metal bump 360. The materials for forming the metal bump 360 include but are not limited to conductive materials such as gold, tin, silver, copper, nickel, etc. that can be realized by electroplating.

[0085] After completing the above steps, the subsequent packaging steps are continued. It should be further noted that the number of stacked wafers is not limited to the five layers shown in this embodiment, and multiple wafers can be stacked within an allowable range.

[0086] In Step Two, the edges of the wafers B1, B2, B3, and B4 are trimmed by cutting. The silicon substrate 100 is cut from top to bottom only to be flush with the bottom of the silicon via 101, so as to save cutting man-hours, reduce the loss of cutting tools, and reduce production costs. Refer to Figure 3Q ; in the subsequent Steps Three and Four, the remaining silicon substrate 100 of the wafer B1 is thinned by a thinning process such as mechanical grinding or chemical etching until the upper surface of the silicon via 101 is exposed, and the trimming of the edges of the wafers B1, B2, B3, and B4 is completed. Refer to Figure 3R . In Step Two, trimming the edges in advance can also prevent the formation of wafer sharp corners after lapping.

[0087] In Step Seven, when the wafers B1, B2, B3, and B4 are stacked in sequence and connected to each other, there is still a gap between the top layers of the metal interconnection layers. This requires filling organic resins such as epoxy resin and phenolic resin (not shown in the figure). The thickness of the organic resin is equal to the thickness of the top layer of the metal interconnection layer. The presence of the organic resin is beneficial to dispersing stress between the wafers and strengthening the entire packaging structure.

[0088] The specific embodiments described above further elaborate in detail the objectives, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only for the specific embodiments of the present invention and is not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A packaging structure for stacked wafers, characterized in that, it includes a wafer stack C1, a wafer A1, and an electrical connection layer (150). The wafer stack C1 is disposed above the wafer A1 and connected through the electrical connection layer (150). The wafer stack C1 includes wafers B1, B2, B3, and B4 stacked in sequence. The wafer B1 in the wafer stack C1 is bonded face to face with the wafer A1 to form a wafer stack C2; Each wafer includes a silicon substrate (100), through-silicon vias (101), a dielectric layer I (110), and a metal interconnect layer (120). The through-silicon vias (101) penetrate the silicon substrate (100) vertically. The dielectric layer I (110) is disposed above the silicon substrate (100) and exposes the metal interconnect layer (120) through an opening in the dielectric layer I; From bottom to top, the wafer sizes decrease layer by layer, and stepped sidewalls are formed around them. Above the wafer A1, a dielectric layer III (300) is coated on the front surface of the wafer stack C2 and a dielectric layer III opening (301) is formed. The dielectric layer III (300) is coated downward on the stepped sidewalls of the wafer stack C2. A metal seed layer (310) and metal bumps (360) are disposed inside the dielectric layer III opening (301). The metal bumps (360) are connected to the metal interconnect layer (120) of an adjacent wafer through the metal seed layer (310); The ratio of the sum of the lengths of the edges of the wafers B1, B2, B3, and B4 after trimming to the edge of the wafer A1 to the total thickness of the wafers B1, B2, B3, and B4 is not less than 2:

1.

2. The packaging structure according to claim 1, characterized in that, the difference in outer ring size spacing △1 between the wafer B1 and the wafer A1 is not greater than 2.5 mm, and the minimum difference in outer ring size spacing △1 between the wafer B1 and the wafer A1 should ensure effective electrical interconnection of the metal contacts (401) of the electroplating fixture.

3. The packaging structure according to claim 2, characterized in that, the ratio of the difference in outer ring size spacing △2 between the wafer B2 and the wafer B1 to the thickness t2 of the wafer B2 itself is not less than 2:

1.

4. The packaging structure according to claim 3, characterized in that, the ratio of the difference in outer ring size spacing △3 between the wafer B3 and the wafer B2 to the thickness t3 of the wafer B3 itself is not less than 2:

1.

5. The packaging structure according to claim 4, characterized in that, the ratio of the difference in outer ring size spacing △4 between the wafer B4 and the wafer B3 to the thickness t4 of the wafer B4 itself is not less than 2:

1.

6. A packaging method for a packaging structure of stacked wafers, and its process steps are as follows: Step 1: Provide wafers A1, B1, B2, B3, and B4. Through-Silicon Vias (TSVs) (101), dielectric layer I (110), and metal interconnect layer (120) are completed on the silicon-based (100) of wafers B1, B2, B3, and B4. Metal is deposited inside the TSVs (101) and connected to the metal interconnect layer (120). The top layer (121) of the metal interconnect layer (120) exposes the dielectric layer I (110). Among them, wafer B1 is the bottommost wafer for packaging and will be interconnected with other wafers in the future, and wafer B4 is the wafer for finally growing metal bumps (360). Step 2: Trim the edges of wafers B1, B2, B3, and B4. After trimming, the length of wafer B1 > wafer B2 > wafer B3 > wafer B4. The thickness of each wafer includes the thickness of the top layer of its metal interconnect layer. Define: The difference in the outer diameter size between wafer B1 and wafer A1 is △1, the difference in the outer diameter size between wafer B2 and wafer B1 is △2, the difference in the outer diameter size between wafer B3 and wafer B2 is △3, and the difference in the outer diameter size between wafer B4 and wafer B3 is △4. Define the trimming length: The difference in the outer diameter size △1 between wafer B1 and wafer A1 should not be greater than 2.5 mm, and the minimum difference in the outer diameter size △1 between wafer B1 and wafer A1 should ensure effective electrical interconnection of the metal contacts (401) of the electroplating fixture. The ratio of the difference in the outer diameter size △1 between wafer B1 and wafer A1 to the thickness t1 of wafer B1 itself should not be less than 2:1; The ratio of the difference in the outer diameter size △2 between wafer B2 and wafer B1 to the thickness t2 of wafer B2 itself should not be less than 2:

1. Correspondingly, the ratio of the difference in the outer diameter size △3 between wafer B3 and wafer B2 to the thickness t3 of wafer B3 itself should not be less than 2:1, and the ratio of the difference in the outer diameter size △4 between wafer B4 and wafer B3 to the thickness t4 of wafer B4 itself should not be less than 2:1; Step 3: Provide a carrier plate (200), and bond the upper surface of wafer B1 to the carrier plate (200) through an adhesive (201); Step 4: Thin the silicon-based (100) of wafer B1 through mechanical grinding or chemical etching to expose the upper surface of the TSVs (101); Step 5: On wafer B1, form a dielectric layer (130) through a coating or chemical deposition process on the TSVs (101) and form a dielectric layer opening (131). The dielectric layer opening (131) exposes the upper surface of the TSVs (101); Step 6: Form a conductive layer in the dielectric layer opening (131) through one or a combination of processes such as evaporation plating, electroplating, or electroless plating. The conductive layer is connected to the TSVs (101); Step 7: Wafer B1 and wafer B2 are interconnected, and the top layer of the metal interconnection layer of wafer B2 is connected to the conductive layer of wafer B1; repeat the above steps, wafer B3 is stacked on wafer B2, and wafer B4 is stacked on wafer B3 to complete layer-by-layer interconnection, forming a wafer stack C1 and a stepped sidewall is formed around it. The same thinning process is performed on wafers B2, B3, and B4, and then their respective dielectric layers are formed through coating or chemical deposition processes, and finally their respective conductive layers are formed; Step 8: After the required number of stacked layers is satisfied, the bonding is released and the carrier plate (200) is removed; Step 9: Then, wafer B1 of the wafer stack C1 is face-to-face bonded to the bottom wafer A1, that is, the top layer (121) of the protruding metal interconnection layer (120) of wafer B1 is interconnected with the pad (151) of the bottom wafer A1 to form a wafer stack C2. Since the trimmed length makes wafer A1 > wafer B1 > wafer B2 > wafer B3 > wafer B4, a stepped sidewall is formed around the wafer stack C2; the back surface of wafer A1 will also be ground and thinned to meet the thickness limit for machine operation; Step 10: A dielectric layer III (300) is coated on the front surface of the wafer stack C2 and the stepped sidewalls around it. The dielectric layer III (300) covers the front surface of wafer B4 and the stepped sidewalls of the wafer stack C2, and its dielectric layer opening (301) exposes the top layer of the metal interconnection layer of wafer B4; Step 11: Using magnetron sputtering or evaporation, a metal seed layer (310) is formed to cover the front surface of the wafer stack C2 and the stepped sidewalls around it. The metal seed layer (310) also covers the top layer of the metal interconnection layer of B4; Step 12: Then, photoresist is further coated on the metal seed layer (310). The thickness T of the photoresist layer (320) needs to be not less than 50% of the thickness of the thickest wafer among wafers B1, B2, B3, and B4, that is, T≥0.5*max{wafer B1, wafer B2, wafer B3, wafer B4}; The photoresist layer opening (323) is exposed in the photoresist layer (320) on the front surface of wafer B4; Step 13: Metal bumps (360) are formed using electroplating technology, the useless photoresist is removed, and the useless metal seed layer (310) is etched away to complete the fabrication of the metal bumps (360).

7. The packaging method according to claim 6, characterized in that, in step 2, the edges of wafers B1, B2, B3, and B4 are trimmed by cutting. The silicon substrate (100) is cut from top to bottom only until it is flush with the bottom of the silicon vias (101); in step 4, the remaining silicon substrate (100) of wafer B1 is thinned by mechanical grinding or chemical etching until the upper surface of the silicon vias (101) is exposed, and the trimming of the edges of wafers B1, B2, B3, and B4 is completed.

8. The packaging method according to claim 7, characterized in that, In step seven, wafers B1, B2, B3, and B4 are stacked in sequence. When they are connected to each other, the gaps between the top layers of the metal interconnect layers are filled with an organic resin, and the thickness of the organic resin is equal to the thickness of the top layer of the metal interconnect layer.

9. The encapsulation method according to claim 8, wherein, the organic resin includes epoxy resin or phenolic resin.

10. The encapsulation method according to claim 9, wherein, the treatment method for the edge of the photoresist layer (320) includes: first, an anti-seepage ring (321) is completed at the edge of wafer B4 by means of light shielding or exposure, and then the photoresist at the edge is developed by means of exposure or light shielding.

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