Semiconductor Devices

Abstract

A semiconductor device includes a substrate, a semiconductor chip located on the substrate, and a first lead and a second lead located between the substrate and the semiconductor chip. The first lead and the second lead extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to the top surface of the substrate. The first lead includes a first bump connector and a first section. The second lead includes a second bump connector. The first bump connector is spaced apart from the second bump connector in the first direction. The first section of the first lead is spaced apart from the second bump connector in a second direction. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. The thickness of the first section of the first lead is less than the thickness of the second bump connector.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0099316 filed on August 14, 2019 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to semiconductor devices, and more particularly, to semiconductor devices including fine pitch leads. Background Art

[0004] Due to the development of electronic technology, the scale of semiconductor devices has been rapidly reduced in recent years. The demand for the functions of electronic devices has increased the number of leads of integrated circuits (ICs) in electronic devices. In order to manufacture more leads in a limited area, research has been conducted to narrow the interval between adjacent leads. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a fine wire structure that prevents and / or reduces current leakage between adjacent wires.

[0006] The objects of the inventive concept are not limited to the above-mentioned embodiments, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0007] According to some example embodiments of the present invention, a semiconductor device may include: a substrate; a semiconductor chip, the semiconductor chip being located on the substrate; and a first lead and a second lead, the first lead and the second lead being located between the substrate and the semiconductor chip. The first lead and the second lead may extend on the substrate below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead may include a first bump connector and a first segment connected to the first bump connector. The second lead may include a second bump connector. The first bump connector may be spaced apart from the second bump connector in the first direction. The first segment of the first lead may be spaced apart from the second bump connector in a second direction. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. The thickness of the first segment of the first lead is less than the thickness of the second bump connector.

[0008] According to some example embodiments of the inventive concept, a semiconductor device may include: a substrate; a semiconductor chip, the semiconductor chip being located on the substrate; a plurality of first leads, the plurality of first leads being located between the semiconductor chip and the substrate; and a plurality of second leads, the plurality of second leads being located between adjacent first leads of the plurality of first leads, respectively. The first leads and the second leads may extend on the substrate below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first leads may extend further in the first direction than the second leads. Each of the first leads may include a first bump connector, and each of the second leads may include a second bump connector. The first bump connector and the second bump connector may be arranged in a zigzag manner along a second direction parallel to the top surface of the substrate and perpendicular to the first direction. Each of the first leads may include a first segment located between adjacent second bump connectors. The level of the top surface of the first segment of each of the first leads may be lower than the level of the top surface of each of the second bump connectors.

[0009] According to some example embodiments of the inventive concept, a semiconductor device may include: a substrate; a semiconductor chip, the semiconductor chip being located on the substrate; a first lead and a second lead, the first lead and the second lead being located between the substrate and the semiconductor chip; a solder resist layer, the solder resist layer being located on a portion of the first lead and a portion of the second lead; and an underfill layer, the underfill layer being located on a portion of the substrate, a portion of the first lead, a portion of the second lead, and a portion of the solder resist layer. The first lead and the second lead may extend on the substrate below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead may extend further than the second lead in the first direction. The first lead and the second lead may be spaced apart from each other in a second direction parallel to the top surface of the substrate and perpendicular to the first direction. The first lead may include a first bump connector, a first segment, and a second segment, the first segment being located between the second segment and the first bump connector. The second lead may include a second bump connector. A dielectric pattern may be located on the first segment of the first lead. The first bump connector may be spaced apart from the second bump connector in the first direction. The first section of the first lead may be spaced apart from the second bump connector in the second direction. The first end of the first section of the first lead may vertically overlap the semiconductor chip, and the second end of the first section of the first lead may vertically overlap the solder resist layer. The thickness of the first section of the first lead may be less than the thickness of the second bump connector, the thickness of the first bump connector, and the thickness of the second section of the first lead. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A A top view of a semiconductor device according to some example embodiments of the inventive concepts is shown.

[0011] Figure 1B Shown along Figure 1A A cross-sectional view taken along line II'.

[0012] Figure 1C Shown along Figure 1A A cross-sectional view taken along line II-II'.

[0013] Figure 1D Shows Shows Figure 1C An enlarged view of portion “aa” of FIG.

[0014] Figure 2A A top view of a semiconductor device according to some example embodiments of the inventive concepts is shown.

[0015] Figure 2BShown along Figure 2A A cross-sectional view taken along line II'.

[0016] Figure 2C Shown along Figure 2A A cross-sectional view taken along line II-II'.

[0017] Figure 2D Shows Shows Figure 2C An enlarged view of part “bb” of FIG.

[0018] Figure 3A and Figure 3B 1 and 2 show the semiconductor devices according to some example embodiments of the present inventive concept. Figure 2A Cross-sectional views taken along line II' and line II-II'.

[0019] FIG. 4A to FIG. 4D Cross-sectional views illustrating methods of fabricating a semiconductor device according to some example embodiments of the inventive concepts are shown.

[0020] FIG. 5A to FIG. 5D Cross-sectional views illustrating methods of fabricating a semiconductor device according to some example embodiments of the inventive concepts are shown. DETAILED DESCRIPTION

[0021] Now, a semiconductor device according to the inventive concept will be described below with reference to the accompanying drawings.

[0022] Figure 1A A top view of a semiconductor device according to some example embodiments of the inventive concepts is shown. Figure 1B Shown along Figure 1A A cross-sectional view taken along line II'. Figure 1C Shown along Figure 1A A cross-sectional view taken along line II-II'. Figure 1D Shows Shows Figure 1C An enlarged view of portion “aa” of FIG.

[0023] Reference Figures 1A to 1D , a semiconductor device 1000 according to some embodiments of the inventive concept may include a substrate 10 , a plurality of first leads 20 , a plurality of second leads 21 , a plurality of solder masks 40 , an underfill layer 50 , and a semiconductor chip 60 .

[0024] The substrate 10 may include, for example, a printed circuit board (PCB) or a flexible film, but the inventive concept is not limited thereto. The flexible film may include, for example, polyimide.

[0025] The plurality of solder resist layers 40 may cover a portion of the first lead 20 and a portion of the second lead 21. The plurality of solder resist layers 40 may prevent and / or reduce oxidation and / or short circuits in the first lead 20 and the second lead 21 during heat treatment when the semiconductor chip 60 is mounted on the substrate 10.

[0026] A plurality of bumps 30 and 31 may be arranged on a pad (not shown) arranged at the bottom of the semiconductor chip 60. A plurality of bumps 30 and 31 may include, for example, gold (Au). A plurality of bumps 30 and 31 may include a first bump 30 and a second bump 31. When viewed in a top view, the first bump 30 and the second bump 31 may be arranged in a zigzag manner. In some embodiments, the first bump 30 may be arranged to extend substantially colinearly along a first axis, and the second bump 31 may be arranged to extend substantially colinearly along a second axis deviating from the first axis. The first bump 30 and the second bump 31 may contact the first lead 20 and the second lead 21, respectively. The first bump 30 and the second bump 31 may be used as a connection terminal for connecting the semiconductor chip 60 to the first lead 20 and the second lead 21.

[0027] The bottom filling layer 50 may be located on the substrate 10, the first lead 20, the second lead 21, and the solder resist layer 40, and / or partially covers the substrate 10, the first lead 20, the second lead 21, and the solder resist layer 40. The bottom filling layer 50 may be located in a space between the first bump 30 and the second bump 31, and / or fills the space between the first bump 30 and the second bump 31. The bottom filling layer 50 may protect the first lead 20, the second lead 21, the first bump 30, the second bump 31, and / or the semiconductor chip 60 from the external environment.

[0028] The semiconductor chip 60 may include an integrated circuit (IC). For example, the semiconductor chip 60 may be a display driver IC (DDI).

[0029] The first lead 20 and the second lead 21 may be disposed on opposite edges on the top surface of the substrate 10. The first lead 20 and the second lead 21 may each have a linear shape extending in a first direction D1 parallel to the top surface of the substrate 10. Each first lead 20 may extend further in the first direction D1 than each second lead 21. For example, the first lead 20 may have an end 20E spaced apart from an end 21E of the second lead 21 in the first direction D1.

[0030] The first lead 20 and the second lead 21 may be spaced apart from each other and alternately arranged with each other along a second direction D2 parallel to the top surface of the substrate 10 and perpendicular to the first direction D1. The end 20E of the first lead 20 and the end 21E of the second lead 21 may be arranged in a zigzag manner along the second direction D2. In some embodiments, the end 20E of the first lead 20 may be arranged to extend substantially collinearly along a first axis in the second direction D2, and the end 21E of the second lead 21 may be arranged to extend substantially collinearly along a second axis in the second direction D2, the second axis deviating from the first axis in the first direction D1.

[0031] The first lead 20 and the second lead 21 may include, for example, a conductive material such as copper (Cu), gold (Au), silver (Ag), and / or iron (Fe).

[0032] In the present specification, the term "horizontal height" may refer to a height from the top surface of the substrate 10 along a third direction D3 perpendicular to the top surface of the substrate 10. The bottom surface of the first lead 20 may be located at substantially the same level as that of the bottom surface of the second lead 21. The bottom surface of the first lead 20 and the bottom surface of the second lead 21 may be located at the same level as or higher than that of the top surface of the substrate 10. The width 202 of the first lead 20 in the second direction D2 may be substantially the same as the width 212 of the second lead 21 in the second direction D2.

[0033] The first lead 20 may include a first bump connector 20a, a first section 20b and a second section 20c. The first bump connector 20a may correspond to the end 20E of the first lead 20. The second section 20c of the first lead 20 may be spaced apart from the first bump connector 20a by the first section 20b of the first lead 20. When viewed in a top view, the first bump connector 20a may overlap with the semiconductor chip 60 (e.g., in a third direction D3). One end of the first section 20b of the first lead 20 may overlap with the semiconductor chip 60 (e.g., in a third direction D3), and the other end may overlap with the solder resist 40 (e.g., in a third direction D3). One end of the second section 20c of the first lead 20 may overlap with the solder resist 40 (e.g., in a third direction D3), and the top surface of the other end of the second section 20c of the first lead 20 is exposed by the solder resist 40 and / or does not overlap with the solder resist 40 (e.g., in a third direction D3).

[0034] The first bump connector 20a of the first lead 20 may have a top surface 20at in contact with the first bump 30. The width of the first bump 30 in the first direction D1 may be smaller than the width of the first bump connector 20a in the first direction D1. The width of the first bump 30 in the second direction D2 may be greater than the width of the first bump connector 20a in the second direction D2. At least a portion of the top surface 20at of the first bump connector 20a may be exposed on the opposite side of the first bump 30. For example, in some embodiments, the top surface 20at of the first bump connector 20a may extend beyond the opposite side of the first bump 30 so that a portion of the top surface 20at of the first bump connector 20a does not overlap with the first bump 30 in the third direction D3.

[0035] The thickness t2 of the first section 20b of the first lead 20 may be less than the thickness t1 of the first bump connector 20a and less than the thickness t3 of the second section 20c of the first lead 20. The thickness t1 of the first bump connector 20a may be substantially the same as the thickness t3 of the second section 20c of the first lead 20.

[0036] The level of the top surface 20bt of the first section 20b of the first lead 20 may be lower than the level of the top surface 20at of the first bump connector 20a, and lower than the level of the top surface 20ct of the second section 20c of the first lead 20. The level of the top surface 20at of the first bump connector 20a may be substantially the same as the level of the top surface 20ct of the second section 20c of the first lead 20.

[0037] The second lead 21 may include a second bump connector 21a and a first section 21b. The second bump connector 21a may correspond to the end 21E of the second lead 21. The first section 21b of the second lead 21 may be connected to the second bump connector 21a. When viewed in a top view, the second bump connector 21a may overlap with the semiconductor chip 60 (e.g., in a third direction D3). One end of the first section 21b of the second lead 21 may overlap with the semiconductor chip 60 (e.g., in a third direction D3), and the top surface of the other end of the first section 21b of the second lead 21 is exposed by the solder resist layer 40 and / or does not overlap with the solder resist layer 40 (e.g., in a third direction D3).

[0038] The second bump connector 21a may contact the second bump 31. The width of the second bump 31 in the first direction D1 and the width in the second direction D2 may be substantially the same as the width of the first bump 30 in the first direction D1 and the width in the second direction D2, respectively. The width of the second bump connector 21a in the first direction D1 may be substantially the same as the width of the first bump connector 20a in the first direction D1. The top surface of the second bump connector 21a may be exposed on the opposite side of the second bump 31. For example, in some embodiments, the top surface of the second bump connector 21a may extend beyond the opposite side of the second bump 31 so that a portion of the top surface of the second bump connector 21a does not overlap with the second bump 31 in the third direction D3.

[0039] When viewed in a top view, a distance ΔH1 between the second bump 31 and the first segment 20b of the first lead 20 in the second direction D2 may be smaller (e.g., shorter) than a distance ΔH2 between the second bump connector 21a and the first segment 20b of the first lead 20 in the second direction D2. A width ΔW1 of the second bump 31 in the first direction D1 may be smaller than a width ΔW2 of the first segment 20b of the first lead 20 in the first direction D1.

[0040] The second lead 21 may have a thickness ta that is uniform along the first direction D1. The thickness ta of the second lead 21 may be substantially the same as the thickness t1 of the first bump connector 20a and the thickness t3 of the second segment 20c of the first lead 20.

[0041] The thickness t2 of the first section 20b of the first lead 20 may be less than the thickness ta of the second bump connector 21a. The thickness t2 of the first section 20b of the first lead 20 may be, for example, in the range of 2 μm to less than 8 μm. The thickness ta of the second bump connector 21a may be, for example, in the range of 8 μm to 10 μm.

[0042] In some embodiments, a level difference between a top surface 21at of the second bump connector 21a of the second lead 21 and a top surface 20bt of the first segment 20b of the first lead 20 may be 2 μm or more.

[0043] The dielectric pattern 70 may be disposed on the first segment 20b of the first lead 20. The dielectric pattern 70 may be located on and / or cover the top surface 20bt of the first segment 20b of the first lead 20, and also located on and / or cover the opposite side surfaces of the first segment 20b of the first lead 20 in the second direction D2. The dielectric pattern 70 may include an organic solderability preservative (OSP).

[0044] The level of the top surface 70 t of the dielectric pattern 70 may be lower than that of the top surface 21 at of the second bump connector 21 a .

[0045] Figure 2A A top view of a semiconductor device according to some example embodiments of the inventive concepts is shown. Figure 2B Shown along Figure 2A A cross-sectional view taken along line II'. Figure 2C Shown along Figure 2A A cross-sectional view taken along line II-II'. Figure 2D Shows Shows Figure 2C Except as discussed below, reference has been made to Figures 1A to 1D The present inventive concept has been described in detail, and thus, further explanation will be omitted.

[0046] Reference FIG. 2A to FIG. 2D , the first lead 20 of the semiconductor device 2000 may include a first bump connector 20a and a first segment 20b. The first bump connector 20a may correspond to the end 20E of the first lead 20. The first segment 20b of the first lead 20 may correspond to the remaining portion except the first bump connector 20a. When viewed in a top view, one end of the first segment 20b of the first lead 20 may overlap with the semiconductor chip 60 (e.g., in the third direction D3), and the top surface of the other end of the first segment 20b of the first lead 20 may be exposed by the solder resist layer 40 (e.g., not overlapping with the solder resist layer 40 in the third direction D3).

[0047] The thickness t2 of the first section 20b of the first lead 20 may be less than the thickness t1 of the first bump connector 20a. The level of the top surface 20bt of the first section 20b of the first lead 20 may be lower than the level of the top surface 20at of the first bump connector 20a.

[0048] The second lead 21 may include a second bump connector 21a and a first segment 21b. The second bump connector 21a may correspond to an end 21E of the second lead 21. The first segment 21b of the second lead 21 may correspond to the remaining portion of the second lead 21 except the second bump connector 21a. One end of the first segment 21b of the second lead 21 may overlap with the semiconductor chip 60 (e.g., in the third direction D3), and the top surface of the other end of the first segment 21b of the second lead 21 may be exposed by the solder resist layer 40 (e.g., not overlap with the solder resist layer 40 in the third direction D3).

[0049] The thickness tb of the first section 21b of the second lead 21 may be less than the thickness ta of the second bump connector 21a. The level of the top surface 21bt of the first section 21b of the second lead 21 may be lower than the level of the top surface 21at of the second bump connector 21a.

[0050] The top surface 21 bt of the first segment 21 b of the second lead 21 may be located at substantially the same level as that of the top surface 20 bt of the first segment 20 b of the first lead 20 .

[0051] The thickness t2 of the first section 20b of the first lead 20 may be less than the thickness ta of the second bump connector 21a. The thickness t2 of the first section 20b of the first lead 20 may be, for example, in the range of 2 μm to 10 μm. For example, the thickness t2 of the first section 20b of the first lead 20 may be in the range of 8 μm to 10 μm.

[0052] The thickness ta of the second bump connector 21a may be, for example, in the range of 10 μm to 16 μm. In some embodiments, there may be a difference of 2 μm to 8 μm between the thickness t2 of the first segment 20b of the first lead 20 and the thickness ta of the second bump connector 21a of the second lead 21 .

[0053] In some embodiments, the horizontal height difference between the top surface 20at of the first bump connector 20a (or the top surface 21at of the second bump connector 21a) and the top surface 20bt of the first segment 20b of the first lead 20 (or the top surface 21bt of the first segment 21b of the second lead 21) can be 2μm or greater (e.g., from 2μm to 8μm, from 2μm to 10μm).

[0054] Figure 3A and Figure 3B 1 and 2 show the semiconductor devices according to some example embodiments of the present inventive concept. Figure 2A Cross-sectional views taken along line II' and line II-II'.

[0055] Reference Figure 3A and Figure 3B, the semiconductor device 2001 may include a dielectric pattern 70 disposed on the first segment 20b of the first lead 20 and also disposed on the first segment 21b of the second lead 21. The dielectric pattern 70 may be located on the top surface of the first segment 20b of the first lead 20 and / or cover the top surface of the first segment 20b of the first lead 20, and also located on the opposite side surfaces of the first segment 20b of the first lead 20 in the second direction D2 and / or cover the opposite side surfaces of the first segment 20b of the first lead 20 in the second direction D2. The dielectric pattern 70 may be located on the top surface of the first segment 21b of the second lead 21 and / or cover the top surface of the first segment 21b of the second lead 21, and may also be located on the opposite side surfaces of the first segment 21b of the second lead 21 in the second direction D2 and / or cover the opposite side surfaces of the first segment 21b of the second lead 21 in the second direction D2. The level of the top surface 70t of the dielectric pattern 70 may be lower than the level of the top surface 21at of the second bump connector 21a.

[0056] FIG. 4A to FIG. 4D Shown along Figure 1A 1 is a cross-sectional view taken along line II′ of FIG. 1 to illustrate a method of fabricating a semiconductor device according to some example embodiments of the inventive concept.

[0057] Reference Figure 4A , a metal layer 200 may be formed on the substrate 10. The metal layer 200 may be attached to the substrate 10 by an adhesive layer (not shown). A plurality of openings ( Figure 4A 2 , one of the plurality of openings is shown in FIG. 2 . The metal layer 200 may be patterned by a first etching process P200 using the first mask pattern MSK1.

[0058] Reference Figure 4B , the metal layer 200 may be patterned to form a plurality of first leads 20 and a plurality of second leads 21. Thereafter, the first mask pattern MSK1 may be removed.

[0059] Reference Figure 4C , a second mask pattern MSK2 exposing a top surface of the first lead 20 may be formed. The second mask pattern MSK2 may protect (eg, not expose) the second lead 21. A second etching process P201 may be performed to partially etch the first lead 20.

[0060] Reference Figure 4D, the first lead 20 may be partially etched to form a first segment 20b of the first lead 20. The thickness t2 of the first segment 20b of the first lead 20 may be less than the thickness ta of the second lead 21 adjacent thereto. A coating process may be performed to form a dielectric pattern 70 on the first segment 20b of the first lead 20. The second mask pattern MSK2 may be removed.

[0061] Return to reference Figure 1B and Figure 1C , a plurality of solder resist layers 40 may be formed on a portion of the first lead 20 and a portion of the second lead 21. A semiconductor chip 60 may be mounted on the substrate 10. While the semiconductor chip 60 is mounted on the substrate 10, the first bump 30 may be aligned with the first bump connector 20a of the first lead 20 and thermally compressed on the first bump connector 20a of the first lead 20, and the second bump 31 may be aligned with the second bump connector 21a of the second lead 21 and thermally compressed on the second bump connector 21a of the second lead 21. An underfill layer 50 may be formed to fill the space between the first bump 30 and the second bump 31.

[0062] FIG. 5A to FIG. 5D Cross-sectional views illustrating a method of fabricating a semiconductor device according to some example embodiments of the inventive concepts are illustrated.

[0063] Reference Figure 5A A metal seed layer 201 may be formed on the substrate 10 . The metal seed layer 201 may include, for example, copper. A first mask pattern MSK1 may be formed on the metal seed layer 201 .

[0064] Reference Figure 5B , the first lead 20 and the second lead 21 may be formed on the metal seed layer 201 exposed by the first mask pattern MSK1. For example, the first lead 20 and the second lead 21 may be deposited using an electroplating process.

[0065] Reference Figure 5C , a second mask pattern MSK2 may be formed on the first mask pattern MSK1 . The second mask pattern MSK2 may have an opening that selectively exposes the end portion 21E of the second lead 21 and the end portion 20E of the first lead 20 .

[0066] Reference Figure 5D , a conductive material (e.g., copper) may be locally deposited on the end 20E of the first lead 20 and the end 21E of the second lead 21, thereby forming the first bump connector 20a and the second bump connector 21a. The second mask pattern MSK2 may be removed, and then the metal seed layer 201 that is not formed into the first lead 20 and the second lead 21 (e.g., a portion of the metal seed layer 201 between the first lead 20 and the second lead 21 on the substrate 10) may be removed from the substrate 10.

[0067] Return to reference Figure 2B , a plurality of solder resist layers 40 may be formed, a semiconductor chip 60 may be mounted on the substrate 10 , and then an underfill layer 50 may be formed.

[0068] In a semiconductor device mounted in a flip chip manner and having staggered bumps and their corresponding leads, leakage current may flow through adjacent leads even when a slight misalignment is established between the bumps and the leads. According to the inventive concept, the step difference between the bump and its adjacent lead can be controlled to prevent and / or reduce current leakage and provide a fine pitch structure.

[0069] Furthermore, a structure for preventing and / or reducing current leakage may be provided between adjacent leads, and thus a greater number of leads may be formed in a limited area.

[0070] Although the present invention has been described in conjunction with some exemplary embodiments of the inventive concept shown in the drawings, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the scope of the inventive concept. Therefore, the embodiments disclosed above should be considered illustrative rather than restrictive.

Claims

1. A semiconductor device, comprising: substrate; a semiconductor chip, wherein the semiconductor chip is located on the substrate; as well as a first lead, a second lead and a third lead, wherein the first lead, the second lead and the third lead are located between the substrate and the semiconductor chip, wherein each of the first lead, the second lead, and the third lead extends on the substrate to below the semiconductor chip along a first direction parallel to the top surface of the substrate, The first lead includes a first bump connector and a first section connected to the first bump connector, Wherein, the second lead includes a second bump connector, Wherein, the third lead includes a third bump connector, wherein the first bump connector is spaced apart from each of the second bump connector and the third bump connector in the first direction and in a second direction, the second direction being parallel to the top surface of the substrate and perpendicular to the first direction, wherein the second bump connector is spaced apart from the third bump connector in the second direction, and the first section of the first lead is between the second bump connector and the third bump connector, The first section of the first lead is linear and extends in the first direction, and The thickness of the first section of the first lead is smaller than the thickness of the second bump connector and the thickness of the third bump connector.

2. The semiconductor device according to claim 1, wherein The thickness of the first section of the first lead is smaller than the thickness of the first bump connector.

3. The semiconductor device according to claim 1, wherein The bottom surface of the first lead is at the same level as the bottom surface of the second lead, and The top surface of the first section of the first lead has a lower level than the top surface of the second bump connector of the second lead.

4. The semiconductor device according to claim 1, wherein: A bottom surface of each of the first lead and the second lead is located at a level that is the same as or higher than a level of the top surface of the substrate.

5. The semiconductor device according to claim 1, wherein: The first lead also includes a second section, wherein the first section of the first lead is located between the second section of the first lead and the first bump connector, and The top surface of the first bump connector and the top surface of the second segment of the first lead are higher in level than the top surface of the first segment of the first lead.

6. The semiconductor device according to claim 5, further comprising a bump, wherein the bump is located on the second bump connector, in, A width of the bump in the first direction is smaller than a width of the first section of the first lead in the first direction. 7 . The semiconductor device according to claim 5 , further comprising a dielectric pattern on the top surface of the first segment of the first lead and on opposite side surfaces of the first segment of the first lead in the second direction.

8. The semiconductor device according to claim 7, wherein: The dielectric pattern includes an organic solderability preservative.

9. The semiconductor device according to claim 1, wherein: The substrate includes: a printed circuit board or a flexible film including polyimide.

10. The semiconductor device according to claim 1, wherein The thickness of the second lead is uniform along the first direction.

11. The semiconductor device according to claim 1, wherein The first section of the first lead extends from an edge of the substrate to below the semiconductor chip, and The thickness of the first section of the first lead is consistent along the first direction.

12. The semiconductor device according to claim 11, wherein The second lead also includes a first section connected to the second bump connector, wherein the second bump connector is located at the end of the second lead, and Wherein, a thickness of the first section of the second lead is smaller than a thickness of the second bump connector. 13 . The semiconductor device of claim 12 , further comprising a dielectric pattern on the first segment of the first lead and on the first segment of the second lead.

14. A semiconductor device, comprising: substrate; a semiconductor chip, wherein the semiconductor chip is located on the substrate; A plurality of first leads, wherein the plurality of first leads are located between the semiconductor chip and the substrate; as well as a plurality of second leads, wherein the plurality of second leads are respectively located between adjacent first leads among the plurality of first leads, wherein the first lead and the second lead extend on the substrate to below the semiconductor chip along a first direction parallel to the top surface of the substrate, wherein the first lead extends further in the first direction than the second lead, Each of the first leads includes a first bump connector, and each of the second leads includes a second bump connector, wherein the first bump connector and the second bump connector are arranged in a zigzag manner along a second direction parallel to the top surface of the substrate and perpendicular to the first direction, Each of the first leads includes a first section located between adjacent second bump connectors, and wherein the top surface of the first section of each of the first leads has a lower level than the top surface of each of the second bump connectors; The semiconductor device further comprises a dielectric pattern, wherein the dielectric pattern is located on the first segment of each of the first leads. The top surface of the dielectric pattern has a lower level than the top surface of the second bump connector of each of the second leads.

15. The semiconductor device according to claim 14, wherein: Each of the first leads further includes a second section, the second section being separated from the first bump connector by the first section, wherein the thickness of the first bump connector and the thickness of the second segment of each of the first leads are greater than the thickness of the first segment of each of the first leads, wherein each of the second leads has a uniform thickness along the first direction, wherein a thickness difference between the second bump connector of each second lead and the first segment of each first lead is in a range of 2 μm to 8 μm, and The thickness of the first segment of each of the first lead wires is in a range of 2 μm to 8 μm.

16. The semiconductor device according to claim 14, wherein: Each of the second leads also includes a first section connected to the second bump connector, wherein the thickness of the second bump connector of each second lead is greater than the thickness of the first section of each second lead, wherein a thickness difference between the second bump connector of each second lead and the first segment of each first lead is in a range of 2 μm to 8 μm, and The thickness of the first section of each of the first lead wires is in a range of 8 μm to 10 μm.

17. The semiconductor device according to claim 14, further comprising: a first bump located on the first bump connector of each of the first leads; as well as a second bump on the second bump connector of each of the second leads, wherein the top surface of the first bump connector extends beyond the opposite side of the first bump, and Wherein, the top surface of the second bump connector extends beyond the opposite side of the second bump.

18. A semiconductor device, comprising: substrate; a semiconductor chip, wherein the semiconductor chip is located on the substrate; a first lead and a second lead, wherein the first lead and the second lead are located between the substrate and the semiconductor chip; a solder resist layer, the solder resist layer being located on a portion of the first lead and a portion of the second lead; as well as an underfill layer, the underfill layer being located on a portion of the substrate, a portion of the first lead, a portion of the second lead, and a portion of the solder resist layer, wherein the first lead and the second lead extend on the substrate to below the semiconductor chip along a first direction parallel to the top surface of the substrate, wherein the first lead extends further in the first direction than the second lead, wherein the first lead and the second lead are spaced apart from each other in a second direction parallel to the top surface of the substrate and perpendicular to the first direction, The first lead includes a first bump connector, a first section, and a second section, wherein the first section is located between the second section and the first bump connector. Wherein, the second lead includes a second bump connector, wherein the dielectric pattern is located on the first segment of the first lead, wherein the first bump connector is spaced apart from the second bump connector in the first direction, wherein the first section of the first lead is spaced apart from the second bump connector in the second direction, wherein a first end of the first segment of the first lead vertically overlaps the semiconductor chip, and a second end of the first segment of the first lead vertically overlaps the solder resist layer, and The thickness of the first section of the first lead is smaller than the thickness of the second bump connector, the thickness of the first bump connector, and the thickness of the second section of the first lead.

19. The semiconductor device according to claim 18, wherein: A thickness difference between the second bump connector and the first section of the first lead is in a range of 2 μm to 8 μm, Wherein, the substrate comprises polyimide, wherein the first lead and the second lead comprise copper, and Wherein, the dielectric pattern includes an organic solderability protectant.

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