Magnetic storage device

Abstract

A magnetic memory device includes a device isolation layer on a substrate and defining an active region; a source region and a drain region in the active region of the substrate and separated from each other; a channel portion in the active region of the substrate and between the source region and the drain region; a spin-orbit torque (SOT) inducing layer on the channel portion of the substrate; a magnetic tunnel junction (MTJ) structure on the SOT inducing layer, the MTJ structure including a free layer on the SOT inducing layer, a tunnel barrier layer on the free layer, and a pinned layer on the tunnel barrier layer; a word line on the MTJ structure; a source line electrically connected to the source region; and a bit line electrically connected to the drain region.

Description

Technical Field

[0001] The implementation involves magnetic storage devices. Background Technology

[0002] Electronic devices utilizing the magnetoresistive properties of magnetic tunnel junction (MTJ) structures have been studied. Summary of the Invention

[0003] The embodiment relates to a magnetic storage device comprising: a device isolation layer on a substrate and defining an active region; a source region and a drain region separated from each other in the active region of the substrate; a channel portion in the channel region of the substrate and between the source and drain regions; a spin-orbit moment (SOT) induced layer on the channel portion of the substrate; a magnetic tunnel junction (MTJ) structure on the SOT induced layer, the MTJ structure including a free layer on the SOT induced layer, a tunnel barrier layer on the free layer, and a pinned layer on the tunnel barrier layer; word lines on the MTJ structure; source lines electrically connected to the source region; and bit lines electrically connected to the drain region.

[0004] The embodiment also relates to a magnetic storage device comprising: a device isolation layer on a substrate defining a plurality of active regions; source and drain regions separated from each other in each of the plurality of active regions; a channel portion between the source and drain regions; a plurality of magnetic storage cells formed on the channel portion; and word lines on the plurality of magnetic storage cells extending in a first direction parallel to the upper surface of the substrate. Each of the plurality of magnetic storage cells may include a spin-orbit moment (SOT) induced layer on the channel portion and a magnetic tunnel junction (MTJ) structure on the SOT induced layer, the MTJ structure including a free layer, a tunnel barrier layer, and a pinned layer. The word lines may be disposed at a height higher than the height of the MTJ structure.

[0005] The embodiments also relate to a magnetic storage device comprising: a channel portion on a substrate and comprising a compound semiconductor; a source region and a drain region on the substrate and separated from each other, with the channel portion located therebetween; an insulating spacer on the channel portion and comprising a magnetic insulator; a magnetic tunnel junction (MTJ) structure on the insulating spacer, the MTJ structure comprising a free layer on the insulating spacer, a tunnel barrier layer on the free layer, and a pinned layer on the tunnel barrier layer; word lines on the MTJ structure; source lines electrically connected to the source region; and bit lines electrically connected to the drain region. Attached Figure Description

[0006] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings.

[0007] Figure 1 A circuit diagram of a memory cell array of a magnetic storage device according to an example embodiment is shown;

[0008] Figure 2 A layout diagram of a magnetic storage device according to an example embodiment is shown;

[0009] Figure 3 A perspective view of a portion of a magnetic storage device according to an example embodiment is shown;

[0010] Figure 4 It shows along Figure 2 A cross-sectional view taken from line A-A';

[0011] Figure 5 It shows Figure 4 Enlarged cross-sectional view of region CX1;

[0012] Figures 6 to 8 Schematic diagrams are shown, illustrating a method for driving a magnetic storage device according to an example embodiment;

[0013] Figure 9 A cross-sectional view of a magnetic storage device according to an example embodiment is shown;

[0014] Figure 10 A cross-sectional view of a magnetic storage device according to an example embodiment is shown;

[0015] Figure 11 A layout diagram of a magnetic storage device according to an example embodiment is shown;

[0016] Figure 12 A perspective view of a portion of a magnetic storage device is shown;

[0017] Figure 13 A cross-sectional view of a magnetic storage device according to an example embodiment is shown;

[0018] Figure 14 and Figure 15 A schematic diagram illustrating a method for driving a magnetic storage device according to an example embodiment is shown; and

[0019] Figure 16 A block diagram of a storage device including a magnetic storage device according to an example embodiment is shown. Detailed Implementation

[0020] Reference will now be made in detail to the embodiments, examples of which are shown in the accompanying drawings.

[0021] Figure 1 This is a circuit diagram of a memory cell array (MCA) of a magnetic storage device according to an example embodiment.

[0022] Reference Figure 1The memory cell array (MCA) may include memory cell units (MCUs) between intersecting bit lines (BL) and word lines (WL). Each memory cell unit (MCU) may include magnetic storage cells (RMs) and select devices (SWs) connected to each other. The select device (SW) controls the flow of charge or current to the magnetic storage cells (RMs), and the magnetic storage cells (RMs) can be switched by the select device (SW). The magnetic storage cells (RMs) may be configured according to free layer 142 (see...). Figure 4 The magnetic storage unit (RM) has variable resistance due to changes in its magnetization direction. For example, data can be stored in a storage unit MCU by utilizing the resistance difference of the magnetic storage unit (RM).

[0023] The selector device SW may include, for example, an NMOS field-effect transistor or a PMOS field-effect transistor. The source of the selector device SW may be connected to a source line SL extending parallel to the bit line BL, and the drain of the selector device SW may be connected to the bit line BL. The gate of the selector device SW may be connected to the word line WL, and the magnetic storage cell RM may be located between the word line WL and the gate of the selector device SW.

[0024] According to this example implementation, in a write operation of the memory cell unit MCU, a write voltage is applied to the word line WL, a source voltage is applied to the source line SL, and a drain voltage is applied to the bit line BL. Here, the write current can flow from the source to the drain of the select device SW. The write current can flow through the spin-orbit moment (SOT) induction layer 130 (see [link to documentation]) included in the magnetic memory cell RM. Figure 4 The write current flows through the SOT-induced layer 130, generating a spin current caused by spin-orbit interaction. The write operation can be performed by the spin current flowing through the magnetic tunnel junction (MTJ) structure 140 included in the magnetic storage cell RM (see...). Figure 4 ) will be executed.

[0025] According to this example implementation, in a read operation of the memory cell unit MCU, a read voltage is applied to the word line WL, and a drain voltage is applied to the bit line BL. Here, the read current can flow from the word line WL to the drain of the select device SW through the magnetic storage cell RM. The data stored in the magnetic storage cell RM can be determined based on the magnitude of the measured read current.

[0026] According to a sample implementation of a memory cell array (MCA), the control of spin-orbit interaction can be switched using a single selection device (SW), thereby improving the integration density of the magnetic storage device. Furthermore, the spin-orbit interaction-based MCA enables fast switching and low-current operation.

[0027] Figure 2 This is a layout diagram of a magnetic storage device 100 according to an example embodiment. Figure 3 This is a perspective view of a portion of the magnetic storage device 100. Figure 4 It is along Figure 2 A cross-sectional view taken from line A-A'. Figure 5 yes Figure 4 Enlarged cross-sectional view of region CX1.

[0028] Reference Figures 2 to 5 The magnetic storage device 100 may include magnetic storage cells RM, word lines 160, source lines 174 and bit lines 178 disposed on a substrate 110.

[0029] Word line 160 may extend at a vertical height above the main surface 110M of substrate 110 in a first direction (X direction) parallel to the main surface 110M of substrate 110. Bit line 178 may extend at a vertical height above the main surface 110M of substrate 110 in a second direction (Y direction) parallel to the main surface 110M of substrate 110 and perpendicular to the first direction (X direction). Source line 174 may extend in the second direction (Y direction) while being separated from (i.e., spaced apart from) bit line 178. Source line 174 may, for example, be located at the same vertical height as bit line 178 (i.e., at the same distance from the upper surface of substrate 110 in the vertical direction (Z direction)).

[0030] In another implementation, unlike Figure 3 As shown, source line 174 may extend parallel to bit line 178 in a second direction (Y direction) at a different vertical height than bit line 178. In another embodiment, unlike... Figure 3 As shown, the source line 174 can extend parallel to the word line 160 in a first direction (X direction) at a different vertical height than the bit line 178.

[0031] The substrate 110 may have a main surface 110M extending in a first direction (X direction) and a second direction (Y direction). The substrate 110 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the substrate 110 may include a group IV semiconductor such as silicon (Si), germanium (Ge), or Si-Ge; a group III-V compound semiconductor such as gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or gallium nitride (GaN); or a group II-VI compound semiconductor such as zinc selenide (ZnSe). The substrate 110 may also be provided as a bulk wafer or an epitaxial layer. In another embodiment, the substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0032] Device isolation layer 112 may be formed on substrate 110 to define a plurality of active regions ACT. Device isolation layer 112 may fill device isolation trenches 112T formed by removing a portion of substrate 110. For example, as Figure 4 As shown, the device isolation layer 112 may have an upper surface disposed at the same height as the main surface 110M of the substrate 110. The device isolation layer 112 may include, for example, silicon oxide, silicon oxide nitride, etc.

[0033] Multiple active regions ACT can be arranged in a matrix in a first direction (X direction) and a second direction (Y direction). For example, multiple active regions ACT may include a first active region ACT1 and a second active region ACT2 arranged sequentially in the first direction (X direction). Word lines 160 can extend in the first direction (X direction) to perpendicularly overlap with the first active region ACT1 and the second active region ACT2. The source lines 174 and bit lines 178 of the perpendicularly overlapping first active region ACT1 can be separated from the source lines 174 and bit lines 178 of the perpendicularly overlapping second active region ACT2. However, in other embodiments, a common source line structure can be used, wherein one source line 174 is connected to the first active region ACT1 and the second active region ACT2 arranged sequentially in the first direction (X direction), and two bit lines 178 are connected to each of the first active region ACT1 and the second active region ACT2.

[0034] In the multiple active regions ACT, the source region 114A and the drain region 114B can be separated from each other. The channel portion CH can be on the substrate 110 between the source region 114A and the drain region 114B. For example, the channel portion CH can be disposed in the portion of the multiple active regions ACT that overlaps perpendicularly with the word line 160.

[0035] Each of the plurality of magnetic storage cells RM can be disposed on a channel portion CH in each of the plurality of active regions ACT. For example, the magnetic storage cells RM can be located between word line 160 and the main surface 110M of substrate 110, i.e., between word line 160 and channel portion CH. The plurality of magnetic storage cells RM can be arranged in a matrix in a first direction (X direction) and a second direction (Y direction). For example, the plurality of magnetic storage cells RM can include a first magnetic storage cell RM1 and a second magnetic storage cell RM2 that are separated from each other in the first direction (X direction). The first magnetic storage cell RM1 can be located on a first active region ACT1, and the second magnetic storage cell RM2 can be located on a second active region ACT2.

[0036] Each of the plurality of magnetic storage cells RM may include a SOT-induced layer 130 and an MTJ structure 140. The MTJ structure 140 may include a free layer 142, a tunnel barrier layer 144, and a pinned layer 146 sequentially disposed on the SOT-induced layer 130. The SOT-induced layer 130 may be directly on the channel portion CH, and the MTJ structure 140 may be directly on the SOT-induced layer 130. Therefore, the entire bottom surface of the SOT-induced layer 130 may contact the upper surface CHU of the channel portion CH. A first insulating layer 150 may be further disposed on the substrate 110, and the first insulating layer 150 may surround the sidewalls of the SOT-induced layer 130 and the sidewalls of the MTJ structure 140.

[0037] The first magnetic storage cell RM1 can be separated from the second magnetic storage cell RM2. Additionally, the first SOT induction layer 130_1 (see [link to documentation]) included in the first magnetic storage cell RM1... Figure 2 It can be used with the second SOT induction layer 130_2 included in the second magnetic storage unit RM2 (see...). Figure 2 Separately. The first insulating layer 150 may surround the sidewalls of the first magnetic storage cell RM1 and the second magnetic storage cell RM2, and the sidewalls of the first SOT induction layer 130_1 and the second SOT induction layer 130_2 may be surrounded by the first insulating layer 150.

[0038] like Figure 2 As shown, for example, the horizontal cross-section of the plurality of magnetic storage cells RM can be rectangular. In other embodiments, the horizontal cross-section of the plurality of magnetic storage cells RM can have various shapes, such as circular, elliptical, triangular, square, rounded rectangle, trapezoidal, polygonal, etc.

[0039] like Figure 5 As shown, for example, the width of each of the plurality of magnetic storage cells RM in the second direction (Y direction) (e.g., the first width W1 of the SOT-induced layer 130 or the second width W2 of the MTJ structure 140) can be smaller than the width W3 of the word line 160 in the second direction (Y direction). Figure 5 Unlike other magnetic storage cells RM, the width of each of the multiple magnetic storage cells RM in the second direction (Y direction) (e.g., the first width W1 of the SOT-induced layer 130 or the second width W2 of the MTJ structure 140) can be the same as the width W3 of the word line 160 in the second direction (Y direction).

[0040] In one example embodiment, the SOT-induced layer 130 may comprise a nonmagnetic material with high spin-orbit coupling properties and may serve as a spin-orbit coupling activation layer for generating spin-orbit moments in an SOT-type MRAM device. In the SOT-type MRAM device, when current flows through the SOT-induced layer 130, the free layer 142 may be switched via the spin Hall effect, i.e., by spin polarization perpendicular to the current direction caused by the interaction between the current and the spins in the lattice of the free layer 142 in contact with the SOT-induced layer 130.

[0041] In one example embodiment, the SOT-inducing layer 130 may comprise a non-magnetic metallic material or a topologically insulating material. For example, the SOT-inducing layer 130 may comprise one or more non-magnetic metallic materials selected from tungsten (W), platinum (Pt), tantalum (Ta), hafnium (Hf), rhenium (Re), iridium (Ir), gold (Au), silver (Ag), titanium (Ti), and copper (Cu), and / or the SOT-inducing layer 130 may comprise one or more topologically insulating materials selected from bismuth telluride (Bi₂Te₃), bismuth selenide (Bi₂Se₃), antimony telluride (Sb₂Te₃), molybdenum sulfide (MoS₂), molybdenum telluride (MoTe₂), tungsten sulfide (WS₂), and tungsten telluride (WTe₂). A topologically insulating material generally refers to a material that has insulating properties in its bulk region, while the portion adjacent to its surface is conductive due to a specific crystallographic periodicity. For example, when the SOT-induced layer 130 includes a topological insulating material, the portion of the SOT-induced layer 130 adjacent to the upper surface CHU of the channel portion CH and / or the portion of the SOT-induced layer 130 adjacent to the free layer 142 may exhibit conductivity.

[0042] In one example embodiment, the MTJ structure 140 can be configured as a vertical magnetic storage device 100 based on a perpendicular magnetic anisotropy (PMA) material. The pinned layer 146 has a fixed easy magnetization axis and can have a fixed magnetization direction. For example, the pinned layer 146 can have an easy magnetization axis in a third direction (Z direction), and the pinned layer 146 can comprise a PMA material. The free layer 142 can have a variable magnetization direction depending on conditions. For example, the free layer 142 can have a variable easy magnetization axis in a third direction (Z direction).

[0043] In another embodiment, the pinned layer 146 may have an easy magnetization axis in a first direction (X direction) parallel to the main surface 110M of the substrate 110, and the free layer 142 may have a variable easy magnetization axis in the first direction (X direction). In this case, a horizontal magnetic storage device can be realized.

[0044] The resistance of the MTJ structure 140 depends on the magnetization direction of the free layer 142. When the magnetization direction of the free layer 142 and the magnetization direction of the pinned layer 146 are parallel to each other, the MTJ structure 140 has a low resistance and can store data "0". When the magnetization direction of the free layer 142 and the magnetization direction of the pinned layer 146 are antiparallel, the MTJ structure 140 has a high resistance and can store data "1". In another embodiment, the MTJ structure 140 can store data "1" when it has a low resistance and can store data "0" when it has a high resistance.

[0045] The free layer 142 may comprise a material with relatively low magnetic saturation (Ms), such as one or more of MnGa, MnGe, MnAl, MnGaNi, MnGeNi, MnGaCo, MnGeCo, MnGaFe, and MnGeFe. When a current flows through the SOT-induced layer 130 in an in-plane direction, the entire bottom surface of the free layer 142 may contact the upper surface 130U of the SOT-induced layer 130, thereby transferring the spin current generated in the SOT-induced layer 130 to the free layer 142 through spin-orbit interaction.

[0046] The tunnel barrier layer 144 may include a non-magnetic insulator. In one example embodiment, the tunnel barrier layer 144 may include one or more of oxides of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium zinc (MgZn), or magnesium boron (MgB) and / or nitrides of titanium (Ti) or vanadium (V). For example, the tunnel barrier layer 144 may include a magnesium oxide (MgO) film or a magnesium aluminum oxide (MgAlO) film. In another embodiment, the tunnel barrier layer 144 may include multiple layers. For example, the tunnel barrier layer 144 may have a stacked structure of Mg / MgO, MgO / Mg, MgO / MgAlO, MgAlO / MgO, Mg / MgAlO / Mg, MgO / MgAlO / MgO, MgAlO / MgO / MgAlO, etc. The tunnel barrier layer 144 may have a NaCl crystal structure (e.g., a face-centered cubic lattice structure). The tunnel barrier layer 144 may have a thickness of, for example, about 1 nm to about 20 nm in a third direction (Z direction) perpendicular to the upper surface of the substrate 110.

[0047] The pinned layer 146 may include at least one of a perpendicular magnetic material, a perpendicular magnetic material having an L10 structure, a CoPt alloy having a hexagonal close-packed lattice structure, and a perpendicular magnetic stack. The perpendicular magnetic material may include one or more of iron (Fe), nickel (Ni), Pt, palladium (Pd), boron (B), Ta, W, Ir, and cobalt (Co), and may include one or more of, for example, CoFeB, CoFeTb, CoFeGd, and CoFeDy. For example, the perpendicular magnetic material having an L10 structure may be Fe... 50 Pt 50 Fe 50 Pd 50 Co 50 Pt 50 Co 50 Pd 50 and Fe 50 Ni 50 One or more of the following. A perpendicular magnetic stack can include a stack structure in which ferromagnetic layers are arranged alternately and repeatedly, or a stack structure in which ferromagnetic layers and non-magnetic layers are arranged alternately and repeatedly. For example, a perpendicular magnetic stack can include one or more of the following: (Co / Pt)n stack structure, (CoFe / Pt)n stack structure, (CoFe / Pd)n stack structure, (Co / Pd)n stack structure, (Co / Ni)n stack structure, (CoNi / Pt)n stack structure, (CoCr / Pt)n stack structure, and (CoCr / Pd)n stack structure (where n is a natural number 1 or greater).

[0048] In another embodiment, the pinned layer 146 may include a synthetic antiferromagnetic material (SAF) having a non-magnetic layer between the ferromagnetic layers. The non-magnetic layer may include a material that enables Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling between the ferromagnetic layers, such as one or more of ruthenium (Ru), iridium (Ir), and rhodium (Rh).

[0049] Word line 160 may extend along a first direction (X direction) on the magnetic storage cell RM and the first insulating layer 150. For example, a word line 160 may connect to a first magnetic storage cell RM1 and a second magnetic storage cell RM2 that are separated from each other in the first direction (X direction). Word line 160 may include conductive materials such as doped polysilicon, titanium, titanium nitride, tantalum, tantalum nitride, titanium tungsten, tungsten, aluminum, cobalt, nickel, copper, etc.

[0050] A second insulating layer 152 covering word line 160 may be on the first insulating layer 150. Source line 174 and bit line 178 may be on the second insulating layer 152. Source line contact 172 may be formed in a source line contact hole 172H passing through the first insulating layer 150 and the second insulating layer 152 to connect source line 174 to source region 114A. Bit line contact 176 may be formed in a bit line contact hole 176H passing through the first insulating layer 150 and the second insulating layer 152 to connect bit line 178 to drain region 114B. A third insulating layer 154 covering source line 174 and bit line 178 may be on the second insulating layer 152.

[0051] like Figure 5 As shown, the sidewalls of the SOT-induced layer 130 can be aligned with the sidewalls of the MTJ structure 140. This structure can be obtained through the following fabrication process: sequentially forming an initial SOT-induced layer, an initial free layer, an initial tunnel barrier layer, and an initial pinned layer on the main surface 110M of the substrate 110, and simultaneously or sequentially patterning these layers. During the patterning process, the sidewalls of the SOT-induced layer 130 and the MTJ structure 140 can be substantially perpendicular to the main surface 110M of the substrate 110, or the sidewalls of the SOT-induced layer 130 and the MTJ structure 140 can be tilted from the main surface 110M of the substrate 110 at a certain angle. For example, when the sidewalls of the SOT-induced layer 130 and the MTJ structure 140 are substantially perpendicular to the main surface 110M of the substrate 110, the SOT-induced layer 130 may have a first width W1 in the second direction (Y direction), and the MTJ structure 140 may have a second width W2 in the second direction (Y direction) that is substantially equal to the first width W1.

[0052] and Figure 5 As shown, the sidewalls of the SOT-inducing layer 130 and the MTJ structure 140 can be tilted at a certain angle from the main surface 110M of the substrate 110, widening towards the main surface 110M of the substrate 110. In another embodiment, the sidewalls of the SOT-inducing layer 130 can protrude outward relative to the sidewalls of the MTJ structure 140. In these cases, the second width W2 of the MTJ structure 140 can be smaller than the first width W1 of the SOT-inducing layer 130. Furthermore, with Figure 5 As shown, the sidewalls of the SOT-inducing layer 130 and the MTJ structure 140 can be tilted at a certain angle from the main surface 110M of the substrate 110 to narrow towards the main surface 110M of the substrate 110. In another embodiment, the sidewalls of the SOT-inducing layer 130 can be recessed inward relative to the sidewalls of the MTJ structure 140. In these cases, the second width W2 of the MTJ structure 140 can be greater than the first width W1 of the SOT-inducing layer 130.

[0053] like Figure 5 As shown, based on the main surface 110M of the substrate 110, the word line 160 can be disposed at a height higher than the height of the SOT-induced layer 130 and the MTJ structure 140. For example, the SOT-induced layer 130, the free layer 142, the tunnel barrier layer 144, the pinned layer 146, and the word line 160 can be sequentially disposed on the upper surface CHU of the channel portion CH. Therefore, the height LV1 of the upper surface 130U of the SOT-induced layer 130 can be higher than the height LV0 of the main surface 110M of the substrate 110, the height LV2 of the upper surface of the MTJ structure 140 can be higher than the height LV1 of the upper surface 130U of the SOT-induced layer 130, and the height LV3 of the upper surface of the word line 160 can be higher than the height LV2 of the upper surface of the MTJ structure 140.

[0054] According to one example embodiment, the tunnel barrier layer 144 can be used as the gate insulating layer of the select transistor TR, which is composed of word line 160, source region 114A, and drain region 114B. When the select transistor TR is turned on, current can flow not only in the channel portion CH but also in the SOT induction layer 130. Therefore, the SOT induction layer 130 can be used as an auxiliary channel portion of the select transistor TR.

[0055] Typically, in spin-transfer torque (STT) type MRAM devices, write current and read current pass through the MTJ structure to perform write and read operations respectively. However, since the path of the write current in a write operation is the same as the path of the read current in a read operation, read interference may occur.

[0056] Meanwhile, in SOT-type MRAM devices utilizing spin-orbit coupling, the write and read currents follow different paths, preventing read interference and exhibiting relatively high tunneling magnetoresistance (TMR), enabling fast switching and low-current operation. However, in conventional SOT-type MRAM devices, two transistors are formed to perform write and read operations. Therefore, since the first transistor, formed by the first word line, is used for selection during write operations, and the second transistor, formed by the second word line, is used for selection during read operations, the area required for a single magnetic storage cell (RM) can be relatively large, potentially limiting the integration density of the MRAM device.

[0057] Conversely, according to this example embodiment, when a write voltage is applied to word line 160, current flows in the channel portion CH between source region 114A and drain region 114B, and current can also flow in the SOT-induced layer 130 (i.e., the portion of SOT-induced layer 130 corresponding to the auxiliary channel portion) that contacts the channel portion CH. Since the current flowing in SOT-induced layer 130 generates a spin current in a direction perpendicular to the upper surface 130U of SOT-induced layer 130, the magnetization direction of free layer 142 can be controlled by using the current flowing in select transistor TR. Therefore, read and write operations can be performed on a magnetic memory cell RM using a single select transistor TR. The magnetic storage device 100 can thus achieve fast switching and low-current operation while exhibiting improved integration.

[0058] In the following text, reference will be made to Figures 6 to 8 A driving method for a magnetic storage device 100 according to an example embodiment is described.

[0059] Figure 6 The diagram schematically illustrates the spin current generated by current in a junction structure of non-magnetic and magnetic materials.

[0060] Reference Figure 6 In a stacked structure of a nonmagnetic material layer NM and a magnetic metal layer FM, current can flow in the longitudinal direction of the nonmagnetic material layer NM (e.g., the longitudinal direction of the stacked structure or...). Figure 6 (in the X direction). For example, the nonmagnetic material layer NM may include a nonmagnetic material with high spin-orbit coupling characteristics, such as a nonmagnetic metallic material or a topological insulating material. Here, the current caused by charge transfer can be represented by J. C This indicates that, due to the high spin-orbit coupling properties of the nonmagnetic material layer NM, electrons with a single spin (e.g., spin-up) can move in the horizontal direction of the nonmagnetic material layer NM (e.g., the vertical direction of the longitudinal direction of the stacked structure or...). Figure 6 Electrons with opposite spin (e.g., spin down) can deflect in the +Z direction, while electrons with the opposite spin can deflect in the other direction (e.g., spin down). Figure 6 The current deflects in the -Z direction. For example, when current flows in the X direction, spin-up electrons accumulate in the +Z direction, and spin-down electrons accumulate in the -Z direction. Adding them together, a spin current can be generated in the -Z direction (or +Z direction). This spin current can be generated by... Figure 6 J in S This indicates that when current flows in the non-magnetic material layer NM, it can interact with the current J. C A spin current J is induced in the direction perpendicular to the direction. S Furthermore, the spin torque can be transmitted to the magnetic metal layer FM, which is in contact with the non-magnetic material layer NM.

[0061] Figure 7 and Figure 8 Write and read operations of a magnetic storage device 100 according to an example embodiment are illustrated schematically.

[0062] Reference Figure 7 In a write operation of the magnetic storage device 100, when a write voltage is applied to word line 160, the select transistor TR can be turned on, the source voltage is applied to source line 174, the drain voltage is applied to bit line 178, and the write current I... write The current flows from the source region 114A to the drain region 114B via the channel portion CH. Here, the current I is written. write It can flow through the channel portion CH and the SOT-induced layer 130 in contact with the channel portion CH. For example, Figure 7 The writing current I is schematically shown. write The portion of the current flowing through the channel section CH is shown as the first write current I1, and the write current I... write The portion flowing through the SOT-induced layer 130 is shown as the second write current I2. Through the spin Hall effect of the SOT-induced layer 130, for example, the spin current I... spin The spin current I2 can be generated in the SOT-induced layer 130 and applied to the free layer 142. spin This can occur perpendicular to the write current I. write (or the direction of the second writing current I2). Therefore, the magnetization direction of the free layer 142 can be determined by the spin current I. spin This allows data to be written to the magnetic storage unit RM.

[0063] Reference Figure 8 When a read voltage is applied to word line 160 and a drain voltage is applied to bit line 178, the read current I... read It can flow through word line 160, MTJ structure 140, SOT induced layer 130, channel portion CH, and drain region 114B. Read current I read The value can vary depending on the resistance state of the MTJ structure 140 (i.e., the magnetization direction of the free layer 142 and the magnetization direction of the pinned layer 146). For example, the MTJ structure 140 can have a low resistance value when the magnetization directions of the free layer 142 and the pinned layer 146 are parallel to each other. Conversely, the MTJ structure 140 can have a high resistance value when the magnetization directions of the free layer 142 and the pinned layer 146 are antiparallel to each other. This is achieved by measuring the read current I... read By comparing the values, it can be detected whether the MTJ structure 140 is in a low-resistance state (data 0 or 1) or a high-resistance state (data 1 or 0). Therefore, the data stored in the MTJ structure 140 can be determined.

[0064] like Figure 7 and Figure 8 As shown, according to the magnetic storage device 100 of this example embodiment, the write current I flowing through the selection transistor TR can be used. write Write operations are performed via the select transistor TR of word line 160. Therefore, although both read and write operations are performed via the select transistor TR of word line 160, the current paths in the read operation and the write operation can be different. Therefore, it is not necessary to form a separate transistor connected to the SOT line for the write operation (e.g., for a single magnetic storage cell, it is not necessary to form a first transistor for the write operation and a second transistor for the read operation), thus improving the integration density of the magnetic storage device 100.

[0065] Figure 9 This is a cross-sectional view of a magnetic storage device 100A according to an example embodiment. Figure 9 It is along Figure 2 A cross-sectional view taken by line A-A'. Figure 9 In, with Figures 1 to 8 The same reference numerals denote the same elements.

[0066] Reference Figure 9 The magnetic storage cell (RMA) may include a metal silicide layer 132, an SOT-inducing layer 130, and an MTJ structure 140. The metal silicide layer 132 may include, for example, nickel silicide, cobalt silicide, tungsten silicide, etc., and the SOT-inducing layer 130 may include one or more non-magnetic metallic materials selected from, for example, W, Pt, Ta, Hf, Re, Ir, Au, Ag, Ti, and Cu.

[0067] According to this exemplary embodiment, the metal silicide layer 132 between the SOT-inducing layer 130 and the channel portion CH can help reduce the contact resistance between the channel portion CH, which includes semiconductor material, and the SOT-inducing layer 130, which includes metal material. Therefore, the write current I flowing through the SOT-inducing layer 130 can be increased by the metal silicide layer 132. write The amount of data allows the magnetic storage device 100A to perform low-power operations. Furthermore, since a single select transistor TR can be used to perform read and write operations relative to a single magnetic storage cell RMA, the integration density of the magnetic storage device 100A can be increased.

[0068] Figure 10 This is a cross-sectional view of a magnetic storage device 100B according to an example embodiment. Figure 10 It is along Figure 2 A cross-sectional view taken by line A-A'. Figure 10 In, with Figures 1 to 9 The same reference numerals denote the same elements.

[0069] Reference Figure 10 The magnetic storage unit RMB according to this example embodiment may include an SOT induction layer 130, an insulating spacer 134, and an MTJ structure 140.

[0070] For example, the insulating spacer 134 may include a magnetic insulator. For example, the magnetic insulator may be yttrium iron garnet (YIG, Y3Fe5O4). 12 Nickel ferrite (NiFe2O4), iron manganese oxide (MnFe2O4), nickel zinc ferrite (Ni 1-x Zn x FeO4) or manganese zinc ferrite (Mn 1-x Zn x FeO4).

[0071] According to this exemplary embodiment, an insulating spacer 134 is disposed between the SOT-induced layer 130 and the free layer 142. Therefore, the tunneling magnetoresistance (TMR) of the magnetic storage cell RMB can be improved, and the magnetic storage device 100B can operate with low power. Furthermore, since a single select transistor TR can be used to perform read and write operations relative to a single magnetic storage cell RMB, the integration density of the magnetic storage device 100B can be increased.

[0072] Figure 11 This is a layout diagram of a magnetic storage device 100C according to an example embodiment. Figure 12 This is a perspective view of a portion of the magnetic storage device 100C.

[0073] Reference Figure 11 and Figure 12 Multiple active regions ACT can be arranged in a matrix form in a first direction (X direction) and a second direction (Y direction). The multiple active regions ACT can include a first active region ACT1 and a second active region ACT2 sequentially arranged in the first direction (X direction). A word line 160 can perpendicularly overlap with the first active region ACT1 and the second active region ACT2, and can extend in the first direction (X direction).

[0074] The plurality of magnetic storage cells RMC may include a first magnetic storage cell RMC1 and a second magnetic storage cell RMC2 arranged in a first direction (X direction), and the SOT induction layer 130C may extend in the first direction (X direction) and may be shared by the first magnetic storage cell RMC1 and the second magnetic storage cell RMC2. That is, the portion of the SOT induction layer 130C included in the first magnetic storage cell RMC1 and the portion of the SOT induction layer 130C included in the second magnetic storage cell RMC2 may be connected to each other.

[0075] According to one example embodiment, the SOT induction layer 130C may contact the upper surface of the substrate 110 and the upper surface of the device isolation layer 112, and may extend in a first direction (X direction).

[0076] In another implementation, with Figure 12 Unlike other methods, a metal silicide layer 132 can be further formed between the SOT-induced layer 130C and the upper surface of the substrate 110 (see...). Figure 9 In addition, with Figure 12 Unlike other structures, an insulating spacer 134, including a magnetic insulator, can be further formed between the SOT-induced layer 130C and the MTJ structure 140 (see...). Figure 10 The metal silicide layer 132 and / or insulating spacer 134 may extend in the first direction (X direction), or may be formed only at a position that perpendicularly overlaps with the first magnetic storage cell RMC1 and the second magnetic storage cell RMC2.

[0077] Figure 13 This is a cross-sectional view of a magnetic storage device 100D according to an example embodiment. Figure 13 It is along Figure 2 A cross-sectional view taken by line A-A'. Figure 13 In, with Figures 1 to 12 The same reference numerals denote the same elements.

[0078] Reference Figure 13 Device isolation layer 112 may be formed on substrate 110 to define a plurality of active regions ACT. In one example embodiment, substrate 110 may include a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, substrate 110 may include a group IV semiconductor such as Si, Ge, or Si-Ge, a group III-V compound semiconductor such as GaAs, InAs, InP, or GaN, or a group II-VI compound semiconductor such as ZnSe.

[0079] A pair of recessed regions 114R formed by removing a portion of the substrate 110 can be formed in the active region ACT, and the source region 114AD and drain region 114BD filling the pair of recessed regions 114R can be separated from each other. The source region 114AD and drain region 114BD may include a semiconductor layer (not shown) formed in the pair of recessed regions 114R using a selective epitaxial growth (SEG) process or the like, wherein the pair of recessed regions 114R are formed by removing a portion of the substrate 110. The source region 114AD and drain region 114BD may include a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor.

[0080] The channel portion CHD can be located on the substrate 110 between the source region 114AD and the drain region 114BD. The channel portion CHD may include the same material as the substrate 110, or it may include a different material from the substrate 110. For example, when the channel portion CHD includes a different material from the substrate 110, the channel portion CHD may include a semiconductor layer 116 formed by performing an epitaxial growth process on the upper surface of the substrate 110.

[0081] In one example embodiment, the channel portion CHD may include a compound semiconductor. For example, the channel portion CHD may include a group III-V compound semiconductor such as GaAs, InAs, InP, or GaN, or a group II-VI compound semiconductor such as ZnSe. In some embodiments, the channel portion CHD may include a compound semiconductor in which a SOT-inducing dopant is included at a first concentration. For example, the SOT-inducing dopant may include one or more of Ga, Al, In, B, and P.

[0082] In one example, the channel portion CHD may include gallium arsenide (e.g., Al) containing aluminum as a SOT-inducing dopant at a first concentration. x Ga 1-x A ternary semiconductor compound of As (0.01 ≤ x ≤ 0.5). In another example, the channel portion CHD may comprise gallium arsenide (e.g., In) containing indium as a SOT-inducing dopant at a first concentration. x Ga 1-x Ternary semiconductor compounds of As (0.01≤x≤0.5)).

[0083] In another example, the channel portion CHD can be formed as a stacked structure including a semiconductor layer 116 and a cover semiconductor layer (not shown) formed on the semiconductor layer 116. The semiconductor layer 116 and the cover semiconductor layer can include one or more of GaAs, InAs, InP, GaN, and ZnSe. Alternatively, the semiconductor layer 116 and / or the cover semiconductor layer can include one or more of GaAs, InAs, InP, GaN, and ZnSe containing a SOT-inducing dopant at a first concentration. In some examples, the semiconductor layer 116 can include gallium arsenide (e.g., In) containing indium as an SOT-inducing dopant at a first concentration. x Ga 1-x The ternary semiconductor compound is As (0.01≤x≤0.5), and the covering semiconductor layer may include GaAs.

[0084] like Figure 13As shown, the bottom surface of the channel portion CHD can be disposed at a height higher than the bottom surfaces of the source region 114AD and the drain region 114BD. For example, the channel portion CHD can be formed by forming a semiconductor layer 116 on the substrate 110 using an epitaxial growth process, and then the pair of recessed regions 114R can be formed by removing a portion of the semiconductor layer 116 and a portion of the substrate 110 together. However, compared with Figure 13 As shown, the bottom surface of the channel portion CHD can be set at the same height as or lower than the bottom surfaces of the source region 114AD and the drain region 114BD.

[0085] In another embodiment, the channel portion CHD can be formed by forming a semiconductor layer 116 on the substrate 110 using an epitaxial growth process, and the source region 114AD and drain region 114BD can be formed by implanting impurities into a portion of the substrate 110 and a portion of the semiconductor layer 116. In this case, the pair of recessed regions 114R may not be formed.

[0086] Multiple magnetic storage cells (RMDs) can be disposed on the channel portion (CHD) of each active region of multiple active regions (ACTs). Each of the multiple magnetic storage cell RMDs may include an insulating spacer 134D and an MTJ structure 140. Word lines 160 extending in a first direction (X direction) may be disposed on the multiple magnetic storage cell RMDs.

[0087] The insulating spacer 134D may be on the channel portion CHD. For example, the insulating spacer 134D may include a magnetic insulator. For example, the magnetic insulator may be Y3Fe5O. 12 NiFe2O4, MnFe2O4, Ni 1-x Zn x FeO4 and Mn 1-x Zn x FeO4. The insulating spacer 134D can be used as the gate insulating layer of the select transistor TRD, which consists of word line 160, source region 114AD and drain region 114BD.

[0088] The MTJ structure 140 can be on the insulating spacer 134D. Therefore, the free layer 142, the tunnel barrier layer 144, and the pinned layer 146 can be sequentially disposed on the insulating spacer 134D.

[0089] According to one example embodiment, the channel portion CHD comprises a compound semiconductor or a compound semiconductor containing a SOT-inducing dopant. The channel portion CHD can serve not only as the channel region of a selectable transistor TRD, but also as a spin-orbit coupling activation layer for generating a spin-orbit moment (SOT) via the spin Hall effect. Therefore, a spin current can be generated in a direction perpendicular to the upper surface of the channel portion CHD by a current flowing in the channel portion CHD, and the spin current can flow to a free layer 142 that is in contact with the channel portion CHD (or connected to the channel portion CHD via an insulating spacer 134D comprising a magnetic insulator).

[0090] The first insulating layer 150 may surround the sidewalls of the magnetic storage cell RMD. For example... Figure 13 As shown, the sidewalls of the insulating spacer 134D and the sidewalls of the MTJ structure 140 can be aligned relative to each other. This can be achieved through a fabrication process that sequentially forms an initial insulating isolation layer, an initial free layer, an initial tunnel barrier layer, and an initial pinned layer on the channel portion CHD, the source region 114AD, the drain region 114BD, and the device isolation layer 112, and then patterns these layers. During the patterning process, the sidewalls of the insulating spacer 134D and the sidewalls of the MTJ structure 140 can be substantially perpendicular to the main surface 110M of the substrate 110, or the sidewalls of the insulating spacer 134D and the sidewalls of the MTJ structure 140 can be tilted from the main surface 110M of the substrate 110 at a certain angle. Figure 13 As shown, the sidewalls of the insulating spacer 134D can be recessed inward or protrude outward from the sidewalls of the MTJ structure 140.

[0091] Figure 14 and Figure 15 This is a schematic diagram illustrating a method for driving a magnetic storage device 100D according to an example embodiment. Figure 14 and Figure 15 Write and read operations of a magnetic storage device 100D according to an example embodiment are illustrated schematically.

[0092] Reference Figure 14 When a write voltage is applied to word line 160, a source voltage is applied to source line 174, and a drain voltage is applied to word line 178, the select transistor TRD can be turned on, and the write current I... write The current flows from the source region 114AD to the drain region 114BD via the channel portion CHD. Here, the spin current I... spin It can be generated through the spin Hall effect of the channel portion of the CHD, and the spin current I spin It can be applied to the free layer 142 via the insulating spacer 134D. For example, spin current I spin It can be perpendicular to the write current I writeThe magnetization direction of the free layer 142 is generated in the direction of the spin current I. Therefore, the magnetization direction of the free layer 142 can be determined by the spin current I. spin This allows data to be written to the magnetic storage unit RMD.

[0093] Reference Figure 15 When the read voltage is applied to word line 160 and the drain voltage is applied to bit line 178, the read current I... read It can flow through word line 160, MTJ structure 140, channel portion CHD, and drain region 114BD. Read current I read The value can vary depending on the resistance state of the MTJ structure 140, i.e., the magnetization direction of the free layer 142 and the magnetization direction of the pinned layer 146. This is achieved by comparing the measured reading current I. read By comparing the values, it is possible to detect whether the MTJ structure 140 is in a low-resistance state (data 0 or 1) or a high-resistance state (data 1 or 0). Therefore, the data stored in the MTJ structure 140 can be determined.

[0094] Figure 16 This is a block diagram of a storage device 200 including a magnetic storage device according to an example embodiment.

[0095] Reference Figure 16 A storage device 200 according to an example embodiment includes a storage cell array 210, a decoder 220, a read / write circuit 230, an input / output buffer 240, and a controller 250. The storage cell array 210 may include reference... Figures 1 to 15 At least one of the magnetic storage devices 100, 100A, 100B, 100C and 100D described.

[0096] Multiple memory cells in memory cell array 210 are connected to decoder 220 via word line WL and to read / write circuitry 230 via bit line BL. Decoder 220 receives external address ADD and, under the control of controller 250 which operates according to control signal CTRL, decodes the row and column addresses to be accessed in memory cell array 210.

[0097] The read / write circuit 230 receives data DATA from the input / output buffer 240 and the data line DL, and can write the data to a selected memory cell of the memory cell array 210 under the control of the controller 250, or can provide the input / output buffer 240 with data read from a selected memory cell of the memory cell array 210 under the control of the controller 250.

[0098] By summarizing and reviewing, as the MTJ cells of highly integrated magnetic random access memory (MRAM) devices have been miniaturized, MRAM devices for storing information by programming the MTJ cells using spin-orbit moments have been considered. Such MRAM devices offer fast switching and low-current operation.

[0099] As described above, the embodiments relate to a magnetic storage device including a magnetic tunnel junction structure.

[0100] One implementation could provide a magnetic storage device capable of performing fast switching and low-current operation.

[0101] This document has disclosed exemplary embodiments, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some cases, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0102] The entire contents of Korean Patent Application No. 10-2019-0099871, entitled “MAGNETIC MEMORY DEVICE”, filed with the Korean Intellectual Property Office on August 14, 2019, are incorporated herein by reference.

Claims

1. A magnetic storage device, comprising: Device isolation layer, on substrate and defining active region; The source region and the drain region are separated from each other in the active region of the substrate; The channel portion is located in the active region of the substrate and between the source region and the drain region; A spin orbital moment (SOT) induced layer is present on the channel portion of the substrate; A magnetic tunnel junction (MTJ) structure on the spin-orbit moment-inducing layer, the magnetic tunnel junction structure comprising: Free layers on the spin orbital moment induced layer, The tunnel barrier layer on the free layer, and The pinned layer on the tunnel barrier layer; Word lines on the magnetic tunnel junction structure; The source line electrically connected to the source region; and The bit line is electrically connected to the drain region.

2. The magnetic storage device according to claim 1, wherein, The entire upper surface of the magnetic tunnel structure is covered by the letter lines.

3. The magnetic storage device according to claim 1, wherein, The spin-orbit moment induction layer includes one or more of tungsten, platinum, tantalum, hafnium, rhenium, iridium, gold, silver, titanium, copper, bismuth telluride, bismuth selenide, antimony telluride, molybdenum sulfide, molybdenum telluride, tungsten sulfide, and tungsten telluride.

4. The magnetic storage device according to claim 1, wherein, The magnetic storage device is configured such that, during a write operation, write current flows from the source region to the drain region through the channel portion and the spin-orbit moment induction layer.

5. The magnetic storage device according to claim 4, wherein, The magnetic storage device is configured such that, during the write operation, when the write current flows through the spin-orbit moment induction layer, the spin current is transmitted to the free layer in contact with the spin-orbit moment induction layer via spin-orbit coupling characteristics.

6. The magnetic storage device according to claim 1, wherein, The magnetic storage device is configured such that, during a read operation, the read current flows from the word line to the drain region through the magnetic tunnel junction structure and the spin orbital moment induction layer.

7. The magnetic storage device according to claim 1, wherein, Based on the upper surface of the substrate, the upper surface of the word line is disposed at a height higher than the upper surface of the magnetic tunnel junction structure and the upper surface of the spin orbital moment induction layer.

8. The magnetic storage device according to claim 1, wherein, The entire bottom surface of the spin orbit moment induction layer is in contact with the upper surface of the channel portion.

9. The magnetic storage device of claim 1, further comprising a metal silicide layer between the spin orbital moment induction layer and the upper surface of the substrate.

10. The magnetic storage device of claim 1, further comprising an insulating spacer between the spin-orbit moment induction layer and the magnetic tunnel junction structure.

11. The magnetic storage device according to claim 10, wherein: The insulating spacer includes a magnetic insulator, and The magnetic insulator includes one or more of yttrium iron garnet, nickel ferrite, iron manganese oxide, nickel zinc ferrite, and manganese zinc ferrite.

12. A magnetic storage device, comprising: A device isolation layer is provided on the substrate and defines multiple active regions. The source region and the drain region are separated from each of the plurality of active regions; The channel portion is located between the source region and the drain region; Multiple magnetic storage cells are respectively formed on the channel portion; as well as Word lines, on the plurality of magnetic storage cells, and extending in a first direction parallel to the upper surface of the substrate, wherein: Each of the plurality of magnetic storage cells includes: Spin-orbit moment (SOT) induced layer on the channel portion; and A magnetic tunnel junction (MTJ) structure on the spin-orbit moment-inducing layer, the MTJ structure comprising a free layer, a tunnel barrier layer, and a pinned layer, and The word line is set at a height higher than the height of the magnetic tunnel structure.

13. The magnetic storage device according to claim 12, wherein: The plurality of magnetic storage units include a first magnetic storage unit and a second magnetic storage unit that are separated from each other in the first direction. The word lines cover both the upper surfaces of the first magnetic storage cell and the upper surfaces of the second magnetic storage cell, and The first spin-orbit moment induction layer included in the first magnetic storage cell is separate from the second spin-orbit moment induction layer included in the second magnetic storage cell.

14. The magnetic storage device of claim 13, further comprising an insulating layer surrounding the sidewalls of the first magnetic storage cell and the second magnetic storage cell. The sidewalls of the first spin-orbit moment induction layer and the sidewalls of the second spin-orbit moment induction layer are surrounded by the insulating layer.

15. The magnetic storage device according to claim 12, wherein: The plurality of magnetic storage units include a first magnetic storage unit and a second magnetic storage unit that are separated from each other in the first direction. The word lines cover both the upper surfaces of the first magnetic storage cell and the upper surfaces of the second magnetic storage cell, and The spin-orbit moment induction layer included in the first magnetic storage unit is connected to the spin-orbit moment induction layer included in the second magnetic storage unit, thus forming a single unit.

16. The magnetic storage device according to claim 15, wherein, The spin-orbit moment induction layer vertically overlaps the plurality of active regions and extends in the first direction.

17. A magnetic storage device, comprising: The channel portion is on a substrate and includes a compound semiconductor, wherein the compound semiconductor includes a spin orbital moment (SOT) induced dopant at a first concentration, and the compound semiconductor includes at least one of group III-V semiconductors and group II-VI semiconductors; The source region and the drain region are on the substrate and separated from each other, and the channel portion is between the source region and the drain region; An insulating spacer is present on the channel portion and includes a magnetic insulator; A magnetic tunnel junction (MTJ) structure on the insulating spacer, the magnetic tunnel junction structure comprising: Free layer on the insulating spacer, The tunnel barrier layer on the free layer, and The pinned layer on the tunnel barrier layer; Word lines on the magnetic tunnel junction structure; The source line electrically connected to the source region; and The bit line is electrically connected to the drain region.

18. The magnetic storage device according to claim 17, wherein, The spin orbital moment induced dopant includes one or more of gallium, aluminum, indium, boron, and phosphorus.

19. The magnetic storage device according to claim 17, wherein: The magnetic storage device is configured such that, during a write operation, write current flows through the channel portion from the source region to the drain region, and The magnetic storage device is configured such that, during the write operation, when the write current flows through the channel portion, the spin current is transmitted to the free layer via an insulating spacer in contact with the channel portion through spin-orbit coupling characteristics.

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