Non-volatile memory devices and storage systems

Abstract

A nonvolatile memory device includes: a memory cell array including a plurality of cell strings, at least one of the cell strings including a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, at least one of the memory cells being a multi-level cell storing at least three bits; and a control logic circuit configured to control a page buffer to read a fast read page of the memory cell using one read voltage and at least two normal read pages of the memory cell using the same number of read voltages.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0102178 filed on August 21, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a nonvolatile memory device. Background Art

[0004] Semiconductor memory can be classified as a volatile memory device or a non-volatile memory device. In the absence of power, a volatile memory device loses the data stored therein. Examples of volatile memory devices include static random access memory (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices retain the data stored therein even in the absence of power. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0005] Various programming techniques are used to increase the number of data bits to be stored per memory cell. However, some data is required to be programmed in a single-level cell (SLC) programming scheme to maintain its reliability. However, when SLC programming is performed on an entire memory block, there is a loss of storage space even if data reliability is guaranteed. Summary of the invention

[0006] An exemplary embodiment of the present invention provides a nonvolatile memory device, the device comprising: a memory cell array, the memory cell array comprising a plurality of cell strings, at least one of the cell strings comprising a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, at least one of the memory cells being a multi-level cell storing at least three bits; and a control logic circuit configured to control a page buffer to read a fast read page of the memory cell using one read voltage and at least two normal read pages of the memory cell using the same number of read voltages.

[0007] An exemplary embodiment of the present invention provides an operating method of a memory device including a memory controller and a non-volatile memory device, the method including: receiving a command for reading data from a fast read page of the non-volatile memory device; and providing the data read from the fast read page to the memory controller through a data line, wherein the fast read page is read using a read voltage, wherein the non-volatile memory device includes a plurality of cell strings, at least one of the cell strings includes a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, and at least one of the memory cells is a multi-level cell storing at least three bits.

[0008] An exemplary embodiment of the present invention provides a storage system comprising: a storage device that exchanges signals with an external device, wherein the storage device comprises a memory controller and a plurality of nonvolatile memories, wherein at least one of the memories comprises: a memory cell array comprising a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate; and a control logic circuit configured to control a page buffer to read a fast read page of the memory cell using one read voltage and at least two normal read pages of the memory cell using the same number of read voltages.

[0009] An exemplary embodiment of the present invention provides a memory device, comprising: a memory controller; and a nonvolatile memory device connected to the memory controller, wherein the memory controller is configured to perform a read operation on the nonvolatile memory device so that a fast read page of the nonvolatile memory device is read using one read voltage and at least two normal read pages of the nonvolatile memory device are read using the same number of read voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features of the present inventive concept will become more apparent by describing exemplary embodiments of the present inventive concept in detail with reference to the attached drawings.

[0011] Figure 1 A storage device according to an exemplary embodiment of the inventive concept is illustrated.

[0012] Figure 2 Show Figure 1 The memory controller shown in FIG.

[0013] Figure 3 Show Figure 1 non-volatile memory device.

[0014] Figure 4 It is shown Figure 3 A circuit diagram of a memory block BLK among a plurality of memory blocks included in a memory cell array.

[0015] Figure 5 An operating method of a storage device according to an exemplary embodiment of the inventive concept is illustrated.

[0016] Figure 6 Is used to describe Figure 5 A timing diagram of an operation method of a storage device.

[0017] Figure 7 Bit ordering according to an exemplary embodiment of the inventive concept and threshold voltage distributions of memory cells programmed based on the bit ordering are illustrated.

[0018] Figure 8 is a timing diagram for describing an operating method of a memory device according to an exemplary embodiment of the inventive concept.

[0019] Fig. 9 Shown when based on Figure 8 An exemplary embodiment of the present invention performs a fast read page read and a normal read page read of a memory device when performing a read operation.

[0020] Fig.10 A page read of a memory device is shown when a read operation of the memory device is performed according to normal bit ordering.

[0021] Fig.11 A bit ordering according to an exemplary embodiment of the inventive concept is illustrated.

[0022] Fig.12 A bit ordering according to an exemplary embodiment of the inventive concept is illustrated.

[0023] Fig.13 A bit ordering according to an exemplary embodiment of the inventive concept is illustrated.

[0024] Fig.14 Show Figure 4 Part of the circuit diagram.

[0025] Fig.15 An operating method of a storage device according to an exemplary embodiment of the inventive concept is illustrated.

[0026] Fig.16 Is used to describe Fig.15 A timing diagram of an operation method of a storage device.

[0027] Fig.17 Is used to describe Fig.15 A timing diagram of an operation method of a storage device.

[0028] Fig.18 is a table showing an average number of read voltages required to determine page data depending on page types.

[0029] Fig.19A : is a table showing the read time taken to determine page data depending on the page type.

[0030] Fig.19B It is shown for Fig.19A Graph showing the read time of corresponding page types.

[0031] Fig. 20 is a graph showing the number of error bits associated with the number of bits to be stored per memory cell for each page type.

[0032] Fig.21 A memory system to which a memory controller and a nonvolatile memory device according to an exemplary embodiment of the inventive concept are applied is illustrated.

[0033] Fig. 22 A memory card to which a nonvolatile memory device according to an exemplary embodiment of the inventive concept is applied is illustrated. DETAILED DESCRIPTION

[0034] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the accompanying drawings, like reference numerals may refer to like elements.

[0035] Hereinafter, the components described with reference to the terms "unit", "module", "block", etc. and the functional blocks shown in the drawings may be implemented using software, hardware, or a combination thereof. For example, the software may be a machine code, firmware, embedded code, or application software. For example, the hardware may include an electrical circuit, an electronic circuit, a processor, a computer, an integrated circuit, an integrated circuit core, a pressure sensor, an inertial sensor, a micro-electromechanical system (MEMS), a passive component, or a combination thereof.

[0036] Figure 1 A memory device 100 according to an exemplary embodiment of the inventive concept is illustrated.

[0037] The memory device 100 includes a memory controller 110 and a nonvolatile memory device 120. For example, the nonvolatile memory device 120 may include a plurality of nonvolatile memories. The nonvolatile memories may be connected to the memory controller 110 through a plurality of channels. In this case, at least two or more nonvolatile memories may be connected to each channel.

[0038] The memory controller 110 may control a read operation and a write operation of the nonvolatile memory device 120. For example, the memory controller 110 may transfer a command CMD, an address ADDR, and data “DATA” to the nonvolatile memory device 120 by using a plurality of data signals DQ. Alternatively, by using a plurality of data signals DQ, the memory controller 110 transfers a command CMD and an address ADDR to the nonvolatile memory device 120 and receives data “DATA” from the nonvolatile memory device 120. The memory controller 110 transfers a control signal CTRL and a data strobe signal DQS to the nonvolatile memory device 120.

[0039] In an exemplary embodiment of the inventive concept, the control signal CTRL, the data strobe signal DQS, and the plurality of data signals DQ may be transferred to the nonvolatile memory device 120 independently of each other through different signal lines. The control signal CTRL and the data strobe signal DQS may be used to identify the plurality of data signals DQ transferred from the memory controller 110 to the nonvolatile memory device 120. Alternatively, the control signal CTRL and the data strobe signal DQS may be used to identify the plurality of data signals DQ exchanged between the memory controller 110 and the nonvolatile memory device 120.

[0040] In response to the received signal, the nonvolatile memory device 120 may receive data “DATA” from the memory controller 110 or may transfer data “DATA” to the memory controller 110. For example, the nonvolatile memory device 120 may recognize a command CMD, an address ADDR, or data “DATA” of a plurality of data signals DQ by using the control signal CTRL.

[0041] In an exemplary embodiment of the inventive concept, the nonvolatile memory device 120 may include a NAND flash memory. However, the inventive concept is not limited thereto. For example, the nonvolatile memory device 120 may include at least one of a volatile or nonvolatile memory such as a static random access memory (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc.

[0042] Figure 2 Show Figure 1 The memory controller shown in FIG.

[0043] The memory controller 110 includes at least one processor 111 , an error checking and correction engine 112 , a host interface circuit 113 , a RAM controller 114 , and a non-volatile memory interface circuit 115 .

[0044] The processor 111 may control the overall operation of the memory controller 110. The processor 111 may drive various firmware / software to control the nonvolatile memory device 120. For example, the processor 111 may drive a flash translation layer for managing a mapping table in which a relationship between a logical address of a host device and a physical address of the nonvolatile memory device 120 is defined.

[0045] The ECC engine 112 may generate an error correction code for writing data to be stored in the nonvolatile memory device 120. The ECC engine 112 may detect and correct errors of the read data based on the error correction code read from the nonvolatile memory device 120.

[0046] The host interface circuit 113 can perform communication with the host device by using a bus with various communication protocols. For example, the format of the bus may include one or more of various interface protocols, such as Universal Serial Bus (USB), Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCIe), Mobile PCIe (M-PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Serial Attached Small Computer System Interface (SCSI) (SAS), Integrated Drive Electronics (IDE), Enhanced IDE (EIDE), High-speed Non-Volatile Memory (NVMe) and Universal Flash Storage (UFS).

[0047] The RAM controller 114 may provide an interfacing between the memory controller 110 and the RAM. The RAM controller 114 may access the RAM in response to a request from the processor 111 or any other intellectual property (IP). For example, the RAM controller 114 may record data in the RAM depending on a write request from the processor 111. Alternatively, the RAM controller 114 may read data from the RAM depending on a read request from the processor 111.

[0048] The nonvolatile memory interface circuit 115 may perform communication with the nonvolatile memory device 120 .

[0049] Figure 3 Show Figure 1 The nonvolatile memory device 120 may include a memory cell array 121 , an address decoder 122 , a page buffer 123 , an input / output circuit 124 , and a control logic circuit 125 .

[0050] The memory cell array 121 may include a plurality of memory blocks BLK1 to BLKm. Each of the memory blocks BLK1 to BLKm may include a plurality of cell strings. Each of the cell strings includes a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines WL. Each of the memory cells may include a single-level cell (SLC) storing one bit or a multi-level cell (MLC) storing at least two bits.

[0051] The address decoder 122 is connected to the memory cell array 121 through a plurality of word lines WL, a string selection line SSL, and a ground selection line GSL. The address decoder 122 may receive a logical address and may decode the received logical address to drive the plurality of word lines WL. For example, the address ADDR may indicate a physical address obtained by translating the logical address. The physical address may be obtained by, for example, the memory controller 110 (refer to Figure 1 ) driven flash translation layer (FTL) to perform the conversion operation.

[0052] The page buffer 123 is connected to the memory cell array 121 through a plurality of bit lines BL. Under the control of the control logic circuit 125, the page buffer 123 may control the bit lines BL so that the data "DATA" received from the input / output circuit 124 is stored in the memory cell array 121. Under the control of the control logic circuit 125, the page buffer 123 may read the data stored in the memory cell array 121 and may transfer the read data to the input / output circuit 124. The page buffer 123 may receive data from the input / output circuit 124 in units of pages, or may read data from the memory cell array 121 in units of pages.

[0053] The input / output circuit 124 may receive data “DATA” from the outside and may provide the received data “DATA” to the page buffer 123 .

[0054] The control logic circuit 125 may receive a command CMD and a control signal CTRL from the outside, and may control the address decoder 122, the page buffer 123, and the input / output circuit 124 in response to the received command CMD and the control signal CTRL. For example, the control logic circuit 125 may control other components in response to the command CMD and the control signal CTRL so that the data "DATA" is stored in the memory cell array 121. Alternatively, the control logic circuit 125 may control other components in response to the command CMD and the control signal CTRL so that the data "DATA" stored in the memory cell array 121 is transferred to the outside. The control signal CTRL may include a signal provided by the memory controller 110 for controlling the nonvolatile memory device 120.

[0055] The control logic circuit 125 may generate various voltages used by the nonvolatile memory device 120 for operation. For example, the control logic circuit 125 may generate a plurality of program voltages, a plurality of pass voltages, a plurality of selection read voltages, a plurality of non-selection read voltages, a plurality of erase voltages, a plurality of verification voltages, etc. The control logic circuit 125 may provide the generated voltages to the address decoder 122 or to the substrate of the memory cell array 121.

[0056] Figure 4 It is shown Figure 3 A circuit diagram of a memory block BLK among a plurality of memory blocks included in a memory cell array.

[0057] The memory block BLK includes a plurality of cell strings CS11, CS12, CS21, and CS22. The plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged in row and column directions to form rows and columns.

[0058] Each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes a plurality of cell transistors. For example, each of the plurality of cell strings CS11, CS12, CS21, and CS22 may include string selection transistors SSTa and SSTb, a plurality of memory cells MC1 to MC128, ground selection transistors GSTa and GSTb, and dummy memory cells DMC1 and DMC2. The cell transistors may be stacked in a height direction that is a direction perpendicular to a plane defined by a row direction and a column direction. Each of the cell transistors may be a charge trap flash (CTF) memory cell.

[0059] In each of the cell strings CS11, CS12, CS21 and CS22, a plurality of memory cells MC1 to MC128 are connected in series. String selection transistors SSTa and SSTb are connected in series. String selection transistors SSTa and SSTb connected in series are provided between the bit line BL1 or BL2 and the memory cells MC1 to MC128 connected in series. Ground selection transistors GSTa and GSTb are connected in series. Ground selection transistors GSTa and GSTb connected in series are provided between the memory cells MC1 to MC128 connected in series and the common source line CSL. A first dummy memory cell DMC1 is provided between the memory cells MC1 to MC128 connected in series and the ground selection transistors GSTa and GSTb connected in series. A second dummy memory cell DMC2 is provided between the string selection transistors SSTa and SSTb connected in series and the memory cells MC1 to MC128 connected in series.

[0060] The ground selection transistors GSTa and GSTb may be connected to the ground selection line GSL in common. Alternatively, the ground selection transistors of the same row may be connected to the same ground selection line. For example, the first ground selection transistors GSTa of the cell strings CS11 and CS12 in the first row may be connected to the first ground selection line, and the first ground selection transistors GSTa of the cell strings CS21 and CS22 in the second row may be connected to the second ground selection line. Alternatively, the ground selection transistors provided at the same height from the substrate may be connected to the same ground selection line. For example, the first ground selection transistors GSTa of the cell strings CS11, CS12, CS21, and CS22 may be connected to the first ground selection line, and the second ground selection transistors GSTb of the cell strings CS11, CS12, CS21, and CS22 may be connected to the second ground selection line.

[0061] Memory cells at the same height from the substrate (or ground selection transistors GSTa and GSTb) are connected to the same word line. In addition, memory cells arranged at different heights from the substrate (or ground selection transistors GSTa and GSTb) can be connected to different word lines. For example, memory cells MC1 to MC128 of cell strings CS11, CS12, CS21, and CS22 are connected to word lines WL1 to WL128.

[0062] The string selection transistors belonging to the same row among the first string selection transistors SSTa of the same height are connected to the same string selection line. For example, the first string selection transistors SSTa of the cell strings CS11 and CS12 in the first row are commonly connected to the string selection line SSL1a, and the first string selection transistors SSTa of the cell strings CS21 and CS22 in the second row are commonly connected to the string selection line SSL2a.

[0063] Likewise, string selection transistors belonging to the same row among second string selection transistors SSTb of the same height are connected to the same string selection line. For example, second string selection transistors SSTb of cell strings CS11 and CS12 in the first row are commonly connected to string selection line SSL1b, and second string selection transistors SSTb of cell strings CS21 and CS22 in the second row are commonly connected to string selection line SSL2b.

[0064] The dummy memory cells of the same height are connected to the same dummy word line. For example, the first dummy memory cell DMC1 is connected to the first dummy word line DWL1, and the second dummy memory cell DMC2 is connected to the second dummy word line DWL2.

[0065] In the memory block BLK, read and write operations may be performed in row units. For example, a row of the memory block BLK may be selected by string selection lines SSL1a, SSL1b, SSL2a, and SSL2b.

[0066] When a turn-on voltage is supplied to string selection lines SSL1a and SSL1b and a turn-off voltage is supplied to string selection lines SSL2a and SSL2b, cell strings CS11 and CS12 in the first row are connected to bit lines BL1 and BL2, respectively. When a turn-on voltage is supplied to string selection lines SSL2a and SSL2b and a turn-off voltage is supplied to string selection lines SSL1a and SSL1b, cell strings CS21 and CS22 in the second row are connected to bit lines BL1 and BL2, respectively. When a word line is driven, a memory cell (having the same height) connected to the driven word line is selected among memory cells MC1 to MC128 of cell strings CS11 to CS22. A read / write operation may be performed on the selected memory cell. The selected memory cell may constitute a page unit.

[0067] For example, in the case where each of the memory cells MC1 to MC128 is a three-level cell (TLC) storing 3-bit data, the memory cell connected to a word line can store three pages. The three pages stored in the memory cell connected to a word line may include a least significant bit (LSB) page, a center significant bit (CSB) page, and a most significant bit (MSB) page. However, the inventive concept is not limited thereto. For example, each memory cell may be implemented using a four-level cell (QLC) storing 4-bit data or any other type of memory cell storing five or more data bits. For example, each memory cell may be implemented using a five-level cell (PLC) storing 5-bit data or a six-level cell (HLC) storing 6-bit data.

[0068] In addition, according to an exemplary embodiment of the present invention, the page of memory cells connected to the selected word line includes a fast read page and a normal read page. The fast read page refers to a page in which data is determined by one read voltage. In other words, only one read voltage can be used to determine the data of the fast read page. The normal read page refers to a page in which data is determined by multiple read voltages. In other words, more than one read voltage is used to determine the data of the normal read page. In the case where one of the pages of memory cells connected to the selected word line is programmed as a fast read page, both SLC programming and MLC programming (or QLC programming) can be performed on the page of memory cells connected to the selected word line. This will be described later.

[0069] In the memory block BLK, an erase operation may be performed for each memory block or for each sub-block. When an erase operation is performed for each memory block, all memory cells MC1 to MC128 of the memory block BLK may be erased simultaneously according to one erase request. When an erase operation is performed for each sub-block, some of the memory cells MC1 to MC128 of the memory block BLK may be erased simultaneously according to one erase request, and erasing of the remaining memory cells of the memory block BLK may be prohibited. A low voltage (e.g., a ground voltage) may be supplied to a word line connected to a memory cell to be erased, and a word line connected to a memory cell for which erasure is prohibited may be floating.

[0070] will understand that in Figure 4 The memory block BLK shown in is only exemplary. The number of cell strings, the number of rows of cell strings, and the number of columns of cell strings may be variable. In addition, in the memory block BLK, the number of string selection transistors, the number of pseudo memory cells, the number of memory cells, and / or the number of ground selection transistors may be increased or decreased, and the height of the memory block BLK may be increased or decreased depending on the number of cell transistors. In addition, the number of string selection lines, the number of pseudo word lines, the number of word lines, and / or the number of ground selection lines may be changed depending on the number of string selection transistors, the number of pseudo memory cells, the number of memory cells, and / or the number of ground selection transistors.

[0071] Figure 5 An operating method of a storage device according to an exemplary embodiment of the inventive concept is shown. Figure 1 , Figure 3 and Figure 5 A method in which an SLC program operation and a TLC program operation are performed together on memory cells connected to a selected word line will be described.

[0072] In operation S110, the nonvolatile memory device 120 receives a program command, an address, and page data associated with each page of the selected word line from the memory controller 110. For example, in the case of performing a TLC program operation on the nonvolatile memory device 120, the program command, the address, and the page data may be repeatedly received three times. In the case of performing a QLC program operation on the nonvolatile memory device 120, the program command, the address, and the page data may be repeatedly received four times.

[0073] In operation S120, based on the program command, address and page data received from the memory controller 110, the memory cell connected to the selected word line is programmed to have a fast read page. The fast read page can be a page in which data is determined by a read voltage. To achieve this, a special bit ordering can be used. For example, data including consecutive bits of "1" and consecutive bits of "0" can be stored in a fast read page. In other words, the data can have a transition from bit "1" to bit "0" (or from bit "0" to bit "1"). More specifically, the data of the fast read page can have only one bit transition.

[0074] The data of each normal read page may consist of a combination of bit "1" and bit "0". However, as the number of data bits to be stored in each memory cell increases, the number of transitions from bit "1" to bit "0" (or from bit "0" to bit "1") may increase. Hereinafter, the transition from bit "1" to bit "0" or from bit "0" to bit "1" may be referred to as a "bit transition". In an exemplary embodiment of the present invention, the number of bit transitions of the data of each normal read page (or the number of time periods in which the bit "1" and the bit "0" of the data of each normal read page are switched in each of them) may be almost the same. Specifically, the data of at least two of the normal read pages other than the fast read page may include the same number of bit transitions. For example, the first normal read page and the second normal read page may each have four bit transitions.

[0075] Figure 6 It is used to describe reference Figure 5 A timing diagram illustrating the method of operation of the described memory device.

[0076] refer to Figure 1 , Figure 5 and Figure 6 , the nonvolatile memory device 120 may receive first page data PD1 , second page data PD2 , and third page data PD3 from the memory controller 110 .

[0077] During the first page setting portion, the nonvolatile memory device 120 may receive a command CM1, a first address ADD1, a first page data PD1, and a command CM11 through a data line. The data line may be connected between the nonvolatile memory device 120 and the memory controller 110. The commands CM1 and CM11 may be a command set for setting the first page data PD1. The first address ADD1 may correspond to an area of ​​memory cells among the memory cells connected to the selected word line in which the first page data PD1 is to be programmed. The nonvolatile memory device 120 may dump the first page data PD1 received through the data line in response to the command CM11. While the first page data PD1 is being dumped, the busy signal R / B may be in a busy state. Figure 6 , tR may correspond to the read access cycle time.

[0078] During the second page setting portion, the nonvolatile memory device 120 may receive a command CM1, a second address ADD2, a second page data PD2, and a command CM12. The commands CM1 and CM12 may be a command set for setting the second page data PD2. The second address ADD2 may correspond to an area of ​​memory cells in which the second page data PD2 is to be programmed among the memory cells connected to the selected word line. The nonvolatile memory device 120 may dump the second page data PD2 received through the data line in response to the command CM12. When the second page data PD2 is dumped, the busy signal R / B may be in a busy state.

[0079] During the third page setting section, the nonvolatile memory device 120 may receive a command CM1, a third address ADD3, a third page data PD3, and a command CM13. The commands CM1 and CM13 may be a command set for setting the third page data PD3. The third address ADD3 may correspond to an area of ​​memory cells in which the third page data PD3 is to be programmed among the memory cells connected to the selected word line. The nonvolatile memory device 120 may dump the third page data PD3 received through the data line in response to the command CM13. When the third page data PD3 is dumped, the busy signal R / B may be in a busy state.

[0080] Afterwards, in the program confirmation section, the nonvolatile memory device 120 may receive command CM21, fourth address ADD4, and command CM22. Commands CM21 and CM22 may be a program confirmation command set for initiating a program operation. In an exemplary embodiment of the inventive concept, the fourth address ADD4 may include information about a programming order.

[0081] The nonvolatile memory device 120 may perform a program operation on the received page data PD1, PD2, and PD3 during the program time tPROG in response to the command CM22. During the program time tPROG, the busy signal R / B may be in a busy state (eg, a low state).

[0082] As described above, the nonvolatile memory device 120 may continuously or sequentially receive a plurality of page data corresponding to a selected word line and may perform a programming operation after the plurality of page data are completely received. However, the inventive concept is not limited thereto. In the case where the number of data bits to be stored in each memory cell exceeds "3", the number of page setting parts in which commands, addresses, and page data are received may be increased as much as the number of increased data bits.

[0083] In an exemplary embodiment of the inventive concept, one of the first to third page setting parts may correspond to a fast read page. For example, in the case where the second page setting part corresponds to the fast read page, the second address ADD2 may indicate the address of the SLC page in which the second page data PD2 is programmed. However, the page setting part corresponding to the fast read page is not limited to the second page setting part. For example, depending on the bit order used to distinguish between the corresponding programming states, the fast read page may correspond to different page setting parts.

[0084] Figure 7 Bit ordering according to an exemplary embodiment of the inventive concept and threshold voltage distributions of memory cells programmed based on the bit ordering are illustrated.

[0085] Below, we will refer to Figure 1 , Figure 3 and Figure 7 A description is given. The memory controller 110 may perform TLC programming in which page data is represented by eight programming states with respect to the memory cells connected to the selected word line. For example, the memory controller 110 may program the memory cells connected to the selected word line in an incremental step pulse programming (ISPP) scheme, and may verify program pass / fail by using the first to seventh verification voltages Vvfy1 to Vvfy7.

[0086] In an exemplary embodiment of the inventive concept, the memory controller 110 programs the memory cells connected to the selected word line so that the data of one page of the three pages is determined by one read voltage. For example, the memory controller 110 programs the memory cells connected to the selected word line so that the erased state "E", the first programming state P1, the second programming state P2, and the third programming state P3 of the center valid bit (CSB) page correspond to bit "1". The memory controller 110 programs the memory cells connected to the selected word line so that the fourth programming state P4, the fifth programming state P5, the sixth programming state P6, and the seventh programming state P7 of the center valid bit (CSB) page correspond to bit "0". According to this scheme, the CSB page includes one bit transition (e.g., P3 to P4 bit transition) in which the bit value changes. In other words, in the case where the memory controller 110 performs a read operation on the CSB page, the data of the CSB page can be determined by one read voltage. In other words, the CSB page can have eight states including the erased state "E", but the data value of the CSB page can be determined by only one read voltage, thereby obtaining an effect similar to SLC programming.

[0087] In an exemplary embodiment of the present invention, the bit ordering may be based on a gray code. In other words, a bit value changes between two adjacent programming states. However, the bit ordering of the present invention is not limited thereto. For example, two or more bit values ​​may change between two adjacent programming states. However, in this case, the number of read voltages required to determine the MSB page data and the LSB page data may be greater than "3".

[0088] In an exemplary embodiment of the inventive concept, the data stored in the fast read page may be hot data that is a frequently read target (or frequently accessed by the memory controller). Alternatively, the data stored in the fast read page may be data that requires high reliability. Alternatively, the data stored in the fast read page may be data associated with the maintenance of the storage device, or metadata. Alternatively, the data stored in the fast read page may be data associated with an application that will be quickly executed or started according to a user's request.

[0089] In contrast, the data stored in the normal read page may be cold data that is not a target for frequent reading. Alternatively, the data stored in the normal read page may be data that requires relatively low reliability. Alternatively, the data stored in the normal read page may be data that is not associated with the maintenance of the storage device, or user data.

[0090] In addition, the memory controller 110 programs the remaining read pages of the three pages other than the fast read page based on the normal TLC programming scheme. Figure 7 As shown, in order to determine the data of the MSB page, the MSB page may include three bit transitions (e.g., between P1 and P2, between P4 and P5, and between P6 and P7), and the LSB page may include three bit transitions (e.g., between "E" and P1, between P2 and P3, and between P5 and P6). According to the above description, with respect to the page corresponding to the selected word line, the same number of read voltages for determining the data of the remaining pages (e.g., normal read pages) other than the fast read page may be the same.

[0091] Figure 8 is a timing diagram for describing an operating method of a memory device according to an exemplary embodiment of the inventive concept.

[0092] refer to Figure 1 , Figure 3 and Figure 8 , the nonvolatile memory device 120 may receive a command CM3, an address ADD2, and a command CM31 from the memory controller 110 through a data line. The commands CM3 and CM31 may be a command set for reading data of a fast read page from the nonvolatile memory device 120. The address ADD2 may indicate an address corresponding to a fast read page.

[0093] In an exemplary embodiment of the inventive concept, commands CM3 and CM31 may be normal read commands. Alternatively, commands CM3 and CM31 may be vendor-specific commands for reading data from a fast read page. In response to command CM31, the nonvolatile memory device 120 may transmit SLC page data R-DATA read from a fast read page to the memory controller 110 through a data line.

[0094] Fig. 9 Shown when based on Figure 8 The exemplary embodiment of the present invention performs a fast read page read and a normal read page read of a memory device when performing a read operation. For better understanding, the bit ordering of the present invention, the threshold voltage distribution according to the bit ordering, and the read voltage for the read operation of each page are described together.

[0095] refer to Figure 1 and Fig. 9, the MSB page has the following bit ordering: the bit value of each of the erased state "E" and the first programming state P1 is "1", the bit value of each of the second to fourth programming states P2, P3 and P4 is "0", the bit value of each of the fifth programming state P5 and the sixth programming state P6 is "1", and the bit value of the seventh programming state P7 is "0". The MSB page has three bit transitions. The CSB page has the following bit ordering: the bit value of each of the erased state "E" and the first to third programming states P1, P2 and P3 is "1", and the bit value of each of the fourth to seventh programming states P4, P5, P6 and P7 is "0". The CSB page has one bit transition. The LSB page has the following bit ordering: the bit value of the erase state "E" is "1", the bit value of each of the first program state P1 and the second program state P2 is "0", the bit value of each of the third to fifth program states P3, P4 and P5 is "1", and the bit value of each of the sixth program state P6 and the seventh program state P7 is "0". The LSB page has three bit transitions.

[0096] In an exemplary embodiment of the inventive concept, up to three read voltages VRD2, VRD5, and VRD7 may be required to read the data of the MSB page. For example, the fifth read voltage VRD5, the second read voltage VRD2, and the seventh read voltage VRD7 may be sequentially applied to the memory cell as read voltages, but the inventive concept is not limited thereto. For example, first, for the purpose of determining the MSB page data of the memory cell, the fifth read voltage VRD5 may be applied to the memory cell having the first programming state P1. In this case, it may be determined that the memory cell is an on-cell, but it may be additionally determined whether it has a value of "1" or a value of "0". Thereafter, the second read voltage VRD2 may be applied to the memory cell. In this case, it may be determined that the memory cell is an on-cell, and thus it may be finally determined that the memory cell has a value of "1".

[0097] In an exemplary embodiment of the inventive concept, only one read voltage VRD4 may be required to read data of a CSB page. For example, in the case where a memory cell has one of an erase state "E" to a third program state P3, the memory controller 110 may apply a fourth read voltage VRD4 to the memory cell to read data stored in the memory cell, and the memory cell may be determined as an on-cell. In the CSB page, since a memory cell having a threshold voltage less than the fourth read voltage VRD4 stores a bit value "1", an additional read voltage for determination is not required.

[0098] In the case where the memory cell has one of the fourth to seventh programming states P4 to P7, the memory controller 110 may apply a fourth read voltage VRD4 to the memory cell to read data stored in the memory cell, and the memory cell may be determined as a OFF cell. In the CSB page, since a memory cell having a threshold voltage greater than the fourth read voltage VRD4 stores a bit value of "0", an additional read voltage for determination is not required.

[0099] In an exemplary embodiment of the inventive concept, up to three read voltages VRD1, VRD3, and VRD6 may be required to read the data of the LSB page. For example, the third read voltage VRD3, the first read voltage VRD1, and the sixth read voltage VRD6 may be sequentially applied to the memory cell as read voltages, but the inventive concept is not limited thereto. For example, first, the third read voltage VRD3 may be applied to the memory cell having the fourth programming state P4 to determine the LSB page data of the memory cell. In this case, it may be determined that the memory cell is a closed cell, but it may be additionally determined whether it has a value of "1" or a value of "0". Thereafter, the sixth read voltage VRD6 may be applied to the memory cell. In this case, it may be determined that the memory cell is an open cell, and thus it may be finally determined that the memory cell has a value of "1".

[0100] According to the above description, since only one read voltage (e.g., VRD4) is required to determine the data of the fast read page, the read speed of a specific page is increased. Since the data of the normal read page is determined by using the same number of read voltages, a uniform read speed can be guaranteed for the normal read page.

[0101] although Fig. 9 The CSB page is shown as a fast read page, but the inventive concept is not limited thereto. Fig. 9 In this case, the fast read page can be the MSB page or the LSB page.

[0102] Fig.10 A page read of a memory device is shown when a read operation of the memory device is performed according to normal bit ordering.

[0103] First, as described above, the bit ordering of the present invention is conceived. Fig.10 The bit ordering shown in is based on Gray code. However, according to Fig.10Due to the bit ordering, the number of read voltages used to perform a read operation on each page is almost the same, and thus the read speed of the page is uniform. For example, two read voltages VRD1 and VRD5 are required to determine the data of the MSB page, three read voltages VRD2, VRD4 and VRD6 are required to determine the data of the CSB page, and two read voltages VRD3 and VRD7 are required to determine the data of the LSB page.

[0104] according to Fig.10 , because the number of read voltages required to determine the data of the CSB page is almost the same as the number of read voltages required to determine the data of each of the MSB page and the LSB page, the read speed of the corresponding pages can be relatively uniform. Fig. 9 The bit ordering of the inventive concept shown in FIG. 1 can ensure a reading speed substantially the same as that of an SLC page by using a fast read page.

[0105] Fig.11 A bit ordering according to an exemplary embodiment of the inventive concept is illustrated.

[0106] Fig.11 The embodiment of FIG. 1 shows the bit ordering associated with a QLC storing 4 bits of data. For example, Fig.11 The bit ordering of is based on Gray code. The memory controller 110 (reference Figure 1 ) QLC programming in which page data is represented by 15 program states can be performed on memory cells connected to the selected word line. The programming process is similar to that of reference Figure 5 and Figure 6 The programming process is described, and thus additional description may be omitted to avoid redundancy.

[0107] according to Fig.11, the MSB page may include four bit transitions (e.g., between P2 and P3, between P6 and P7, between P8 and P9, and between P12 and P13). In other words, the number of read voltages required to determine the data of the MSB page is 4 (VRD3, VRD7, VRD9, and VRD13). The number of read voltages required to determine the data of the 3rd significant bit (3SB) page is 5 (VRD2, VRD4, VRD6, VRD11, and VRD15) because the number of bit transitions is 5, and the number of read voltages required to determine the data of the 2nd significant bit (2SB) page is 5 (VRD1, VRD5, VRD10, VRD12, and VRD14) because the number of bit transitions is 5. The three pages described above (in other words, the MSB page, the 3SB page, and the 2SB page) may be referred to as “normal read pages”. In an exemplary embodiment of the inventive concept, the normal page may not include at least two pages in which the number of read voltages required to determine the data increases by a power of 2.

[0108] In the LSB page, the bit value of each of the erase state "E" to the seventh programming state P7 is "1", and the bit value of each of the eighth programming state P8 to the fifteenth programming state P15 is "0". According to this bit ordering, the number of read voltages required to determine the data of the LSB page is 1 (VRD8). This is so because there is only one bit transition. For example, in the case where the memory cell has one of the eighth programming state P8 to the fifteenth programming state P15, the memory controller 110 can apply only the eighth read voltage VRD8 to the memory cell to read the data stored in the memory cell. As a result, the memory cell can be determined as a closed cell. In the LSB page, because the memory cell having a threshold voltage greater than the eighth read voltage VRD8 stores the bit value "0", no additional read voltage is required for determination.

[0109] According to the above description, since only one read voltage (e.g., VRD8) is required to determine the data of the fast read page, the read speed of the fast read page (e.g., LSB page) is increased. Through this bit sorting, the same effect as that obtained in the case of reading data from the memory cell programmed by SLC can be basically obtained. In addition, the number of read voltages required to determine the data of each of the normal read pages (e.g., MSB page, 3SB page, and 2SB page) other than the fast read page is almost the same. For example, with respect to at least two pages of the normal read page, the number of read voltages required to determine the data is the same. Fig.11 , the 3SB page and the 2SB page use the same number of read voltages.

[0110] Fig.12A bit ordering according to an exemplary embodiment of the inventive concept is illustrated.

[0111] Fig.11 The embodiment of FIG. 1 shows the bit ordering associated with a five-level cell (PLC) storing 5 bits of data. For example, Fig.12 The bit ordering of is based on Gray code. The memory controller 110 (reference Figure 1 ) can perform PLC programming in which page data is represented by 31 programming states on the memory cells connected to the selected word line. The programming process is similar to that of reference Figure 5 and Figure 6 The programming process is described, and thus additional description may be omitted to avoid redundancy.

[0112] according to Fig.12 , the LSB page may include eight bit transitions (e.g., between "E" and P1, between P4 and P5, between P9 and P10, between P11 and P12, between P13 and P14, between P16 and P17, between P22 and P23, and between P29 and P30). In other words, the number of read voltages required to determine the data of the LSB page is 8 (VRD1, VRD5, VRD10, VRD12, VRD14, VRD17, VRD23, and VRD30).

[0113] The number of read voltages required to determine the data of the 2SB page is 8 (VRD2, VRD9, VRD15, VRD18, VRD20, VRD24, VRD27, and VRD29), the number of read voltages required to determine the data of the 3SB page is 7 (VRD3, VRD6, VRD8, VRD13, VRD21, VRD25, and VRD28), and the number of read voltages required to determine the data of the 4th significant bit (4SB) page is 7 (VRD4, VRD7, VRD11, VRD19, VRD22, VRD26, and VRD31). The four pages described above (in other words, the LSB page, the 2SB page, the 3SB page, and the 4SB page) may be referred to as “normal read pages”.

[0114] In the MSB page, the bit value of each of the erase state "E" to the fifteenth programming state P15 is "1", and the bit value of each of the sixteenth programming state P16 to the 31st programming state P31 is "0". According to this bit ordering, the number of read voltages required to determine the data of the MSB page is 1 (VRD16). For example, in the case where a memory cell has one of the sixteenth programming state P16 to the 31st programming state P31, the memory controller 110 may apply only the sixteenth read voltage VRD16 to the memory cell to read the data stored in the memory cell. As a result, the memory cell may be determined as a closed cell. In the MSB page, since a memory cell having a threshold voltage greater than the sixteenth read voltage VRD16 stores a bit value "0", no additional read voltage is required for determination.

[0115] As a result, by using Fig.12 The bit ordering shown in FIG. 1 increases the read speed of a fast read page (eg, an MSB page). By this bit ordering, substantially the same effect as that obtained in the case of reading data from a memory cell programmed with an SLC can be obtained. For example, according to Fig.12 , with respect to at least two normal read pages, the number of read voltages required to determine data is the same. For example, in the case of an LSB page and a 2SB page, the number of read voltages required to determine data is 8; and in the case of a 3SB page and a 4SB page, the number of read voltages required to determine data is 7.

[0116] Fig.13 A bit ordering according to an exemplary embodiment of the inventive concept is illustrated.

[0117] as Fig.12 An embodiment of Fig.13 The embodiment of FIG. 1 shows the bit ordering of a PLC storing 5 bits of data. For example, Fig.13 The bit ordering is based on Gray code.

[0118] according to Fig.13, the LSB page may include 15 bit transitions (e.g., between “E” and P1, between P2 and P3, between P3 and P4, between P6 and P7, between P8 and P9, between P10 and P11, between P12 and P13, between P14 and P15, between P16 and P17, between P18 and P19, between P20 and P21, between P22 and P23, between P25 and P26, between P28 and P29, between P30 and P31). In other words, the number of read voltages required to determine the data of the LSB page is 15 (VRD1, VRD3, VRD5, VRD7, VRD9, VRD11, VRD13, VRD15, VRD17, VRD19, VRD21, VRD23, VRD26, VRD29 and VRD31).

[0119] The number of read voltages required to determine the data of the 2SB page is 9 (VRD2, VRD6, VRD10, VRD14, VRD18, VRD22, VRD25, VRD27, and VRD30), the number of read voltages required to determine the data of the 3SB page is 4 (VRD4, VRD12, VRD20, and VRD28), and the number of read voltages required to determine the data of the 4SB page is 2 (VRD8 and VRD24). The four pages described above (in other words, the LSB page, the 2SB page, the 3SB page, and the 4SB page) may be referred to as “normal read pages”.

[0120] In the MSB page, the bit value of each of the erase state "E" to the fifteenth program state P15 is "1", and the bit value of each of the sixteenth program state P16 to the thirty-first program state P31 is "0". According to this bit ordering, the number of read voltages required to determine the data of the MSB page is 1 (VRD16). Regardless of whether the memory cell has any program state, only the sixteenth read voltage VRD16 is required to determine the data stored in the memory cell, and no additional read voltage for determination is required.

[0121] According to the bit ordering, a hierarchical memory can be implemented by allowing pages of memory cells connected to a selected word line to have different read speeds. For example, data requiring the highest reliability or requiring the fastest read speed can be stored in the MSB page. In contrast, data that does not require the highest reliability or does not require the fastest read speed can be stored in the LSB page. Depending on the required reliability and / or the required read speed, data can be stored in appropriate pages among the 2SB page, the 3SB page, and the 4SB page.

[0122] According to the exemplary embodiments of the inventive concept described above, it is possible to prevent the waste of memory area by performing only SLC programming on the memory cells connected to the selected word line. For example, assume that the entire memory block is SLC programmed and provides a capacity of 1MB. In this case, when the entire memory block is TLC programmed, the memory block provides a capacity of 3MB. In addition, when the entire memory block is QLC programmed, the memory block provides a capacity of 4MB. In other words, when the entire memory block is SLC programmed, the loss of memory space is considerable.

[0123] However, according to an exemplary embodiment of the present invention, the memory cell connected to the selected word line includes a fast read page in which data is determined by using one read voltage, and a normal read page in which data is determined by using multiple read voltages. Because the data of the fast read page is determined by using only one read voltage, the same effect as that obtained by SLC programming can be substantially obtained. In other words, the read speed of the fast read page is the same as the read speed of the SLC page in which each memory cell stores one bit. In addition, storage area waste can be prevented by using SLC programming.

[0124] Fig.14 Show Figure 4 part of the circuit diagram. Figure 12 to Figure 14 The physical locations of memory blocks where fast read pages are stored according to exemplary embodiments of the inventive concept are described.

[0125] Compared with SLC storing one bit, MLC, TLC, QLC and PLC, each storing multiple bits, are prone to degradation. For example, as the number of bits to be stored per cell increases, degradation may be more serious. Therefore, SLC programming can be performed on memory cells connected to word lines (e.g., WL1, or WL1 and WL2) adjacent to ground selection transistors GSTa and GSTb. As the distance from ground selection transistors GSTa and GSTb increases, the number of data bits to be stored in the memory cell can increase.

[0126] In an exemplary embodiment of the inventive concept, SLC programming may be performed on the memory cells MC1 and MC2 connected to the first word line WL1 and the second word line WL2. PLC programming may be performed on the memory cell MC3 connected to the third word line WL3. In this case, according to Fig.12 In the bit ordering shown in FIG. 1 , the MSB page may be a fast read page that requires a read voltage to determine data, and the remaining pages may be normal read pages.

[0127] SLC programming may be performed on memory cells connected to word lines (e.g., WL127, or WL127 and WL128) adjacent to string selection transistors SSTa and SSTb. As the distance from string selection transistors SSTa and SSTb increases, the number of data bits to be stored in the memory cells may increase. PLC programming may be performed on memory cells connected to the 126th word line WL126. The MSB page in the page of the memory cells connected to the 126th word line WL126 may be a fast read page that requires a read voltage to determine data, and the remaining pages of the memory cells connected to the 126th word line may be normal read pages.

[0128] In another exemplary embodiment of the present inventive concept, SLC programming may be performed on the memory cell MC1 connected to the first word line WL1. TLC programming may be performed on the memory cell MC2 connected to the second word line WL2. In this case, the CSB page in the page of the memory cell MC2 connected to the second word line WL2 may be as shown in reference Fig. 9 The described fast read page, and the LSB page and the MSB page can be normal read pages. QLC programming can be performed on the memory cell MC3 connected to the third word line WL3. In this case, the LSB page in the page of the memory cell MC3 connected to the third word line WL3 can be a fast read page that requires a read voltage to determine the data, and the remaining pages of the memory cells connected to the third word line WL3 can be normal read pages.

[0129] In addition, the scheme of programming the fast read page depending on the position of the word line is not limited to the above-described embodiment. In other words, a similar programming method can be implemented so that the number of bits to be stored per memory cell increases as the distance from the ground selection transistor or the string selection transistor increases.

[0130] Fig.15 An operating method of a storage device according to an exemplary embodiment of the inventive concept is shown. Figure 1 , Figure 3 and Fig.15 A method in which a fast page read is performed on memory cells connected to a selected word line is described.

[0131] In operation S210, the nonvolatile memory device 120 receives a first program command, a first address, and first data from the memory controller 110. The first program command may be associated with SLC programming, and the first address may be associated with an address of a page in which the SLC programming is performed.

[0132] In an exemplary embodiment of the present invention, the first data may be hot data that is a frequently read target. Alternatively, the first data may be data that requires high reliability. Alternatively, the first data may be data associated with maintenance of a system device, or metadata. Alternatively, the first data may be data associated with an application that will be executed quickly depending on a user's request.

[0133] In operation S220 , first data may be programmed in memory cells connected to a first selected word line through SLC programming.

[0134] In operation S230, the nonvolatile memory device 120 receives a second program command, a second address, and second data from the memory controller 110. The second program command may be associated with TLC programming, QLC programming, or PLC programming, and the second address may be associated with an address of a page in which TLC / QLC / PLC programming is performed.

[0135] In an exemplary embodiment of the inventive concept, unlike the first data, the second data may be data that does not require high reliability. Alternatively, the second data may be data that is not associated with maintenance of the system device, or is not metadata.

[0136] In operation S240 , memory cells connected to the second selected word line are programmed based on the first data previously stored in the nonvolatile memory device 120 , and the second command, the second address, and the second data received from the memory controller 110 .

[0137] For example, first data previously stored in the nonvolatile memory device 120 may be stored at a fast read page of memory cells connected to the second selected word line. Second data received from the memory controller 110 may be stored at a normal read page of memory cells connected to the second selected word line. For example, the bit ordering forming the fast read page and the normal read page may be based on the reference Fig. 9 , Fig.11 , Fig.12 or Fig.13 The bit ordering described above. Therefore, the data of the fast read page can be composed of consecutive bits of "1" and consecutive bits of "0", so that the data value of the fast read page can be determined by one read voltage. However, the bit ordering is not limited to Fig. 9 , Fig.11 , Fig.12 and Fig.13 For example, the inventive concept may be applied to various bit orderings that enable fast page reading.

[0138] Fig.16 It is used to describe reference Fig.15The timing diagram of the method of operation of the described storage device will be referred to together with Figure 1 , Fig.15 and Fig.16 1 to describe a programming method for a nonvolatile memory device 120 using copy-back programming with random data commands. For example, Fig.16 Associated with programming of TLCs storing 3 bits of data.

[0139] During the write-back read, the nonvolatile memory device 120 may receive a command CM4, an address ADD0, and a command CM41 from the memory controller 110. The commands CM4 and CM41 may be a command set for performing a write-back read on the SLC page data stored at the address ADD0 of the nonvolatile memory device 120. The address ADD0 may be a source address where the SLC page data as the write-back target is stored. In other words, the address ADD0 may be an SLC page address.

[0140] In response to the command CM41, the nonvolatile memory device 120 may transfer the SLC page data R-DATA stored in the area corresponding to the address ADD0 to the memory controller 110. For example, the SLC page data R-DATA may be hot data that is a target of frequent reading, data requiring high reliability, data associated with maintenance of the system, metadata, etc.

[0141] During the first page setup portion, the nonvolatile memory device 120 may receive a command CM5, a first address ADD1, and a first page data PD1 from the memory controller 110. The command CM5 may be a command for programming the SLC page data R-DATA read from the nonvolatile memory device 120 in the nonvolatile memory device 120 again. In other words, the first page data PD1 may be the same as the SLC page data R-DATA. The first address ADD1, which is part of the destination address, may correspond to a fast read page in a page of memory cells connected to the selected word line. The first address ADD1 may be different from the address ADD0 and may belong to the same or different block as the storage block to which the address ADD0 belongs. The nonvolatile memory device 120 may dump the first page data PD1 in response to the command CM5.

[0142] During the second page setting portion, the nonvolatile memory device 120 may receive a command CM5, a second address ADD2, a second page data PD2, and a command CM51 from the memory controller 110. The commands CM5 and CM51 may be commands for setting the second page data PD2. The second address ADD2 as part of the destination address may correspond to a normal read page in a page of memory cells connected to the selected word line. The nonvolatile memory device 120 may dump the second page data PD2 in response to the command CM51.

[0143] During the third page setting portion, the nonvolatile memory device 120 may receive a command CM5, a third address ADD3, a third page data PD3, and a command CM52 from the memory controller 110. The commands CM5 and CM52 may be commands for setting the third page data PD3. The third address ADD3 as part of the destination address may correspond to a normal read page in a page of memory cells connected to the selected word line. The nonvolatile memory device 120 may dump the third page data PD3 in response to the command CM52.

[0144] Three page setup sections for TLC programming have been described as examples only, but the number of page setup sections may vary depending on the number of data bits to be stored in memory cells.

[0145] Afterwards, the first page data PD1, the second page data PD2, and the third page data PD3 may be programmed in the memory cells connected to the selected word line. In an exemplary embodiment of the inventive concept, the first page may be a fast read page in which data is determined by one read voltage, and the second and third pages may be normal read pages in which multiple read voltages are required to determine data.

[0146] Fig.17 It is used to describe reference Fig.15 Timing diagram of the method of operation of the described storage device. Except that the vendor-specific commands are used instead of the write-back commands, Fig.17 An embodiment similar to Fig.16 Therefore, reference will be made to Figure 1 , Fig.15 and Fig.17 Mainly describe the differences.

[0147] During SLC data reading, the nonvolatile memory device 120 may receive a command CM6, an address ADD0, and a command CM61 from the memory controller 110. The nonvolatile memory device 120 may read the SLC page data R-DATA in response to the command CM61.

[0148] During the first page setting portion, the nonvolatile memory device 120 may receive a command CM7, a first address ADD1, a first page data PD1, and a command CM71 from the memory controller 110. The nonvolatile memory device 120 may dump the SLC page data R-DATA in response to the command CM71. The operations of the second page setting portion and the third page setting portion are similar to the above operations of the first page setting portion. For example, during the second page setting portion, the nonvolatile memory device 120 may receive a command CM7, a second address ADD2, a second page data PD2, and a command CM72 from the memory controller 110, and during the third page setting portion, the nonvolatile memory device 120 may receive a command CM7, a third address ADD3, a third page data PD3, and a command CM73 from the memory controller 110.

[0149] The above commands CM6 and CM7 may be vendor-specific commands for programming the SLC page data previously stored in the nonvolatile memory device 120 and the newly received first to third page data PD1 to PD3 in memory cells connected to the selected word line.

[0150] Fig.18 is a table showing an average number of read voltages required to determine page data depending on page types.

[0151] As described above, in the fast read page and the normal SLC page according to an exemplary embodiment of the inventive concept, the number of read voltages required to determine page data is also '1'.

[0152] In the case of TLC, the number of read voltages required to normally read data of a page according to the bit ordering of an exemplary embodiment of the inventive concept is determined to be "3". Fig. 9 The number of read voltages required to determine data of each of the MSB page and the LSB page is “3” according to the bit ordering shown in FIG. 1 , and thus the average number of read voltages in each page may be “3”.

[0153] In the case of QLC, the number of read voltages required to normally read data of a page according to the bit ordering of an exemplary embodiment of the inventive concept is determined to be "4.7". Fig.11 , the number of read voltages required to determine data of each of the 2SB page, the 3SB page, and the MSB page are "5," "5," and "4," respectively, and thus the average number of read voltages in each page may be "4.7."

[0154] In the case of PLC, the number of read voltages required to normally read the data of a page according to the bit ordering of an exemplary embodiment of the inventive concept is determined to be "7.5". Fig.12, the number of read voltages required to determine data of each of the 2SB page, the 3SB page, and the MSB page are "8," "8," and "7," respectively, and thus the average number of read voltages in each page may be "7.5."

[0155] and Fig. 9 , Fig.11 and Fig.12 Unlike the bit ordering shown in , in the case of a six-level cell (HLC), the bit ordering according to the inventive concept determines that the average number of read voltages required to normally read data of a page is "12.4".

[0156] exist Fig.18 , pages according to the existing bit ordering are represented as legacy pages, and the average number of read voltages required to determine the data of the TLC page, the average number of read voltages required to determine the data of the QLC page, the average number of read voltages required to determine the data of the PLC page, and the average number of read voltages required to determine the data of the HLC page are "2.3", "3.8", "6.2", and "10.5", respectively.

[0157] Comparing the number of read voltages required to determine the data of each page according to the bit ordering of the exemplary embodiment conceived by the present invention with the number of read voltages required to determine the data of each page according to the existing bit ordering, the number of read voltages for the normal read page according to the exemplary embodiment conceived by the present invention can be slightly more than the number of read voltages for the existing legacy read page. The reason is that the memory cells connected to the selected word line include a fast read page in which data is determined by one read voltage. However, considering the following, the exemplary embodiment conceived by the present invention is advantageous: programming the fast read page and the normal read page at the same time in the memory cells connected to the selected word line, compared with the case where only SLC programming is performed, the reliability of the data through the fast read page is guaranteed, and additional storage space is guaranteed.

[0158] Fig.19A is a table showing a reading time taken to determine page data depending on a page type, and Fig.19B It is shown for Fig.19A Graph showing the read time of corresponding page types.

[0159] refer to Fig.19A and Fig.19B, the read latency of the fast read page according to the bit ordering of the exemplary embodiment of the inventive concept and the read latency of the SLC page according to the existing bit ordering are equally 26 microseconds. As the number of bits to be stored per memory cell increases, the read latency also increases. For example, the normal read latency ranges from 78 to 322 microseconds and the legacy read latency ranges from 61 to 273 microseconds. As analyzed by Fig.18 In the mode obtained by the table of FIG. 1 , because the number of read voltages for the normal read page is slightly greater than the number of read voltages for the legacy page according to the bit sorting of the exemplary embodiment of the inventive concept, the read latency of the normal read page is slightly greater than the read latency of the legacy page. However, the exemplary embodiment of the inventive concept is advantageous in view of the following: compared with the case where only SLC programming is performed, data reliability is guaranteed by quickly reading the page and additional storage space is guaranteed.

[0160] Fig. 20 is a graph showing the number of error bits associated with the number of bits to be stored per memory cell for each page type.

[0161] As understood from the diagram, the number of error bits associated with the fast read page according to the bit ordering of the exemplary embodiment of the inventive concept is substantially the same as the number of error bits associated with the SLC page according to the existing bit ordering.

[0162] However, in the case where the bit ordering according to the exemplary embodiment of the inventive concept is used for the read operation of the normal read page, because the number of read voltages required to determine the page data is more than that of the legacy page, the number of error bits of the normal read page is more than that of the legacy page. However, considering that high reliability of data is ensured by fast read pages, the increase in the number of error bits in the normal read page can be sufficiently offset.

[0163] Fig.21 A memory system 1000 to which a memory controller and a nonvolatile memory device according to an exemplary embodiment of the inventive concept are applied is shown. The memory system 1000 may include a host 1100 and a memory device 1200 .

[0164] The storage device 1200 exchanges a signal SIG with the host 1100 through a signal connector 1201 and is supplied with power PWR through a power connector 1202. The storage device 1200 includes a solid state drive (SSD) controller 1210, a plurality of nonvolatile memories 1221 to 122n, an auxiliary power supply 1230, and a buffer memory 1240. Each of the plurality of nonvolatile memories 1221 to 122n may include a reference Figures 1 to 20In other words, the nonvolatile memories 1221 to 122n may include the nonvolatile memory devices described in the reference Figures 1 to 20 The described bit ordering is for fast read pages.

[0165] The SSD controller 1210 may control the nonvolatile memories 1221 to 122n in response to a signal SIG received from the host 1100. The nonvolatile memories 1221 to 122n may operate under the control of the SSD controller 1210. The auxiliary power supply 1230 is connected to the host 1100 through the power connector 1202. The auxiliary power supply 1230 may be charged by the power PWR supplied from the host 1100. When the power PWR is not smoothly supplied from the host 1100, the auxiliary power supply 1230 may supply power to the storage device 1200. The SSD controller 1210 may be a reference Figures 1 to 20 A memory controller 110 is described.

[0166] Fig. 22 A memory card to which a nonvolatile memory device according to an exemplary embodiment of the inventive concept is applied is shown. Fig. 22 , the memory card 2200 connected to the host 2100 includes a memory controller 2210 and a non-volatile memory device 2220. The memory controller 2210 may include an SRAM 2212, a CPU 2213, a host interface 2215, an ECC engine 2217, and a memory interface 2219. The memory controller 2210 is configured to depend on the reference Figures 1 to 20 The described bit ordering performs a read operation and a write operation on the nonvolatile memory device 2220. The nonvolatile memory device 2220 may be implemented using various nonvolatile memory devices such as a NAND flash memory device or a NOR flash memory device. For example, the memory controller 2210 and the nonvolatile memory device 2220 may be integrated in one semiconductor device to constitute a device such as a universal flash storage (UFS) card.

[0167] According to an exemplary embodiment of the inventive concept, a specific page among pages of memory cells connected to a selected word line is provided as a fast read page in which data is determined by one read voltage.

[0168] According to an exemplary embodiment of the inventive concept, among pages of memory cells connected to a selected word line, remaining pages other than fast read pages are provided as normal read pages.

[0169] As a result, it is possible to ensure fast read speed and data reliability through fast read pages and to ensure large data capacity through normal read pages.

[0170] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A non-volatile memory device, comprising: a memory cell array, the memory cell array comprising a plurality of cell strings, at least one of the cell strings comprising a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, at least one of the memory cells being a multi-level cell storing at least three bits; as well as a control logic circuit configured to control the page buffer to read a fast read page of the memory cell using one read voltage and to read at least two normal read pages of the memory cell using the same number of multiple read voltages, The fast read page refers to a page in which data is determined by a read voltage, and the bit sequence of the fast read page has only one bit transition, and The normal read page refers to a page in which data is determined by a plurality of read voltages, and the bit sequence of each of the at least two normal read pages has more than one bit transition.

2. The nonvolatile memory device according to claim 1, wherein: Only the one read voltage is used to read the data of the fast read page.

3. The nonvolatile memory device according to claim 2, wherein: The data of the fast read page is frequently accessed.

4. The nonvolatile memory device according to claim 3, wherein: When data of the fast read page is accessed, a read or program operation is performed.

5. The nonvolatile memory device according to claim 1, wherein: At least three read voltages are used to read data of each of the at least two normal read pages.

6. The nonvolatile memory device according to claim 1, wherein: The plurality of memory cells of the at least one cell string are disposed between a string selection line and a ground selection line.

7. The nonvolatile memory device according to claim 6, wherein: The at least one cell string includes a dummy memory cell disposed between one of the memory cells and a string selection transistor or between one of the memory cells and a ground selection transistor.

8. The nonvolatile memory device according to claim 1, wherein: Each of the memory cells is a charge trapping flash memory transistor.

9. The nonvolatile memory device according to claim 1, wherein: The multi-level cell is a four-level cell, a five-level cell or a six-level cell.

10. The nonvolatile memory device according to claim 1, wherein: The fast read page is one of a least significant bit page, a center significant bit page, and a most significant bit page.

11. The nonvolatile memory device according to claim 1, wherein: The fast read page is one of a plurality of center valid bit pages.

12. The nonvolatile memory device according to claim 1, wherein: The first memory cell is programmed with single level cell SLC data, and the second memory cell is programmed with triple level cell TLC, quad level cell QLC, or penta level cell PLC data.

13. The non-volatile memory device according to claim 12, wherein: One of the TLC, QLC or PLC includes the fast read page and the normal read page.

14. A storage system comprising: A storage device that exchanges signals with an external device, wherein the storage device includes a memory controller and a plurality of non-volatile memories, wherein at least one of the memories includes: a memory cell array including a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate; and a control logic circuit configured to control the page buffer to read a fast read page of the memory cell using one read voltage and to read at least two normal read pages of the memory cell using the same number of multiple read voltages, The fast read page refers to a page in which data is determined by a read voltage, and the bit sequence of the fast read page has only one bit transition, and The normal read page refers to a page in which data is determined by a plurality of read voltages, and the bit sequence of each of the at least two normal read pages has more than one bit transition.

15. The storage system according to claim 14, wherein: The fast read page stores data that is a target of frequent reading.

16. The storage system according to claim 14, wherein: The memory cell includes a multi-level cell storing at least three bits. 17 . The memory system of claim 14 , further comprising a power supply configured to supply power to the memory controller.

18. A memory device comprising: Memory controller; as well as a nonvolatile memory device connected to the memory controller, wherein the memory controller is configured to perform a read operation on the nonvolatile memory device such that a fast read page of the nonvolatile memory device is read using one read voltage and at least two normal read pages of the nonvolatile memory device are read using the same number of multiple read voltages, The fast read page refers to a page in which data is determined by a read voltage, and the bit sequence of the fast read page has only one bit transition, and The normal read page refers to a page in which data is determined by a plurality of read voltages, and the bit sequence of each of the at least two normal read pages has more than one bit transition.

19. The memory device of claim 18, further comprising an interface for connecting to an external device.

20. The memory device of claim 18, wherein: A read latency of the fast read page is shorter than a read latency of each of the normal read pages.

21. The memory device of claim 18, wherein: The data of the fast read page is accessed more frequently than the data of each page of the normal read page.

22. The memory device of claim 18, wherein: The memory controller includes a memory interface for communicating data with the non-volatile memory device.

Images