Semiconductor chip including a low-k dielectric layer

Abstract

A semiconductor chip is provided, which includes: a device layer located on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and an interlayer dielectric layer located on the device layer, the interlayer dielectric layer surrounding the wiring structure and having a dielectric constant lower than that of silicon oxide; an upper interlayer dielectric layer disposed on the interlayer dielectric layer; isolation recesses disposed along the edge of the substrate, the isolation recesses being formed on the side surfaces of the interlayer dielectric layer and the upper interlayer dielectric layer and having a bottom surface at a level equal to or lower than the bottom surface of the interlayer dielectric layer; and a covering dielectric layer covering the side surfaces of the interlayer dielectric layer and the upper interlayer dielectric layer and the bottom surface of the isolation recesses.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0101872, filed with the Korean Intellectual Property Office on Aug. 20, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor chip, and more particularly, to a semiconductor chip including a low-k dielectric layer. Background Art

[0003] With the rapid development of the electronics industry and user demands, electronic devices and equipment have become lighter and more compact than ever. Accordingly, semiconductor chips / packages used in electronic devices have become more highly integrated than ever, and thus, the design rules for components used in semiconductor chips / packages have been reduced. Accordingly, a low-k dielectric layer has been introduced to reduce parasitic capacitance in a semiconductor chip (more specifically, between wirings). Summary of the Invention

[0004] The inventive concept provides a semiconductor chip for ensuring mechanical reliability during monolithicization of a semiconductor chip.

[0005] According to an aspect of the inventive concept, there is provided a semiconductor chip. The semiconductor chip includes: a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and an interlower-wiring dielectric layer, both on the device layer, the interlower-wiring dielectric layer surrounding the wiring structure and having a dielectric constant lower than that of silicon oxide; an interupper-wiring dielectric layer on the interlower-wiring dielectric layer, the interupper-wiring dielectric layer having a dielectric constant equal to or higher than that of silicon oxide; isolation recesses along an edge of the substrate, the isolation recesses formed on side surfaces of the interlower-wiring dielectric layer and the interupper-wiring dielectric layer and having a bottom surface at a level equal to or lower than a bottom surface of the interlower-wiring dielectric layer; and a covering dielectric layer covering side surfaces of the interlower-wiring dielectric layer and the interupper-wiring dielectric layer and a bottom surface of the isolation recesses.

[0006] According to another aspect of the inventive concept, there is provided a semiconductor chip including: a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and an interlower-wiring dielectric layer, both on the device layer, the interlower-wiring dielectric layer surrounding the wiring structure; an interupper-wiring dielectric layer on the interlower-wiring dielectric layer; isolation recesses disposed along an entire edge of the substrate and extending from a top surface of the interupper-wiring dielectric layer to at least a level same as a level of a bottom surface of the interlower-wiring dielectric layer; and an upper covering dielectric layer filling the isolation recesses, covering at least a part of a top surface of the interupper-wiring dielectric layer, and having a stepped portion along at least a part of an edge of the substrate.

[0007] According to another aspect of the inventive concept, there is provided a semiconductor chip including: a device layer on a substrate, the substrate having four sides forming a rectangular shape in a plan view, the device layer including a plurality of semiconductor devices; a wiring structure and an interlower dielectric layer, both on the device layer, the interlower dielectric layer surrounding the wiring structure; an upper interdielectric layer on the interlower dielectric layer; isolation recesses disposed along an entire edge of the substrate and extending at least to a level equal to a bottom surface level of the interlower dielectric layer from a top surface of the upper interdielectric layer; a pad pattern and a pad via, the pad pattern on the upper interdielectric layer, the pad via passing through the upper interdielectric layer, the pad via electrically connecting the pad pattern to the wiring structure; and an upper capping dielectric layer filling the isolation recesses, covering at least a part of a top surface of the upper interdielectric layer, and having a stepped portion along at least one of the four sides of the substrate, the stepped portion being at a level higher than a top surface level of the interlower dielectric layer and lower than a top surface level of the upper interdielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figures 1 to 7 is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment;

[0010] Figure 8A and Figure 8B are a cross-sectional view and a plan view, respectively, showing main elements of a semiconductor chip according to an embodiment;

[0011] Figure 9 is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment;

[0012] Figure 10 is a cross-sectional view showing main elements of a semiconductor chip according to an embodiment;

[0013] Figures 11 to 15 is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment;

[0014] Figure 16 is a cross-sectional view showing main elements of a semiconductor chip according to an embodiment;

[0015] Figure 17 is a cross-sectional view showing main elements of a semiconductor chip according to an embodiment;

[0016] Figure 18A and Figure 18B are a cross-sectional view and a plan view, respectively, showing main elements of a semiconductor chip according to an embodiment;

[0017] Figure 19A and Figure 19B are a cross-sectional view and a plan view showing the main elements of a semiconductor chip according to an embodiment, respectively;

[0018] Figure 20 is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment;

[0019] Figure 21 is a cross-sectional view showing the main elements of a semiconductor chip according to an embodiment;

[0020] Figures 22 to 24 is a cross-sectional view showing the main elements of a semiconductor chip according to an embodiment;

[0021] Figure 25 and Figure 26 is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment;

[0022] Figure 27 is a cross-sectional view showing the main elements of a semiconductor chip according to an embodiment;

[0023] Figures 28 to 30 is a cross-sectional view showing the main elements of a semiconductor chip according to an embodiment;

[0024] Figure 31A and Figure 31B are a cross-sectional view and a plan view showing the main elements of a semiconductor chip according to an embodiment, respectively;

[0025] Figures 32 to 34 is a cross-sectional view showing the main elements of a semiconductor chip according to an embodiment;

[0026] Figure 35 and Figure 36 is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment;

[0027] Figure 37A and Figure 37B are a cross-sectional view and a plan view showing the main elements of a semiconductor chip according to an embodiment, respectively;

[0028] Figure 38 is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment; and

[0029] Figure 39A and Figure 39B are a cross-sectional view and a plan view showing the main elements of a semiconductor chip according to an embodiment, respectively. Detailed Description

[0030] Figures 1 to 7It is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment. Figure 8A and Figure 8B are respectively a cross-sectional view and a plan view showing main elements of a semiconductor chip according to an embodiment.

[0031] Referring to Figure 1 , a device layer 130 including a plurality of semiconductor devices 120 is formed on a substrate 110. The substrate 110 may include a device region DR in which the semiconductor devices 120 are arranged and a scribe lane region SR. The scribe lane region SR may surround each of the plurality of device regions DR in a plan view. Although Figure 1 only shows two device regions DR and one scribe lane region SR located between the two device regions DR, the substrate 110 may include a plurality of device regions DR in a matrix and scribe lane regions SR arranged between adjacent device regions DR to surround each of the device regions DR in a plan view. The scribe lane region SR may be a region that can be removed from a wafer in which the device region DR is formed while maintaining the operability of devices (e.g., integrated circuit devices) formed in the device region DR. The scribe lane region SR between the device regions DR may include a region in which no circuit (e.g., no transistor) is formed and / or no circuit (e.g., no transistor) that is part of an integrated circuit of the integrated circuit device in the device region DR is formed.

[0032] The scribe lane region SR may include a cut-out region BR and a remaining scribe region RR. In the scribe lane region SR, the remaining scribe region RR may be a part in contact with the device region DR, the cut-out region BR may be a part separated from the device region DR, and the remaining scribe region RR is located between the cut-out region BR and the device region DR.

[0033] In order to obtain Figure 8A and Figure 8B the semiconductor chip 1 in, a cutting process may be performed to cut the substrate 110 along the scribe lane region SR in which no semiconductor device 120 is arranged. During the cutting process, the cut-out region BR is removed, and the remaining scribe region RR may be retained around the device region DR. Therefore, the device region DR and the remaining scribe region RR retained around the device region DR and in contact with the device region DR may form a singulated semiconductor chip, and thus may be collectively referred to as a chip region CR.

[0034] The excision region BR and the remaining scribing region RR included in the scribing lane region SR are defined due to the cutting process and may not be clearly defined before the cutting process is performed. However, since the scribing lane region SR is formed to have an area larger than that of the excision region BR to prevent the device region DR from being damaged during the cutting process, the semiconductor chip 1 that has been singulated includes the device region DR and the remaining scribing region RR, that is, the portion of the scribing lane region SR that contacts the device region DR along the edge of the device region DR.

[0035] The substrate 110 may include, for example, silicon (Si). The substrate 110 may include a semiconductor element (e.g., germanium (Ge)) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the substrate 110 may include a buried oxide (BOX) layer. The substrate 110 may include a conductive region, e.g., a doped well or a doped structure. The substrate 110 may have various isolation structures including a shallow trench isolation (STI) structure. The substrate 110 may have an active side and an inactive side opposite to the active side. The device layer 130 including the semiconductor devices 120 may be formed on the active side of the substrate 110. For example, the active side may be the main surface of the substrate 110 on which circuits and semiconductor devices 120 are formed, and the inactive side may be the bottom surface of the substrate 110 opposite to the main surface of the substrate 110.

[0036] At least some of the semiconductor devices 120 may be transistors. For example, at least some of the semiconductor devices 120 may be bipolar junction transistors (BJTs) or field effect transistors (FETs). For example, at least some of the semiconductor devices 120 may be planar transistors or FinFETs. When at least some of the semiconductor devices 120 are FinFETs, a plurality of fin-shaped active regions may protrude from the substrate 110 and extend parallel to each other in the horizontal direction.

[0037] The semiconductor devices 120 may form logic units. The logic units may include a plurality of circuit elements such as transistors and registers in various ways. The logic units may constitute, for example, AND gates, NAND gates, OR gates, NOR gates, exclusive OR (XOR) gates, exclusive NOR (XNOR) gates, inverters (INV), adders (ADD), buffers (BUF), delayers (DLY), filters (FIL), multiplexers (MXT / MXIT), OR / AND / inverter (OAI) gates, AND / OR (AO) gates, AND / OR / inverter (AOI) gates, D flip-flops, reset flip-flops, master-slave flip-flops, or latches. The logic units may constitute standard units that perform desired logic functions such as counters or buffers.

[0038] The semiconductor device 120 may include various individual devices for constituting, for example, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a dynamic random access memory (DRAM) device, a static RAM (SRAM) device, a flash memory device, an electrically erasable programmable read only memory (EEPROM) device, a phase change RAM (PRAM) device, a magnetic RAM (MRAM) device, or a resistive RAM (RRAM) device.

[0039] The device layer 130 may include the semiconductor device 120, conductive lines and conductive plugs electrically connecting the semiconductor device 120, and an interlayer dielectric layer between the conductive plugs, and may include various kinds and shapes of conductive materials, semiconductor materials, and insulating materials. In some embodiments, the interlayer dielectric layer disposed between the conductive lines and the conductive plugs may include an oxide.

[0040] The auxiliary structure 190 may be disposed in the scribe lane region SR. The auxiliary structure 190 is not related to the operation of the semiconductor device 120 and may include any structure that is used assistively during the manufacture of the semiconductor device 120 or for evaluating the electrical and / or physical characteristics of the semiconductor device 120. The auxiliary structure 190 may include, for example, a test element group (TEG) or an alignment key. In the scribe lane region SR, although the auxiliary structure 190 is shown disposed in the device layer 130, this is merely an example, and the auxiliary structure 190 may be formed in the substrate 110, the device layer 130, or Figures 2 to 7 a portion shown to be at a level higher in the vertical direction from the substrate 110 than the device layer 130.

[0041] In the specification, the term “level” refers to the height from the main surface (e.g., the top surface) of the substrate 110 in the vertical direction. For example, “at the same level” or “at a certain level” means “having the same height from the main surface of the substrate 110 in the vertical direction” or “being at a certain position having a certain distance from the main surface of the substrate 110 in the vertical direction”, and “at a low / high level” means “being at a low / high position relative to the main surface of the substrate 110 in the vertical direction”. For example, the height / level may be the distance from the top surface of the substrate 110 in the vertical direction relative to the top surface of the substrate 110.

[0042] Refer to Figure 2, a wiring structure MS and a first inter-wiring dielectric layer 210 surrounding the wiring structure MS are formed on a substrate 110 having a device layer 130. The first inter-wiring dielectric layer 210 may include an insulating material having a dielectric constant lower than that of silicon oxide. In some embodiments, the first inter-wiring dielectric layer 210 may include an ultra-low-k (ULK) film having an ultra-low dielectric constant of about 2.2 to about 2.4. The ULK film may include a SiOC film or a SiCOH film. The first inter-wiring dielectric layer 210 may be referred to as a low-k dielectric layer. In some embodiments, the level of the top surface of the first inter-wiring dielectric layer 210 may be substantially constant. For example, the top surface of the first inter-wiring dielectric layer 210 may be flat.

[0043] When referring to an orientation, layout, position, shape, size, quantity, or other metric, terms such as "same", "equal", "flat", or "coplanar" used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other metric, but are intended to include orientations, layouts, positions, shapes, sizes, quantities, or other metrics that are nearly the same within acceptable variations that may occur (e.g., due to manufacturing processes). Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, terms described as "substantially the same", "substantially equal", or "substantially flat" may be exactly the same, exactly equal, or exactly flat, or may be the same, equal, or flat within acceptable variations that may occur (e.g., due to manufacturing processes).

[0044] The wiring structure MS may include a plurality of wiring layers ML and a plurality of via plugs MV electrically / directly connected to the wiring layers ML. The wiring structure MS may include, for example, a metal such as aluminum, copper, or tungsten. In some embodiments, the wiring structure MS may include a wiring barrier layer and a wiring metal layer. The wiring barrier layer may include a nitride or oxide of a metal (such as Ti, Ta, Ru, Mn, Co, or W) or an alloy (such as cobalt tungsten phosphide (CoWP), cobalt tungsten boron (CoWB), or cobalt tungsten boron phosphide (CoWBP)). The wiring metal layer may include at least one metal selected from W, Al, Ti, Ta, Ru, Mn, and Cu.

[0045] It will be understood that when an element is referred to as being "connected" to or "coupled" to another element or "on" another element, the element can be directly connected to or directly coupled to the other element or directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" to or "directly coupled" to another element, or is referred to as "contacting" another element or "in contact" with another element, there are no intervening elements. Other words used to describe the relationship between elements (e.g., "between" and "directly between", "adjacent" and "directly adjacent", etc.) should be interpreted in the same manner. Unless the context otherwise indicates, the term "contact" as used herein refers to direct connection (i.e., touching).

[0046] The wiring layer ML may have a multi-layer structure having wiring layers ML at different levels. The first inter-wiring dielectric layer 210 may have a multi-layer structure corresponding to the multi-layer structure of the wiring layer ML in which a plurality of low-k dielectric layers are stacked. In some embodiments, the first inter-wiring dielectric layer 210 may have a multi-layer structure in which an insulating material having a dielectric constant lower than that of silicon oxide and another insulating material having a dielectric constant equal to or greater than that of silicon oxide are stacked. For example, the multi-layer structure of the first inter-wiring dielectric layer 210 may include at least one oxide layer or nitride layer. For example, the first inter-wiring dielectric layer 210 may include an etch stop layer including nitride in the process for forming the wiring layer ML, but the proportion of the etch stop layer including nitride in the first inter-wiring dielectric layer 210 may be relatively very low. For example, the total thickness of the etch stop layer may be less than one-tenth of the total thickness of the first inter-wiring dielectric layer 210. In certain embodiments, layers having a dielectric constant lower than that of silicon oxide and layers having a dielectric constant higher than that of silicon oxide may be alternately stacked in the first inter-wiring dielectric layer 210.

[0047] In some embodiments, the bottom surface of the lower wiring layer ML-L at the lowest level among the wiring layers ML may be at the same level as the bottom surface of the first inter-wiring dielectric layer 210.

[0048] Although the top surface of the wiring layer ML at the highest level among the wiring layers ML is shown to be at the same level as the top surface of the first inter-wiring dielectric layer 210 in Figure 2 , the embodiments are not limited thereto. In some embodiments, the bottom surface of the wiring layer ML at the highest level among the wiring layers ML may be at the same level as the top surface of the first inter-wiring dielectric layer 210.

[0049] The lowest-level lower vias plug MV-L in the vias plug MV can extend from the bottom surface of the lower wiring layer ML-L towards the device layer 130. The wiring structure MS can be electrically connected to the semiconductor device 120. The vias plug MV can extend from the bottom surface of each of the wiring layers ML at different levels in the multilayer structure of the wiring layer ML towards the substrate 110.

[0050] Some of the vias plugs MV in the vias plug MV can electrically / directly connect the wiring layers ML at different levels to each other, and other vias plugs MV in the vias plug MV can electrically connect some of the wiring layers ML to the semiconductor device 120. For example, the lower vias plug MV-L can electrically connect the lower wiring layer ML-L to the semiconductor device 120.

[0051] A second inter-wiring dielectric layer 220 and a lower pad (or "pad") via SPV are formed on the wiring structure MS and the first inter-wiring dielectric layer 210. The lower pad via SPV passes through the second inter-wiring dielectric layer 220 and is electrically connected to the wiring structure MS. A lower pad SPD is formed on the second inter-wiring dielectric layer 220 to electrically connect the lower pad SPD to the lower pad via SPV.

[0052] In some embodiments, the lower pad via SPV and the lower pad SPD can include a barrier layer and a metal layer. The barrier layer can include a nitride or oxide of a metal (such as Ti, Ta, Ru, Mn, Co, or W) or an alloy (such as CoWP, CoWB, or CoWBP). The metal layer can include at least one metal selected from W, Al, Ti, Ta, Ru, Mn, and Cu.

[0053] The second inter-wiring dielectric layer 220 can include an oxide layer, a carbide layer, a polymer, or a combination thereof. For example, the second inter-wiring dielectric layer 220 can include an oxide. In some embodiments, the second inter-wiring dielectric layer 220 can include tetraethyl orthosilicate (TEOS). In some embodiments, the level of the top surface of the second inter-wiring dielectric layer 220 can be substantially constant. For example, the top surface of the second inter-wiring dielectric layer 220 can be flat.

[0054] A third inter-wiring dielectric layer 230, a protective dielectric layer 240, and a fourth inter-wiring dielectric layer 250 are sequentially formed on the lower pad SPD and the second inter-wiring dielectric layer 220. The third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250 can include an oxide layer, a carbide layer, a polymer, or a combination thereof.

[0055] For example, the third inter-wiring dielectric layer 230 may include an oxide. In some embodiments, the third inter-wiring dielectric layer 230 may include a high density plasma (HDP) oxide. For example, the third inter-wiring dielectric layer 230 may include an oxide layer (e.g., a silicon dioxide layer), and the oxide layer may be formed by a high density plasma deposition process. In some embodiments, the level of the top surface of the third inter-wiring dielectric layer 230 may change along with the steps according to the level of the underlying SPD and the top surface of the second inter-wiring dielectric layer 220. For example, the underlying SPD may protrude from the top surface of the second inter-wiring dielectric layer 220, and the third inter-wiring dielectric layer 230 may have an uneven top surface corresponding to the underlying SPD and the top surface of the second inter-wiring dielectric layer 220.

[0056] For example, the protective dielectric layer 240 may include a nitride. The protective dielectric layer 240 may conformally cover the third inter-wiring dielectric layer 230. In some embodiments, the protective dielectric layer 240 may vary along with the steps according to the level of the top surface of the third inter-wiring dielectric layer 230.

[0057] For example, the fourth inter-wiring dielectric layer 250 may include an oxide. In some embodiments, the fourth inter-wiring dielectric layer 250 may include TEOS. In some embodiments, the level of the top surface of the fourth inter-wiring dielectric layer 250 may be substantially constant. For example, the top surface of the fourth inter-wiring dielectric layer 250 may be flat.

[0058] A pad via PV is formed through the third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250, and a pad pattern PD is electrically connected to the pad via PV and disposed on the fourth inter-wiring dielectric layer 250. In some embodiments, the pad via PV and the pad pattern PD may include a barrier layer and a metal layer. The barrier layer may include a nitride or oxide of a metal (such as Ti, Ta, Ru, Mn, Co, or W) or an alloy (such as CoWP, CoWB, or CoWBP). The metal layer may include at least one metal selected from W, Al, Ti, Ta, Ru, Mn, and Cu. The pad via PV may electrically connect the underlying SPD to the pad pattern PD. The pad pattern PD may include a redistribution pattern and a chip pad connected to the redistribution pattern. For example, the pad pattern PD may be electrically connected to the redistribution pattern and the chip pad. For example, the pad pattern PD may be directly / integrally connected to the redistribution pattern (e.g., the pad pattern PD and the redistribution pattern may be patterns of the same metal layer).

[0059] The second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250 may include a material having a dielectric constant greater than that of the first inter-wiring dielectric layer 210. For example, each of the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250 may include an insulating material having a dielectric constant equal to or higher than that of silicon oxide.

[0060] Referring to Figure 3 , a hard mask layer 270 covering the fourth inter-wiring dielectric layer 250 and the pad pattern PD is formed. In some embodiments, the hard mask layer 270 may include a carbon base layer. For example, the carbon base layer may include an amorphous carbon layer (ACL) or a carbon-based spin-on hard mask (C-SOH) layer. Figure 3 A cross-section of a wafer is shown, in which complete semiconductor devices are integrally formed in each of the device regions DR. Although only two device regions DR are shown, it will be understood that the device regions DR may be formed in rows and columns (in a two-dimensional array with respect to the top view of the wafer) within the wafer. The device regions DR may be separated from each other by a scribe lane region SR (e.g., a grid is formed, where the cells of the grid correspond to the device regions DR).

[0061] Referring to Figure 4 , the hard mask layer 270 is partially removed to form an opening OP exposing the fourth inter-wiring dielectric layer 250 in the scribe lane region SR. In some embodiments, the portion of the fourth inter-wiring dielectric layer 250 located in the scribe lane region SR and the portion of the fourth inter-wiring dielectric layer 250 located in the portion of the device region DR adjacent to the scribe lane region SR may be exposed through the opening OP. For example, the portion of the device region DR where a portion of the fourth inter-wiring dielectric layer 250 is exposed through the opening OP may have a width of about 5 μm or less from the scribe lane region SR.

[0062] Thereafter, using the hard mask layer 270 as an etching mask, the fourth inter-wiring dielectric layer 250, the protective dielectric layer 240, the third inter-wiring dielectric layer 230, and the second inter-wiring dielectric layer 220 are partially removed such that an isolation recess SRS exposing the first inter-wiring dielectric layer 210 is formed.

[0063] For example, an etching / ashing process may be used to partially remove the fourth inter-wiring dielectric layer 250, the protective dielectric layer 240, the third inter-wiring dielectric layer 230, and the second inter-wiring dielectric layer 220.

[0064] Referring to Figure 5, remove the exposed portion of the first interlayer dielectric layer 210 in the bottom surface of the isolation recess SRS to expose the device layer 130. Remove the portion of the first interlayer dielectric layer 210 such that the isolation recess SRS can extend into / inside the first interlayer dielectric layer 210 and expose the device layer 130 in the bottom surface of the isolation recess SRS. The bottom surface of the isolation recess SRS can be at the same level as the top surface of the device layer 130.

[0065] The portion of the first interlayer dielectric layer 210 can be removed using a dry etching process such as sputtering or reactive ion etching (RIE).

[0066] In some embodiments, the side surfaces of each of the fourth interlayer dielectric layer 250, the protective dielectric layer 240, the third interlayer dielectric layer 230, the second interlayer dielectric layer 220, and the first interlayer dielectric layer 210 that are exposed in the isolation recess SRS can be substantially smooth. For example, the isolation recess SRS can be formed on the side surfaces of the first interlayer dielectric layer 210, the second interlayer dielectric layer 220, the third interlayer dielectric layer 230, and the fourth interlayer dielectric layer 250, on the side surface of the protective dielectric layer 240, and on the top surface of the device layer 130. For example, as Figure 5 shown, the cross-sectional view of the sidewall of the isolation recess SRS can be linear.

[0067] After removing the portion of the first interlayer dielectric layer 210, the remaining hard mask layer 270 (in Figure 4 ) can be removed.

[0068] Referring to Figure 6 , form the upper capping dielectric layer 290 to fill at least a portion of the isolation recess SRS and cover the fourth interlayer dielectric layer 250 and the pad pattern PD. For example, the upper capping dielectric layer 290 can include an oxide. In some embodiments, the upper capping dielectric layer 290 can include TEOS. The upper capping dielectric layer 290 can include a material having a dielectric constant greater than that of the first interlayer dielectric layer 210. The upper capping dielectric layer 290 can cover both the inner surface and the bottom surface of the isolation recess SRS. In some embodiments, the lowest level of the top surface of the upper capping dielectric layer 290 can be higher than the level of the top surface of the first interlayer dielectric layer 210. For example, the upper capping dielectric layer 290 can completely fill the space of the portion of the isolation recess SRS formed in the first interlayer dielectric layer 210.

[0069] The upper capping dielectric layer 290 can include a recessed portion 290R in which the top surface of the upper capping dielectric layer 290 descends corresponding to the isolation recess SRS. For example, the recessed portion 290R can correspond to the isolation recess SRS.

[0070] Referring toFigure 7 , the upper portion of the upper cover dielectric layer 290 is removed so that the level of the top surface of the upper cover dielectric layer 290 is substantially constant in the device region DR. For example, the top surface of the upper cover dielectric layer 290 may be flat in the device region DR. In some embodiments, the level of the top surface of the upper cover dielectric layer 290 may be lower in a part of the remaining scribe region RR than in the device region DR. For example, when the upper portion of the upper cover dielectric layer 290 is removed, the upper cover dielectric layer 290 may include a recessed portion 290R corresponding to the isolation recess SRS. For example, a chemical mechanical polishing (CMP) process may be used to remove the upper portion of the upper cover dielectric layer 290.

[0071] In some embodiments, the bottom surface of the recessed portion 290R may be at a level lower than the top surface of the fourth inter-wiring dielectric layer 250.

[0072] Referring to Figure 7 、 Figure 8A and Figure 8B , a part of the upper cover dielectric layer 290 located on the pad pattern PD is removed so that the chip pad portion CPD of the pad pattern PD can be exposed. At least a part of the pad pattern PD covered by the upper cover dielectric layer 290 may be a redistribution pattern. For example, the chip pad portion CPD may be directly connected to the redistribution pattern or integrally formed with the redistribution pattern.

[0073] Thereafter, a dicing process is performed to cut the substrate 110 along the scribe lane region SR so that the semiconductor chip 1 is singulated. For example, the dicing process for obtaining the semiconductor chip 1 may be performed by using a blade saw / cutting. Figures 1 to 7 The width of the excision region BR in Figures 1 to 7 may be substantially the same as the kerf width of the blade used in the dicing process for obtaining the semiconductor chip 1. The kerf width of the blade may be smaller than the width of the scribe lane region SR defined between two adjacent device regions DR in (

[0074] The semiconductor chip 1 includes a device layer 130 including semiconductor devices 120 located on the substrate 110. The substrate 110 may include a device region DR in which the semiconductor devices 120 are arranged and a remaining scribe region RR surrounding the device region DR along the edge of the semiconductor chip 1. The remaining scribe region RR may be Figures 1 to 7 the scribe lane region SR in

[0075] A wiring structure MS and a first inter-wiring dielectric layer 210 surrounding the wiring structure MS are disposed on a substrate 110 having a device layer 130. The first inter-wiring dielectric layer 210 may include an insulating material having a dielectric constant lower than that of silicon oxide. The first inter-wiring dielectric layer 210 may be referred to as a low-k dielectric layer. In some embodiments, the level of the top surface of the first inter-wiring dielectric layer 210 may be substantially constant.

[0076] The wiring structure MS may include a wiring layer ML and a via plug MV electrically connected to the wiring layer ML. The wiring structure MS may be electrically connected to a semiconductor device 120. The wiring layer ML may have a multi-layer structure having wiring layers ML at different levels. The via plug MV may extend from the bottom surface of each of the wiring layers ML in the multi-layer structure of the wiring layer ML toward the substrate 110. Some of the via plugs MV among the via plugs MV may electrically / directly connect the wiring layers ML at different levels to each other, and other via plugs MV among the via plugs MV may electrically / directly connect some of the wiring layers ML to the semiconductor device 120.

[0077] In some embodiments, the bottom surface of the lower wiring layer ML-L among the wiring layers ML at the lowest level may be at the same level as the bottom surface of the first inter-wiring dielectric layer 210. The lower via plug MV-L among the via plugs MV at the lowest level may extend from the bottom surface of the lower wiring layer ML-L toward the device layer 130. For example, the lower via plug MV-L may electrically connect the lower wiring layer ML-L to the semiconductor device 120.

[0078] A second inter-wiring dielectric layer 220 and a lower pad via SPV are disposed on the wiring structure MS and the first inter-wiring dielectric layer 210. The lower pad via SPV passes through the second inter-wiring dielectric layer 220 and is electrically connected to the wiring structure MS. A lower pad SPD is disposed on the second inter-wiring dielectric layer 220 to be electrically connected to the lower pad via SPV. In some embodiments, the level of the top surface of the second inter-wiring dielectric layer 220 may be substantially constant. In some embodiments, the lower pad via SPV and the lower pad SPD may be omitted.

[0079] The third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250 are sequentially stacked on the underlying SPD and the second inter-wiring dielectric layer 220. In some embodiments, the level of the top surface of the third inter-wiring dielectric layer 230 may change along with the steps according to the levels of the top surfaces of the underlying SPD and the second inter-wiring dielectric layer 220. The protective dielectric layer 240 may conformally cover the third inter-wiring dielectric layer 230. In some embodiments, the level of the top surface of the protective dielectric layer 240 may change according to the level of the top surface of the third inter-wiring dielectric layer 230, for example, including steps. The protective dielectric layer 240 may be used as a passivation layer for protecting the semiconductor chip 1. In some embodiments, the level of the top surface of the fourth inter-wiring dielectric layer 250 may be substantially constant.

[0080] The pad pattern PD may be disposed on the fourth inter-wiring dielectric layer 250, and the pad via PV may pass through the third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250 to electrically connect the underlying SPD to the pad pattern PD.

[0081] For ease of description, the first inter-wiring dielectric layer 210 may be referred to as the lower inter-wiring dielectric layer 210, and the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250 may be collectively referred to as the upper inter-wiring dielectric layers. For example, the semiconductor chip 1 may include a substrate 110, a device layer 130 including semiconductor devices 120 located on the substrate 110, a wiring structure MS located on the device layer 130, a lower inter-wiring dielectric layer 210 surrounding the wiring structure MS, an upper inter-wiring dielectric layer located on the lower inter-wiring dielectric layer 210, a pad pattern PD including chip pads located on the upper inter-wiring dielectric layer, and a pad via PV electrically connecting the pad pattern PD to the wiring structure MS.

[0082] The upper cover dielectric layer 290 may cover a part of the pad pattern PD and the fourth inter-wiring dielectric layer 250. The portion of the pad pattern PD not covered by the upper cover dielectric layer 290 may be the chip pad portion CPD, and the portion of the pad pattern PD covered by the upper cover dielectric layer 290 may be at least partially a redistribution pattern. For example, the pad pattern PD may include a chip pad portion CPD and a redistribution pattern.

[0083] The upper cover dielectric layer 290 may cover the side surfaces of the first inter-wiring dielectric layer 210, the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250 in the isolation recess SRS. The upper cover dielectric layer 290 may cover the top surface of the device layer 130 at the bottom surface of the isolation recess SRS. For example, the upper cover dielectric layer 290 may cover the top surface of the inter-layer dielectric layer of the device layer 130.

[0084] The upper cover dielectric layer 290 may have a stepped portion ST at the edge of the semiconductor chip 1. For example, the stepped portion ST may be a region of the upper cover dielectric layer 290 that is stepped down from the highest flat surface of the upper cover dielectric layer 290. For example, the stepped portion ST may include a step formed in the upper cover dielectric layer 290. In certain embodiments, the stepped portion ST may refer to the step itself. In some embodiments, the stepped portion ST of the upper cover dielectric layer 290 may be formed in the remaining scribe region RR. In some embodiments, the stepped portion ST of the upper cover dielectric layer 290 may be formed to straddle the remaining scribe region RR and a portion of the device region DR adjacent to the remaining scribe region RR. For example, the remaining scribe region RR may be an edge portion of the semiconductor chip 1. For example, semiconductor devices may not be provided in the edge portion of the semiconductor chip 1. For example, a portion of the device region DR that is vertically stacked with the stepped portion ST may be vertically stacked with the semiconductor devices formed in the device region DR.

[0085] The stepped portion ST may surround the device region DR along the edge of the semiconductor chip 1. For example, when the semiconductor chip 1 has four sides forming a rectangular shape in a plan view, the stepped portion ST may be arranged to surround the device region DR along the four sides of the semiconductor chip 1. In some embodiments, the stepped portion ST may extend along the four sides of the semiconductor chip 1 with a substantially uniform horizontal width. For example, the stepped portion ST may extend along the four sides of the semiconductor chip 1 with a horizontal width of about 5 μm or less. The isolation recess SRS may be arranged along the edge of the semiconductor chip 1. For example, the isolation recess SRS may extend along the four sides of the semiconductor chip 1.

[0086] The edge or four sides of the semiconductor chip 1 may be referred to as the edge or four sides of the substrate 110.

[0087] The stepped portion ST (e.g., the top surface of the stepped portion ST) may be at a level lower than the top surface of the fourth inter-wiring dielectric layer 250. The stepped portion ST (e.g., the top surface of the stepped portion ST) may be at a level higher than the top surface of the first inter-wiring dielectric layer 210. The side surface of the upper cover dielectric layer 290 may extend substantially in the vertical direction below the stepped portion ST. For example, the side surface of the upper cover dielectric layer 290 may extend substantially in the vertical direction with respect to the main surface of the substrate 110 in a portion around the first inter-wiring dielectric layer 210 (i.e., a portion between the level of the top surface and the level of the bottom surface of the first inter-wiring dielectric layer 210). In some embodiments, the side surface of the upper cover dielectric layer 290 may extend with an acute angle with respect to the main surface of the substrate 110 above the stepped portion ST.

[0088] According to an embodiment, during a dicing process for singulating a semiconductor chip 1, a first inter-wiring dielectric layer 210 (i.e., a low-k dielectric layer) is not torn by a blade. For example, during a process for obtaining a singulated semiconductor chip 1, a dicing process using a blade can be performed through an upper cover dielectric layer 290, a device layer 130, and a substrate 110. Thus, the blade can pass through the upper cover dielectric layer 290, the device layer 130, and the substrate 110, and can not contact the first inter-wiring dielectric layer 210 disposed in a device region DR of the semiconductor chip 1. Accordingly, tearing of the low-k dielectric layer that may occur when dicing the low-k dielectric layer using a blade can be prevented. For example, a tearing defect of the low-k dielectric layer that occurs when the blade contacts / passes through the low-k dielectric layer during a dicing process can be improved by the embodiments described above. Accordingly, a side surface of the semiconductor chip 1 can be substantially smooth, such that when an adhesive film such as a non-conductive film (NCF) is attached to a bottom surface of the substrate 110 of the semiconductor chip 1 and a dicing process is performed to singulate the semiconductor chip 1, or when an adhesive film (such as an NCF) is attached to a top surface or a bottom surface of the semiconductor chip 1 to stack a plurality of semiconductor chips 1, the adhesive film (such as an NCF) is not torn at an edge of the semiconductor chip 1, which would be due to tearing of the low-k dielectric layer and / or due to the torn low-k dielectric layer.

[0089] Figure 9 is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment. Figure 10 is a cross-sectional view showing main elements of a semiconductor chip according to an embodiment. Figure 9 is subsequent to Figure 4 The stage of. Redundant descriptions similar or identical to those already given with reference to Figures 1 to 8B may be omitted. In Figures 1 to 10 identical reference numerals denote identical elements.

[0090] Referring to Figure 9 a device layer 130 can be partially removed in a process of partially removing the first inter-wiring dielectric layer 210 to expose the device layer 130, such that an isolation recess SRSa can pass through the first inter-wiring dielectric layer 210 and extend into the device layer 130. A bottom surface of the isolation recess SRSa can be at a level lower than a top end of the device layer 130.

[0091] Referring to Figure 10 a semiconductor chip 1a is formed by performing the same process as the process described with reference to Figures 6 to 8B .

[0092] The semiconductor chip 1a includes a device layer 130 including semiconductor devices 120 located on a substrate 110. The substrate 110 may include a device region DR in which the semiconductor devices 120 are arranged and a remaining scribed region RR surrounding the device region DR along the edge of the semiconductor chip 1a.

[0093] The upper covering dielectric layer 290 may cover the side surfaces of the first inter-wiring dielectric layer 210, the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250 in the isolation recess SRSa and cover the side surfaces of the upper portion of the device layer 130. The upper covering dielectric layer 290 may extend into the device layer 130 such that in the isolation recess SRSa, the bottom surface of the upper covering dielectric layer 290 is at a level lower than the top / surface of the device layer 130. The upper covering dielectric layer 290 may have a step portion ST at the edge of the semiconductor chip 1a.

[0094] Figures 11 to 15 is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment. Figure 16 is a cross-sectional view showing main elements of a semiconductor chip according to an embodiment. Figure 11 is subsequent to Figure 1 a cross-sectional view of a stage after that stage. Redundant descriptions similar or identical to those already given with reference to Figures 1 to 8B may be omitted. In Figures 1 to 16 the same reference numerals denote the same elements.

[0095] Referring to Figure 11 , the through electrode 150 is formed to pass through the device layer 130 and extend into the substrate 110. Although in Figure 11 the through electrode 150 extends from the top to the bottom of the substrate 110 through the substrate 110, this is merely an example. The through electrode 150 may be formed to extend into the substrate 110, and back grinding or back thinning may be performed in a subsequent process to partially remove the lower portion of the substrate 110 such that the through electrode 150 is exposed at the bottom of the substrate 110.

[0096] The via electrode 150 may include a conductive plug and a conductive barrier layer covering the surface of the conductive plug. For example, the conductive barrier layer may be disposed on the side surface of the conductive plug. For example, the conductive plug may include Cu or W. In some embodiments, the conductive plug may include Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or an alloy of W, but is not limited thereto. In some embodiments, the conductive barrier layer may include at least one material selected from Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. In some embodiments, a via dielectric layer may be disposed between the via electrode 150 and the device layer 130 and between the via electrode 150 and the substrate 110. For example, the via dielectric layer may include an oxide layer, a nitride layer, a carbide layer, a polymer, or a combination thereof.

[0097] In some embodiments, physical vapor deposition (PVD) or chemical vapor deposition (CVD) may be used to form the conductive barrier layer and the conductive plug, but the embodiments are not limited thereto. In some embodiments, the via dielectric layer may include a high aspect ratio process (HARP) oxide film formed using an ozone / tetraethyl orthosilicate (O3 / TEOS)-based sub-atmospheric CVD process.

[0098] Before or after forming the via electrode 150, the lower via plug MV-L may be formed to extend from the top surface of the device layer 130 into the device layer 130.

[0099] Referring to Figure 12 , a capping dielectric film 160 is formed to cover the device layer 130, the lower via plug MV-L, and the via electrode 150. The capping dielectric film 160 may include, for example, a nitride.

[0100] Referring to Figure 13 , the capping dielectric film 160 is partially removed to expose at least a portion of the top surfaces of the lower via plug MV-L and the via electrode 150, and then a lower wiring layer ML-L is formed to connect to the lower via plug MV-L and the via electrode 150. Although the capping dielectric film 160 is not located between the lower wiring layer ML-L and the device layer 130 in Figure 13 , the embodiments are not limited thereto. For example, the capping dielectric film 160 may be located between the lower wiring layer ML-L and the device layer 130 where the lower via plug MV-L and the via electrode 150 are not disposed.

[0101] Referring to Figure 14, a buried dielectric layer 170 is formed to cover the side surfaces of the lower wiring layer ML-L. For example, the buried dielectric layer 170 may include an oxide. In some embodiments, the buried dielectric layer 170 may include TEOS. In some embodiments, the level of the top surface of the buried dielectric layer 170 may be substantially constant. For example, the top surfaces of the buried dielectric layer 170 and the lower wiring layer ML-L may be coplanar.

[0102] The capping dielectric film 160 and the buried dielectric layer 170 may include an insulating material having a dielectric constant equal to or higher than that of silicon oxide.

[0103] Referring to Figure 15 , a wiring structure MS and a first inter-wiring dielectric layer 210a surrounding the wiring structure MS are formed on a substrate 110 having a lower wiring layer ML-L and a buried dielectric layer 170. The wiring structure MS may include a plurality of wiring layers ML and a plurality of via plugs MV connected to the wiring layers ML. The wiring layer ML includes the lower wiring layer ML-L, and the via plug MV includes the lower via plug MV-L. However, since the lower via plug MV-L and the lower wiring layer ML-L have been formed as described in Figure 12 and Figure 13 , the wiring structure MS can be formed by forming the wiring layers ML and the via plugs MV except for the lower wiring layer ML-L and the lower via plug MV-L after forming the buried dielectric layer 170.

[0104] The first inter-wiring dielectric layer 210a may include an insulating material having a dielectric constant lower than that of the capping dielectric film 160 and the buried dielectric layer 170. The first inter-wiring dielectric layer 210a may include an insulating material having a dielectric constant lower than that of silicon oxide. In some embodiments, the first inter-wiring dielectric layer 210a may include an ULK film having an ultra-low dielectric constant of about 2.2 to about 2.4. The first inter-wiring dielectric layer 210a may be referred to as a low-k dielectric layer. In some embodiments, the level of the top surface of the first inter-wiring dielectric layer 210a may be substantially constant.

[0105] In some embodiments, the top surface of the lowest-level lower wiring layer ML-L among the wiring layers ML may be at the same level as the bottom surface of the first inter-wiring dielectric layer 210a.

[0106] Referring to Figure 16 , the second inter-wiring dielectric layer 220, the lower pad via SPV, the lower pad SPD, the third inter-wiring dielectric layer 230, the protective dielectric layer 240, the fourth inter-wiring dielectric layer 250, the pad via PV, and the pad pattern PD are formed by performing the process described in Figure 2 . Thereafter, perform the process described in Figures 3 to 8AThe described process, and a bottom pad 155 connected to the through electrode 150 is formed on the bottom surface of the substrate 110, such that a semiconductor chip 2 is formed. For example, the bottom pad 155 may include Ti, Cu, Ni, Au, NiV, NiP, TiNi, TiW, TaN, Al, Pd, CuCr, or a combination thereof.

[0107] The semiconductor chip 2 may be different from Figure 8A the semiconductor chip 1 in that the top surface of the lower wiring layer ML-L, which is at the lowest level among the wiring layers ML, is at the same level as the bottom surface of the first inter-wiring dielectric layer 210a. Additionally, the semiconductor chip 2 may further include the through electrode 150 and the bottom pad 155. Although in Figure 16 the through electrode 150 penetrates the device layer 130 and the substrate 110, the embodiment is not limited thereto. For example, the through electrode 150 may be formed to extend from the top surface of the substrate 110 to the bottom surface of the substrate 110 through the substrate 110, and may be electrically connected to the lower wiring layer ML-L through the lower via plug MV-L or another conductive structure.

[0108] The upper capping dielectric layer 290 may cover the side surfaces of the first inter-wiring dielectric layer 210a, the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250 in the isolation recess SRSb. The bottom surface of the isolation recess SRSb that may correspond to the bottom surface of the upper capping dielectric layer 290 may be at the same level as the top surface of the buried dielectric layer 170. The upper capping dielectric layer 290 may cover the top surface of the buried dielectric layer 170 at the bottom surface of the isolation recess SRSb.

[0109] Figure 17 is a cross-sectional view showing the main elements of a semiconductor chip according to an embodiment. Redundant descriptions similar or identical to those already given with reference to Figures 1 to 16 may be omitted. In Figures 1 to 17 the same reference numerals denote the same elements.

[0110] Referring to Figure 17 , the semiconductor chip 2a includes an upper capping dielectric layer 290 filling the isolation recess SRSc. The isolation recess SRSc may penetrate the first inter-wiring dielectric layer 210a and extend into the buried dielectric layer 170. The bottom surface of the isolation recess SRSc may be at a level lower than the top surface of the buried dielectric layer 170.

[0111] The upper covering dielectric layer 290 may cover at least a part of the side surfaces of the first inter-wiring dielectric layer 210a, the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250 in the isolation recess SRSc, and the side surface of the buried dielectric layer 170 in the isolation recess SRSc. The bottom surface of the upper covering dielectric layer 290 may be at a level lower than the top surface of the buried dielectric layer 170, and the upper covering dielectric layer 290 may extend into the buried dielectric layer 170.

[0112] In some embodiments, the isolation recess SRSc may penetrate through the buried dielectric layer 170 and the capping dielectric film 160 and extend into the device layer 130. The bottom surface of the isolation recess SRSc may be at a level lower than the level of the top end of the device layer 130. In this case, the upper covering dielectric layer 290 may cover the side surfaces of the buried dielectric layer 170 and the capping dielectric film 160 and the side surfaces of the upper part of the device layer 130.

[0113] Figure 18A and Figure 18B are a cross-sectional view and a plan view showing main elements of a semiconductor chip according to an embodiment, respectively. Redundant descriptions similar or identical to those already given may be omitted. In Figures 1 to 16 the descriptions already given, the same reference numerals denote the same elements. Figures 1 to 18B In

[0114] Referring to Figure 18A and Figure 18B , the upper covering dielectric layer 290 of the semiconductor chip 3 may have a stepped portion ST in the edge portion of the semiconductor chip 3. In some embodiments, the stepped portion ST of the upper covering dielectric layer 290 may be formed in the remaining scribing region RR.

[0115] The semiconductor chip 3 may have the stepped portion ST only in a part of the edge of the semiconductor chip 3. The stepped portion ST may be Figure 7 a part of the bottom surface of the recessed portion 290R in Figure 18B , where the part remains after performing a dicing process to form the semiconductor chip 3. Although in

[0116] the stepped portion ST extends along two of the four sides of the semiconductor chip 3 and does not extend along the other two sides, the embodiments are not limited thereto. For example, the stepped portion ST may not be arranged along at least one of the four sides of the semiconductor chip 3 but may be arranged along one to three other sides.

[0116] In the dicing process for obtaining the semiconductor chip 3, sawing using a blade may be performed along the four sides of the semiconductor chip 3. At this time, when sawing using a blade along at least one side of the semiconductor chip 3, the ( Figure 7When all of the recessed portions 290R in ) are cut off, the stepped portion ST is not provided at at least one side of the semiconductor chip 3 and can extend along other sides of the semiconductor chip 3. The isolation recess SRS can extend along four sides of the semiconductor chip 3.

[0117] Figure 19A and Figure 19B are a cross-sectional view and a plan view showing main elements of a semiconductor chip according to an embodiment, respectively. Redundant descriptions similar or identical to the descriptions already given may be omitted. In Figures 1 to 16 the same reference numerals denote the same elements. Figures 1 to 19B

[0118] Referring to Figure 19A and Figure 19B , the semiconductor chip 3a includes an upper cover dielectric layer 290 having a trench portion STR adjacent to an edge of the semiconductor chip 3a. In some embodiments, the trench portion STR of the upper cover dielectric layer 290 may be formed in the remaining scribe region RR. The trench portion STR may be disposed in a part of the upper cover dielectric layer 290, where the part has a horizontal distance of several micrometers (μm) or less from the edge of the semiconductor chip 3a.

[0119] The semiconductor chip 3a may have the trench portion STR in only a part of the edge. The trench portion STR may be Figure 7 a part of the recessed portion 290R in Figure 19B which remains after performing a cutting process to form the semiconductor chip 3a. Although in

[0120] the trench portion STR extends along two of the four sides of the semiconductor chip 3a and does not extend along the other two sides in Figure 7When the recessed portion 290R is retained along some of the four sides of the semiconductor chip 3a and is completely cut off along other sides of the semiconductor chip 3a during a sawing process using a blade, the groove portion STR may extend along some sides of the semiconductor chip 3a without extending along other sides of the semiconductor chip 3a.

[0121] Figure 8A , Figure 8B , Figure 10 , Figure 16 , Figure 17 , Figure 18A and Figure 18B The step ST and Figure 19A and Figure 19B The groove portion STR in can be collectively referred to as a recessed structure.

[0122] Figure 20 is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment. Figure 21 is a cross-sectional view showing main elements of a semiconductor chip according to an embodiment. Figure 20 It is the successor Figure 5 The cross-sectional view of the stage after the stage can be omitted with reference to Figures 1 to 8B Redundant descriptions that are similar or identical to those already given. Figures 1 to 21 In the drawings, like reference numerals denote like elements.

[0123] Reference Figure 20 , the upper cover dielectric layer 290a is formed to completely fill the isolation recess SRS and cover the fourth inter-wiring dielectric layer 250 and the pad pattern PD. For example, the upper cover dielectric layer 290a may include an oxide. In some embodiments, the upper cover dielectric layer 290a may include TEOS. The upper cover dielectric layer 290a may include a material having a dielectric constant greater than that of the first inter-wiring dielectric layer 210.

[0124] The upper capping dielectric layer 290 a may have a flat top surface having a substantially constant level.

[0125] Reference Figure 21 , partially remove the upper portion of the upper cover dielectric layer 290a. For example, the upper portion of the upper cover dielectric layer 290a may be partially removed using CMP. Thereafter, a portion of the upper cover dielectric layer 290a located on the pad pattern PD may be removed to expose the chip pad portion CPD of the pad pattern PD. Thereafter, a cutting process is performed to cut the substrate 110 along the scribe line region SR, thereby singulating the semiconductor chip 4.

[0126] The semiconductor chip 4 may include an upper cover dielectric layer 290a covering a part of the pad pattern PD and the fourth inter-wiring dielectric layer 250. The portion of the pad pattern PD not covered by the upper cover dielectric layer 290a may be the chip pad portion CPD, and at least a part of the pad pattern PD covered by the upper cover dielectric layer 290a may be a redistribution pattern.

[0127] The upper cover dielectric layer 290a may cover side surfaces of the first inter-wiring dielectric layer 210, the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the protection dielectric layer 240, and the fourth inter-wiring dielectric layer 250 in the isolation recess SRS. The upper cover dielectric layer 290a may cover the top surface of the device layer 130 at the bottom surface of the isolation recess SRS.

[0128] The upper cover dielectric layer 290a may have side surfaces extending substantially along the edge of the semiconductor chip 4 in a vertical direction with respect to the substrate 110 (e.g., with respect to the top surface of the substrate 110). The side surfaces of the upper cover dielectric layer 290a may extend in the vertical direction with respect to the substrate 110 (e.g., with respect to the top surface of the substrate 110) from the top surface of the device layer 130 to at least a level higher than the top surface of the fourth inter-wiring dielectric layer 250. For example, the upper cover dielectric layer 290a may not have Figure 8A and Figure 8B the stepped portion ST shown in

[0129] Figures 22 to 24 is a cross-sectional view showing main elements of a semiconductor chip according to an embodiment. Redundant descriptions similar or identical to those already given may be omitted. In Figures 1 to 20 the same reference numerals denote the same elements. Figures 1 to 24 In

[0130] Referring to Figure 22 and Figure 21 unlike the isolation recess SRS of the semiconductor chip 4 in

[0131] the semiconductor chip 4a may include an isolation recess SRSa having a bottom surface at a level lower than the level of the top end of the device layer 130. Figure 23 Referring to Figure 16 unlike the upper cover dielectric layer 290 having the stepped portion ST in the semiconductor chip 2 in Figure 21 the semiconductor chip 5 may include an upper cover dielectric layer 290a similar to the upper cover dielectric layer 290a of the semiconductor chip 4 in

[0132] Referring to Figure 24 and Figure 17 unlike the upper cover dielectric layer 290 having the stepped portion ST in the semiconductor chip 2a inFigure 21 A capping dielectric layer 290a similar to the capping dielectric layer 290a of the semiconductor chip 4.

[0133] Figure 25 and Figure 26 are cross-sectional views of stages in a method of manufacturing a semiconductor chip according to an embodiment. Figure 27 is a cross-sectional view showing main elements of a semiconductor chip according to an embodiment. Figure 25 is a cross-sectional view of a stage subsequent to the stage of Figure 3 . Redundant descriptions similar or identical to those already given with reference to Figures 1 to 8B may be omitted. In Figures 1 to 27 , the same reference numerals denote the same elements.

[0134] Referring to Figure 25 , as described above with reference to Figure 4 , the hard mask layer 270 is partially removed to form an opening OP exposing the fourth inter-wiring dielectric layer 250 in the scribe line region SR. Thereafter, using the hard mask layer 270 as an etch mask, the fourth inter-wiring dielectric layer 250, the protection dielectric layer 240, the third inter-wiring dielectric layer 230, the second inter-wiring dielectric layer 220, and the first inter-wiring dielectric layer 210 are partially removed to form an isolation recess SRSd exposing the device layer 130.

[0135] For example, an ashing / etch process may be used to partially remove the fourth inter-wiring dielectric layer 250, the protection dielectric layer 240, the third inter-wiring dielectric layer 230, the second inter-wiring dielectric layer 220, and the first inter-wiring dielectric layer 210. For example, although the isolation recess SRS in Figure 5 may be formed by separately performing a process of removing the fourth inter-wiring dielectric layer 250, the protection dielectric layer 240, the third inter-wiring dielectric layer 230, and the second inter-wiring dielectric layer 220 and a process of removing the first inter-wiring dielectric layer 210, the isolation recess SRSd in Figure 25 may be formed by performing a single process of removing all of the fourth inter-wiring dielectric layer 250, the protection dielectric layer 240, the third inter-wiring dielectric layer 230, the second inter-wiring dielectric layer 220, and the first inter-wiring dielectric layer 210.

[0136] In some embodiments, the side surfaces of each of the fourth inter-wiring dielectric layer 250, the protective dielectric layer 240, the third inter-wiring dielectric layer 230, and the second inter-wiring dielectric layer 220 that are exposed in the isolation recess SRSd may be substantially smooth, and the side surface of the first inter-wiring dielectric layer 210 that is exposed in the isolation recess SRSd may have uneven portions RGN. For example, the uneven portions RGN of the first inter-wiring dielectric layer 210 may be rougher than the side surfaces of the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the protective dielectric layer 240, and the fourth inter-wiring dielectric layer 250.

[0137] Referring to Figure 26 , a lower covering dielectric layer 260 is formed to conformally cover the inner surface and bottom surface of the isolation recess SRSd and the top surfaces of the fourth inter-wiring dielectric layer 250 and the pad pattern PD. For example, the lower covering dielectric layer 260 may include a nitride. The lower covering dielectric layer 260 may cover the uneven portions RGN in the side surface of the first inter-wiring dielectric layer 210.

[0138] Referring to Figure 27 , a process same as the process described with reference to Figures 6 to 8B is performed. When a part of the upper covering dielectric layer 290 located on the pad pattern PD is removed to expose the chip pad portion CPD of the pad pattern PD, a part of the lower covering dielectric layer 260 located on the pad pattern PD is also removed, thereby forming a semiconductor chip 6. The lower covering dielectric layer 260 and the upper covering dielectric layer 290 may be collectively referred to as a covering dielectric layer.

[0139] Different from the semiconductor chip 1 of Figure 8A , the semiconductor chip 6 may further include the uneven portions RGN in the side surface of the first inter-wiring dielectric layer 210 and the lower covering dielectric layer 260 that covers the inner surface and bottom surface of the isolation recess SRSd, the top surface of the fourth inter-wiring dielectric layer 250, a part of the top surface of the pad pattern PD, and the side surface. The upper covering dielectric layer 290 may be disposed on the lower covering dielectric layer 260.

[0140] Since the uneven portions RGN in the side surface of the first inter-wiring dielectric layer 210 are covered by the lower covering dielectric layer 260 and the upper covering dielectric layer 290 in the semiconductor chip 6, the uneven portions RGN do not cause damage to the upper covering dielectric layer 290 or tearing of an adhesive film (e.g., NCF).

[0141] Figures 28 to 30 is a cross-sectional view showing main elements of a semiconductor chip according to an embodiment. Redundant descriptions similar or identical to the descriptions already given with reference to Figures 1 to 27 may be omitted. In Figures 1 to 30 , the same reference numerals denote the same elements.

[0142] Referring toFigure 28 , different from the semiconductor chip 1a of Figure 10 , the semiconductor chip 6a may further include uneven portions RGN in a side surface of the first inter-wiring dielectric layer 210, and a lower covering dielectric layer 260 covering an inner surface and a bottom surface of the isolation recess SRSe, a top surface of the fourth inter-wiring dielectric layer 250, and a part of a top surface and a side surface of the pad pattern PD, and an upper covering dielectric layer 290 may be disposed on the lower covering dielectric layer 260. Similar to Figure 10 the isolation recess SRSa of the semiconductor chip 1a of

[0143] Refer to Figure 29 , different from the semiconductor chip 2 of Figure 16 , the semiconductor chip 7 may further include uneven portions RGN in a side surface of the first inter-wiring dielectric layer 210, and a lower covering dielectric layer 260 covering an inner surface and a bottom surface of the isolation recess SRSf, a top surface of the fourth inter-wiring dielectric layer 250, and a part of a top surface and a side surface of the pad pattern PD, and an upper covering dielectric layer 290 may be disposed on the lower covering dielectric layer 260. Similar to Figure 16 the isolation recess SRSb of the semiconductor chip 2 of

[0144] Refer to Figure 30 , different from the semiconductor chip 2a of Figure 17 , the semiconductor chip 7a may further include uneven portions RGN in a side surface of the first inter-wiring dielectric layer 210, and a lower covering dielectric layer 260 covering an inner surface and a bottom surface of the isolation recess SRSg, a top surface of the fourth inter-wiring dielectric layer 250, a part of a top surface and a side surface of the pad pattern PD, and an upper covering dielectric layer 290 may be disposed on the lower covering dielectric layer 260. Similar to Figure 17 the isolation recess SRSc of the semiconductor chip 2a of

[0145] Figure 31A and Figure 31B are respectively a cross-sectional view and a plan view showing main elements of a semiconductor chip according to an embodiment. Redundant descriptions similar or identical to those already given with reference to Figures 1 to 30 may be omitted. In Figures 1 to 31BIn the following, like reference numerals denote like elements.

[0146] Referring to Figure 31A and Figure 31B , the semiconductor chip 8 may include an upper cover dielectric layer 295 different from the upper cover dielectric layer 290 included in the semiconductor chip 6 included in Figure 27 . The upper cover dielectric layer 295 may not fill the isolation recess SRSd and may be disposed only on a part of the lower cover dielectric layer 260, where the part of the lower cover dielectric layer 260 covers the top surface of the fourth inter-wiring dielectric layer 250 and a part and side surfaces of the top surface of the pad pattern PD. For example, the upper cover dielectric layer 295 may include photosensitive polyimide (PSPI).

[0147] The isolation recess SRSd may extend along four sides of the semiconductor chip 8.

[0148] Since the uneven portions RGN in the side surfaces of the first inter-wiring dielectric layer 210 are covered by the lower cover dielectric layer 260 in the semiconductor chip 8, tearing of an adhesive film (e.g., NCF) is not caused by the uneven portions RGN of the first inter-wiring dielectric layer 210.

[0149] Figures 32 to 34 is a cross-sectional view showing main elements of a semiconductor chip according to an embodiment. Redundant descriptions similar or identical to the descriptions already given with reference to Figures 1 to 31B may be omitted. In Figures 1 to 34 , like reference numerals denote like elements.

[0150] Referring to Figure 32 , the semiconductor chip 8a may include an upper cover dielectric layer 295 different from the upper cover dielectric layer 290 included in the semiconductor chip 6a included in Figure 28 . The upper cover dielectric layer 295 may not fill the isolation recess SRSe and may be disposed only on a part of the lower cover dielectric layer 260, where the part of the lower cover dielectric layer 260 covers the top surface of the fourth inter-wiring dielectric layer 250 and a part and side surfaces of the top surface of the pad pattern PD.

[0151] Referring to Figure 33 , the semiconductor chip 9 may include an upper cover dielectric layer 295 different from the upper cover dielectric layer 290 included in the semiconductor chip 7 included in Figure 29 . The upper cover dielectric layer 295 may not fill the isolation recess SRSf and may be disposed only on a part of the lower cover dielectric layer 260, where the part of the lower cover dielectric layer 260 covers the top surface of the fourth inter-wiring dielectric layer 250 and a part and side surfaces of the top surface of the pad pattern PD.

[0152] Referring to Figure 34, the semiconductor chip 9a may include an upper covering dielectric layer 295 different from the upper covering dielectric layer 290 included in the semiconductor chip 7a included in Figure 30 . The upper covering dielectric layer 295 may not fill the isolation recess SRSg and may be disposed only on a part of the lower covering dielectric layer 260, where the part of the lower covering dielectric layer 260 covers the top surface of the fourth inter-wiring dielectric layer 250 and a part of the top surface and the side surface of the pad pattern PD.

[0153] Figure 35 and Figure 36 are cross-sectional views of stages in a method of manufacturing a semiconductor chip according to an embodiment. Figure 37A and Figure 37B are a cross-sectional view and a plan view showing main elements of a semiconductor chip according to an embodiment, respectively. Figure 35 is a cross-sectional view of a stage subsequent to the stage of Figure 5 . Redundant descriptions similar or identical to those already given with reference to Figures 1 to 8B may be omitted. In Figures 1 to 37B , the same reference numerals denote the same elements.

[0154] Referring to Figure 35 , similar to the upper covering dielectric layer 290 in Figure 6 and Figure 7 , the upper covering dielectric layer 290 may be formed to fill at least a part of the isolation recess SRS and cover the fourth inter-wiring dielectric layer 250 and the pad pattern PD, and an upper part of the upper covering dielectric layer 290 may be partially removed. The level of the top surface of the upper covering dielectric layer 290 is substantially constant in the device region DR. The upper covering dielectric layer 290 may include a recessed portion 290Ra corresponding to the isolation recess SRS.

[0155] In some embodiments, the bottom surface of the recessed portion 290Ra may be at a level higher than the level of the top surface of the fourth inter-wiring dielectric layer 250. In some embodiments, the bottom surface of the recessed portion 290Ra may be at a level lower than the level of the top surface of the pad pattern PD.

[0156] Referring to Figure 36, an extended recess 292R is formed by removing a portion of the upper cover dielectric layer 290 adjacent to the recess 290Ra. The extended recess 292R can be formed by removing a portion of the upper cover dielectric layer 290 adjacent to the recess 290Ra using a photolithography process or an etching process. The extended recess 292R can be formed to communicate with or open to the recess 290Ra. Although the recess 290Ra and the extended recess 292R are separately formed and thus separately named, the recess 290Ra can be considered to extend to the extended recess 292R according to the result of forming the extended recess 292R. Therefore, the recess 290Ra and the extended recess 292R can be collectively referred to as a recess.

[0157] Although in Figure 36 the bottom surface of the extended recess 292R is at a level higher than the level of the bottom surface of the recess 290Ra, the embodiments are not limited thereto. For example, the bottom surface of the extended recess 292R can be at the same level as the bottom surface of the recess 290Ra or can be at a level lower than the level of the bottom surface of the recess 290Ra.

[0158] In the process of removing a portion of the upper cover dielectric layer 290 to form the extended recess 292R, a portion of the upper cover dielectric layer 290 located between the recess 290Ra and the extended recess 292R (i.e., the portion of the upper cover dielectric layer 290 where the recess 290Ra and the extended recess 292R overlap) is further removed, so that a trench portion SLP can be formed between the recess 290Ra and the extended recess 292R. The bottom end of the trench portion SLP can be at a level lower than the level of the bottom surface of the recess 290Ra and the level of the bottom surface of the extended recess 292R. For example, the trench portion SLP can include a narrow channel extending as formed on the surface of the upper cover dielectric layer 290 between the extended recess 292R and the recess 290Ra. In some embodiments, the trench portion SLP can refer to the trench itself.

[0159] Referring to Figures 36 to 37B , a portion of the upper cover dielectric layer 290 located on the pad pattern PD can be removed to expose the chip pad portion CPD of the pad pattern PD.

[0160] Thereafter, a dicing process is performed to cut the substrate 110 along the scribe lane region SR, thereby singulating the semiconductor chip 10.

[0161] With Figure 8AUnlike the semiconductor chip 1, the semiconductor chip 10 includes an upper cover dielectric layer 290 having a stepped portion STa with a part adjacent to the remaining scribe region RR and across the remaining scribe region RR and the device region DR. In some embodiments, the stepped portion STa may extend along the four sides of the semiconductor chip 10 with a substantially uniform horizontal width. For example, the stepped portion STa may extend along the four sides of the semiconductor chip 10 with a horizontal width of about 10 μm or less.

[0162] The stepped portion STa may be at a level higher than the top surface of the fourth inter-wiring dielectric layer 250. The stepped portion STa may be at a level lower than the top surface of the chip pad portion CPD.

[0163] The stepped portion STa may have a groove portion SLP in its bottom surface. The groove portion SLP may surround the device region DR along the edge of the semiconductor chip 10. For example, when the semiconductor chip 10 has four sides forming a rectangular shape in a plan view, the groove portion SLP may be arranged to surround the device region DR along the four sides of the semiconductor chip 10.

[0164] Figure 38 is a cross-sectional view of a stage in a method of manufacturing a semiconductor chip according to an embodiment. Figure 39A and Figure 39B are a cross-sectional view and a plan view showing main elements of a semiconductor chip according to an embodiment, respectively. Figure 38 is Figure 35 a cross-sectional view of a stage following the stage of. Redundant descriptions similar or identical to those already given with reference to Figures 1 to 37B may be omitted. In Figures 1 to 39B the same reference numerals denote the same elements.

[0165] Referring to Figure 38 , an extended recess 292Ra is formed by removing a part of the upper cover dielectric layer 290 adjacent to the recess 290Ra. The extended recess 292Ra may be formed by removing a part of the upper cover dielectric layer 290 adjacent to the recess 290Ra using a lithography process or an etching process. The extended recess 292Ra may be formed to communicate with the recess 290Ra or open to the recess 290Ra. Although the recess 290Ra and the extended recess 292Ra are separately formed and thus separately named, the recess 290Ra may be considered to extend to the extended recess 292Ra as a result of forming the extended recess 292Ra. Therefore, the recess 290Ra and the extended recess 292Ra may be collectively referred to as the recess.

[0166] Although in Figure 38The bottom surface of the extended recess 292Ra is at a level higher than the level of the bottom surface of the recess 290Ra, but the embodiment is not limited thereto. For example, the bottom surface of the extended recess 292Ra may be at the same level as the bottom surface of the recess 290Ra or may be at a level lower than the level of the bottom surface of the recess 290Ra.

[0167] In the process of removing a part of the upper covering dielectric layer 290 to form the extended recess 292Ra, less of the upper covering dielectric layer 290 located between the recess 290Ra and the extended recess 292Ra may be removed, so that a protrusion PRP can be formed between the recess 290Ra and the extended recess 292Ra. The top of the protrusion PRP may be at a level higher than the level of the bottom surface of the recess 290Ra and the level of the bottom surface of the extended recess 292Ra. For example, the protrusion PRP may include a protrusion extending along the recess 290Ra and the extended recess 292Ra on the surface of the upper covering dielectric layer 290 and between the recess 290Ra and the extended recess 292Ra. In some embodiments, the protrusion PRP may refer to the protrusion itself.

[0168] Referring to Figures 38 to 39B , a part of the upper covering dielectric layer 290 located on the pad pattern PD may be removed to expose the chip pad portion CPD of the pad pattern PD.

[0169] Thereafter, a dicing process is performed to cut the substrate 110 along the scribe lane region SR, thereby singulating the semiconductor chip 10a.

[0170] Unlike Figure 37A the semiconductor chip 10, the semiconductor chip 10a includes an upper covering dielectric layer 290 having a stepped portion STb with a part adjacent to the remaining scribe region RR across the remaining scribe region RR and the device region DR. In some embodiments, the stepped portion STb may extend along the four sides of the semiconductor chip 10a with a substantially uniform horizontal width. For example, the stepped portion STb may extend along the four sides of the semiconductor chip 10a with a horizontal width of about 10 μm or less.

[0171] The stepped portion STb may be at a level higher than the level of the top surface of the fourth inter-wiring dielectric layer 250. The stepped portion STb may be at a level lower than the level of the top surface of the chip pad portion CPD.

[0172] The stepped portion STb may have a protrusion PRP on its bottom surface. The protrusion PRP may surround the device region DR along the edge of the semiconductor chip 10a. For example, when the semiconductor chip 10a has four sides forming a rectangular shape in a plan view, the protrusion PRP may be arranged to surround the device region DR along the four sides of the semiconductor chip 10a.

[0173] Although not shown, similar to the semiconductor chip 3 of Figure 18A and Figure 18B the semiconductor chips 10 of Figure 37A and Figure 37B and the semiconductor chips 10a of Figure 39A and Figure 39B may respectively have stepped portions STa and STb, and each of the stepped portions STa and STb is not arranged along at least one of the four sides of the semiconductor chip 10 or 10a but is arranged along one to three other sides. Similar to the semiconductor chip 3a of Figure 19A and Figure 19B the semiconductor chips 10 of Figure 37A and Figure 37B and the semiconductor chips 10a of Figure 39A and Figure 39B may have a trench portion STR instead of the stepped portions STa or STb, and the trench portion STR is not arranged along at least one of the four sides of the semiconductor chip 10 or 10a but is arranged along one to three other sides.

[0174] In some embodiments, Figure 37A and Figure 37B the groove portion SLP of the semiconductor chip 10 of Figure 39A and Figure 39B the protrusion portion PRP of the semiconductor chip 10a of

[0175] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor chip, the semiconductor chip comprising: A device layer located on a substrate, the device layer including a plurality of semiconductor devices; A wiring structure and an inter-layer dielectric layer, both located on the device layer, the inter-layer dielectric layer surrounding the wiring structure and having a dielectric constant lower than that of silicon oxide; An upper inter-layer dielectric layer located on the inter-layer dielectric layer, the upper inter-layer dielectric layer having a dielectric constant equal to or higher than that of silicon oxide; Isolation recesses along the edge of the substrate, the isolation recesses formed on the side surfaces of the inter-layer dielectric layer and the upper inter-layer dielectric layer, the isolation recesses having a bottom surface at a level equal to or lower than the bottom surface of the inter-layer dielectric layer; And A covering dielectric layer covering the side surfaces of the inter-layer dielectric layer and the upper inter-layer dielectric layer and the bottom surface of the isolation recesses, Wherein the substrate has four sides forming a rectangular shape in a plan view, Wherein the covering dielectric layer has a stepped portion along at least one of the four sides of the substrate, and Wherein a groove or a protrusion is formed in the bottom surface of the stepped portion along at least one of the four sides of the substrate.

2. The semiconductor chip according to claim 1, wherein, The stepped portion of the covering dielectric layer extends along the four sides of the substrate.

3. The semiconductor chip according to claim 1, wherein, The stepped portion of the covering dielectric layer is at a level higher than the top surface of the inter-layer dielectric layer and at a level lower than the top surface of the upper inter-layer dielectric layer.

4. The semiconductor chip according to claim 1, wherein, The stepped portion of the covering dielectric layer is at a level higher than the top surface of the upper inter-layer dielectric layer.

5. The semiconductor chip according to claim 1, wherein, The covering dielectric layer has a groove portion along some of the four sides of the substrate.

6. The semiconductor chip according to claim 1, wherein, In the isolation recess, the side surface of the inter-layer dielectric layer has uneven portions, and The covering dielectric layer includes a lower covering dielectric layer that covers the uneven portions of the inter-layer dielectric layer and conformally covers at least a part of the top surface of the upper inter-layer dielectric layer and the inner surface and the bottom surface of the isolation recess.

7. The semiconductor chip according to claim 6, wherein, The covering dielectric layer further includes an upper covering dielectric layer that fills the isolation recess and covers the lower covering dielectric layer.

8. The semiconductor chip according to claim 6, wherein, The covering dielectric layer further includes an upper covering dielectric layer that covers the portion of the lower covering dielectric layer located on the top surface of the upper inter-layer dielectric layer.

9. The semiconductor chip according to claim 1, wherein, The wiring structure includes a plurality of wiring layers, the plurality of wiring layers including a lower wiring layer that is at the lowest level among the plurality of wiring layers, and The bottom surface of the lower wiring layer is at the same level as the bottom surface of the inter-layer dielectric layer.

10. The semiconductor chip according to claim 1, wherein, The wiring structure includes a plurality of wiring layers, the plurality of wiring layers including a lower wiring layer that is at the lowest level among the plurality of wiring layers, and The top surface of the lower wiring layer is at the same level as the bottom surface of the interlayer dielectric layer between the lower wirings.

11. The semiconductor chip according to claim 10, wherein the semiconductor chip further comprises: a bottom pad located on the bottom surface of the substrate; and a through electrode passing through the device layer and the substrate and electrically connecting the lower wiring layer to the bottom pad.

12. A semiconductor chip, comprising: a device layer located on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and an interlayer dielectric layer between the lower wirings, both located on the device layer, the interlayer dielectric layer between the lower wirings surrounding the wiring structure; an upper interlayer dielectric layer located on the interlayer dielectric layer between the lower wirings; an isolation recess disposed along the entire edge of the substrate and extending at least from the top surface of the upper interlayer dielectric layer to the same level as the bottom surface of the interlayer dielectric layer between the lower wirings; an upper cover dielectric layer filling the isolation recess, covering at least a part of the top surface of the upper interlayer dielectric layer, and having a stepped portion along at least a part of the edge of the substrate; and a groove or a protrusion located in the bottom surface of the stepped portion.

13. The semiconductor chip according to claim 12, wherein the isolation recess further extends into the device layer below the level of the bottom surface of the interlayer dielectric layer between the lower wirings.

14. The semiconductor chip according to claim 2, wherein the interlayer dielectric layer between the lower wirings is a low-k dielectric layer having a dielectric constant lower than that of silicon oxide, and the dielectric constant of the upper interlayer dielectric layer is greater than the dielectric constant of the interlayer dielectric layer between the lower wirings.

15. The semiconductor chip according to claim 12, wherein the stepped portion of the upper cover dielectric layer is at a level higher than the level of the top surface of the interlayer dielectric layer between the lower wirings.

16. A semiconductor chip, comprising: a device layer located on a substrate, the substrate having four sides forming a rectangular shape in a plan view, the device layer including a plurality of semiconductor devices; a wiring structure and an interlayer dielectric layer between the lower wirings, both located on the device layer, the interlayer dielectric layer between the lower wirings surrounding the wiring structure; an upper interlayer dielectric layer located on the interlayer dielectric layer between the lower wirings; an isolation recess disposed along the entire edge of the substrate and extending at least from the top surface of the upper interlayer dielectric layer to the same level as the bottom surface of the interlayer dielectric layer between the lower wirings; a pad pattern and a pad via hole, the pad pattern being located on the upper interlayer dielectric layer, the pad via hole passing through the upper interlayer dielectric layer, and the pad via hole electrically connecting the pad pattern to the wiring structure; and an upper cover dielectric layer filling the isolation recess, covering at least a part of the top surface of the upper interlayer dielectric layer, and having a stepped portion along at least one of the four sides of the substrate, the stepped portion being at a level higher than the level of the top surface of the interlayer dielectric layer between the lower wirings and lower than the level of the top surface of the upper interlayer dielectric layer; and a groove or a protrusion located in the bottom surface of the stepped portion along at least one of the four sides of the substrate.

17. The semiconductor chip according to claim 16, wherein the stepped portion of the upper cover dielectric layer extends along the four sides of the substrate.

18. The semiconductor chip according to claim 16, wherein the isolation recess extends along the four sides of the substrate.

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