Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises: a gate pattern spanning a substrate, the gate pattern comprising a gate insulating layer, a gate electrode and a gate cap pattern sequentially stacked on the substrate; a gate spacer covering the sidewall of the gate pattern; a source / drain pattern on the substrate, the source / drain pattern being adjacent to the sidewall of the gate pattern; a contact pad on the source / drain pattern, the top surface of the contact pad being lower than the top surface of the gate electrode; a source / drain contact plug on the contact pad; and a protection spacer between the gate spacer and the source / drain contact plug, the protection spacer having a ring shape surrounding the source / drain contact plug.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] Semiconductor devices are regarded as important elements in the electronics industry due to their small size, multifunctionality and / or low cost. Semiconductor devices are classified as semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including both storage elements and logic elements. As the electronics industry develops, the demand for semiconductor devices with improved characteristics continues to grow. For example, the demand for semiconductor devices with high reliability, high performance and / or multiple functions continues to grow. In order to meet this demand, the complexity and / or integration density of semiconductor devices are increased. Summary of the invention

[0003] According to one embodiment, a semiconductor device may include: a gate pattern spanning a substrate and including a gate insulating layer, a gate electrode, and a gate cap pattern stacked in sequence on the substrate; a gate spacer covering a sidewall of the gate pattern; a source / drain pattern disposed on the substrate and beside the gate pattern; a contact pad disposed on the source / drain pattern to have a top surface lower than a top surface of the gate electrode; a source / drain contact plug on the contact pad; and a protection spacer inserted between the gate spacer and the source / drain contact plug to have a ring shape surrounding the source / drain contact plug.

[0004] According to one embodiment, a semiconductor device may include: an active fin protruding from a substrate and extending in a first direction; a gate pattern spanning the active fin and including a gate insulating layer, a gate electrode, and a gate cap pattern stacked in sequence on the substrate; a gate spacer covering a sidewall of the gate pattern; a source / drain pattern disposed on the active fin and beside the gate pattern; a contact pad disposed on the source / drain pattern to have a top surface lower than a top surface of the gate electrode; a source / drain contact plug on the contact pad; and a protection spacer inserted between the gate spacer and the source / drain contact plug, the protection spacer having a ring shape surrounding the source / drain contact plug and having a width greater than that of the gate spacer.

[0005] According to an embodiment, a method for manufacturing a semiconductor device may include: forming a gate pattern, a gate spacer, a source / drain pattern, and an interlayer insulating layer on a substrate, the gate patterns spanning the substrate and being adjacent to each other, the gate spacer covering the sidewalls of the gate pattern, the source / drain pattern being disposed between adjacent gate patterns in the gate pattern, the interlayer insulating layer being formed to cover the gate pattern, the gate spacer, and the source / drain pattern, each of the gate patterns including a gate insulating layer, a gate electrode, and a gate cap pattern stacked in sequence; performing an anisotropic etching process on the interlayer insulating layer to form a first hole exposing the source / drain pattern; The interlayer insulating layer performs an isotropic etching process to expand the width of the first hole and expose the sidewall of the gate spacer; forms a contact pad in the first hole, the contact pad contacts the source / drain pattern; forms a protection spacer in the first hole, the protection spacer covers the sidewall of the adjacent gate spacer in the gate spacer, exposes the top surface of the contact pad, and has a ring shape when viewed in a top view; etches the gate cap pattern of at least one of the gate patterns to form a second hole exposing the gate electrode; and forms a source / drain contact plug in contact with the contact pad in the first hole, and forms a gate contact plug in contact with the gate electrode in the second hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0007] Figure 1A A top view of a semiconductor device according to an embodiment is shown.

[0008] Figure 1B The semiconductor device according to one embodiment is shown. Figure 1A Cross-sectional views taken along lines A-A', B-B' and CC'.

[0009] Figure 1C The semiconductor device according to one embodiment is shown. Figure 1A Cross-sectional views taken along lines A-A', B-B' and CC'.

[0010] Figure 1D The semiconductor device according to one embodiment is shown. Figure 1A Cross-sectional views taken along lines A-A', B-B' and CC'.

[0011] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A Shows that in manufacturing with Figure 1AA top view of a semiconductor device with a planar structure at a stage in a process is shown.

[0012] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B The Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A and 8A Cross-sectional views taken along lines AA', BB' and CC'.

[0013] Fig. 9A A top view of a semiconductor device according to an embodiment is shown.

[0014] Fig. 9B Shown along Fig. 9A Cross-sectional views taken along lines A-A', B-B' and CC'.

[0015] Fig.10 Shows the manufacturing Fig. 9B A cross-sectional view of a cross-sectional process of a semiconductor device.

[0016] Fig.11A A top view of a semiconductor device according to an embodiment is shown.

[0017] Fig. 11B Shown along Fig.11A Cross-sectional views taken along lines A-A', B-B' and CC'.

[0018] Fig.12 Shows the manufacturing Fig. 11B A cross-sectional view of a cross-sectional process of a semiconductor device.

[0019] Fig.13A A top view of a semiconductor device according to an embodiment is shown.

[0020] Fig. 13B Shown along Fig.13A Cross-sectional views taken along lines A-A', B-B' and CC'.

[0021] Fig.14 Shows the manufacturing Fig. 13B A cross-sectional view of a cross-sectional process of a semiconductor device.

[0022] Fig.15 and Fig.16 Top views are shown, each showing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0023] Example embodiments will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0024] Figure 1A is a top view showing a semiconductor device according to an embodiment. Figure 1B A semiconductor device according to an embodiment of the present invention Figure 1A Cross-sectional views taken along lines A-A', B-B' and CC'. Figure 1B The semiconductor device may correspond to an example of a fin field effect transistor (FinFET) device.

[0025] Reference Figure 1A and Figure 1B , the active fin AF may protrude from the substrate 1. The device isolation layer 3 may be disposed on a portion of the substrate 1 located next to the active fin AF, for example, the device isolation layer 3 may be adjacent to the active fin AF along a second direction Y parallel to the top surface of the substrate 1. The active fin AF may have a top surface and an upper side located at a height (level) higher than the top surface of the device isolation layer 3, for example, along a third direction Z perpendicular to the top surface of the substrate 1. The substrate 1 may be a single crystal silicon wafer or a silicon on insulator (SOI) wafer. The device isolation layer 3 may be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, or include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may have a single-layer structure or a multi-layer structure. The active fin AF may be a stripe pattern or a linear pattern elongated in a first direction X parallel to the top surface of the substrate 1.

[0026] Each of the gate patterns GP1, GP2, GP3, and GP4 may be provided to cross the active fin AF in a second direction Y crossing the first direction X. The gate patterns GP1, GP2, GP3, and GP4 may be spaced apart from each other in the first direction X. Each of the gate patterns GP1, GP2, GP3, and GP4 may include a gate insulating layer GO, a gate electrode GE, and a gate capping pattern GC sequentially stacked on the substrate 1.

[0027] The gate insulating layer GO may include, for example, silicon oxide and at least one of a high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material may include a metal oxide (e.g., aluminum oxide). The gate electrode GE may be formed of at least one of a metallic material (e.g., tungsten, copper, and aluminum), or include at least one of a metallic material (e.g., tungsten, copper, and aluminum). A work function layer, a diffusion barrier layer, and the like may be interposed between the gate electrode GE and the gate insulating layer GO. The diffusion barrier layer may include a metal nitride layer (e.g., a titanium nitride layer). The gate cap pattern GC may be formed of, for example, silicon nitride, or include, for example, silicon nitride.

[0028] The gate spacer GS may be provided to cover the sidewalls of the gate patterns GP1, GP2, GP3, and GP4, respectively. The gate spacer GS may include, for example, a silicon nitride layer, or a double layer or triple layer including a silicon nitride layer and a silicon oxide layer. The gate insulating layer GO may extend into a region between the gate electrode GE and the gate spacer GS, and may contact the gate cap pattern GC.

[0029] The recessed region R1 may be formed in the active fin AF and beside the gate spacer GS, for example, the recessed region R1 may be formed in the active fin AF between adjacent gate patterns in the gate patterns GP1, GP2, GP3, and GP4. The source / drain pattern SD may be provided in the recessed region R1 to be adjacent to the sidewall of the corresponding gate pattern in the gate patterns GP1, GP2, GP3, and GP4. The source / drain pattern SD may be an epitaxial layer formed of the same material as the substrate 1. For example, the source / drain pattern SD may be a silicon epitaxial layer. Alternatively, the source / drain pattern SD may include a material different from the substrate 1. For example, the source / drain pattern SD may be a silicon germanium epitaxial layer. The source / drain pattern SD may be doped with n-type or p-type impurities. For example, the source / drain pattern SD may be doped with phosphorus or boron. The gate patterns GP1, GP2, GP3, and GP4, the spacer GS, and the source / drain pattern SD may be covered with an interlayer insulating layer IL. The interlayer insulating layer IL may be formed of or include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a porous insulating material, and may have a single layer structure or a multilayer structure.

[0030] The first hole H1 may be formed in the interlayer insulating layer IL to overlap the source / drain pattern SD, for example, to expose the source / drain pattern SD. Figure 1A As shown, the first hole H1 may be positioned to overlap a portion of the active fin AF between adjacent gate patterns among the gate patterns GP1, GP2, GP3, and GP4. Figure 1B As shown in the cross section AA' of FIG. 1 , the sidewall of the gate spacer GS may overlap with the first hole H1, for example, be exposed through the first hole H1. Figure 1B As further shown in the cross-section AA', the uppermost width of the first hole H1 along the first direction X (ie, the width of the first hole H1 above the gate patterns GP1, GP2, GP3 and GP4 along the first direction X) may be greater than the width of the source / drain pattern SD along the first direction X.

[0031] The contact pad CP may be disposed in the first hole H1 and may be in contact with the source / drain pattern SD. Figure 1BAs shown in the cross section AA' of FIG. 1 , the sidewall of the contact pad CP may be in contact with the sidewall of the gate spacer GS, for example, along the first direction X. Figure 1B As shown in the cross section CC' of FIG. 1 , the sidewall of the contact pad CP may be in contact with the inner sidewall of the first hole H1, for example, along the second direction Y. Figure 1A-1B , the contact pad CP may partially fill the first hole H1 directly over the source / drain pattern SD, so that the side walls of the contact pad CP opposite to each other along the first direction X may directly contact the facing gate spacer GS of the adjacent gate pattern, and the side walls of the contact pad CP opposite to each other along the second direction Y may directly contact the facing inner side walls of the same first hole H1, that is, directly contact the facing side walls of the interlayer insulating layer IL. The contact pad CP may be formed of or include a metal-semiconductor material (e.g., cobalt silicide), a diffusion barrier material (e.g., titanium nitride), or a metallic material (e.g., tungsten and aluminum).

[0032] The upper side SW of the source / drain pattern SD may be inclined at an angle, for example, downward from the uppermost surface of the source / drain pattern SD, and the lower portion of the contact pad CP may extend to contact the inclined upper side SW of the source / drain pattern SD. Figure 1B As shown in the cross section CC' of FIG. 1 , the bottom of the contact pad CP may be conformal along the uppermost surface of the source / drain pattern SD and at least partially along the upper side SW of the source / drain pattern SD, eg, tilted downward.

[0033] On the contact pad CP, the inner sidewall of the first hole H1 may be covered with a protection spacer LS, such as Figure 1B For example, Figure 1B As shown in the cross-sections AA' and CC' of FIG. 1 , the protection spacer LS may extend continuously along the remaining portion of the first hole H1 not filled by the contact pad CP, for example, the entire inner sidewall, for example, to contact the top surface of the contact pad CP. Figure 1B As shown in the cross section CC' of FIG. 1 , the outer sidewall of the protection spacer LS, such as the sidewall of the contact interlayer insulating layer IL, can be aligned with the sidewall of the contact interlayer insulating layer IL of the contact pad CP, such as being in line. For example, the sidewall of the protection spacer LS between two facing gate spacers GS of adjacent gate patterns (e.g., not overlapping the gate pattern and the gate spacer) can be aligned with the sidewall of the contact pad CP in the direction in which the gate pattern extends. Figure 1B As shown in the cross section AA' of FIG. 8 , the protection spacer LS may be in contact with the sidewall of the gate spacer GS.

[0034] When viewed in a top plan view, the protection spacer LS may have a closed ring shape (eg, Figure 1AIn the present embodiment, the protection spacer LS may have an elliptical ring shape when viewed in a top view. The protection spacer LS may overlap with the gate spacer GS, for example, when viewed in a top view ( Figure 1A ), one elliptical ring-shaped protection spacer LS in the single first hole H1 may overlap with two facing gate spacers GS of the adjacent gate pattern. The width of the protection spacer LS may be greater than the width of the gate spacer GS, for example, the top of one elliptical ring-shaped protection spacer LS in the single first hole H1 may extend beyond the two facing gate spacers GS of the adjacent gate pattern to contact with a portion of the top surface of the gate cap pattern GC (in Figure 1A For example, Figure 1B As shown, a width of the protection spacer LS, for example measured along the first direction X above the gate pattern, may be greater than a width of the gate spacer GS, for example measured along the first direction X from a sidewall of the gate pattern adjacent to the protection spacer LS.

[0035] In one embodiment, the protection spacer LS may be formed of a low-k dielectric material having a lower dielectric constant than the dielectric constant of the gate spacer GS, or include the low-k dielectric material. For example, the gate spacer GS may be formed of silicon oxycarbide (SiOC), or include silicon oxycarbide (SiOC). The protection spacer LS may have a shape protruding above the gate patterns GP1, GP2, GP3, and GP4, for example, to at least partially overlap with the top surface of the gate cap pattern GC. The top surface of the protection spacer LS may be coplanar with the top surface of the interlayer insulating layer IL. Adjacent protection spacers in the protection spacer LS may be spaced apart from each other along the first direction X, and a portion of the interlayer insulating layer IL may be located between adjacent protection spacers in the protection spacer LS.

[0036] The second hole H2 defined by the inner sidewall of the protection spacer LS may be disposed in the first hole H1, for example, the first hole H1 and the second hole H2 may be concentric. The second hole H2 may expose a portion of the top surface of the contact pad CP that is not covered by the protection spacer LS. The source / drain contact plug SCT may be disposed in the second hole H2, for example, the source / drain contact plug SCT may completely fill the second hole H2. The protection spacer LS may have, for example, a top view ( Figure 1A ) in a ring shape (e.g., an elliptical ring shape) surrounding (e.g., completely surrounding) the source / drain contact plug SCT, and a tubular cylindrical shape (e.g., an entire sidewall shape) surrounding the source / drain contact plug SCT. Figure 1B Due to the protection spacer LS, the source / drain contact plug SCT may have a width smaller than that of the contact pad CP, for example, in each of the first direction X and the second direction Y.

[0037] The first gate contact plug GCT1 may be disposed between adjacent protection spacers in the protection spacer LS and on the second gate pattern GP2. The first gate contact plug GCT1 may be provided to penetrate the gate cap pattern GC of the second gate pattern GP2 and contact the gate electrode GE. The first gate contact plug GCT1 may be disposed in the third hole H3. The inner sidewall of the third hole H3 may be composed of the sidewall of the gate cap pattern GC and the sidewall of the interlayer insulating layer IL. The first gate contact plug GCT1 may contact the protection spacer LS.

[0038] The second gate contact plug GCT2 may be disposed on the third gate pattern GP3. The second gate contact plug GCT2 may be provided to penetrate the gate cap pattern GC of the third gate pattern GP3 and contact the gate electrode GE. Figure 1B As shown in the cross-section BB' of FIG. 1 , the second gate contact plug GCT2 may vertically overlap the device isolation layer 3. The second gate contact plug GCT2 may be disposed in the fourth hole H4. The inner sidewall of the fourth hole H4 may be composed of the sidewall of the gate cap pattern GC and the sidewall of the interlayer insulating layer IL. The second gate contact plug GCT2 may be spaced apart from the protection spacer LS.

[0039] Figure 1C FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention. Figure 1A Cross-sectional views taken along lines A-A', B-B' and CC'. Figure 1C The semiconductor device may correspond to a multi-bridge channel field effect transistor Examples of devices.

[0040] Reference Figure 1C , the channel pattern CH may be disposed on the active fin AF to be spaced apart from the active fin AF. The channel pattern CH may include first to third semiconductor patterns CH1, CH2, and CH3 stacked on the active fin AF. The first to third semiconductor patterns CH1, CH2, and CH3 may be spaced apart from each other. In one embodiment, the first to third semiconductor patterns CH1, CH2, and CH3 may include, for example, silicon. The gate electrode GE may cover the top surface and the side surface of the channel pattern CH. The width of the second semiconductor pattern CH2 may be different from the width of the third semiconductor pattern CH3.

[0041] The gate electrode GE may include first to fourth gate portions G1, G2, G3 and G4 connected to form a single object. The first gate portion G1 may be located between the active fin AF and the first semiconductor pattern CH1. The second gate portion G2 may be located between the first semiconductor pattern CH1 and the second semiconductor pattern CH2. The third gate portion G3 may be located between the second semiconductor pattern CH2 and the third semiconductor pattern CH3. The gate insulating layer GO may be interposed between the gate electrode GE and the channel pattern CH and between the gate electrode GE and the active fin AF. The source / drain pattern SD may extend to an area under the gate spacer GS to contact a sidewall of the channel pattern CH. The width of the source / drain pattern SD may be greater than the width of the contact pad CP. In addition to the above features, the semiconductor device according to the present embodiment may be configured to have the same Figure 1B The features of the semiconductor device described are substantially the same features.

[0042] Figure 1D FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention. Figure 1A Cross-sectional views taken along lines A-A', B-B' and CC'. Figure 1D The semiconductor device may correspond to a multi-bridge channel field effect transistor Examples of devices.

[0043] Reference Figure 1D The semiconductor device according to the present embodiment may further include a blocking insulating pattern BP interposed between the source / drain pattern SD and the gate insulating layer GO surrounding the first to third gate portions G1, G2, and G3. The blocking insulating pattern BP may be formed of a material different from the gate insulating layer GO (e.g., silicon nitride), or include a material different from the gate insulating layer GO (e.g., silicon nitride). The blocking insulating pattern BP may prevent the possible occurrence of a gap between the first to third gate portions G1, G2, and G3 and the source / drain pattern SD during manufacturing. Figure 1D In addition to the above-mentioned features, the semiconductor device according to the present embodiment can be configured to have the same characteristics as those of the reference embodiment. Figure 1C The features of the semiconductor device described are substantially the same features.

[0044] In accordance with Figures 1A-1D In the semiconductor device of the embodiment of the present invention, the top surface of the contact pad CP may be, for example, along Figure 1BThe third direction Z of the gate electrode GE is lower than the top surface of the gate electrode GE, so the distance between the contact pad CP and the gate electrode GE can be increased to prevent the bridging problem between the contact pad CP and the gate electrode GE. In addition, due to the protection spacer LS, the distance between the gate electrode GE and the source / drain contact plug SCT can be increased, thereby preventing the bridging problem between the gate electrode GE and the source / drain contact plug SCT. In addition, because the protection spacer LS includes a low-k dielectric material, the parasitic capacitance between the gate electrode GE and the source / drain contact plug SCT can be reduced, thereby reducing or minimizing the signal interference problem. Therefore, the reliability of the semiconductor device can be improved.

[0045] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A It is shown that manufacturing has Figure 1A A top view of a semiconductor device with a planar structure at a stage in a process is shown. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B Along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A Cross-sectional views taken along lines A-A', B-B' and CC'.

[0046] Reference Figure 2A and Figure 2B , the substrate 1 may be etched to form an active fin AF, which is a portion of the substrate 1. A device isolation layer 3 may be formed on a portion of the substrate 1 located next to the active fin AF. A dummy gate pattern may be formed to intersect the active fin AF, and a gate spacer GS may be formed to cover the sidewall of the dummy gate pattern. The recessed region R1 may be formed by etching an exposed portion of the active fin AF near the gate spacer GS. A selective epitaxial growth (SEG) process and an in-situ doping process may be performed to form a source / drain pattern SD in the recessed region R1. As Figure 2BAs shown in the cross section CC' of , each of the source / drain patterns SD may be formed in, for example, a pentagon having an inclined upper side SW. The dummy gate pattern may be removed, and then, gate patterns GP1, GP2, GP3, and GP4 may be formed in regions, such as openings, defined by the removed dummy gate pattern, respectively. An interlayer insulating layer IL may be formed to cover the gate patterns GP1, GP2, GP3, and GP4 and the source / drain patterns SD. In one embodiment, the interlayer insulating layer IL may be formed of, for example, tetraethyl orthosilicate (TEOS), or include, for example, tetraethyl orthosilicate (TEOS).

[0047] Reference Figure 3A and Figure 3B , a first mask pattern MK1 may be formed on the interlayer insulating layer IL. The first mask pattern MK1 may include an opening overlapping the source / drain pattern SD. The first mask pattern MK1 may be formed of or include at least one of materials having an etching selectivity relative to the interlayer insulating layer IL (e.g., photoresist, polysilicon, spin-on hard mask (SOH), spin-on carbon (SOC), and amorphous carbon layer (ACL) materials). The interlayer insulating layer IL may be anisotropically etched using the first mask pattern MK1 as an etching mask to form first holes H1 that respectively expose the source / drain patterns SD. Here, the upper portion of the source / drain pattern SD may also be etched, such as Figure 3B Each of the first holes H1 may be formed to have a cross section CC' as shown in FIG. Figure 3B The interlayer insulating layer IL faces the sidewalls along Figure 2A The first hole H1 may have a first width W1 measured in a first direction X of the gate spacer GS. The first hole H1 may expose a sidewall of the gate spacer GS. Even when misalignment occurs during the formation of the first hole H1, the sidewalls of the gate patterns GP1, GP2, GP3, and GP4 may be protected by the gate spacer GS. The anisotropic etching process for forming the first hole H1 may be performed by a self-alignment method using the etching selectivity of the gate spacer GS. In some cases, the anisotropic etching process may cause damage to the upper portion of the gate spacer GS.

[0048] Reference Figure 4A and Figure 4B , the first mask pattern MK1 may be removed to expose the top surface of the interlayer insulating layer IL. An isotropic etching process of selectively etching the interlayer insulating layer IL may be performed to expand the width of the first hole H1 to, for example, Figure 4B The etched interlayer insulating layer IL faces the sidewall along Figure 2A The second width W2 measured in the first direction X is greater than the first width W1. Figure 4B As shown in the cross section CC', the first hole H1 may also have Figure 2A The width of the source / drain pattern SD is enlarged in the second direction Y, so the inclined upper side SW of the source / drain pattern SD can be at least partially exposed. The isotropic etching process can be performed using, for example, hydrofluoric acid or hydrogen fluoride gas. Because the isotropic etching process is performed to selectively etch the interlayer insulating layer IL, the gate spacer GS can be prevented from being damaged during the isotropic etching process.

[0049] Reference Figure 5A and Figure 5B , a conductive layer may be formed on the substrate 1 and may be recessed by, for example, an etch-back process. Therefore, a contact pad CP may be formed in the first hole H1. Here, because the first hole H1 is enlarged to have a second width W2, a deposition source gas and an etchant may be effectively supplied through the first hole H1, thereby more effectively performing the process of forming the conductive layer and recessing the conductive layer. In one embodiment, the contact pad CP may be formed normally without any malfunction. The contact pad CP may be in contact with the inclined upper side SW of the source / drain pattern SD. The top surface of the contact pad CP may be lower than the top surface of the gate electrode GE. In some cases, the upper portion of the gate spacer GS may be damaged by the etch-back process.

[0050] Reference Figure 5A , Figure 5B , Fig. 6A and Figure 6B , a protection layer may be formed on the substrate 1, and then, an etch-back process of the protection layer may be performed to form a protection spacer LS covering the inner sidewall of the first hole H1. In some embodiments, the formation of the protection spacer LS may include filling the hole H1 with the protection layer, performing a chemical mechanical polishing (CMP) process to form a protection pattern in the first hole H1, and performing an anisotropic etching process on the protection pattern. Due to the protection spacer LS, the second hole H2 may be formed to partially expose the top surface of the contact pad CP. The protection spacer LS may cover and protect the damaged upper portion of the gate spacer GS.

[0051] Reference Fig. 6A , Figure 6B , Fig. 7A and Figure 7B, a second mask pattern MK2 may be formed on the substrate 1. The second mask pattern MK2 may include an opening that overlaps a portion of the second gate pattern GP2 between adjacent protection spacers in the protection spacer LS and a portion of the third gate pattern GP3 that is spaced apart from the protection spacer LS. The second mask pattern MK2 may be formed of, for example, at least one of a spin-on hard mask (SOH) material, or include, for example, at least one of a spin-on hard mask (SOH) material. The second mask pattern MK2 may fill the second hole H2. The interlayer insulating layer IL and the gate cap pattern GC of the second and third gate patterns GP2 and GP3 may be etched using the second mask pattern MK2 as an etching mask. Therefore, the third hole H3 and the fourth hole H4 may be formed to expose the gate electrode GE, respectively. During the formation of the third hole H3 and the fourth hole H4, the second mask pattern MK2 may protect the contact pad CP and the protection spacer LS.

[0052] Reference Fig. 7A , Figure 7B , Fig. 8A and Figure 8B , the second mask pattern MK2 may be removed to expose the second to fourth holes H2, H3, and H4. The removal of the second mask pattern MK2 may be performed by, for example, an ashing process in which oxygen is used.

[0053] Reference Fig. 8A , Figure 8B , Figure 1A and Figure 1B , a conductive layer may be formed on the substrate 1 to fill the second to fourth holes H2, H3, and H4. Thereafter, a CMP process may be performed to form source / drain contact plugs SCT, first gate contact plugs GCT1, and second gate contact plugs GCT2 in the second to fourth holes H2, H3, and H4, respectively. In some embodiments, the upper portion of the protection spacer LS and the upper portion of the interlayer insulating layer IL may also be removed during the CMP process.

[0054] If the protection spacer LS is not formed, during the formation of the conductive layer, the conductive layer may contact the gate electrode GE through the damaged upper portion of the gate spacer GS, thereby possibly forming a bridge between the source / drain contact plug SCT and the gate electrode GE. As the integration density of semiconductor devices increases, the width of the gate spacer GS decreases, thereby increasing the possibility of forming such a bridge.

[0055] In contrast, according to an embodiment, the protection spacer LS prevents the formation of such a bridge. In addition, when the protection spacer LS is formed at a specific desired area, for example, so as not to cover the entire top surface of the interlayer insulating layer IL, the manufacturing method can exhibit reduced process failures and improved yields, for example, because there is no need to change the process conditions to determine the etching stop point responsible for the entire top surface covered by the interlayer insulating layer IL.

[0056] Fig. 9A is a top view showing a semiconductor device according to an embodiment. Fig. 9B is along Fig. 9A Cross-sectional views taken along lines A-A', B-B' and CC'.

[0057] Reference Fig. 9A and Fig. 9B , the first auxiliary insulating pattern PL1 may be inserted between the inner sidewall of the first hole H1 and the protection spacer LS and between the inner sidewall of the first hole H1 and the contact pad CP. The first auxiliary insulating pattern PL1 may be formed of a material different from the protection spacer LS, or include a material different from the protection spacer LS. The first auxiliary insulating pattern PL1 may be formed of the same material as the gate spacer GS (e.g., silicon nitride), or include the same material as the gate spacer GS (e.g., silicon nitride). The first auxiliary insulating pattern PL1 may be used to strengthen a damaged portion of the gate spacer GS. The first auxiliary insulating pattern PL1 may be inserted between the protection spacer LS and the gate spacer GS and between the protection spacer LS and the interlayer insulating layer IL. When viewed in a top view, the first auxiliary insulating pattern PL1 may have a ring shape surrounding the protection spacer LS.

[0058] Fig.10 It shows the manufacturing Fig. 9A and Fig. 9B A cross-sectional view of a process of a semiconductor device.

[0059] Reference Fig.10 , an auxiliary insulating layer PL may be formed on the substrate 1 to conformally cover Figure 4B The auxiliary insulating layer PL may be used to reinforce a damaged portion of the gate spacer GS that may be formed during the process of forming the first hole H1. Figure 5B As shown, the contact pad CP may be formed and then Figure 6B As shown in FIG. 1 , a protection spacer LS may be formed. Here, the auxiliary insulating layer PL may also be etched to form a first auxiliary insulating pattern PL1. Figure 7B , Figure 8B and Figure 1B The subsequent processes are performed in the same manner as described.

[0060] Fig.11A is a top view showing a semiconductor device according to an embodiment. Fig. 11B is along Fig.11A Cross-sectional views taken along lines A-A', B-B' and CC'.

[0061] Reference Fig.11A and Fig. 11B , the second auxiliary insulating pattern PL2 may be interposed between the inner sidewall of the second hole H2 and the source / drain contact plug SCT. The second auxiliary insulating pattern PL2 may be formed of a material different from the protection spacer LS, or include a material different from the protection spacer LS. For example, the second auxiliary insulating pattern PL2 may be formed of at least one of silicon nitride, silicon oxide, and silicon oxynitride, or include at least one of silicon nitride, silicon oxide, and silicon oxynitride. The second auxiliary insulating pattern PL2 may be interposed between the protection spacer LS and the source / drain contact plug SCT. When viewed in a top view, the second auxiliary insulating pattern PL2 may have a ring shape surrounding the source / drain contact plug SCT.

[0062] Fig.12 It shows the manufacturing Fig.11A and Fig. 11B A cross-sectional view of a process of a semiconductor device.

[0063] Reference Fig.12 , in such Figure 6B After forming the protection spacer LS as shown, the auxiliary insulating layer PL may be conformally formed on the entire top surface of the substrate 1. Thereafter, an anisotropic etching process may be performed on the auxiliary insulating layer PL to form a second auxiliary insulating pattern PL2. Figure 7B , Figure 8B and Figure 1B The subsequent processes are performed in the same manner as described.

[0064] Fig.13A is a top view showing a semiconductor device according to an embodiment. Fig. 13B is along Fig.13A Cross-sectional views taken along lines A-A', B-B' and CC'.

[0065] Reference Fig.13A and Fig. 13B, the second auxiliary insulating pattern PL2 may be interposed between the inner sidewall of the second hole H2 and the source / drain contact plug SCT. In addition, the third auxiliary insulating pattern PL3 may be interposed between the inner sidewall of the third hole H3 and the first gate contact plug GCT1 and between the inner sidewall of the fourth hole H4 and the second gate contact plug GCT2. The third auxiliary insulating pattern PL3 may be interposed between the protection spacer LS and the first gate contact plug GCT1. The second auxiliary insulating pattern PL2 and the third auxiliary insulating pattern PL3 may be formed of a material different from that of the protection spacer LS, or include a material different from that of the protection spacer LS. The second auxiliary insulating pattern PL2 may be formed of the same material as that of the third auxiliary insulating pattern PL3, or include the same material as that of the third auxiliary insulating pattern PL3. The second auxiliary insulating pattern PL2 and the third auxiliary insulating pattern PL3 may be formed of, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride, or include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride. When viewed in a plan view, the second auxiliary insulating pattern PL2 may have a ring shape surrounding the source / drain contact plug SCT. When viewed in a plan view, the third auxiliary insulating pattern PL3 may have a ring shape surrounding the first and second gate contact plugs GCT1 and GCT2, respectively.

[0066] Fig.14 It shows the manufacturing Fig.13A and Fig. 13B A cross-sectional view of a process of a semiconductor device.

[0067] Reference Fig.14 , in such Figure 8B After exposing the second to fourth holes H2, H3, and H4 as shown and before forming the conductive layer, the auxiliary insulating layer PL may be conformally formed. Thereafter, an anisotropic etching process may be performed on the auxiliary insulating layer PL to form a second auxiliary insulating pattern PL2 and a third auxiliary insulating pattern PL3. Next, the auxiliary insulating layer PL may be formed in the same manner as in the reference pattern. Figure 1A and Figure 1B The conductive layer is formed in a manner that is the same as or similar to the described manner, and a CMP process may be performed on the conductive layer.

[0068] Under the condition of no contradiction, refer to FIG. 9A to FIG. 14 The described embodiments may be combined with each other in various forms. For example, the semiconductor device in the combined embodiment may be configured to include all of the first to third auxiliary insulating patterns PL1, PL2, and PL3, or to include only the first auxiliary insulating pattern PL1 and the second auxiliary insulating pattern PL2.

[0069] Fig.15 and Fig.161 and 2 are top views, each of which shows a semiconductor device according to an embodiment. The protection spacer LS may have a rectangular closed loop shape, such as Fig.15 Alternatively, the protection spacer LS may have a circular closed ring shape, such as Fig.16 shown.

[0070] As a summary and review, embodiments provide a semiconductor device with improved reliability and a method for manufacturing a semiconductor device with increased yield. That is, according to an embodiment, the semiconductor device may include a protection spacer that prevents a bridge pattern from being formed between gate electrodes and source / drain contact plugs adjacent to each other and reduces parasitic capacitance therebetween. In addition, a method for manufacturing a semiconductor device according to an embodiment may include forming a protection spacer, thereby reducing process failures and increasing yield. Therefore, the reliability of the semiconductor device may be improved.

[0071] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art upon filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0072] Korean Patent Application No. 10-2019-0103975, filed on August 23, 2019 in the Korean Intellectual Property Office and entitled “Semiconductor Device and Method of Manufacturing Semiconductor Device,” is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: A gate pattern spanning across the substrate, the gate pattern comprising a gate insulating layer, a gate electrode and a gate cap pattern sequentially stacked on the substrate; a gate spacer covering a sidewall of the gate pattern; a source / drain pattern on the substrate, the source / drain pattern being adjacent to the sidewall of the gate pattern; a contact pad on the source / drain pattern and in direct contact with a side surface of the gate spacer, wherein a top surface of the contact pad is lower than a top surface of the gate electrode; source / drain contact plugs on the contact pads; as well as a protection spacer between the gate spacer and the source / drain contact plug and in direct contact with each of the gate spacer and the source / drain contact plug, the protection spacer overlapping with a top of the gate spacer and a top of the gate cap pattern, the protection spacer having a ring shape surrounding the source / drain contact plug, wherein the protection spacer is in direct contact with the side surface and the top of the gate spacer, and The first width of the protection spacer is greater than the second width of the gate spacer, the first width of the protection spacer is the maximum width of the protection spacer measured along a first direction above the gate pattern, and the second width of the gate spacer is the maximum width of the gate spacer measured at the bottom of the gate spacer along the first direction starting from the sidewall of the gate pattern, and the first direction is perpendicular to the sidewall of the gate pattern. 2 . The semiconductor device according to claim 1 , wherein the protection spacer has a dielectric constant lower than a dielectric constant of the gate spacer. 3 . The semiconductor device according to claim 1 , wherein a sidewall of the protection spacer that does not overlap the gate pattern and the gate spacer is aligned with a sidewall of the contact pad in a direction in which the gate pattern extends. 4 . The semiconductor device according to claim 1 , wherein the protection spacer surrounds the entire outer sidewall of the source / drain contact plug. 5 . The semiconductor device according to claim 1 , wherein a width of the source / drain contact plug is smaller than a width of the contact pad. 6 . The semiconductor device of claim 1 , wherein the source / drain pattern has an inclined upper side, and the contact pad is in contact with the inclined upper side. 7 . The semiconductor device according to claim 1 , wherein the protection spacer comprises a first protection spacer and a second protection spacer having different materials from each other, the first protection spacer contacts the source / drain contact plug, and the second protection spacer contacts the gate spacer.

8. The semiconductor device according to claim 1, further comprising a channel pattern, the channel pattern comprising a first semiconductor pattern and a second semiconductor pattern sequentially stacked on the substrate, The gate electrode covers a top surface and a side surface of the channel pattern and includes a first gate portion between the first semiconductor pattern and the second semiconductor pattern. 9 . The semiconductor device according to claim 1 , wherein the source / drain contact plug surrounded by the protection spacer is a single source / drain contact plug, and the source / drain contact plug and the protection spacer have a one-to-one correspondence. 10 . The semiconductor device of claim 1 , wherein the protection spacer continuously extends toward the gate capping pattern to only partially cover the top of the gate capping pattern.

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