Semiconductor Device and Method of Forming the Same

Abstract

In some embodiments of the method, patterning the opening includes: projecting a radiation beam onto a second dielectric layer, the radiation beam having a pattern of the opening. In some embodiments of the method, the single patterning lithography process is an extreme ultraviolet (EUV) lithography process. In some embodiments of the method, filling the opening with a conductive material includes: plating the conductive material in the opening; and planarizing the conductive material and the second dielectric layer to form a first metal line from the remaining portion of the conductive material, after planarization, the top surfaces of the first metal line and the second dielectric layer are flat. Embodiments of the present invention also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of forming the same. Background Art

[0002] Typically, active devices and passive devices are formed on and within a semiconductor substrate. Once formed, these active and passive devices can be interconnected with each other and to external devices using a series of conductive and insulating layers. These layers can assist in interconnecting a variety of active and passive devices and providing electrical connections to external devices through, for example, contact pads.

[0003] To form these interconnections within these layers, a series of lithography, etching, deposition, and planarization techniques can be employed. However, as the sizes of active and passive devices have decreased, the use of such techniques has become more complex, resulting in a need to also reduce the size of the interconnects. Accordingly, there is a need to improve the formation and structure of the interconnects in order to make the overall device smaller, cheaper, and more efficient, while having fewer defects or problems. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device, comprising: a substrate having a first p-type well region, a second p-type well region, and an n-type well region disposed between the first p-type well region and the second p-type well region; a first pull-up transistor located in the n-type well region, the first pull-up transistor including a first source / drain region; a second pull-up transistor located in the n-type well region, the second pull-up transistor including a second source / drain region; and a first conductive member electrically connected to a power supply voltage node, the first conductive member having a main portion, a first pad portion extending from a first side of the main portion, and a second pad portion extending from a second side of the main portion, the first pad portion being located above the first source / drain region of the first pull-up transistor and electrically connected to the first source / drain region of the first pull-up transistor, the second pad portion being located above the second source / drain region of the second pull-up transistor and electrically connected to the second source / drain region of the second pull-up transistor, each of the first pad portion and the second pad portion having a first width, and the main portion having a second width, the first width being less than the second width.

[0005] Another embodiment of the present invention provides a semiconductor device, comprising: a substrate having a first p-type well region, a second p-type well region, and an n-type well region disposed between the first p-type well region and the second p-type well region; a first pull-up transistor located in the n-type well region, the first pull-up transistor including a first source / drain region; a first pull-down transistor located in the first p-type well region, the first pull-down transistor including a second source / drain region; a first via electrically connected to the first source / drain region of the first pull-up transistor, the first via having a first width; and a second via electrically connected to the second source / drain region of the first pull-down transistor, the second via having a second width, the first width being greater than the second width, and each of the first width and the second width being measured along the same direction,

[0006] wherein the first via and the second via are spaced apart by a first distance, the first distance being in the range of 70 nm to 90 nm.

[0007] Yet another embodiment of the present invention provides a method of forming a semiconductor device, comprising: forming a first fin extending from an n-type well region of a substrate; growing a first source / drain region in the first fin; forming a second fin extending from the n-type well region of the substrate; growing a second source / drain region in the second fin; depositing a first dielectric layer over the first source / drain region and the second source / drain region; forming a first via through the first dielectric layer to electrically couple the first source / drain region, the first via having a width in the range of 15 nm to 20 nm; forming a second via through the first dielectric layer to electrically couple the second source / drain region, the second via having a width in the range of 15 nm to 20 nm; depositing a second dielectric layer over the first dielectric layer, the first via, and the second via; patterning an opening in the second dielectric layer using a single patterning lithography process, the opening having a main portion, a first protruding portion extending from a first side of the main portion, and a second protruding portion extending from a second side of the main portion, the first protruding portion and the main portion of the opening exposing the first via, and the second protruding portion and the main portion of the opening exposing the second via; and filling the opening with a conductive material to form a first metal wire physically and electrically coupled to the first via and the second via. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present invention are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0009] Figure 1 is a block diagram of a memory according to some embodiments.

[0010] Figure 2 is a circuit diagram of a memory cell according to some embodiments.

[0011] Figure 3 Shows an example of a simplified fin field-effect transistor (FinFET) in a three-dimensional view according to some embodiments.

[0012] Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9A and Figure 9B Are various views of intermediate stages in the fabrication of a memory cell according to some embodiments.

[0013] Figure 10 Shows a schematic diagram of a metal wire according to some embodiments.

[0014] Figure 11 Shows a simplified three-dimensional view of a memory according to some embodiments.

[0015] Figure 12 Shows a schematic diagram of a memory according to some embodiments. Detailed Description

[0016] The following disclosure provides many different embodiments or examples for implementing different components of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, spatially relative terms (such as "below", "beneath", "under", "above", "upper", etc.) may be used herein to facilitate describing the relationship of one element or component shown in the figures to another (some) element or component. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0018] According to some embodiments, metal wires for memory cells are formed to interconnect the transistors of the memory cells. The memory cells can be, for example, static random access memory (SRAM) cells. The metal wires are formed by using next-generation lithography techniques (e.g., extreme ultraviolet (EUV) lithography). Thus, metal wires of arbitrary shapes and very small sizes can be formed. Advantageously, the metal wires can be formed to have a main line portion and a pad portion. The pad portion is wider than the main line portion and can be used to couple to the underlying conductive vias. The contact area with the underlying conductive vias is larger, which can reduce the resistivity of the contacts.

[0019] Figure 1 FIG. 4 is a block diagram of a memory 50 according to some embodiments. The memory 50 includes a memory cell array 52, a row decoder 54, a read / write circuit 56, and a column decoder 58. The memory cell array 52 includes memory cells 60 arranged in rows and columns. The row decoder 54 can be, for example, a static CMOS decoder, a pseudo-NMOS decoder, etc. During operation, the row decoder 54 selects a desired memory cell 60 in a row of the memory cell array 52 by activating the corresponding word line WL for the row. The read / write circuit 56 can include a writer driver, a sense amplifier, combinations thereof, etc. During operation, the read / write circuit 56 reads data from or writes data to a desired memory cell 60 in the memory cell array 52 by using complementary bit lines BL and BLB. The column decoder 58 can be, for example, a static CMOS decoder, a pseudo-NMOS decoder, etc. During operation, the column decoder 58 selects complementary bit lines BL and BLB for a desired memory cell 60 in a column of the memory cell array 52.

[0020] Figure 2 FIG. 8 is a circuit diagram of a memory cell 60 according to some embodiments. The memory cell 60 is a six-transistor SRAM cell. The memory cell 60 includes pull-up transistors PU1 and PU2 and pull-down transistors PD1 and PD2, which together store one bit. The pull-up transistors PU1 and PU2 are connected to a power supply voltage node V dd , and the pull-down transistors PD1 and PD2 are connected to a ground voltage node V ss . The memory cell 60 further includes transmission gate transistors PG1 and PG2, which are connected to the word line WL for the memory cell 60 and the complementary bit lines BL and BLB. When the transmission gate transistors PG1 and PG2 are enabled, the value of the memory cell 60 can be read by using the complementary bit lines BL and BLB, and a new value can be written to the memory cell 60 by using the complementary bit lines BL and BLB.

[0021] Figure 3Shows an example of a simplified fin field-effect transistor (FinFET) in a three-dimensional view according to some embodiments. For clarity, some other components of the FinFET (discussed below) are omitted. The illustrated FinFET can be electrically connected or coupled in a manner such as one or more transistors (e.g., four transistors) operate. As further discussed below, memory cell 60 (see Figure 1 and Figure 2 ) can be implemented using FinFETs (e.g., the FinFET shown in Figure 3 ).

[0022] The FinFET includes fins 72 extending from a substrate 70. Shallow trench isolation (STI) regions 74 are disposed above the substrate 70, and the fins 72 protrude above adjacent STI regions 74 and protrude from between adjacent STI regions 74. Additionally, although the fins 72 are shown as a single continuous material of the substrate 70, the fins 72 and / or the substrate 70 can include a single material or multiple materials. In context, the fins 72 refer to the portions extending between adjacent STI regions 74.

[0023] The substrate 70 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 70 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, such as a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate (usually a silicon or glass substrate). Other substrates can also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate 70 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. For example, when forming a p-type device, the substrate 70 can be a strained material, such as silicon germanium (Si x Ge 1-x , where x can range from 0 to 1), such that a FinFET with a p-type fully strained channel (PFSC) region is formed.

[0024] The fins 72 are semiconductor strips. In some embodiments, the fins 72 can be formed in the substrate 70 by etching trenches in the substrate 70, where the remaining material of the substrate 70 between the trenches forms the fins 72. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. The etching process can be anisotropic.

[0025] The STI region 74 is formed of an insulating material. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (material deposition based on chemical vapor deposition (CVD) in a remote plasma system and cured to convert it into another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by the FCVD process. In some embodiments, a liner (not shown) can be first formed along the surfaces of the substrate 70 and the fins 72, and a filling material (e.g., the above-mentioned insulating material) can be formed on the liner. A removal process is applied to the insulating material to expose the fins 72. In some embodiments, a planarization process (e.g., chemical mechanical polishing (CMP), etch-back process, a combination thereof, etc.) can be utilized to expose the fins, where a portion of the insulating material is retained after the planarization process for forming the STI region 74.

[0026] The above process is only an example of how the fins 72 can be formed. Any acceptable process can be utilized to form the fins 72 and the STI region 74. For example, in another embodiment, the fins 72 can be formed by an epitaxial growth process.

[0027] The gate spacers 76 are along the sidewalls of the fins 72 and above the top surfaces of the fins 72. The gate stack 78 is disposed between adjacent pairs of gate spacers 76. The gate stack 78 includes a gate dielectric 79 on the fins 72 and the STI region 74, and a gate electrode 80 above the gate dielectric 79. The source / drain regions 82 are epitaxial growth regions above the fins 72 on opposite sides of the gate dielectric 79 and the gate electrode 80. The gate spacers 76 separate the source / drain regions 82 from the gate dielectric 79 and the gate electrode 80. In embodiments where multiple transistors are formed, the source / drain regions 82 can be shared among the individual transistors. In an embodiment where a single transistor is formed of multiple fins 72, adjacent source / drain regions 82 can be electrically connected, e.g., by merging the source / drain regions 82 via epitaxial growth, or by coupling the source / drain regions 82 to the same source / drain contact.

[0028] The gate dielectric 79 and the gate electrode 80 can be formed using a front-gate process or a back-gate process. When using the front-gate process, the gate dielectric 79 and the gate electrode 80 are first formed over the channel region of the fin 72, and then the gate spacers 76 are deposited along the sidewalls of the gate dielectric 79 and the gate electrode 80. When using the back-gate process, a dummy gate stack is first formed over the channel region of the fin 72, the gate spacers 76 are deposited along the sidewalls of the dummy gate stack, and then the dummy gate stack is replaced with the gate dielectric 79 and the gate electrode 80.

[0029] The gate spacers 76 can be formed of a dielectric material (e.g., silicon nitride, silicon carbonitride, combinations thereof, etc.). In some embodiments (not shown), the gate spacers 76 are formed of a multi-layer insulating material and include multiple layers. For example, the gate spacers 76 can include multiple layers of silicon nitride, or can include a silicon oxide layer disposed between two layers of silicon nitride.

[0030] The gate dielectric 79 can be formed of a dielectric material (e.g., silicon oxide, silicon nitride, or multi-layers thereof). In some embodiments, the gate dielectric 79 includes a high-k dielectric material, and in these embodiments, the gate dielectric 79 can have a k value greater than about 7.0, and can include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The method of forming the gate dielectric 79 can include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. The gate electrode 80 is deposited separately over the gate dielectric 79. The gate electrode 80 can include a metal-containing material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multi-layers thereof. For example, although a single-layer gate electrode 80 is shown, the gate electrode 80 can include any number of liner layers, any number of work function adjustment layers, and fill materials. After filling the gate electrode 80, a planarization process (e.g., CMP) can be performed to remove the excess portions of the gate dielectric 79 and the gate electrode 80 located above the gate spacers 76.

[0031] The source / drain regions 82 can be formed by an epitaxial growth process. In such an embodiment, a recess is formed in the fin 72 adjacent to the gate spacer 76. One or more epitaxial processes are performed to grow the source / drain regions 82 in the recess. The source / drain regions 82 can be formed of any acceptable material for p-type or n-type devices. For example, when an n-type device is desired, the source / drain regions 82 can include a material that applies tensile strain in the channel region of the fin 72, such as silicon, SiC, SiCP, SiP, etc. Similarly, when a p-type device is desired, the source / drain regions 82 can include a material that applies compressive strain in the channel region of the fin 72, such as SiGe, SiGeB, Ge, GeSn, etc. The source / drain regions 82 are doped with n-type and / or p-type impurities and can be doped in-situ during growth or can be implanted with dopants after growth.

[0032] Figures 4A to 9B are various views of an intermediate stage in the fabrication of a memory cell 60 according to some embodiments. A memory cell 60 is fabricated using a FinFET similar to the one shown in Figure 3 . The fabrication of the interconnects for the FinFET is shown, where the resulting structure interconnects the FinFETs to form the memory cell 60. Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A are schematic diagrams of the memory cell 60. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B are cross-sectional views of the memory cell 60 taken along reference section B-B in Figure 4A . The cross-section B-B extends through the source / drain regions 82 of the FinFET.

[0033] In Figure 4A and Figure 4B , the fins 72 are formed on the substrate 70. The STI regions 74 are formed such that the fins 72 are separated. The gate stack 78 is formed over the channel region of the fins 72. The source / drain regions 82 are formed in the fins 72, adjacent to the gate stack 78. Although the gate spacers 76 are not shown in Figure 4A , it should be understood that the gate spacers 76 are provided between the gate stack 78 and the source / drain regions 82. Additionally, it should be understood that some components are omitted for clarity of illustration. For example, dummy gate stacks can be formed on the ends of the fins 72.

[0034] Six transistors are formed for forming a memory cell 60. The formed transistors include pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, and transfer gate transistors PG1 and PG2. The first pull-up transistor PU1 includes a first gate stack 78A located above a first channel region, a first source / drain region 82A, and a second source / drain region 82B. The second pull-up transistor PU2 includes a second gate stack 78B located above a second channel region, a third source / drain region 82C, and a fourth source / drain region 82D. The first pull-down transistor PD1 includes a first gate stack 78A located above a third channel region, a fifth source / drain region 82E, and a sixth source / drain region 82F. The second pull-down transistor PD2 includes a second gate stack 78B located above a fourth channel region, a seventh source / drain region 82G, and an eighth source / drain region 82H. The first transfer gate transistor PG1 includes a third gate stack 78C located above a fifth channel region, a sixth source / drain region 82F, and a ninth source / drain region 82I. The second transfer gate transistor PG2 includes a fourth gate stack 78D located above a sixth channel region, a tenth source / drain region 82J, and a seventh source / drain region 82G.

[0035] Four fins 72 are formed for forming six transistors. The first fin 72A is used for forming the first pull-up transistor PU1. The second fin 72B is used for forming the second pull-up transistor PU2. The third fin 72C is used for forming the first pull-down transistor PD1 and the first transfer gate transistor PG1. The fourth fin 72D is used for forming the second pull-down transistor PD2 and the second transfer gate transistor PG2. Since the pull-up transistors PU1 and PU2 are p-type devices, the fins 72A and 72B are formed in the n-type well region of the substrate 70. Similarly, since the pull-down transistors PD1 and PD2 and the transfer gate transistors PG1 and PG2 are n-type devices, the fins 72C and 72D are formed in the p-type well region of the substrate 70. The n-type well region is disposed between the p-type well regions.

[0036] In Figure 5A and Figure 5B a dielectric layer 84 is formed above the source / drain regions 82 and the STI regions 74. The dielectric layer 84 is shown as a transparent layer in Figure 5A to better show the components located below the dielectric layer 84, such as the fins 72. The dielectric layer 84 may also be referred to as an interlayer dielectric (ILD) layer. The dielectric layer 84 can be formed of any desired dielectric material and can be deposited by any suitable method (e.g., CVD, plasma enhanced CVD (PECVD), or FCVD). The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0037] Then, source / drain contact 86 is formed through dielectric layer 84 to physically and electrically couple source / drain region 82. An opening for source / drain contact 86 is formed to pass through dielectric layer 84. Acceptable lithography and etching techniques can be used to form the opening. A liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process (e.g., CMP) can be performed to remove excess material from the surface of dielectric layer 84. The remaining liner and conductive material form source / drain contact 86 in the opening. An annealing process can be performed to form a silicide (not shown) at the interface between source / drain region 82 and source / drain contact 86.

[0038] Some of source / drain contacts 86 span multiple source / drain regions 82, thereby physically and electrically coupling the source / drain regions 82 of corresponding transistors. Some of source / drain contacts 86 physically and electrically couple a single source / drain region 82. First source / drain contact 86A is coupled to first source / drain region 82A. Second source / drain contact 86B is coupled to second source / drain region 82B and sixth source / drain region 82F. Third source / drain contact 86C is coupled to third source / drain region 82C. Fourth source / drain contact 86D is coupled to fourth source / drain region 82D and seventh source / drain region 82G. Fifth source / drain contact 86E is coupled to fifth source / drain region 82E. Sixth source / drain contact 86F is coupled to eighth source / drain region 82H. Seventh source / drain contact 86G is coupled to ninth source / drain region 82I. Eighth source / drain contact 86H is coupled to tenth source / drain region 82J.

[0039] At Figure 6A and Figure 6B In, dielectric layer 88 is deposited over dielectric layer 84 and source / drain contacts 86. Dielectric layer 88 is shown as a transparent layer in Figure 6A to better show the components below dielectric layer 88, such as fin 72. Dielectric layer 88 can also be referred to as an ILD layer. In some embodiments, dielectric layer 88 is a flowable film formed by a flowable CVD method. In some embodiments, dielectric layer 88 is formed of materials such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method (e.g., CVD and PECVD).

[0040] Then, a conductive via 90 is formed through the dielectric layer 88 to couple the source / drain contact 86 and the gate stack 78. An opening for the conductive via 90 is formed to pass through the dielectric layer 88. As an example of forming the opening, a photoresist can be formed over the dielectric layer 88. The photoresist can be patterned using a pattern corresponding to the conductive via 90. The patterning of the photoresist can be accomplished by using next-generation lithography techniques (e.g., extreme ultraviolet (EUV) lithography, deep ultraviolet (DUV) lithography, X-ray lithography, soft X-ray (SX) lithography, ion beam projection lithography, electron beam projection lithography, etc.). In one embodiment, the etching process is accomplished by EUV lithography. EUV lithography is performed by generating electromagnetic radiation in an atmosphere of H 2 plasma to produce an incident radiation beam having a desired range of wavelengths. The electromagnetic radiation can be generated using a plasma source (e.g., xenon, oxygen, lithium, combinations thereof, etc.). A mask having the pattern of the conductive via 90 patterns the incident radiation beam to the pattern formed in the photoresist. The mask can be a transmissive mask, a reflective mask (sometimes referred to as a “reticle”), an optical proximity correction (OPC) mask, etc. Then, an optic such as a projection optical box (POB) is used to collect the patterned radiation beam, magnify or demagnify the patterned radiation beam, and then project the patterned radiation beam onto the photoresist, thereby patterning the photoresist with the pattern of the opening of the conductive via 90. Then, an etching process (e.g., dry or wet etching) can be performed to transfer the pattern of the photoresist to the dielectric layer 88. A diffusion barrier layer can be formed of TaN, Ta, TiN, Ti, CoW, etc., and the diffusion barrier layer can be formed in the opening of the dielectric layer 88 by a deposition process (e.g., ALD, etc.). Then, a conductive material (e.g., copper, aluminum, tungsten, silver, and combinations thereof, etc.) is formed over the diffusion barrier layer in the opening of the dielectric layer 88. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, etc., or a combination thereof. In one embodiment, the conductive material is copper, and the diffusion barrier layer is a thin barrier layer that prevents copper from diffusing into the dielectric layer 88. After forming the diffusion barrier layer and the conductive material, excess conductive material and material of the diffusion barrier layer can be removed from the dielectric layer 88 by a planarization process (e.g., CMP, etc.).

[0041] The conductive vias 90 include vias physically and electrically coupled to the gate stack 78, vias physically and electrically coupled to the source / drain contact 86, and vias physically and electrically coupled to both the gate stack 78 and the source / drain contact 86 (e.g., shared vias), which are used to cross-couple the inverters formed by the transistors PU1, PD1, PU2, and PD2. The first gate via 90A is coupled to the third gate stack 78C, and the second gate via 90B is coupled to the fourth gate stack 78D. The first source / drain via 90C is coupled to the first source / drain contact 86A, the second source / drain via 90D is coupled to the third source / drain contact 86C, the third source / drain via 90E is coupled to the fifth source / drain contact 86E, the fourth source / drain via 90F is coupled to the sixth source / drain contact 86F, the fifth source / drain via 90G is coupled to the seventh source / drain contact 86G, and the sixth source / drain via 90H is coupled to the eighth source / drain contact 86H. The first shared via 90I is coupled to the first gate stack 78A and the fourth source / drain contact 86D, and the second shared via 90J is coupled to the second gate stack 78B and the second source / drain contact 86B.

[0042] The conductive vias 90 are formed with different widths. As Figure 5A shown, the first source / drain region 82A and the third source / drain region 82C are not aligned along a common longitudinal axis. Instead, the fins 72A and 72B have laterally offset longitudinal axes, and thus the first source / drain region 82A and the third source / drain region 82C are also laterally offset. In other words, the fins 72A and 72B have parallel longitudinal axes such that the longitudinal axes do not overlap. However, as discussed further below, the first source / drain region 82A and the third source / drain region 82C will both be coupled to the upper power supply voltage V dd line (see Figure 7A and Figure 7B ) to form the memory cell 60. To achieve contact with the power supply voltage V dd line, the first source / drain via 90C and the second source / drain via 90D are formed near the edge regions of the first source / drain contact 86A and the third source / drain contact 86C, respectively. In addition, the first source / drain via 90C and the second source / drain via 90D are formed with a greater width than the other conductive vias in the conductive vias 90. Since the conductive vias 90 are formed by using next-generation lithography technology, they can be formed with a small width. For example, the first source / drain via 90C and the second source / drain via 90D are formed with a first width W 1 , e.g., a first width W in the range of about 15 nm to about 20 nm 1, and other conductive vias 90A / 90B / 90E / 90F / 90G / 90H / 90I / 90J are formed to a second width W 2 , for example, a second width W in the range of about 10 nm to about 15 nm 2 . The width W 1 and W 2 are measured along a direction perpendicular to the longitudinal axis of the fin 72. The first width W 1 is greater than the second width W 2 . As a result, the first source / drain via 90C and the second source / drain via 90D can have a rectangular shape or an oval shape, and the other conductive vias 90A / 90B / 90E / 90F / 90G / 90H / 90I / 90J can have a square shape or a circular shape. Forming the first source / drain via 90C and the second source / drain via 90D to a large width W 1 , even when the first source / drain via 90C and the second source / drain via 90D are respectively formed near the edge regions of the first source / drain contact 86A and the third source / drain contact 86C, allows increasing the contact areas of the first source / drain via 90C and the second source / drain via 90D. Therefore, the contact resistance to the upper power supply voltage V dd line can be reduced, thereby increasing the pull-up current for the pull-up transistors PU1 and PU2, and thus improving the performance of the memory cell 60. In addition, the landing areas of the first source / drain contact 86A and the third source / drain contact 86C can be increased, thereby increasing the process window for the memory cell 60.

[0043] Because the conductive vias 90 are formed by using next-generation lithography technology, they can be formed to be spaced apart by a small distance, as Figure 6B shown. For example, the second source / drain via 90D can be spaced apart from the fourth source / drain via 90F by a first distance D 1 , for example, a first distance D in the range of about 70 nm to about 90 nm 1 . Similarly, the second source / drain via 90D can be spaced apart from the fifth source / drain via 90G by a second distance D 2 , for example, a second distance D in the range of about 45 nm to about 65 nm 2 . Although not shown in Figure 6B , the first source / drain via 90C and the sixth source / drain via 90H can also be spaced apart by the first distance D 1 , and the first source / drain via 90C and the third source / drain via 90E can also be spaced apart by the second distance D 2 . The small distance between the conductive vias 90 allows a greater density of memory cells 60.

[0044] In Figure 7A and Figure 7B , a dielectric layer 92 is deposited over the dielectric layer 88 and the conductive via 90. In Figure 7A , the dielectric layer 92 is shown as a transparent layer to better show components located below the dielectric layer 92, such as the fin 72. The dielectric layer 92 may be referred to as an inter-metal dielectric (IMD) layer. The dielectric layer 92 may be a layer formed of a low-k dielectric material having a k-value of less than about 3.0. The dielectric layer 92 may be a layer formed of an ultra-low-k (ELK) dielectric material having a k-value of less than 2.5. In some embodiments, the dielectric layer 92 may be formed of black diamond (a registered trademark of Applied Materials), a low-k dielectric material containing oxygen and / or carbon, hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), etc. In some embodiments, the dielectric layer 92 is formed of a porous material (e.g., SiOCN, SiCN, SiOC, SiOCH, etc.) and may be formed by initially forming a precursor layer including a pore former and then removing the pore former to form pores within the dielectric layer 92.

[0045] Then, a conductive component 94 is formed through the dielectric layer 92 to couple the conductive via 90. An opening is formed in the dielectric layer 92 using, for example, an etching process. As an example of forming the opening, a photoresist may be formed over the dielectric layer 92. The photoresist may be patterned using a pattern corresponding to the conductive component 94. The patterning of the photoresist may be accomplished by using next-generation lithography techniques (e.g., extreme ultraviolet (EUV) lithography, deep ultraviolet (DUV) lithography, X-ray lithography, soft X-ray (SX) lithography, ion beam projection lithography, electron beam projection lithography, etc.). In one embodiment, the etching process is accomplished by EUV lithography. By in H 2Electromagnetic radiation is generated in a plasma atmosphere to perform EUV lithography to produce an incident radiation beam having a desired range of wavelengths. The electromagnetic radiation can be generated using a plasma source (e.g., xenon, oxygen, lithium, combinations thereof, etc.). A mask having a pattern of conductive components 94 patterns the incident radiation beam against a pattern formed in a photoresist. The mask can be a transmissive mask, a reflective mask (sometimes referred to as a "reticle"), an optical proximity correction (OPC) mask, etc. Then, an optical device such as a projection optical box (POB) is used to collect the patterned radiation beam, magnify or reduce the patterned radiation beam, and then project the patterned radiation beam onto the photoresist, thereby patterning the photoresist with the pattern of the openings of the conductive components 94. Then, an etching process (e.g., dry or wet etching) can be performed to transfer the pattern of the photoresist to the dielectric layer 92. A diffusion barrier layer can be formed of TaN, Ta, TiN, Ti, CoW, etc., and the diffusion barrier layer can be formed in the openings of the dielectric layer 92 by a deposition process (e.g., ALD, etc.). Then, a conductive material (e.g., copper, aluminum, tungsten, silver, and combinations thereof, etc.) is formed above the diffusion barrier layer in the openings of the dielectric layer 92. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, etc., or a combination thereof. In one embodiment, the conductive material is copper and the diffusion barrier layer is a thin barrier layer that prevents copper from diffusing into the dielectric layer 92. After forming the diffusion barrier layer and the conductive material, excess conductive material and material of the diffusion barrier layer can be removed from the dielectric layer 92 by a planarization process (e.g., CMP).

[0046] Because the conductive components 94 are formed using next-generation lithography techniques, they can be formed to be spaced apart by a small distance, as Figure 7A shown. For example, the conductive components 94 can be spaced apart by a third distance D 3 , e.g., a third distance D in the range of about 35 nm to about 55 nm 3 . The small distance between the conductive components 94 allows for a greater density of memory cells 60.

[0047] The conductive components 94 include metal pads and metal lines that are physically and electrically coupled to conductive vias 90. A first metal pad 94A is coupled to a first gate via 90A, and a second metal pad 94B is coupled to a second gate via 90B. The first metal pad 94A and the second metal pad 94B will be coupled to the word line WL for the memory cell 60 above (see Figure 9A and Figure 9B ). A third metal pad 94C is coupled to a third source / drain via 90E and a fourth metal pad 90D is coupled to a fourth source / drain via 90F. The third metal pad 94C and the fourth metal pad 94D will be coupled to the voltage V above for the memory cell 60 ssLine (see Figure 9A and Figure 9B ). The first metal line 94E is coupled to the fifth source / drain via 90G, and the second metal line 94F is coupled to the sixth source / drain via 90H. The first metal line 94E is the bit line BL for the memory cell 60 (see Figure 2 ), and the second metal line 94F is the complementary bit line BLB for the memory cell 60 (see Figure 2 ), and both will be coupled (discussed further below) to the column decoder 58 and the read / write circuit 56. The third metal line 94G is coupled to the first source / drain via 90C and the second source / drain via 90D. The third metal line 94G is the power supply voltage V dd line for the memory cell 60 (see Figure 2 ). The first metal line 94E, the second metal line 94F, and the third metal line 94G extend through one or more memory cells 60 in a column of the memory cell array 52 (see Figure 1 ).

[0048] Figure 7C is a detailed view of the third metal line 94G (e.g., the power supply voltage V dd line), showing additional components. As described above, the etching process for forming the third metal line 94G can be accomplished by EUV lithography. EUV lithography allows the dielectric layer 92 to be patterned by a single patterning lithography process rather than by a multiple patterning lithography process with immersion lithography. Thus, the conductive component 94, and in particular the third metal line 94G, can have an arbitrary shape and very small dimensions. For example, the third metal line 94G can be formed in a shape other than a straight line. In particular, the third metal line 94G is formed to include a main portion 96A and pad portions 96B. The main portion 96A has a longitudinal axis parallel to the longitudinal axes of the fins 72A and 72B. Further, in the schematic diagram, the main portion 96A is disposed laterally between the fins 72A and 72B. Each of the pad portions 96B is an extension of the main portion 96A (e.g., a protrusion extending from the main portion 96A), and each memory cell 60 includes a pair of pad portions 96B extending from opposite sides of the main portion 96A. As described above, the third metal line 94G (e.g., the power supply voltage V ddThe (line) is formed to couple the first source / drain region 82A and the third source / drain region 82C, and the first source / drain region 82A and the third source / drain region 82C are not aligned along a common longitudinal axis. The pad portion 96B is located above the first source / drain via 90C and the second source / drain via 90D, and physically and electrically couples the first source / drain via 90C and the second source / drain via 90D, thereby allowing the third metal line 94G to couple the first source / drain region 82A and the third source / drain region 82C even when the first source / drain region 82A and the third source / drain region 82C are not aligned along a common longitudinal axis. Some portions of the first source / drain via 90C and the second source / drain via 90D may also physically and electrically couple the main portion 96A, but most of the first source / drain via 90C and the second source / drain via 90D physically and electrically couple the pad portion 96B. Thus, although the main portion 96A may not cover the first source / drain via 90C and the second source / drain via 90D, the pad portion 96B allows the third metal line 94G to cover the first source / drain via 90C and the second source / drain via 90D. In addition, forming the conductive component 94 by EUV lithography allows the conductive component 94 to be formed with a very small width. For example, the main portion 96A of the third metal line 94G may have a third width W in the range of about 10 nm to about 18 nm 3 , and the pad portion 96B of the third metal line 94G may have a fourth width W in the range of about 5 nm to about 15 nm 4 . The third width W 3 and the fourth width W 4 can both be less than the first width W 1 . In addition, the third width W 3 can be greater than the fourth width W 4 .

[0049] In Figure 8A and Figure 8B , a dielectric layer 98 is deposited over the dielectric layer 92 and the conductive component 94. In Figure 8AIn [the figure], the dielectric layer 98 is shown as a transparent layer to better show the components located below the dielectric layer 98, such as the fin 72. The dielectric layer 98 can be referred to as an IMD layer. The dielectric layer 98 can be formed in a similar manner and with similar materials as the dielectric layer 92. Then, conductive vias 100 are formed through the dielectric layer 98 to physically and electrically couple the conductive components 94. The conductive vias 100 can be formed in a similar manner and with similar materials as the conductive vias 90. The first conductive via 100A is coupled to the first metal pad 94A, and the second conductive via 100B is coupled to the second metal pad 94B. The first conductive via 100A and the second conductive via 100B will be coupled to the word line WL for the memory cell 60 above (see Figure 9A and Figure 9B ). The third conductive via 100C is coupled to the third metal pad 94C, and the fourth conductive via 100D is coupled to the fourth metal pad 94D. The third conductive via 100C and the fourth conductive via 100D will be coupled to the voltage V ss line for the memory cell 60 above (see Figure 9A and Figure 9B ).

[0050] In Figure 9A and Figure 9B , a dielectric layer 102 is deposited above the dielectric layer 98. In Figure 9A , the dielectric layer 102 is shown as a transparent layer to better show the components located below the dielectric layer 102, such as the fin 72. The dielectric layer 102 can be referred to as an IMD layer. The dielectric layer 102 can be formed in a similar manner and with similar materials as the dielectric layer 92. Then, conductive components 104 are formed through the dielectric layer 102 to couple the conductive vias 100. The conductive components 104 can be formed in a similar manner and with similar materials as the conductive components 94. The conductive components 104 include metal lines that are physically and electrically coupled to the wire vias 100. The first metal line 104A and the second metal line 104B are respectively coupled to the first metal pad 94A and the second metal pad 94B. Each of the first metal line 104A and the second metal line 104B is a word line WL for the memory cell 60 (see Figure 2 ) and is coupled to the row decoder 54. The third metal line 104C and the fourth metal line 104D are respectively coupled to the third metal pad 94C and the fourth metal pad 94D. Each of the third metal line 104C and the fourth metal line 104D is a ground voltage V ss line for the memory cell 60 (see Figure 2 ).

[0051] Although the process for forming the memory cell 60 is described as a single damascene process, it should be understood that other processes may be used and, depending on the process used, some layers may be replicated or omitted. For example, other damascene processes, such as dual damascene processes, may also be used. When a dual damascene process is used, the dielectric layers 88 and 92 may be a single dielectric layer, and the conductive vias 90 and the conductive members 94 may be formed in a single sputtering process to pass through the single dielectric layer. Similarly, the dielectric layers 98 and 102 may also be a single dielectric layer, and the conductive vias 100 and the conductive members 104 may be formed in a single sputtering process to pass through the single dielectric layer. In addition, it should be understood that some layers are omitted for clarity. For example, one or more etch stop layers (ESLs) may be formed between each of the dielectric layers 84, 88, 92, 98, and 102.

[0052] As described above, the etching process for forming the conductive member 94 may be accomplished by EUV lithography, allowing the conductive member 94 to be formed in any shape and with very small dimensions. Although the third metal line 94G (described above with reference to Figure 7C is described as having any shape, other conductive members 94 may also have any shape. Figure 10 A schematic diagram of a first metal line 94E and a second metal line 94F according to some embodiments is shown. The first metal line 94E and the second metal line 94F may also be formed in shapes other than straight lines, which may assist in metal line routing. Specifically, each of the first metal line 94E and the second metal line 94F may be formed to include a main portion 106A, a pad portion 106B, and a peripheral portion 106C. The pad portion 106B connects the main portion 106A to the peripheral portion 106C. The main portion 106A extends through one or more memory cells 60 and corresponds to complementary bit lines BL and BLB. The pad portion 106B is disposed at the edge of the memory cell array 52, and one or more main portions 106A are connected to each of the pad portions 106B. The peripheral portion 106C connects the pad portion 106B to peripheral circuitry, such as read / write circuitry 56 and / or column decoder 58 for the memory 50. The pad portion 106B has a width W 6 greater than the width W 7 of the main portion 106A and the width W 5 of the peripheral portion 106C. For example, the width W 5 may be in the range of about 40 nm to about 80 nm, the width W 6 may be in the range of about 20 nm to about 30 nm, and the width W 7It can be in the range of about 15 nm to about 25 nm. The main portion 106A, the pad portion 106B, and the peripheral portion 106C for each of the first metal line 94E and the second metal line 94F are disposed in the same dielectric layer, for example, disposed in the dielectric layer 92 (see Figure 9A and Figure 9B ). Therefore, the metal wire routing of the complementary bit lines BL and BLB to the peripheral circuits (e.g., the read / write circuit 56 and / or the column decoder 58) can be performed in the same layer. Figure 11 A simplified three-dimensional view of the memory 50 is shown, showing the first metal line 94E. As shown, forming the first metal line 94E using the pad portion 106B allows the signal routing between the memory cell array 52 and the peripheral circuits (e.g., the read / write circuit 56 and / or the column decoder 58) to be performed in the same layer. Therefore, the manufacturing cost of the memory 50 can be reduced.

[0053] Figure 12 A schematic diagram of the memory 50 according to some embodiments is shown. Figure 12 A memory cell 60 is shown, and additional details of the metal lines 94E / 94F / 94G are also shown. The metal lines 94E / 94F / 94G connect the memory cells 60 of the memory cell array 52 to the read / write circuit 56 and / or the column decoder 58 for the memory 50. As shown, the first metal line 94E and the second metal line 94F have a main portion 106A, a pad portion 106B, and a peripheral portion 106C. In addition, the third metal line 94G has a main portion 96A and a pad portion 96B. The main portions 96A and 106A have parallel longitudinal axes.

[0054] Although the memory cell 60 is described as an SRAM cell, it should be understood that the embodiments can be applied to other types of memories. For example, metal lines having any shape can also be used to form interconnects for dynamic random access memory (DRAM) cells, resistive random access memory (RRAM) cells, magnetoresistive random access memory (MRAM) cells, etc. In addition, the embodiments can be applied to other types of devices. For example, metal lines having any shape can also be used to form logic devices, application specific integrated circuits, etc.

[0055] Embodiments can achieve advantages. Forming an opening for the conductive member 94 by EUV lithography allows the conductive member 94 to be formed with an arbitrary shape and a very small size. Thus, the third metal line 94G can be formed to have a pad portion 96B for coupling to the first source / drain via 90C and the second source / drain via 90D. Accordingly, the widths of the first source / drain via 90C and the second source / drain via 90D can be increased, thereby allowing an increase in the landing area for the first source / drain contact 86A and the third source / drain contact 86C. Thus, the contact resistance to the third metal line 94G can be reduced, thereby increasing the pull-up current for the pull-up transistors PU1 and PU2 and improving the performance of the memory cell 60. In addition, the first metal line 94E and the second metal line 94F can also be formed to have a pad portion 106B for coupling a plurality of main portions 106A. Thus, the routing of the first metal line 94E and the second metal line 94F can also be improved.

[0056] In one embodiment, a device includes: a substrate having a first p-type well region, a second p-type well region, and an n-type well region disposed between the first p-type well region and the second p-type well region; a first pull-up transistor located in the n-type well region, the first pull-up transistor including a first source / drain region; a second pull-up transistor located in the n-type well region, the second pull-up transistor including a second source / drain region; and a first conductive member electrically connected to a power supply voltage node, the first conductive member having a main portion, a first pad portion extending from a first side of the main portion, and a second pad portion extending from a second side of the main portion, the first pad portion being located above the first source / drain region of the first pull-up transistor and electrically connected to the first source / drain region of the first pull-up transistor, the second pad portion being located above the second source / drain region of the second pull-up transistor and electrically connected to the second source / drain region of the second pull-up transistor, each of the first pad portion and the second pad portion having a first width, and the main portion having a second width, the first width being less than the second width.

[0057] In some embodiments, the device further includes: a first transmission gate transistor located in a first P-type well region, the first transmission gate transistor including a third source / drain region; a second transmission gate transistor located in a second P-type well region, the second transmission gate transistor including a fourth source / drain region; a second conductive component, the second conductive component being located above the third source / drain region of the first transmission gate transistor and electrically connected to the third source / drain region of the first transmission gate transistor; a third conductive component located above the fourth source / drain region of the second transmission gate transistor and electrically connected to the fourth source / drain region of the second transmission gate transistor; and a first dielectric layer surrounding each of the first conductive component, the second conductive component, and the third conductive component. In some embodiments of the device, the first transmission gate transistor further includes a first gate, the second transmission gate transistor further includes a second gate, and the device further includes: a fourth conductive component located above the first gate and electrically connected to the first gate; a fifth conductive component located above the second gate and electrically connected to the second gate; a first pull-down transistor located in the first P-type well region, the first pull-down transistor including a fifth source / drain region; a second pull-down transistor located in the second P-type well region, the second pull-down transistor including a sixth source / drain region; a sixth conductive component electrically connected to a ground voltage node, the sixth conductive component being located above the fifth source / drain region of the first pull-down transistor and electrically connected to the fifth source / drain region of the first pull-down transistor; a seventh conductive component electrically connected to the ground voltage node, the seventh conductive component being located above the sixth source / drain region of the second pull-down transistor and electrically connected to the sixth source / drain region of the second pull-down transistor; and a second dielectric layer surrounding each of the fourth conductive component, the fifth conductive component, the sixth conductive component, and the seventh conductive component. In some embodiments, the device further includes: a first via electrically connecting the first conductive component to a first source / drain region, the first via having a third width; and a second via electrically connecting the sixth conductive component to the fifth source / drain region, the second via having a fourth width, the third width being greater than the fourth width. In some embodiments of the device, the first via and the second via are spaced apart by a first distance, the first distance being in the range of 70 nm to 90 nm. In some embodiments, the device further includes: a row decoder electrically connected to each of the fourth conductive component and the fifth conductive component. In some embodiments, the device further includes: a column decoder electrically connected to each of the second conductive component and the third conductive component. In some embodiments of the device, each of the second conductive component and the third conductive component has a main portion, a pad portion, and a peripheral portion, the pad portion connecting the main portion to the peripheral portion, the peripheral portion being connected to the column decoder, wherein each of the main portion, the pad portion, and the peripheral portion is disposed in the first dielectric layer.In some embodiments, the device further includes: a first fin located in the n-type well region, the first fin including a first pull-up transistor, the first fin being disposed along a first longitudinal axis; and a second fin located in the n-type well region, the second fin including a second pull-up transistor, the second fin being disposed along a second longitudinal axis different from the first longitudinal axis, wherein a main portion of the first conductive member is disposed along a third longitudinal axis that is laterally disposed between the first longitudinal axis and the second longitudinal axis.

[0058] In one embodiment, a device includes: a substrate having a first p-type well region, a second p-type well region, and an n-type well region disposed between the first p-type well region and the second p-type well region; a first pull-up transistor located in the n-type well region, the first pull-up transistor including a first source / drain region; a first pull-down transistor located in the first p-type well region, the first pull-down transistor including a second source / drain region; a first via electrically connected to the first source / drain region of the first pull-up transistor, the first via having a first width; and a second via electrically connected to the second source / drain region of the first pull-down transistor, the second via having a second width, the first width being greater than the second width, each of the first width and the second width being measured along the same direction, wherein the first via and the second via are separated by a first distance within a range of 70 nm to 90 nm.

[0059] In some embodiments, the device further includes: a first dielectric layer located over the first via and the second via; and a metal line located in the first dielectric layer, the metal line having a main portion and a first protruding portion extending laterally from the main portion, the first via being physically and electrically connected to the first protruding portion and the main portion. In some embodiments of the device, the main portion of the metal line has a third width that is less than the first width. In some embodiments of the device, the first protruding portion of the metal line has a fourth width that is less than the first width. In some embodiments of the device, the third width is greater than the fourth width. In some embodiments, the device further includes: a first fin that includes a first pull-up transistor; and a second fin that includes a first pull-down transistor, wherein the first fin, the second fin, and the main portion of the metal line are parallel. In some embodiments of the device, the main portion of the metal line does not laterally overlap with the first fin or the second fin.

[0060] In one embodiment, a method includes: forming a first fin extending from an n-type well region of a substrate; growing a first source / drain region in the first fin; forming a second fin extending from the n-type well region of the substrate; growing a second source / drain region in the second fin; depositing a first dielectric layer over the first source / drain region and the second source / drain region; forming a first via through the first dielectric layer to electrically couple the first source / drain region, the first via having a width in the range of 15 nm to 20 nm; forming a second via through the first dielectric layer to electrically couple the second source / drain region, the second via having a width in the range of 15 nm to 20 nm; depositing a second dielectric layer over the first dielectric layer, the first via, and the second via; patterning an opening in the second dielectric layer using a single-patterning lithography process, the opening having a main portion, a first protruding portion extending from a first side of the main portion, and a second protruding portion extending from a second side of the main portion, the first protruding portion and the main portion of the opening exposing the first via, and the second protruding portion and the main portion of the opening exposing the second via; and filling the opening with a conductive material to form a first metal line physically and electrically coupled to the first via and the second via.

[0061] In some embodiments of the method, patterning the opening includes: projecting a radiation beam onto the second dielectric layer, the radiation beam having the pattern of the opening. In some embodiments of the method, the single-patterning lithography process is an extreme ultraviolet (EUV) lithography process. In some embodiments of the method, filling the opening with a conductive material includes: plating the conductive material in the opening; and planarizing the conductive material and the second dielectric layer to form the first metal line from the remaining portion of the conductive material, after planarization, the top surface of the first metal line and the second dielectric layer is planar.

[0062] The features of several embodiments are outlined above so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis to design or modify other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a substrate having a first p-type well region, a second p-type well region, and an n-type well region disposed between the first p-type well region and the second p-type well region; a first pull-up transistor located in the n-type well region, the first pull-up transistor including a first source / drain region; a second pull-up transistor located in the n-type well region, the second pull-up transistor including a second source / drain region; and a first conductive component electrically connected to a power supply voltage node, the first conductive component having a main portion, a first pad portion extending from a first side of the main portion, and a second pad portion extending from a second side of the main portion, the first pad portion being located above the first source / drain region of the first pull-up transistor and electrically connected to the first source / drain region of the first pull-up transistor, the second pad portion being located above the second source / drain region of the second pull-up transistor and electrically connected to the second source / drain region of the second pull-up transistor, each of the first pad portion and the second pad portion having a first width, the main portion having a second width, and the first width being less than the second width; a first via physically contacting the main portion and the first pad portion and fully landing within the first conductive component, and electrically connecting the first conductive component to the first source / drain region, the first via having a third width, wherein the third width is greater than the first width and the second width.

2. The semiconductor device according to claim 1, further comprising: a first transmission gate transistor located in the first p-type well region, the first transmission gate transistor including a third source / drain region; a second transmission gate transistor located in the second p-type well region, the second transmission gate transistor including a fourth source / drain region; a second conductive component located above the third source / drain region of the first transmission gate transistor and electrically connected to the third source / drain region of the first transmission gate transistor; a third conductive component located above the fourth source / drain region of the second transmission gate transistor and electrically connected to the fourth source / drain region of the second transmission gate transistor; and a first dielectric layer surrounding each of the first conductive component, the second conductive component, and the third conductive component.

3. The semiconductor device according to claim 2, wherein the first transmission gate transistor further includes a first gate, wherein the second transmission gate transistor further includes a second gate, and the semiconductor device further includes: a fourth conductive component located above the first gate and electrically connected to the first gate; a fifth conductive component located above the second gate and electrically connected to the second gate; a first pull-down transistor located in the first p-type well region, the first pull-down transistor including a fifth source / drain region; a second pull-down transistor located in the second p-type well region, the second pull-down transistor including a sixth source / drain region; A sixth conductive component is electrically connected to a ground voltage node. The sixth conductive component is located above the fifth source / drain region of the first pull-down transistor and is electrically connected to the fifth source / drain region of the first pull-down transistor. A seventh conductive component is electrically connected to the ground voltage node. The seventh conductive component is located above the sixth source / drain region of the second pull-down transistor and is electrically connected to the sixth source / drain region of the second pull-down transistor. And A second dielectric layer surrounds each of the fourth conductive component, the fifth conductive component, the sixth conductive component, and the seventh conductive component.

4. The semiconductor device according to claim 3, further comprising: A second via electrically connects the sixth conductive component to the fifth source / drain region. The second via has a fourth width, and the third width is greater than the fourth width.

5. The semiconductor device according to claim 4, wherein the first via and the second via are spaced apart by a first distance, and the first distance is in the range of 70 nm to 90 nm.

6. The semiconductor device according to claim 3, further comprising: A row decoder is electrically connected to each of the fourth conductive component and the fifth conductive component.

7. The semiconductor device according to claim 2, further comprising: A column decoder is electrically connected to each of the second conductive component and the third conductive component.

8. The semiconductor device according to claim 7, wherein each of the second conductive component and the third conductive component has a main portion, a pad portion, and a peripheral portion. The pad portion connects the main portion to the peripheral portion, and the peripheral portion is connected to the column decoder. Each of the main portion, the pad portion, and the peripheral portion is disposed in the first dielectric layer.

9. The semiconductor device according to claim 1, further comprising: A first fin is located in the n-type well region. The first fin includes the first pull-up transistor, and the first fin is disposed along a first longitudinal axis; and A second fin is located in the n-type well region. The second fin includes the second pull-up transistor, and the second fin is disposed along a second longitudinal axis, and the second longitudinal axis is different from the first longitudinal axis. wherein the main portion of the first conductive component is disposed along a third longitudinal axis, and the third longitudinal axis is horizontally disposed between the first longitudinal axis and the second longitudinal axis.

10. A semiconductor device, comprising: A substrate having a first p-type well region, a second p-type well region, and an n-type well region disposed between the first p-type well region and the second p-type well region; A first pull-up transistor located in the n-type well region. The first pull-up transistor includes a first source / drain region; A first pull-down transistor located in the first p-type well region. The first pull-down transistor includes a second source / drain region; A first via electrically connects to the first source / drain region of the first pull-up transistor. The first via has a first width; and A second via hole, electrically connected to the second source / drain region of the first pull-down transistor, the second via hole having a second width, the first width being greater than the second width, each of the first width and the second width being measured along the same direction, A first dielectric layer, located above the first via hole and the second via hole; And A metal wire, located in the first dielectric layer, the metal wire having a main portion and a first protruding portion extending laterally from the main portion, the first via hole physically and electrically connecting to the first protruding portion and the main portion and fully landing within the metal wire, Wherein, the main portion of the metal wire has a third width, the first protruding portion of the metal wire has a fourth width, the third width and the fourth width being less than the first width, Wherein, the first via hole is spaced from the second via hole by a first distance, the first distance being in the range of 70 nm to 90 nm.

11. The semiconductor device according to claim 10, Wherein: The second width is in the range of 10 nm to 15 nm.

12. The semiconductor device according to claim 10, Wherein, The third width is in the range of 10 nm to 18 nm.

13. The semiconductor device according to claim 10, Wherein, The fourth width is in the range of 5 nm to 15 nm.

14. The semiconductor device according to claim 10, Wherein, The third width is greater than the fourth width.

15. The semiconductor device according to claim 11, further Comprising: A first fin, including the first pull-up transistor; And A second fin, including the first pull-down transistor, Wherein, the first fin, the second fin and the main portion of the metal wire are parallel.

16. The semiconductor device according to claim 15, Wherein, The main portion of the metal wire does not laterally overlap with the first fin or the second fin.

17. A method of forming a semiconductor device, Comprising: Forming a first fin extending from an n-type well region of a substrate; Growing a first source / drain region in the first fin; Forming a second fin extending from the n-type well region of the substrate; Growing a second source / drain region in the second fin; Depositing a first dielectric layer above the first source / drain region and the second source / drain region; Forming a first via hole through the first dielectric layer to electrically couple the first source / drain region, the first via hole having a width in the range of 15 nm to 20 nm; Forming a second via hole through the first dielectric layer to electrically couple the second source / drain region, the second via hole having a width in the range of 15 nm to 20 nm; Depositing a second dielectric layer above the first dielectric layer, the first via hole and the second via hole; Pattern openings in the second dielectric layer using a single patterning lithography process, the openings having a main portion, a first protruding portion extending from a first side of the main portion, and a second protruding portion extending from a second side of the main portion, the first protruding portion and the main portion of the opening exposing the first through hole, and the second protruding portion and the main portion of the opening exposing the second through hole; and fill the openings with a conductive material to form a first metal wire physically and electrically coupled to the first through hole and the second through hole, wherein the width of the first through hole is greater than the width of the main portion, the width of the first protruding portion, and the width of the second protruding portion, and the first through hole completely lands within the first metal wire.

18. The method according to claim 17, wherein patterning the openings includes: projecting a radiation beam onto the second dielectric layer, the radiation beam having the pattern of the openings.

19. The method according to claim 17, wherein the single patterning lithography process is an extreme ultraviolet (EUV) lithography process.

20. The method according to claim 17, wherein filling the openings with the conductive material includes: electroplating the conductive material in the openings; and planarizing the conductive material and the second dielectric layer to form the first metal wire from the remaining portion of the conductive material, after the planarization, the top surfaces of the first metal wire and the second dielectric layer are planar.

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