semiconductor devices

Abstract

A semiconductor device comprising: a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction intersecting the first direction; and first to third power rails connected to the first to third active patterns, respectively, wherein a width of the second active pattern in the first direction is at least twice a width of the first active pattern in the first direction and at least twice a width of the third active pattern in the first direction, the first active pattern does not vertically overlap with the first power rail, the second active pattern vertically overlaps with the second power rail, and the third active pattern does not vertically overlap with the third power rail.

Description

Technical Field

[0001] Embodiments relate to semiconductor devices. Background Art

[0002] Semiconductor devices are important components in the electronics industry due to their small size, multifunctionality, and / or low cost. Semiconductor devices can include semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that include both memory and logic elements. Summary of the Invention

[0003] An embodiment may be implemented by providing a semiconductor device including: a substrate; at least one first active pattern, at least one second active pattern, and at least one third active pattern on an upper portion of the substrate, the at least one first active pattern, the at least one second active pattern, and the at least one third active pattern being sequentially arranged in a first direction and extending in a second direction intersecting the first direction; a first power rail connected to the at least one first active pattern; a second power rail connected to the at least one second active pattern; and a third power rail connected to the at least one third active pattern, wherein a width of the at least one second active pattern in the first direction is at least twice a width of the at least one first active pattern in the first direction and at least twice a width of the at least one third active pattern in the first direction, the at least one first active pattern does not vertically overlap with the first power rail, the at least one second active pattern vertically overlaps with the second power rail, and the at least one third active pattern does not vertically overlap with the third power rail.

[0004] An embodiment can be implemented by providing a semiconductor device including: a substrate; a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern sequentially arranged on an upper portion of the substrate and in a first direction; a first source / drain pattern, a second source / drain pattern, a third source / drain pattern, and a fourth source / drain pattern respectively on the first active pattern, the second active pattern, the third active pattern, and the fourth active pattern; a gate electrode crossing the first active pattern, the second active pattern, the third active pattern, and the fourth active pattern and extending in the first direction; and a first power rail, a second power rail, a third power rail, and a fourth power rail respectively connected to the first source / drain pattern, the second source / drain pattern, the third source / drain pattern, and the fourth source / drain pattern. rails, the first power rail, the second power rail, the third power rail, and the fourth power rail extend in a second direction intersecting the first direction, wherein a width of the second active pattern in the first direction is at least twice a width of the first active pattern in the first direction, a width of the third active pattern in the first direction is at least twice a width of the first active pattern in the first direction, a width of the second active pattern in the first direction is at least twice a width of the fourth active pattern in the first direction, a width of the third active pattern in the first direction is at least twice a width of the fourth active pattern in the first direction, the first active pattern does not vertically overlap with the first power rail, the second active pattern vertically overlaps with the second power rail, the third active pattern vertically overlaps with the third power rail, and the fourth active pattern does not vertically overlap with the fourth power rail.

[0005] An embodiment may be implemented by providing a semiconductor device including: a first power rail, a second power rail, and a third power rail sequentially arranged on a substrate and in a first direction; a first logic cell including a first active pattern, the first active pattern being between the first power rail and the second power rail; and a second logic cell including a second active pattern, the second active pattern being between the second power rail and the third power rail and extending to an area below the third power rail, wherein a width of the second active pattern in the first direction is two to three times a width of the first active pattern in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0007] Figure 1A A top view of a semiconductor device according to an embodiment is shown.

[0008] Figure 1B 、 Figure 1C 、 Figure 1D and Figure 1E Shown are respectively along Figure 1ACross-sectional views taken along lines AA', BB', CC' and DD'.

[0009] Figure 2A and Figure 3A A top view illustrating a stage in a method of fabricating a semiconductor device according to an embodiment.

[0010] Figure 2B and Figure 3B Shown are the Figure 2A and Figure 3A A cross-sectional view taken along line AA'.

[0011] Figure 3C 、 Figure 3D and Figure 3E Shown are respectively along Figure 3A Cross-sectional views taken along lines BB', CC' and DD'.

[0012] Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A and Figure 8A Top views are shown, each of which shows a semiconductor device according to an embodiment.

[0013] Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B and Figure 8B Shown are the Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A and Figure 8A A cross-sectional view taken along line AA'.

[0014] Figure 4C 、 Figure 5C 、 Figure 6C 、 Figure 7C and Figure 8C Shown are the Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A and Figure 8A A cross-sectional view taken along line BB'.

[0015] Figures 9 to 12 A semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0016] Figure 1A A top view of a semiconductor device according to an embodiment is shown. Figure 1B 、 Figure 1C 、 Figure 1D and Figure 1EShown are respectively along Figure 1A Cross-sectional views taken along lines AA', BB', CC' and DD'.

[0017] Reference Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and Figure 1E A substrate 100 including a first region RG1 and a second region RG2 may be provided. The first region RG1 and the second region RG2 may be alternately arranged in or along a first direction D1. The first direction D1 may be a direction parallel to the top surface of the substrate 100. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon wafer, a germanium wafer, or a silicon-on-insulator (SOI) wafer.

[0018] In one implementation, each of the first and second regions RG1 and RG2 of the substrate 100 may be a memory cell region on which a plurality of memory cells for storing data are formed. In this case, a plurality of memory cell transistors constituting an SRAM cell may be on the memory cell region of the substrate 100.

[0019] In one embodiment, the first region RG1 and the second region RG2 of the substrate 100 may be logic cell regions on which logic transistors constituting a logic circuit of the semiconductor device are disposed. In this case, logic transistors constituting a processor core or an I / O terminal may be located in the logic cell regions of the substrate 100.

[0020] The first transistor may be on the first region RG1, and the second transistor may be on the second region RG2. The first transistor and the second transistor may have different conductivity types from each other. For example, the first region RG1 may be a p-type metal oxide semiconductor field effect transistor (PMOSFET) region, and the first transistor may be a PMOSFET, and the second region RG2 may be an n-type metal oxide semiconductor field effect transistor (NMOSFET) region, and the second transistor may be an NMOSFET. For example, the first transistor on the first region RG1 may include a first source / drain pattern SD1 doped with n-type impurities, and the second transistor on the second region RG2 may include a second source / drain pattern SD2 doped with p-type impurities. In one implementation, the first transistor may be an NMOSFET, and the second transistor may be a PMOSFET.

[0021] A first active pattern AP1, a second active pattern AP2, a third active pattern AP3, and a fourth active pattern AP4 may be defined in an upper portion of the substrate 100. In one implementation, a pair of first active patterns AP1, second active pattern AP2, third active pattern AP3, and a pair of fourth active patterns AP4 may be sequentially arranged in the first direction D1. The pair of first active patterns AP1 may be located in the first region RG1. The second active pattern AP2 may be located in the second region RG2. The third active pattern AP3 may be located in the first region RG1. The pair of fourth active patterns AP4 may be located in the second region RG2.

[0022] Each of the first to fourth active patterns AP1, AP2, AP3, and AP4 may be a linear pattern or a stripe pattern extending in the second direction D2 (eg, lengthwise). The second direction D2 may be a direction parallel to the top surface of the substrate 100 and perpendicular to the first direction D1.

[0023] The width of the first active pattern AP1 in the first direction D1 may be defined as a first width W1. The width of the second active pattern AP2 in the first direction D1 may be defined as a second width W2. The width of the third active pattern AP3 in the first direction D1 may be defined as a third width W3. The width of the fourth active pattern AP4 in the first direction D1 may be defined as a fourth width W4.

[0024] The first width W1 and the fourth width W4 may be equal to or different from each other. The second width W2 and the third width W3 may be equal to or different from each other. The second width W2 may be at least twice the first width W1. The second width W2 may be at least twice the fourth width W4. The third width W3 may be at least twice the first width W1. The third width W3 may be at least twice the fourth width W4.

[0025] In one embodiment, as shown in the figure, two active patterns AP2 and AP3 may be between a pair of first active patterns AP1 and a pair of fourth active patterns AP4 (i.e., between the first active pattern AP1 and the fourth active pattern AP4 positioned adjacent to each other). In one embodiment, three or more active patterns may be between a pair of first active patterns AP1 and a pair of fourth active patterns AP4. In one embodiment, such a structure may be repeated in the semiconductor device, wherein active patterns having relatively large widths (i.e., the second active pattern AP2 and the third active pattern AP3) are between a pair of active patterns having relatively small widths (i.e., the first active pattern AP1) and another pair of active patterns having relatively small widths (i.e., the fourth active pattern AP4).

[0026] The device isolation layer ST may be on the substrate 100. The device isolation layer ST may fill the lower portion of the first trench TR1. The first trench TR1 may be between active patterns AP1, AP2, AP3, and AP4 that are adjacent to each other along the first direction D1. The first trench TR1 may be arranged in the first direction D1. The first trench TR1 may extend (lengthwise) in the second direction D2.

[0027] The first region RG1 may include a pair of single diffusion barrier regions SDB. In the first region RG1, the single diffusion barrier regions SDB may be spaced apart from each other in the second direction D2. The second region RG2 may include a pair of double diffusion barrier regions DDB. In the second region RG2, the double diffusion barrier regions DDB may be spaced apart from each other in the second direction D2.

[0028] The active patterns AP1, AP2, AP3, and AP4 may be between a pair of single diffusion barrier regions SDB and between a pair of double diffusion barrier regions DDB. For example, a pair of first active patterns AP1 may be between a pair of single diffusion barrier regions SDB, and a second active pattern AP2 may be between a pair of double diffusion barrier regions DDB.

[0029] The second trench TR2 may be on the double diffusion barrier region DDB. The second trench TR2 may extend in the first direction D1. A lower portion of the second trench TR2 may be filled with a device isolation layer ST.

[0030] The third trench TR3 may be formed on the double diffusion barrier region DDB and the single diffusion barrier region SDB. The third trench TR3 may extend along the single diffusion barrier region SDB and the double diffusion barrier region DDB arranged in the first direction D1. For example, the third trench TR3 may extend (lengthwise) in the first direction D1. The third trench TR3 may be filled with a diffusion barrier pattern DBP. In one embodiment, the diffusion barrier pattern DBP may be formed of or include silicon oxide or silicon oxynitride. When used herein, the term "or" is not an exclusive term; for example, "A or B" includes A, B, or both.

[0031] In the double diffusion barrier region DDB, the upper portion of the second trench TR2 (e.g., the portion away from the substrate 100 in the third direction D3) may be defined as a third trench TR3. For example, in the double diffusion barrier region DDB, the lower portion of the second trench TR2 may be filled with the device isolation layer ST, and the upper portion of the second trench TR2 above the device isolation layer ST may be filled with the diffusion barrier pattern DBP. The level of the bottom surface of the second trench TR2 may be lower than that of the bottom surface of the third trench TR3 (in the third direction D3).

[0032] The shapes of the active patterns AP1, AP2, AP3, and AP4 may be defined by the first to third trenches TR1, TR3, and TR3. The top surface of the device isolation layer ST may be lower than the top surfaces of the active patterns AP1, AP2, AP3, and AP4. A first source / drain pattern SD1 may be on each first active pattern AP1, a second source / drain pattern SD2 may be on the second active pattern AP2, a third source / drain pattern SD3 may be on the third active pattern AP3, and a fourth source / drain pattern SD4 may be on each fourth active pattern AP4.

[0033] The channel pattern CH may be located in each of a region between a pair of adjacent first source / drain patterns SD1, a region between a pair of adjacent second source / drain patterns SD2, a region between a pair of adjacent third source / drain patterns SD3, and a region between a pair of adjacent fourth source / drain patterns SD4.

[0034] Each channel pattern CH may include first to third semiconductor patterns SP1, SP2, and SP3 stacked sequentially. The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from one another in a third direction D3 perpendicular to the top surface of the substrate 100 (e.g., perpendicular to the first direction D1 and the second direction D2). The first to third semiconductor patterns SP1, SP2, and SP3 may vertically overlap one another (e.g., when viewed in a top plan view). Each of the first to fourth source / drain patterns SD1, SD2, SD3, and SD4 may be in direct contact with a side surface of each of the first to third semiconductor patterns SP1, SP2, and SP3. For example, the first to third semiconductor patterns SP1, SP2, and SP3 may connect two adjacent source / drain patterns SD1, SD2, SD3, and SD4 in the second direction to one another.

[0035] The first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or include silicon (Si), germanium (Ge), or silicon germanium (SiGe). In one implementation, as shown in the figure, the channel pattern CH may include the first to third semiconductor patterns SP1, SP2, and SP3 or a different number of semiconductor patterns.

[0036] The first to third semiconductor patterns SP1, SP2, and SP3 of the channel pattern CH on the first active pattern AP1 (e.g., aligned with the first active pattern AP1 in the third direction D3) may have a width measured in the first direction D1 that is substantially equal to the first width W1. The first to third semiconductor patterns SP1, SP2, and SP3 of the channel pattern CH on the second active pattern AP2 may have a width measured in the first direction D1 that is substantially equal to the second width W2. The first to third semiconductor patterns SP1, SP2, and SP3 of the channel pattern CH on the third active pattern AP3 may have a width measured in the first direction D1 that is substantially equal to the third width W3. The first to third semiconductor patterns SP1, SP2, and SP3 of the channel pattern CH on the fourth active pattern AP4 may have a width measured in the first direction D1 that is substantially equal to the fourth width W4. For example, the width of the first to third semiconductor patterns SP1, SP2, and SP3 of the channel pattern CH on the second active pattern AP2 in the first direction D1 may be at least twice the width of the first to third semiconductor patterns SP1, SP2, and SP3 of the channel pattern CH on the first active pattern AP1 in the first direction D1.

[0037] In one implementation, each of the first to fourth active patterns AP1 , AP2 , AP3 , and AP4 may include an active fin instead of the channel pattern CH. A semiconductor device including the active fin will be described in more detail below.

[0038] Each of the source / drain patterns SD1 , SD2 , SD3 , and SD4 may be an epitaxial pattern formed using the first to third semiconductor patterns SP1 , SP2 , and SP3 of the channel pattern CH and its corresponding active patterns AP1 , AP2 , AP3 , and AP4 as a seed layer.

[0039] The first and third source / drain patterns SD1 and SD3 may be p-type impurity regions. The first and third source / drain patterns SD1 and SD3 may include a material that can apply compressive stress to the channel pattern CH. For example, the first and third source / drain patterns SD1 and SD3 may include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100.

[0040] The second source / drain pattern SD2 and the fourth source / drain pattern SD4 may be n-type impurity regions. The second source / drain pattern SD2 and the fourth source / drain pattern SD4 may include a semiconductor material having a lattice constant smaller than that of the substrate 100. In one implementation, the second source / drain pattern SD2 and the fourth source / drain pattern SD4 may include the same semiconductor material as the semiconductor material of the substrate 100 (e.g., Si).

[0041] The maximum width of the first source / drain pattern SD1 in the first direction D1 may be defined as a fifth width W5. The maximum width of the second source / drain pattern SD2 in the first direction D1 may be defined as a sixth width W6. The maximum width of the third source / drain pattern SD3 in the first direction D1 may be defined as a seventh width W7. The maximum width of the fourth source / drain pattern SD4 in the first direction D1 may be defined as an eighth width W8. The sixth width W6 may be at least twice the fifth width W5. The sixth width W6 may be at least twice the eighth width W8. The seventh width W7 may be at least twice the fifth width W5. The seventh width W7 may be at least twice the eighth width W8.

[0042] The gate electrode GE may intersect the channel pattern CH and extend in the first direction D1. The gate electrodes GE may be spaced apart from each other in the second direction D2. The gate electrode GE may vertically overlap the channel pattern CH. In one implementation, the gate electrode GE may be formed of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) or a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum), or include a conductive metal nitride (e.g., titanium nitride or tantalum nitride) or a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0043] The gate electrode GE may surround each of the first to third semiconductor patterns SP1, SP2, and SP3 of the channel pattern CH. For example, the gate electrode GE may cover or face a top surface, a bottom surface, and side surfaces opposite to each other (for example, see FIG. Figure 1C 、 Figure 1D and Figure 1E ). For example, the first transistor and the second transistor may be gate-all-around field effect transistors.

[0044] The gate electrode GE may include first to fourth portions GP1, GP2, GP3, and GP4. The first to fourth portions GP1-GP4 of the gate electrode GE may be on each of the first to fourth active patterns AP1, AP2, AP3, and AP4. The first portion GP1 may be between each of the first to fourth active patterns AP1, AP2, AP3, and AP4 and the first semiconductor pattern SP1, the second portion GP2 may be between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, the third portion GP3 may be between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and the fourth portion GP4 may be on the third semiconductor pattern SP3.

[0045] For example, the width of the first to fourth portions GP1, GP2, GP3 and GP4 on the second active pattern AP2 in the first direction D1 may be at least twice the width of the first to fourth portions GP1, GP2, GP3 and GP4 on the first active pattern AP1 in the first direction D1.

[0046] The insulating pattern IL may be between the gate electrodes GE. Due to the insulating pattern IL, the gate electrodes GE may be spaced apart from each other in the first direction D1. The insulating pattern IL may be between the pair of first active patterns AP1. The insulating pattern IL may be between the pair of fourth active patterns AP4.

[0047] One first active pattern AP1, one second active pattern AP2, one third active pattern AP3, and one fourth active pattern AP4 may be between each pair of adjacent insulating patterns IL (eg, see FIG. 1 ). Figure 1C ).

[0048] A pair of gate spacers GS may be provided on opposite side surfaces of each gate electrode GE. The gate spacers GS may extend along the gate electrode GE and in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE (e.g., further from the substrate 100 in the third direction D3). The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer insulating layer 110, which will be described below. The gate spacer GS may be formed of or include SiCN, SiCON, or SiN. In one implementation, the gate spacer GS may have a multilayer structure including at least two different materials selected from SiCN, SiCON, and SiN.

[0049] The gate dielectric pattern GI may be between the gate electrode GE and the channel pattern CH. The gate dielectric pattern GI may surround each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate dielectric pattern GI may be between each of the first to third semiconductor patterns SP1, SP2, and SP3 and the gate electrode GE. The gate dielectric pattern GI may be formed of or include a high-k dielectric material. High-k dielectric materials may include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0050] A gate capping pattern GP may be formed on each gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE and in the first direction D1. The gate capping pattern GP may be formed of a material selected to have an etching selectivity with respect to the first interlayer insulating layer 110, which will be described below, or include a material selected to have an etching selectivity with respect to the first interlayer insulating layer 110, which will be described below. For example, the gate capping pattern GP may be formed of or include SiON, SiCN, SiCON, or SiN.

[0051] A first interlayer insulating layer 110 may be on the substrate 100. The first interlayer insulating layer 110 may cover the device isolation layer ST, the gate electrode GE, and the first to fourth source / drain patterns SD1, SD2, SD3, and SD4. A top surface of the first interlayer insulating layer 110 may be substantially coplanar with a top surface of the gate capping pattern GP. A top surface of the first interlayer insulating layer 110 may be substantially coplanar with a top surface of the diffusion barrier pattern DBP. A second interlayer insulating layer 120 may be on the first interlayer insulating layer 110. For example, the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may be formed of or include silicon oxide or silicon oxynitride.

[0052] The first contact CT1 may penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and may be connected to the first to fourth source / drain patterns SD1, SD2, SD3, and SD4, respectively. For example, the first contact CT1 may be formed of or include a metallic material such as titanium, tantalum, tungsten, copper, or aluminum.

[0053] The third interlayer insulating layer 130 may be on the second interlayer insulating layer 120. For example, the third interlayer insulating layer 130 may be formed of or include silicon oxide or silicon oxynitride.

[0054] The second contacts CT2 may be in the third interlayer insulating layer 130 and may be connected to the first contacts CT1, respectively. In one implementation, the second contacts CT2 may be formed of or include a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0055] The first conductive line CL1, the second conductive line CL2, the first power rail PW1, the second power rail PW2, the third power rail PW3, and the fourth power rail PW4 may be in the third interlayer insulating layer 130. Each of the first conductive lines CL1 may connect the second contacts CT2 connected to the pair of first source / drain patterns SD1 to each other. The second conductive line CL2 may connect the second contacts CT2 connected to the pair of fourth source / drain patterns SD4 to each other.

[0056] The first to fourth power rails PW1, PW2, PW3, and PW4 may extend in the second direction D2. The first power rail PW1 may be connected to the first source / drain pattern SD1 via a first conductive line CL1 and a second contact CT2. The second power rail PW2 may be connected to the second source / drain pattern SD2 via a second contact CT2. The third power rail PW3 may be connected to the third source / drain pattern SD3 via a second contact CT2. The fourth power rail PW4 may be connected to the fourth source / drain pattern SD4 via a second conductive line CL2 and a second contact CT2. The first power rail PW1 connected to the first source / drain pattern SD1 may not vertically overlap with the first active pattern AP1 (e.g., may not be located above the first active pattern AP1 in the third direction D3). When viewed in a top view, the first power rail PW1 may be between a pair of first active patterns AP1. The first power rail PW1 may be connected to the pair of first active patterns AP1. The second power rail PW2 connected to the second source / drain pattern SD2 may vertically overlap with the second active pattern AP2. The second power rail PW2 may be connected to one second active pattern AP2. The third power rail PW3 connected to the third source / drain pattern SD3 may vertically overlap the third active pattern AP3. The third power rail PW3 may be connected to one third active pattern AP3. The fourth power rail PW4 connected to the fourth source / drain pattern SD4 may not vertically overlap the fourth active pattern AP4. When viewed from above, the fourth power rail PW4 may be between a pair of fourth active patterns AP4. The fourth power rail PW4 may be connected to a pair of fourth active patterns AP4.

[0057] In an implementation, the second and third active patterns AP2 and AP3 and the channel patterns CH thereon may have a relatively large width in the first direction D1 , and this may make it possible to improve electrical characteristics of the semiconductor device.

[0058] Figure 2A and Figure 3A A top view illustrating a stage in a method of fabricating a semiconductor device according to an embodiment. Figure 2B and Figure 3B Shown are the Figure 2A and Figure 3A A cross-sectional view taken along line AA'. Figure 3C 、 Figure 3D and Figure 3E Shown are respectively along Figure 3A Cross-sectional views taken along lines BB', CC' and DD'.

[0059] Reference Figure 2A and Figure 2B, first to fourth active patterns AP1, AP2, AP3, and AP4 and a preliminary pattern PAP may be formed. The formation of the first to fourth active patterns AP1, AP2, AP3, and AP4 and the preliminary pattern PAP may include alternately and repeatedly stacking sacrificial layers 102 and semiconductor layers 101 on the substrate 100 and forming first trenches TR1.

[0060] The sacrificial layer 102 may be formed of a material selected to have an etching selectivity with respect to the semiconductor layer 101, or include a material selected to have an etching selectivity with respect to the semiconductor layer 101. For example, the semiconductor layer 101 may be formed of a material that is hardly etched in the process of etching the sacrificial layer 102, or include a material that is hardly etched in the process of etching the sacrificial layer 102. In one implementation, in the process of etching the sacrificial layer 102, the ratio of the etching rate of the sacrificial layer 102 to the etching rate of the semiconductor layer 101 may be in the range of 10:1 to 200:1. In one implementation, the sacrificial layer 102 may be formed of or include silicon germanium (SiGe) or germanium (Ge), and the semiconductor layer 101 may be formed of or include silicon (Si).

[0061] The sacrificial layer 102 and the semiconductor layer 101 may be formed by an epitaxial growth process in which the substrate 100 is used as a seed layer. The sacrificial layer 102 and the semiconductor layer 101 may be formed continuously in the same chamber. Each of the sacrificial layer 102 and the semiconductor layer 101 may be conformally grown on the substrate 100.

[0062] The formation of the first trench TR1 may include patterning the sacrificial layer 102, the semiconductor layer 101, and the substrate 100. As a result of the patterning of the sacrificial layer 102, the semiconductor layer 101, and the substrate 100, the first trench TR1 may extend in the second direction D2. The substrate 100 may be patterned to define first to fourth active patterns AP1, AP2, AP3, and AP4 between the first trench TR1. The sacrificial layer 102 and the semiconductor layer 101 may be patterned to form a preliminary pattern PAP on each of the first to fourth active patterns AP1, AP2, AP3, and AP4. Each preliminary pattern PAP may include patterned portions of the sacrificial layer 102 and the semiconductor layer 101. Each preliminary pattern PAP may vertically overlap each of the first to fourth active patterns AP1, AP2, AP3, and AP4.

[0063] The first to fourth active patterns AP1 , AP2 , AP3 , and AP4 and the preliminary pattern PAP may have a line shape or a bar shape extending in the second direction D2 .

[0064] The second trench TR2 may be formed on the double diffusion barrier region DDB located on the second region RG2 of the substrate 100 by patterning the second active pattern AP2, the fourth active pattern AP4, and the preliminary pattern PAP thereon.

[0065] The device isolation layer ST may fill the first trench TR1 and the second trench TR2. The formation of the device isolation layer ST may include forming an insulating layer on the substrate 100 and recessing the insulating layer to completely expose the preliminary pattern PAP. As a result, the device isolation layer ST may have a top surface lower than the top surfaces of the first to fourth active patterns AP1, AP2, AP3, and AP4.

[0066] Reference Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D and Figure 3E , source / drain patterns SD1 , SD2 , SD3 , and SD4 and a channel pattern CH may be formed.

[0067] The formation of the source / drain patterns SD1, SD2, SD3 and SD4 and the channel pattern CH may include forming a sacrificial pattern crossing the initial pattern PAP, forming a pair of gate spacers GS on side surfaces opposite to each other of each sacrificial pattern, etching the initial pattern PAP using the sacrificial pattern and the gate spacers GS as masks, and forming the source / drain patterns SD1, SD2, SD3 and SD4 using an epitaxial growth process.

[0068] The sacrificial pattern may have a line shape or a bar shape extending in the first direction D1. The sacrificial pattern may be formed of or include polysilicon.

[0069] The formation of the gate spacer GS may include conformally forming a spacer layer on the substrate 100 and performing an anisotropic etching process on the spacer layer.

[0070] The channel pattern CH may be formed by patterning the preliminary pattern PAP using the sacrificial pattern and the gate spacer GS as a mask. The semiconductor layer 101 of the preliminary pattern PAP may be patterned to form first to third semiconductor patterns SP1, SP2, and SP3.

[0071] The recess RS may be formed by patterning the preliminary pattern PAP using the sacrificial pattern and the gate spacer GS as a mask. The channel pattern CH may be between a pair of adjacent recesses RS.

[0072] The source / drain patterns SD1, SD2, SD3, and SD4 may fill the recess RS. The formation of the source / drain patterns SD1, SD2, SD3, and SD4 may include performing a selective epitaxial process in which each of the active patterns AP1, AP2, AP3, and AP4 and the first to third semiconductor patterns SP1, SP2, and SP3 is used as a seed layer.

[0073] During or after the selective epitaxial process, the first and third source / drain patterns SD1 and SD3 may be doped with p-type impurities, and the second and fourth source / drain patterns SD2 and SD4 may be doped with n-type impurities.

[0074] A first interlayer insulating layer 110 may be formed on the substrate 100 to cover the source / drain patterns SD1, SD2, SD3, and SD4 and the device isolation layer ST. A planarization process of the first interlayer insulating layer 110 may be performed to expose the sacrificial pattern.

[0075] The sacrificial patterns exposed by the planarization process may be removed. As a result of the removal of the sacrificial patterns, an empty space EP may be formed between the pair of gate spacers GS. The empty space EP may expose the channel patterns CH and the sacrificial layer 102 between the channel patterns CH.

[0076] The sacrificial layer 102 exposed by the empty space EP may be removed. As a result of the removal of the sacrificial layer 102, a first cavity SA1 may be formed between each of the active patterns AP1, AP2, AP3, and AP4 and the first semiconductor pattern SP1, a second cavity SA2 may be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third cavity SA3 may be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3. Side surfaces of the source / drain patterns SD1, SD2, SD3, and SD4 may be partially exposed by the first to third cavities SA1, SA2, and SA3.

[0077] Return to reference Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and Figure 1E, a gate dielectric pattern GI and a gate electrode GE may be formed in the empty space EP and the first to third cavities SA1, SA2, and SA3. Forming the gate dielectric pattern GI and the gate electrode GE may include conformally forming a gate dielectric layer in the empty space EP and the first to third cavities SA1, SA2, and SA3, and forming a gate electrode layer to completely fill the empty space EP and the first to third cavities SA1, SA2, and SA3. Portions of the gate electrode layer filling the first to third cavities SA1, SA2, and SA3 may serve as first to third portions GP1, GP2, and GP3 of the gate electrode GE, respectively.

[0078] A gate capping pattern GP may be formed on the gate electrode GE.

[0079] The third trench TR3 may be formed on the double diffusion barrier region DDB and the single diffusion barrier region SDB. Forming the third trench TR3 may include removing the gate electrode layer on the double diffusion barrier region DDB and removing portions of the gate electrode layer, the channel pattern CH, and the active patterns AP1, AP2, AP3, and AP4 on the single diffusion barrier region SDB. The diffusion barrier pattern DBP may fill the third trench TR3.

[0080] A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110, the gate capping pattern GP, and the diffusion barrier pattern DBP. First contacts CT1 may penetrate the first and second interlayer insulating layers 110 and 120 and be connected to the source / drain patterns SD1, SD2, SD3, and SD4. A third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120. Second contacts CT2, first and second conductive lines CL1 and CL2, and first to fourth power rails PW1, PW2, PW3, and PW4 may be formed in the third interlayer insulating layer 130.

[0081] Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A and Figure 8A A top view of a semiconductor device according to an embodiment is shown. Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B and Figure 8B Shown are the Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A and Figure 8A A cross-sectional view taken along line AA'. Figure 4C 、 Figure 5C 、 Figure 6C 、 Figure 7C and Figure 8C Shown are the Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A and Figure 8A For the sake of brevity of description, the above elements may be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0082] Reference Figure 4A 、 Figure 4B and Figure 4C The semiconductor device according to the present embodiment may include a fifth active pattern AP5, a sixth active pattern AP6, and a seventh active pattern AP7 defined in an upper portion of the substrate 100. The plurality of sixth active patterns AP6 may be between the pair of fifth active patterns AP5 and the pair of seventh active patterns AP7. For example, the pair of fifth active patterns AP5, the plurality of sixth active patterns AP6, and the pair of seventh active patterns AP7 may be sequentially arranged in the first direction D1.

[0083] The width of the fifth active pattern AP5 in the first direction D1 may be defined as a ninth width W9, the width of the sixth active pattern AP6 in the first direction D1 may be defined as a tenth width W10, and the width of the seventh active pattern AP7 in the first direction D1 may be defined as an eleventh width W11. The tenth width W10 may be greater than the ninth width W9. The tenth width W10 may be greater than the eleventh width W11. The ninth width W9 and the eleventh width W11 may be substantially equal to each other.

[0084] In one embodiment, such a structure can be repeated in a semiconductor device, wherein an active pattern having a relatively large width (i.e., the sixth active pattern AP6) is between a pair of active patterns having a relatively small width (i.e., the fifth active pattern AP5) and another pair of active patterns having a relatively small width (i.e., the seventh active pattern AP7).

[0085] One fifth active pattern AP5 and one seventh active pattern AP7 may be between each pair of adjacent insulating patterns IL, and a plurality of sixth active patterns AP6 may be between the one fifth active pattern AP5 and the one seventh active pattern AP7 (eg, see FIG. 1 ). Figure 4C ).

[0086] Each of the pair of fifth active patterns AP5 can be connected to a corresponding one of the first contacts CT1. For example, one fifth active pattern AP5 can be connected to one first contact CT1. A pair of sixth active patterns AP6 can be connected to a corresponding one of the first contacts CT1. For example, two sixth active patterns AP6 can be connected to one first contact CT1. Each of the pair of seventh active patterns AP7 can be connected to a corresponding one of the first contacts CT1. For example, one seventh active pattern AP7 can be connected to one first contact CT1.

[0087] Reference Figure 5A 、 Figure 5B and Figure 5C The semiconductor device according to the present embodiment may include eighth, ninth, tenth, and eleventh active patterns AP8, AP9, AP10, and AP11 defined in an upper portion of the substrate 100. The eighth to eleventh active patterns AP8, AP9, AP10, and AP11 may be sequentially arranged in the first direction D1.

[0088] The width of the eighth active pattern AP8 in the first direction D1 may be defined as a twelfth width W12, the width of the ninth active pattern AP9 in the first direction D1 may be defined as a thirteenth width W13, the width of the tenth active pattern AP10 in the first direction D1 may be defined as a fourteenth width W14, and the width of the eleventh active pattern AP11 in the first direction D1 may be defined as a fifteenth width W15. The thirteenth width W13 may be at least twice the twelfth width W12. The thirteenth width W13 may be at least twice the fifteenth width W15. The fourteenth width W14 may be at least twice the twelfth width W12. The fourteenth width W14 may be at least twice the fifteenth width W15. The twelfth width W12 and the fifteenth width W15 may be substantially equal to each other. The thirteenth width W13 and the fourteenth width W14 may be substantially equal to each other.

[0089] In one embodiment, such a structure can be repeated in a semiconductor device, wherein active patterns having relatively large widths (e.g., the ninth active pattern AP9 and the tenth active pattern AP10) are between an active pattern having relatively small widths (i.e., the eighth active pattern AP8) and another active pattern having relatively small widths (i.e., the eleventh active pattern AP11).

[0090] One eighth active pattern AP8, one ninth active pattern AP9, and one tenth active pattern AP10 may be between each pair of adjacent insulating patterns IL (eg, see FIG. 1 ). Figure 5C ).

[0091] When measured in the first direction D1, the shortest distance between the eighth active pattern AP8 and the ninth active pattern AP9 may be defined as a first distance L1. When measured in the first direction D1, the shortest distance between the tenth active pattern AP10 and the eleventh active pattern AP11 may be defined as a second distance L2. The second distance L2 may be at least twice the first distance L1.

[0092] The eighth active pattern AP8 may not vertically overlap the first power rail PW1. The first power rail PW1 may be connected to one eighth active pattern AP8. The ninth active pattern AP9 may vertically overlap the second power rail PW2. The tenth active pattern AP10 may vertically overlap the third power rail PW3. The eleventh active pattern AP11 may not vertically overlap the fourth power rail PW4. The fourth power rail PW4 may be connected to one eleventh active pattern AP11.

[0093] Reference Figure 6A 、 Figure 6B and Figure 6C The semiconductor device according to the present embodiment may include a twelfth active pattern AP12, a thirteenth active pattern AP13, a fourteenth active pattern AP14, a fifteenth active pattern AP15, and a sixteenth active pattern AP16 defined in an upper portion of the substrate 100. The twelfth to sixteenth active patterns AP12, AP13, AP14, AP15, and AP16 may be sequentially arranged in or along the first direction D1.

[0094] The width of the twelfth active pattern AP12 in the first direction D1 may be defined as a sixteenth width W16, the width of the thirteenth active pattern AP13 in the first direction D1 may be defined as a seventeenth width W17, the width of the fourteenth active pattern AP14 in the first direction D1 may be defined as an eighteenth width W18, the width of the fifteenth active pattern AP15 in the first direction D1 may be defined as a nineteenth width W19, and the width of the sixteenth active pattern AP16 in the first direction D1 may be defined as a twentieth width W20.

[0095] The sixteenth width W16, the eighteenth width W18, and the nineteenth width W19 may be substantially equal to each other. The seventeenth width W17 and the twentieth width W20 may be substantially equal to each other. The sixteenth width W16, the eighteenth width W18, and the nineteenth width W19 may be at least twice the seventeenth width W17 or the twentieth width W20.

[0096] When measured in the first direction D1, the shortest distance between the twelfth active pattern AP12 and the thirteenth active pattern AP13 may be defined as a third distance L3. When measured in the first direction D1, the shortest distance between the thirteenth active pattern AP13 and the fourteenth active pattern AP14 may be defined as a fourth distance L4. When measured in the first direction D1, the shortest distance between the fourteenth active pattern AP14 and the fifteenth active pattern AP15 may be defined as a fifth distance L5. When measured in the first direction D1, the shortest distance between the fifteenth active pattern AP15 and the sixteenth active pattern AP16 may be defined as a sixth distance L6.

[0097] The third distance L3 and the fifth distance L5 may be substantially equal to each other. The fourth distance L4 and the sixth distance L6 may be substantially equal to each other. The fourth distance L4 and the sixth distance L6 may be at least twice the third distance L3 or the fifth distance L5.

[0098] The twelfth active pattern AP12 may vertically overlap the first power rail PW1. The thirteenth active pattern AP13 may not vertically overlap the second power rail PW2. The fourteenth active pattern AP14 may vertically overlap the third power rail PW3. The fifteenth active pattern AP15 may vertically overlap the fourth power rail PW4. The sixteenth active pattern AP16 may not vertically overlap the fifth power rail PW5.

[0099] One fourteenth active pattern AP14 and one fifteenth active pattern AP15 may be between each pair of adjacent insulating patterns IL (eg, see Figure 6C ).

[0100] Each of the twelfth to sixteenth active patterns AP12, AP13, AP14, AP15, and AP16 may include a plurality of active fins AF. The active fins AF may be located in an upper portion of each of the twelfth to sixteenth active patterns AP12, AP13, AP14, AP15, and AP16 and may be spaced apart from each other in the first direction D1. A device isolation layer ST may be provided between the active fins AF. A void VO may be provided between the active fins AF and between the source / drain pattern SD and the device isolation layer ST. In one embodiment, the void VO may be filled with air.

[0101] The number of active fins AF in the thirteenth active pattern AP13 may be equal to the number of active fins AF in the sixteenth active pattern AP16. The number of active fins AF in the twelfth active pattern AP12, the number of active fins AF in the fourteenth active pattern AP14, and the number of active fins AF in the fifteenth active pattern AP15 may be the same. The number of active fins AF in the fourteenth active pattern AP14 may be at least twice the number of active fins AF in the thirteenth active pattern AP13. In one implementation, the number of active fins AF in the thirteenth active pattern AP13 may be two, and the number of active fins AF in the fourteenth active pattern AP14 may be six.

[0102] Reference Figure 7A 、 Figure 7B and Figure 7C , the semiconductor device according to the present embodiment may include seventeenth and eighteenth active patterns AP17 and AP18 defined in an upper portion of the substrate 100. The seventeenth and eighteenth active patterns AP17 and AP18 may be arranged in the first direction D1.

[0103] The width of the seventeenth active pattern AP17 in the first direction D1 may be defined as a twenty-first width W21, and the width of the eighteenth active pattern AP18 in the first direction D1 may be defined as a twenty-second width W22. The twenty-second width W22 may be at least twice the twenty-first width W21.

[0104] When measured in the first direction D1, the shortest distance between adjacent seventeenth active patterns among the seventeenth active patterns AP17 may be defined as a seventh distance L7. The shortest distance in the first direction D1 between the eighteenth active pattern AP18 and the seventeenth active pattern AP17 adjacent to a first side of the eighteenth active pattern AP18 may be defined as an eighth distance L8. The shortest distance in the first direction D1 between the eighteenth active pattern AP18 and the seventeenth active pattern AP17 adjacent to a second side of the eighteenth active pattern AP18 may be defined as a ninth distance L9. The first side and the second side may be opposite to each other.

[0105] The seventh distance L7 and the eighth distance L8 may be substantially equal to each other. The ninth distance L9 may be at least twice the seventh distance L7 or the eighth distance L8.

[0106] Each of the seventeenth active patterns AP17 may not vertically overlap with a corresponding one of the power rails PW. Each of the eighteenth active patterns AP18 may vertically overlap with a corresponding one of the power rails PW.

[0107] Three seventeenth active patterns AP17 and one eighteenth active pattern AP18 may be between each pair of adjacent insulating patterns IL (eg, see Figure 7C ).

[0108] In an implementation, a structure in which three active patterns having relatively small widths (ie, the seventeenth active pattern AP17 ) and one active pattern having a relatively large width (ie, the eighteenth active pattern AP18 ) are sequentially disposed may be repeated in a semiconductor device.

[0109] Reference Figure 8A 、 Figure 8B and Figure 8C , the semiconductor device according to the present embodiment may include nineteenth active patterns AP19 and twentieth active patterns AP20 defined in an upper portion of the substrate 100. The nineteenth active patterns AP19 and the twentieth active patterns AP20 may be alternately arranged in the first direction D1.

[0110] The width of the nineteenth active pattern AP19 in the first direction D1 may be defined as a twenty-third width W23, and the width of the twentieth active pattern AP20 in the first direction D1 may be defined as a twenty-fourth width W24. The twenty-fourth width W24 may be at least twice the twenty-third width W23.

[0111] The shortest distance between the twentieth active pattern AP20 and the nineteenth active pattern AP19 adjacent to the first side of the twentieth active pattern AP20 in the first direction D1 may be defined as a tenth distance L10. The shortest distance between the twentieth active pattern AP20 and the nineteenth active pattern AP19 adjacent to the second side of the twentieth active pattern AP20 in the first direction D1 may be defined as an eleventh distance L11. The first side and the second side may be opposite to each other. The tenth distance L10 may be at least twice the eleventh distance L11.

[0112] Each of the nineteenth active patterns AP19 may not vertically overlap with a corresponding one of the power rails PW. Each of the twentieth active patterns AP20 may vertically overlap with a corresponding one of the power rails PW.

[0113] One nineteenth active pattern AP19 and one twentieth active pattern AP20 may be between each pair of adjacent insulating patterns IL (eg, see Figure 8C ).

[0114] In an implementation, a structure in which an active pattern having a relatively small width (ie, the nineteenth active pattern AP19 ) and an active pattern having a relatively large width (ie, the twentieth active pattern AP20 ) are sequentially disposed may be repeated in a semiconductor device.

[0115] In one embodiment, the source / drain pattern SD on the nineteenth active pattern AP19 may be a p-type impurity region, and the source / drain pattern SD on the twentieth active pattern AP20 may be an n-type impurity region. For example, the width of the active pattern below the n-type impurity region may be at least twice the width of the active pattern below the p-type impurity region.

[0116] In an implementation, the source / drain pattern SD on the nineteenth active pattern AP19 may be an n-type impurity region, and the source / drain pattern SD on the twentieth active pattern AP20 may be a p-type impurity region.

[0117] Figures 9 to 12 FIG2 shows a semiconductor device according to some embodiments. Figure 9 The semiconductor device according to the present embodiment may include power rails sequentially arranged in a first direction D1. For example, the semiconductor device may include a first VDD rail VDD1, a VSS rail VSS, and a second VDD rail VDD2. The first VDD rail and the second VDD rail may be interconnects to which a drain voltage (Vdd) (e.g., a power supply voltage) is supplied, and the VSS rail may be an interconnect to which a source voltage (Vss) (e.g., a ground voltage) is supplied.

[0118] In one implementation, the semiconductor device may include first to fourth single active patterns SAP1-SAP4 sequentially arranged in the first direction D1. The first to fourth single active patterns SAP1-SAP4 may be active patterns locally placed in a region between rails but not under the rails. In one implementation, the first to fourth single active patterns SAP1-SAP4 may correspond to Figures 1A to 1D The first active pattern AP1 and the fourth active pattern AP4 are shown.

[0119] The first single-height cell SC1 may be between the first VDD rail VDD1 and the VSS rail VSS. The second single-height cell SC2 may be between the second VDD rail VDD2 and the VSS rail VSS. The first single-height cell SC1 may include a first single active pattern SAP1 and a second single active pattern SAP2, as well as gate electrodes and source / drain patterns on the first single active pattern SAP1 and the second single active pattern SAP2. The second single-height cell SC2 may include a third single active pattern SAP3 and a fourth single active pattern SAP4, as well as gate electrodes and source / drain patterns on the third single active pattern SAP3 and the fourth single active pattern SAP4. A PMOSFET region and an NMOSFET region may be between a pair of adjacent power rails. In one implementation, one of the PMOSFET region and the NMOSFET region may be between a pair of adjacent power rails, as in the filler cell described below.

[0120] Adjacent regions between which a power rail is disposed may have the same conductivity type. For example, a PMOSFET region, an NMOSFET region, an NMOSFET region, a PMOSFET region, a PMOSFET region, and an NMOSFET region may be sequentially disposed in the first direction D1. Each of the first single-height cell SC1 and the second single-height cell SC2 may include a first region RG1 and a second region RG2. The first region RG1 may be a PMOSFET region, and the second region RG2 may be an NMOSFET region. As an example, the first single active pattern SAP1 and the fourth single active pattern SAP4 may be active patterns on the PMOSFET region, and the second single active pattern SAP2 and the third single active pattern SAP3 may be active patterns on the NMOSFET region. The second region RG2 of the first single-height cell SC1 may be adjacent to the second region RG2 of the second single-height cell SC2.

[0121] Each of the first single-height cell SC1 and the second single-height cell SC2 may constitute a logic cell. In this specification, a logic cell may mean a logic device configured to perform a specific function (e.g., an inverter, a flip-flop, etc.). In one implementation, a logic cell may include a transistor (which constitutes a logic device and includes at least one active region, a source / drain region, and a gate electrode) and interconnect lines connecting the transistors to each other.

[0122] Reference Figure 10 The semiconductor device according to the present embodiment may include power rails sequentially arranged in a first direction D1. For example, the semiconductor device may include a first VDD rail VDD1, a VSS rail VSS, and a second VDD rail VDD2.

[0123] The semiconductor device according to the present embodiment may include a double height cell DHC on a substrate 100. The double height cell DHC may refer to a structure (e.g., including an active pattern, source / drain, or gate electrode) in a region between a first VDD rail VDD1 and a second VDD rail VDD2. The VSS rail VSS may span the double height cell DHC. The double height cell DHC may constitute a logic unit. When measured in a first direction D1, the double height cell DHC may have a width of Figure 9 The width of a logic cell may be defined as the maximum distance between power rails in the logic cell.

[0124] The double-height cell DHC may include a single active pattern SAP, a dual active pattern DAP, a gate electrode thereon, and source / drain patterns. The single active pattern SAP may be adjacent to the second VDD rail VDD2. In one implementation, the single active pattern SAP may be an active pattern on the first region RG1 (e.g., a PMOSFET region). In another implementation, the single active pattern SAP may be an active pattern on the NMOSFET region.

[0125] In one implementation, the double-height cell DHC may include a filler cell FI. The filler cell FI may be located near the first VDD rail VDD1. In one implementation, the filler cell FI may not be provided, and the single active pattern SAP may be located in the area designated for the filler cell FI. The dual active pattern DAP may vertically overlap the VSS rail VSS. The dual active pattern DAP may be located between the single active pattern SAP and the filler cell FI.

[0126] The dual active pattern DAP may be similar to a structure in which Figure 9 The second single active pattern SAP2 and the third single active pattern SAP3 adjacent to the VSS rail VSS in the semiconductor device are merged. The dual active pattern DAP may be an active pattern that overlaps the rail and extends to an area below the rail. In one implementation, the dual active pattern DAP may correspond to Figures 1A to 1D In one embodiment, the dual active pattern DAP may be an active pattern on the second region RG2 (e.g., an NMOSFET region) having a different conductivity type from the first region RG1. In one embodiment, the dual active pattern DAP may be an active pattern on the PMOSFET region.

[0127] The filler cell FI may be an area in which no active pattern is formed. For example, the filler cell FI may be a gate structure and / or a source / drain pattern formed on a device isolation layer. The filler cell FI may be a dummy structure formed to reduce process variations and not electrically connected to a logic cell or a rail adjacent thereto. In one implementation, in a semiconductor device according to an embodiment, wherein a Figure 9 No active pattern may be formed in a region of the first single active pattern SAP1 of the semiconductor device, and a filler unit FI may be provided in the region.

[0128] Reference Figure 11 The semiconductor device according to the present embodiment may include power rails sequentially arranged in a first direction D1. For example, the semiconductor device may include a first VDD rail VDD1, a first VSS rail VSS1, a second VDD rail VDD2, and a second VSS rail VSS2.

[0129] The semiconductor device according to the present embodiment may include a three-height cell THC on the substrate 100. The three-height cell THC may be between the first VDD rail VDD1 and the second VSS rail VSS2. The first VSS rail VSS1 and the second VDD rail VDD2 may span the three-height cell THC. The three-height cell THC may constitute a logic unit. When measured in the first direction D1, the three-height cell THC may have a width of Figure 9 The triple height cell THC may include a first filler cell FI1, a second filler cell FI2, a first dual active pattern DAP1, and a second dual active pattern DAP2. The first filler cell FI1 may be adjacent to the first VDD rail VDD1. The second filler cell FI2 may be adjacent to the second VSS rail VSS2. In one implementation, at least one of the filler cells FI1 and FI2 may not be provided, and a single active pattern SAP may be provided in the area for the filler cells FI1 and FI2.

[0130] The first dual active pattern DAP1 may vertically overlap the first VSS rail VSS1. The second dual active pattern DAP2 may vertically overlap the second VDD rail VDD2. The first dual active pattern DAP1 and the second dual active pattern DAP2 may correspond to Figures 1A to 1D The first dual active pattern DAP1 and the second dual active pattern DAP2 may be active patterns located in regions of different conductivity types. In one implementation, the first dual active pattern DAP1 may be an active pattern located in the second region RG2 (e.g., an NMOSFET region), and the second dual active pattern DAP2 may be an active pattern located in the first region RG1 (e.g., a PMOSFET region).

[0131] Reference Figure 12 The semiconductor device according to the present embodiment may include first to seventh power rails sequentially arranged in the first direction D1. For example, the semiconductor device may include a first VSS rail VSS1, a first VDD rail VDD1, a second VSS rail VSS2, a second VDD rail VDD2, a third VSS rail VSS3, a third VDD rail VDD3, and a fourth VSS rail VSS4.

[0132] The semiconductor device according to this embodiment may include a first logic cell, a second logic cell, and a third logic cell sequentially arranged in a first direction D1 on a substrate 100. Each of the first logic cell, the second logic cell, and the third logic cell may include a PMOSFET region and an NMOSFET region. The first logic cell may be a single-height cell SC between a first VSS rail VSS1 and a first VDD rail VDD1 and including a pair of single active patterns SAP. The single active pattern SAP adjacent to the first VSS rail VSS1 may be located in the second region RG2 (e.g., the NMOSFET region), and the single active pattern SAP adjacent to the first VDD rail VDD1 may be located in the first region RG1 (e.g., the PMOSFET region).

[0133] The second logic cell may be a double-height cell DHC including a dual active pattern DAP between the first VDD rail VDD1 and the second VDD rail VDD2. The dual active pattern DAP may be between the first VDD rail VDD1 and the second VDD rail VDD2 and may extend to an area below the second VSS rail VSS2. For example, the dual active pattern DAP may vertically overlap the second VSS rail VSS2. The width of the dual active pattern DAP in the first direction D1 may be two to three times the width of a single active pattern SAP in the first direction D1. The dual active pattern DAP may be located in the second region RG2 (e.g., an NMOSFET region).

[0134] The double height cell DHC may include a single active pattern SAP adjacent to the first VDD rail VDD1 and the second VDD rail VDD2. The single active pattern SAP may be on the first region RG1 (eg, the PMOSFET region). At least one of the single active patterns SAP may be replaced by a filler cell FI.

[0135] The third logic cell may be on the substrate 100. The third logic cell may be spaced apart from the second logic cell in the first direction D1. The third logic cell may be a triple height cell THC, which includes a first dual active pattern DAP1 and a second dual active pattern DAP2 between the second VDD rail VDD2 and the fourth VSS rail VSS4. The first dual active pattern DAP1 may be below the third VSS rail VSS3, and the second dual active pattern DAP2 may be below the third VDD rail VDD3. The first dual active pattern DAP1 may be on the second region RG2 (e.g., an NMOSFET region), and the second dual active pattern DAP2 may be on the first region RG1 (e.g., a PMOSFET region). The width of each of the dual active patterns DAP1 and DAP2 in the first direction D1 may be two to three times the width of a single active pattern SAP in the first direction D1.

[0136] The triple-height cell THC may include a single active pattern SAP adjacent to the second VDD rail VDD2 and the fourth VSS rail VSS4. The single active pattern SAP adjacent to the second VDD rail VDD2 may be located in the first region RG1 (e.g., a PMOSFET region). The single active pattern SAP adjacent to the fourth VSS rail VSS4 may be located in the second region RG2 (e.g., an NMOSFET region). At least one of the single active patterns SAP may be replaced by a filler cell FI.

[0137] In summary and review, with the development of the electronics industry, there is a growing demand for semiconductor devices with improved characteristics. For example, semiconductor devices can have high reliability, high performance, and / or multi-functions. The complexity and / or integration density of semiconductor devices can be increased.

[0138] One or more embodiments may provide a semiconductor device including a gate-all-around transistor.

[0139] One or more embodiments may provide a semiconductor device in which a gate-all-around type transistor having improved electrical characteristics is provided.

[0140] Example embodiments have been disclosed herein, and although specific terms are employed, they will be used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art at the time of filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly indicated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0141] Korean Patent Application No. 10-2019-0102583, filed on August 21, 2019, in the Korean Intellectual Property Office and entitled “Semiconductor Device,” is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device comprising: substrate; at least one first active pattern, at least one second active pattern, and at least one third active pattern on an upper portion of the substrate, the at least one first active pattern, the at least one second active pattern, and the at least one third active pattern being sequentially arranged in a first direction and extending in a second direction crossing the first direction; a first power rail connected to the at least one first active pattern; a second power rail connected to the at least one second active pattern; as well as a third power rail connected to the at least one third active pattern, in: The width of the at least one second active pattern in the first direction is at least twice the width of the at least one first active pattern in the first direction, and at least twice the width of the at least one third active pattern in the first direction, the at least one first active pattern does not vertically overlap the first power rail, The at least one second active pattern vertically overlaps the second power rail, and The at least one third active pattern does not vertically overlap the third power rail. 2 . The device of claim 1 , wherein the at least one second active pattern comprises a plurality of second active patterns.

3. The device according to claim 1 , further comprising channel patterns provided on the at least one first active pattern, the at least one second active pattern, and the at least one third active pattern, respectively. in: Each of the channel patterns includes a first semiconductor pattern and a second semiconductor pattern stacked in a third direction perpendicular to the first direction and the second direction, and When measured in the first direction, a width of the channel pattern on the at least one second active pattern is at least twice a width of the channel pattern on the at least one first active pattern and at least twice a width of the channel pattern on the at least one third active pattern.

4. The device according to claim 1, further comprising: a fourth active pattern between the at least one second active pattern and the at least one third active pattern; a first source / drain pattern on the at least one second active pattern; as well as a second source / drain pattern on the fourth active pattern, in: The width of the at least one second active pattern in the first direction is substantially equal to the width of the fourth active pattern in the first direction, and The first source / drain pattern and the second source / drain pattern have different conductivity types from each other.

5. The device according to claim 4, further comprising a third source / drain pattern on the at least one first active pattern, in: The width of the first source / drain pattern in the first direction is at least twice the width of the third source / drain pattern in the first direction, and A width of the second source / drain pattern in the first direction is at least twice the width of the third source / drain pattern in the first direction. 6 . The device of claim 4 , wherein a shortest distance between the at least one third active pattern and the fourth active pattern in the first direction is at least twice a shortest distance between the at least one first active pattern and the at least one second active pattern in the first direction. 7 . The device of claim 1 , wherein the at least one first active pattern comprises a pair of first active patterns connected to the first power rail.

8. The device according to claim 7, further comprising: a gate electrode extending in the first direction; as well as an insulating pattern separating the gate electrodes from each other in the first direction, The insulating pattern is between the pair of first active patterns. 9 . The device of claim 7 , wherein the at least one third active pattern comprises a pair of third active patterns connected to the third power rail.

10. The device according to claim 1, further comprising: a first source / drain pattern on the at least one first active pattern; as well as a second source / drain pattern on the at least one third active pattern, The first source / drain pattern and the second source / drain pattern have different conductivity types from each other. 11 . The device of claim 1 , wherein each of the at least one first active pattern, the at least one second active pattern, and the at least one third active pattern includes an active fin in an upper portion thereof.

12. A semiconductor device comprising: substrate; a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern sequentially arranged on an upper portion of the substrate and in a first direction; a first source / drain pattern, a second source / drain pattern, a third source / drain pattern, and a fourth source / drain pattern on the first active pattern, the second active pattern, the third active pattern, and the fourth active pattern, respectively; a gate electrode crossing the first active pattern, the second active pattern, the third active pattern, and the fourth active pattern and extending in the first direction; as well as a first power rail, a second power rail, a third power rail, and a fourth power rail respectively connected to the first source / drain pattern, the second source / drain pattern, the third source / drain pattern, and the fourth source / drain pattern, the first power rail, the second power rail, the third power rail, and the fourth power rail extending in a second direction intersecting the first direction, in: The width of the second active pattern in the first direction is at least twice the width of the first active pattern in the first direction, The width of the third active pattern in the first direction is at least twice the width of the first active pattern in the first direction, The width of the second active pattern in the first direction is at least twice the width of the fourth active pattern in the first direction, The width of the third active pattern in the first direction is at least twice the width of the fourth active pattern in the first direction, the first active pattern does not vertically overlap the first power rail, the second active pattern vertically overlaps the second power rail, The third active pattern vertically overlaps the third power rail, and The fourth active pattern does not vertically overlap the fourth power rail. 13 . The device of claim 12 , wherein the width of the first active pattern in the first direction is substantially equal to the width of the fourth active pattern in the first direction.

14. The device according to claim 12, wherein: The shortest distance between the first active pattern and the second active pattern in the first direction is at least twice the shortest distance between the second active pattern and the third active pattern in the first direction, and A shortest distance between the third active pattern and the fourth active pattern in the first direction is at least twice the shortest distance between the second active pattern and the third active pattern in the first direction. 15 . The device of claim 12 , wherein a shortest distance between the first active pattern and the second active pattern in the first direction is substantially equal to a shortest distance between the third active pattern and the fourth active pattern in the first direction.

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