Method of forming a semiconductor device

Abstract

A semiconductor device and a method of forming the semiconductor device are provided herein, and the semiconductor device includes source / drain regions having a V-shaped lower surface and extending under a gate spacer adjacent to a gate stack. In one embodiment, the method includes forming a gate stack on a fin; forming gate spacers on sidewalls of the gate stack; etching the fin by an anisotropic first etching process to form a first recess adjacent to the gate spacer; etching the fin by a second etching process to remove an etch residue from the first recess, and the second etching process uses an etchant different from that used in the first etching process; etching a surface of the first recess by an anisotropic third etching process to form a second recess, the second recess extending under the gate spacer and having a V-shaped lower surface, and the third etching process uses an etchant different from that used in the first etching process; and epitaxially forming source / drain regions in the second recess.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly to improved source / drain regions and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication process of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layer materials on a semiconductor substrate, and patterning the various material layers using lithography to form electronic components and cells thereon.

[0003] The semiconductor industry continues to shrink the minimum feature size to continuously improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, or the like), enabling more components to be integrated into a given area. However, as the minimum feature size shrinks, additional problems arise that need to be solved. Summary of the Invention

[0004] A method of forming a semiconductor device according to an embodiment of the present invention includes forming a gate stack on a fin extending from a substrate; forming gate spacers on sidewalls of the gate stack; etching the fin by a first etching process to form a first recess adjacent to the gate spacers, wherein the first etching process is anisotropic; etching the fin by a second etching process to remove etch residues from the first recess, and the second etching process uses an etchant different from that used in the first etching process; etching a surface of the first recess by a third etching process to form a second recess, the second recess extending under the gate spacers in a direction perpendicular to a major surface of the substrate, and the second recess having a V-shaped lower surface, wherein the third etching process is anisotropic along a crystal plane of the substrate and the third etching process uses an etchant different from that used in the first etching process; and epitaxially forming source / drain regions in the second recess.

[0005] A semiconductor device according to an embodiment of the present invention includes: a fin extending from a substrate; a gate stack located on the fin; gate spacers located on sidewalls of the gate stack; and source / drain regions located in the fin adjacent to the gate spacers, the source / drain regions having a V-shaped lower surface in a (111) crystal plane, the source / drain regions extending under the gate spacers in a direction parallel to the major surface of the substrate and in a (110) crystal plane, wherein the source / drain regions extend at least 4 nm to 8 nm under the gate spacers in a depth of 20 nm to 30 nm and in a direction parallel to the major surface of the substrate.

[0006] A method for forming a semiconductor device according to an embodiment of the present invention includes: forming fins in a semiconductor substrate; forming dummy gate stacks on the fins; etching the fins adjacent to the dummy gate stacks using a first etching process to form a first recess, the first etching process anisotropically etching the fins, and the etching direction being perpendicular to the main surface of the semiconductor substrate; after etching the fins using the first etching process, removing the etching residues from the first recess; etching the first recess using a second etching process to form a second recess, the second etching process being anisotropic along the (111) crystal plane and along the (110) crystal plane; forming source / drain regions in the second recess; and replacing the dummy gates with gate stacks. Description of the Drawings

[0007] Figure 1 is a three-dimensional view of a fin field-effect transistor in some embodiments.

[0008] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 19A 、 Figure 19B 、 Figure 20A 、and Figure 20B is a cross-sectional view of an intermediate stage of forming a fin field-effect transistor in some embodiments.

[0009] Figure 13A and Figure 13B is a schematic diagram of a system for performing a plasma cleaning process in some embodiments.

[0010] Description of the Reference Numerals:

[0011] θ1: Angle

[0012] A-A, B-B, C-C: Sections

[0013] D1: Distance

[0014] D2, D3: Depth

[0015] D4: Diameter

[0016] 50: Substrate

[0017] 50N, 50P: Regions

[0018] 51: Separation line

[0019] 52: Fin

[0020] 54: Insulating material

[0021] 56: Shallow trench isolation region

[0022] 58: Channel region

[0023] 60: dummy dielectric layer

[0024] 62: dummy gate layer

[0025] 64: Mask layer

[0026] 72: dummy gate

[0027] 74: Mask

[0028] 80: Gate seal spacer

[0029] 82: Epitaxial source / drain region

[0030] 86: Gate spacer

[0031] 87: Contact etch stop layer

[0032] 88: First interlayer dielectric layer

[0033] 89: Region

[0034] 90, 102, 103: Depressions

[0035] 92: Gate dielectric layer

[0036] 94: Gate

[0037] 94A: Buffer layer

[0038] 94B: Work function adjustment layer

[0039] 94C: Filling material

[0040] 96: Gate mask

[0041] 104: Etching residue

[0042] 108: The second interlayer dielectric layer

[0043] 110: Gate contact

[0044] 112: Source / drain contact

[0045] 200: Etching system

[0046] 203: Process chamber

[0047] 205: First supply system

[0048] 207: Second supply system

[0049] 209: Gas supplier

[0050] 211: Gas flow controller

[0051] 213: Gas controller

[0052] 215: Control unit

[0053] 219: Manifold

[0054] 221: Duct

[0055] 223: Plasma generation chamber

[0056] 225: Housing

[0057] 227: Exhaust outlet

[0058] 229: Vacuum pump

[0059] 231: Spraying head

[0060] 233: Gas distribution plate

[0061] 235, 235a, 235b, 235c: Opening

[0062] 237: Mounting platform

[0063] 239: First electrode

[0064] 241: Second radio frequency generator

[0065] 243: First radio frequency generator Detailed implementation manners

[0066] The following different embodiments or examples provided can implement different structures of the present invention. The embodiments of the following specific components and arrangements are used to simplify the content of the present invention rather than limit the present invention. For example, the description of forming a first component on a second component includes embodiments where the two are in direct contact, or embodiments where there are other additional components between the two rather than in direct contact. In addition, in the embodiments of the present invention, a structure is formed on another structure, connected to another structure, and / or coupled to another structure. The structure can be in direct contact with another structure, or additional structures can be formed between the structure and another structure (i.e., the structure is not in contact with another structure). In addition, multiple examples of the present invention may reuse the same reference numerals for simplicity, but the elements with the same reference numerals in multiple embodiments and / or settings do not necessarily have the same corresponding relationships.

[0067] In addition, spatial relative terms such as "below", "beneath", "lower", "above", "upper", or similar terms can be used to simplify the description of the relative relationship between one element and another element in the drawings. The spatial relative terms can extend to elements used in other directions, not limited to the directions in the drawings. The element can also be rotated 90° or other angles, so the directional terms are only used to illustrate the directions in the drawings.

[0068] Multiple embodiments provide improved source / drain regions for semiconductor devices and methods for forming the same. The method for forming the source / drain regions can be to etch a recess in a semiconductor fin using an anisotropic etching process, remove the etch residues from the recess using ammonia-based etching, and expand the recess using hydrogen-based plasma etching. The completed recess can have a V-shaped lower surface and can extend under the gate spacer. Then, source / drain regions are formed in the recesses. The semiconductor device including such source / drain regions can have an improved difference between the on-current and off-current (such as increasing the on-current and decreasing the off-current), a reduced drain-induced barrier lowering effect, fewer device defects, and overall improved device performance.

[0069] Figure 1 is a three-dimensional view of a fin field-effect transistor in some embodiments. The fin field-effect transistor includes a fin 52 on a substrate 50 (such as a semiconductor substrate). Shallow trench isolation regions 56 are located in the substrate 50, and the fin 52 is formed between adjacent shallow trench isolation regions 56 and protrudes above the shallow trench isolation regions 56. Although the shallow trench isolation regions 56 and the substrate 50 are shown separately in the drawings and the description, the term "substrate" used herein can be regarded as only a semiconductor substrate or a semiconductor substrate containing isolation regions. In addition, although the fin 52 in the drawings is a single continuous material such as the substrate 50, the fin 52 and / or the substrate 50 can include a single material or multiple materials. In this case, the fin 52 can be regarded as the part extending between adjacent shallow trench isolation regions 56.

[0070] The gate dielectric layer 92 is along the sidewalls and the upper surface of the fin 52, and the gate 94 is located on the gate dielectric layer 92. The epitaxial source / drain regions 82 are located on both sides of the fin 52 with respect to the gate dielectric layer 92 and the gate 94. Figure 1 Also shown are the reference cross-sections used in the subsequent figures. Cross-section A-A is along the longitudinal axis of the gate 94 and its direction is perpendicular to the current direction between the epitaxial source / drain regions 82 of the fin field-effect transistor. Cross-section B-B is perpendicular to cross-section A-A and along the longitudinal axis of the fin 52, and its direction is the current direction between the epitaxial source / drain regions 82 of the fin field-effect transistor. Cross-section C-C is parallel to cross-section A-A and extends through the source / drain regions of the fin field-effect transistor. The subsequent figures can be based on these reference cross-sections to make the figures clear.

[0071] Some of the embodiments described herein for forming a fin field-effect transistor employ a gate-last process. In other embodiments, a gate-first process can be used. In addition, some embodiments can be used for planar devices such as planar field-effect transistors.

[0072] Figures 2 to 12B and Figures 14A to 20B are cross-sectional views of intermediate stages of forming a fin field-effect transistor in some embodiments. Figures 2 to 7 Along Figure 1 the reference cross-section A-A shown, with the difference being multiple fins or fin field-effect transistors. Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、and Figure 20A Along Figure 1 the reference cross-section A-A shown, while Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 18C 、 Figure 19B 、and Figure 20B Along Figure 1 a similar cross-section B-B shown, with the difference being multiple fins or fin field-effect transistors. Figure 14C and Figure 14D Along Figure 1 the reference cross-section C-C shown, with the difference being multiple fins or fin field-effect transistors.

[0073] In Figure 2 , a substrate 50 is provided. The substrate 50 can be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator substrate, or the like, which can be doped (such as doped with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer can be a buried oxide layer, a silicon oxide layer, or the like. The insulating layer can be provided on the substrate, typically a silicon substrate or a glass substrate. Other substrates such as a multi-layer substrate or a compositionally graded substrate can also be used. In some embodiments, the semiconductor material of the substrate 50 can include silicon, germanium, semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon-germanium, gallium phosphoarsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium phosphide, and / or gallium phosphoindium arsenide), or a combination of the above.

[0074] The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form n-type devices such as n-type metal-oxide semiconductor transistors (such as n-type fin field-effect transistors). The region 50P can be used to form p-type devices such as p-type transistors (such as p-type fin field-effect transistors). The region 50N and the region 50P are physically separated (as shown by the separation line 51), and there can be any number of device structures (such as other active devices, doped regions, isolation structures, or the like) between the region 50N and 50P.

[0075] In Figure 3 , fins 52 are formed on the substrate 50. The fins 52 can be semiconductor strips. In some embodiments, trenches can be etched in the substrate 50 to form the fins 52 in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching, neutral beam etching, similar methods, or a combination of the above. The etching can be anisotropic.

[0076] The fins can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the fins, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography with self-alignment processes, which produce a pattern pitch smaller than that obtained by using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed along the sides of the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and the remaining spacers can be used to pattern the fins. In some embodiments, a mask (or another layer) can be retained on the fins 52.

[0077] In Figure 4In [description], an insulating material 54 is formed between the substrate 50 and the adjacent fin 52. The insulating material 54 can be an oxide such as silicon oxide, a nitride, the like, or a combination of the above, and the forming method thereof can be high density plasma chemical vapor deposition, flowable chemical vapor deposition (such as depositing a chemical vapor deposition-based material in a remote plasma system and then curing the material to transform it into another material such as an oxide), the like, or a combination of the above. Other insulating materials formed by any acceptable process can also be used. In the described embodiment, the insulating material 54 is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material 54 is formed such that the excess insulating material 54 covers the fin 52. Although the insulating material 54 in the drawings is a single layer, some embodiments can use a multi-layer insulating material 54. For example, in some embodiments, a liner layer (not specifically illustrated) can be formed first along the surfaces of the substrate 50 and the fin 52. Then a filling material can be formed thereon as described above.

[0078] In Figure 5 [description], a removal process is applied to the insulating material 54 to remove the excess insulating material 54 on the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing, a re-etching process, a combination of the above, or a similar process can be used. The planarization process exposes the fin 52, so that the fin 52 can be flush with the upper surface of the insulating material 54 after the planarization process is completed. In an embodiment where a mask remains on the fin 52, the planarization process can expose the mask or remove the mask, so that the upper surface of the mask or the fin 52 after the planarization process is completed is flush with the upper surface of the insulating material 54.

[0079] In Figure 6 [description], the insulating material 54 is recessed to form a shallow trench isolation region 56. Since the insulating material 54 is recessed, the upper side portions of the fins 52 in the regions 50N and 50P protrude between the adjacent shallow trench isolation regions 56. In addition, the upper surface of the shallow trench isolation region 56 can have a flat surface as shown, a convex surface, a concave surface (such as a dish shape), or a combination of the above. The upper surface of the shallow trench isolation region 56 can be flat and / or recessed (caused by appropriate etching). The method of recessing the shallow trench isolation region 56 can use an acceptable etching process, such as an etching process selective to the insulating material 54 (the etching rate of which for the insulating material is greater than the etching rate for the material of the fin 52). For example, the method of removing an oxide can use dilute hydrofluoric acid.

[0080] Figures 2 to 6The process shown is merely an example of how to form the fin 52. In some embodiments, the method of forming the fin 52 can be an epitaxial growth process. For example, a dielectric layer can be formed on the upper surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure can be epitaxially grown in the trenches and the dielectric layer can be recessed, so that the homoepitaxial structure protrudes from the dielectric layer to form the fin 52. In addition, a heteroepitaxial structure in some embodiments can be used for the fin 52. For example, Figure 5 the fin 52 therein can be recessed, and other materials different from the material of the fin 52 can be epitaxially grown on the recessed fin 52. In these embodiments, the fin 52 includes the recessed material, and the epitaxially grown material is located on the recessed material. In another embodiment, a dielectric layer can be formed on the upper surface of the substrate 50, and trenches can be etched through the dielectric layer. Then a heteroepitaxial structure with a material different from the substrate 50 can be epitaxially grown in the trenches and the dielectric layer can be recessed, so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In embodiments of epitaxially growing a homoepitaxial structure or a heteroepitaxial structure, the epitaxially grown material can be in-situ doped during growth, which can omit implantation before or after. However, in-situ doping and implantation doping can also be used in combination.

[0081] In addition, it is advantageous that the material grown in the region 50N (such as an n-type metal oxide semiconductor region) is different from the material in the region 50P (such as a p-type metal oxide semiconductor region). In various embodiments, the composition of the upper side portion of the fin 52 can be silicon germanium (Si x Ge 1-x , where x can be from 0 to 1), silicon carbide, pure germanium or substantially pure germanium, III-V semiconductor compounds, II-VI semiconductor compounds, or the like. For example, viable materials for forming III-V semiconductor compounds include but are not limited to indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, or the like.

[0082] In Figure 6 , suitable wells (not shown) can also be formed in the fin 52 and / or the substrate 50. In some embodiments, a p-well can be formed in the region 50N, and an n-well can be formed in the region 50P. In some embodiments, a p-well (or n-well) can be formed in both the region 50N and the region 50P.

[0083] In embodiments with different well configurations, a photoresist or other mask (not shown) may be employed to achieve different implantation steps for regions 50N and 50P. For example, a photoresist may be formed on the shallow trench isolation regions 56 and fins 52 in region 50N. The photoresist is patterned to expose region 50P (such as a p-type metal oxide semiconductor region) of the substrate 50. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity may be implanted in region 50P, and the photoresist serves as a mask to substantially prevent the n-type impurity from being implanted into region 50N (such as an n-type metal oxide semiconductor region). The n-type impurity may be phosphorus, arsenic, antimony, or the like, and the concentration implanted into the region is less than or equal to 10 18 cm -3 , such as between about 10 16 cm -3 and about 10 18 cm -3 . After implantation, the photoresist may be removed, and the removal method may be an acceptable ashing process.

[0084] After implanting region 50P, a photoresist may be formed on the shallow trench isolation regions 56 and fins 52 in region 50P. The photoresist is patterned to expose region 50N (such as an n-type metal oxide semiconductor region) of the substrate 50. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity may be implanted in region 50N, and the photoresist serves as a mask to substantially prevent the p-type impurity from being implanted into region 50P (such as a p-type metal oxide semiconductor region). The p-type impurity may be boron, boron fluoride, indium, or the like, and the concentration implanted into the region is less than or equal to 10 18 cm -3 , such as between about 10 16 cm -3 and about 10 18 cm -3 . After implantation, the photoresist may be removed, and the removal method may be an acceptable ashing process.

[0085] After implanting regions 50N and 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material may be in-situ doped during the growth of the epitaxial fins, which may obviate the need for implantation. However, in-situ doping and implantation doping may be used in combination.

[0086] In Figure 7In [the figure], a dummy dielectric layer 60 is formed on the fin 52. For example, the dummy dielectric layer 60 can be silicon oxide, silicon nitride, a combination of the above, or the like, and the dummy dielectric layer 60 can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60, and then the dummy gate layer 62 is planarized by processes such as chemical mechanical polishing. The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material, which can be amorphous silicon, polysilicon, polycrystalline silicon germanium, metal nitride, metal silicide, metal oxide, or metal. The deposition method of the dummy gate layer 62 can be physical vapor deposition, chemical vapor deposition, sputtering deposition, or other known techniques used in the art for depositing selected materials. The composition of the dummy gate layer 62 can be other materials with high etch selectivity when etching the isolation region. For example, the mask layer 64 can include silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed in regions 50N and 50P. It should be noted that the dummy dielectric layer 60 only covers the fin 52 in the drawing, but this configuration is for illustrative purposes only. In some embodiments, the dummy dielectric layer 60 can be deposited so that the dummy dielectric layer 60 covers the shallow trench isolation region 56 (extending between the dummy gate layer 62 and the shallow trench isolation region 56).

[0087] Figures 8A to 12B And Figures 14A to 20B Shows a variety of additional steps for forming the device of the embodiment. Figures 8A to 12B And Figures 14A to 20B Shows the structures in regions 50N and 50P. For example, Figures 8A to 12B And Figures 14A to 20B The structures shown can be used in regions 50N and 50P. If there are any differences in the structures of regions 50N and 50P, these differences will be described with the accompanying drawings.

[0088] In Figure 8A And Figure 8B In [the figure], acceptable photolithography and etching techniques can be used to pattern the mask layer 64 (see Figure 7 ) to form a mask 74. Acceptable etching techniques can be used to transfer the pattern of the mask 74 to the dummy gate layer 62 to form a dummy gate 72. In some embodiments, the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60. The dummy gate 72 covers the individual channel regions 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each of the dummy gates 72 from adjacent dummy gates. The longitudinal direction of the dummy gate 72 can also be substantially perpendicular to the longitudinal direction of the individual epitaxial fins.

[0089] In Figure 8A And Figure 8BIn [the above], a gate seal spacer 80 can be formed on the exposed surfaces of the dummy gate 72, the mask 74, and / or the fin 52. After thermal oxidation or deposition, anisotropic etching can be performed to form the gate seal spacer 80. The composition of the gate seal spacer 80 can be silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0090] After forming the gate seal spacer 80, implantation for the lightly doped source / drain regions can be performed. In embodiments of different device configurations, a mask such as photoresist can be formed on the region 50N and the region 50P can be exposed, similar to the above-described implantation shown, and impurities of a suitable type (such as p-type) can be implanted into the fins 52 exposed in the region 50P. Then the mask can be removed. After that, a mask such as photoresist can be formed on the region 50P and the region 50N can be exposed, and impurities of a suitable type (such as n-type) can be implanted into the fins 52 exposed in the region 50N. Then the mask can be removed. The n-type impurities can be any of the aforementioned n-type impurities, and the p-type impurities can be any of the aforementioned p-type impurities. The impurity concentration of the lightly doped source / drain regions can be about 10 Figure 6 shown above. 15 cm -3 to about 10 19 cm -3 . Annealing can be used to repair implantation damage and activate the implanted impurities.

[0091] In Figure 9A and Figure 9B , a gate spacer 86 is formed on the gate seal spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The method of forming the gate spacer 86 can be conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination of the above, or the like.

[0092] It should be noted that the above generally describes the processes of forming spacers and lightly doped source / drain regions. Other processes and sequences can also be used. For example, fewer or more spacers can be used or different step sequences can be employed, such as not etching the gate seal spacer 80 to obtain an L-shaped gate seal spacer before forming the gate spacer 86, forming and removing spacers, and / or similar methods. In addition, different structures or steps can be used to form n-type and p-type devices. For example, the lightly doped source / drain region for the n-type device can be formed before forming the gate seal spacer 80, and the lightly doped source / drain region for the p-type device can be formed after forming the gate seal spacer 80.

[0093] Figures 10A to 12B Shows the process of forming a recess 102 (see Figure 12B ) in the fin 52 between adjacent dummy gates 72. In Figure 10A andFigure 10B In this case, a recess 103 is formed in the fin 52. The recess 103 may extend between adjacent gate spacers 86. The method of etching the recess 103 may employ a suitable etching process, such as an anisotropic dry etching process using the gate spacers 86, gate seal spacers 80, and mask 74 as a combined mask. In some embodiments, the method of etching the recess 103 may employ reactive ion etching, neutral beam etching, a combination of the above, or the like. In some embodiments where the recess 103 is formed by reactive ion etching, process parameters such as the process gas mixture, bias voltage, or radio frequency power may be selected such that the etching is mainly physical etching such as ion bombardment rather than chemical etching such as radical etching via chemical reactions. In some embodiments, the bias voltage may be increased to increase the ion energy used in the ion bombardment process and increase the physical etching rate. Since physical etching is anisotropic and chemical etching is isotropic, the etching rate in the vertical direction of this etching process is greater than that in the lateral direction. In some embodiments, a process gas mixture containing fluoromethane, methane, hydrogen bromide, oxygen, argon, a combination of the above, or the like may be used for the anisotropic etching process.

[0094] As Figure 10B shown, the recess 103 may have a U-shaped lower surface. After etching the recess, etch residues 104 may remain on the surface of the recess 103. The etch residues 104 may include native oxides and carbon residues formed along the surface of the recess 103. The thickness of the etch residues 104 may be from about 0.1 nm to about 1 nm. After forming the epitaxial source / drain regions 82, if the etch residues 104 are present in the completed device, it may increase the resistance and cause defects. Thus, it is necessary to remove the etch residues 104.

[0095] In Figure 11A and Figure 11BIn [the above], a first etching process can be used to remove the etch residue 104 from the recess 103. In some embodiments, the first etching process can use ammonia gas, nitrogen trifluoride, a combination of the above, or the like, and can include a carrier gas such as helium gas or the like. In some examples, the first etching process can reduce or remove the carbon residue and native oxide of the etch residue formed on the sidewall and / or the lower surface of the recess 103. The ammonia gas flow rate during the first etching process can be about 100 sccm to about 200 sccm, the nitrogen trifluoride flow rate during the first etching process can be about 10 sccm to about 50 sccm, and the carrier gas flow rate during the first etching process can be about 100 sccm to about 500 sccm. The temperature of the first etching process can be about 100 °C to about 200 °C. The pressure of the first etching process is about 1 Torr to about 5 Torr. The time of the first etching process is sufficient to physically clean the etch residue 104 from the recess 103. For example, the first etching process in some embodiments lasts about 10 seconds to about 50 seconds. A short first etching process can reduce the risk of damaging the recess 103 or the profile of the dummy gate 72 during the first etching process. The etchant and etching parameters used in the first etching process can be different from Figure 10A and Figure 10B the etchant and etching parameters used in forming the recess 103 as described above. Removing the etch residue 104 can reduce the resistance of the subsequently formed epitaxial source / drain region 82 and reduce the defects of the final device containing the epitaxial source / drain region 82.

[0096] In Figure 12A and Figure 12B [the above], a second tool is used to expand the recess 103 to form the recess 102. The fin 52 is exposed to a second etching process to expand the recess 103. The second etching process exposes the fin 52 to hydrogen radicals (H·) to remove a part of the fin 52. Exposing the fin 52 to hydrogen radicals can increase the hydrogen concentration in the fin 52, such that after the fin 52 is exposed to the second etching process, the hydrogen concentration in the fin 52 adjacent to the recess 102 is about 5x10 18 atoms / cm 3 to about 5x10 19 atoms / cm 3 . For example, the method of forming hydrogen radicals can be to flow hydrogen gas into a plasma generation chamber (such as the plasma generation chamber 223 shown in Figure 13A ) and ignite the plasma in the plasma generation chamber 223. In some embodiments, an additional gas such as argon can be ignited in the plasma generation chamber 223. In some embodiments, the substrate 50 can be placed in a process chamber (such as Figure 13Athe process chamber 203 shown, and the plasma generation chamber 223 can be a separate chamber connected to the process chamber 203. In this way, the generated plasma can be remote plasma. An example of a system for performing the second etching process will be described in conjunction with Figure 13A and Figure 13B as follows. The tool for performing the second etching process can be the same as or different from the tool for performing the first etching process. In some embodiments, the same etchant and process parameters can be used for the first etching process and the second etching process. In addition, the etchant and process parameters used for the first etching process and the second etching process can be different from the etchant and process parameters used for forming the recess 103, such as described in conjunction with Figure 10A and Figure 10B . In other embodiments, the first etching process can be performed as appropriate, and the second etching process can be used to remove the etch residue 104 and expand the recess 103 to form the recess 102.

[0097] In the second etching process, the hydrogen gas flow rate into the plasma generation chamber (such as Figure 13A the plasma generation chamber 223 shown) can be from about 50 sccm to about 200 sccm, and the carrier gas flow rate into the plasma generation chamber can be from about 100 sccm to about 500 sccm. The power applied to the plasma generation chamber can be from about 20 W to about 400 W, and its frequency can be greater than or equal to about 13.56 MHz. In the process chamber (such as Figure 13A the process chamber 203 shown), the pressure of the second etching process can be from about 0.1 Torr to about 1 Torr, and the temperature can be from about 250 °C to about 450 °C. The time for performing the second etching process in the process chamber can be from about 10 seconds to about 200 seconds.

[0098] In some embodiments, the hydrogen radicals in the second etching process are more likely to etch some crystal planes of the semiconductor material of the fin 52, so it can be an anisotropic etching along the crystal planes. For example, in an embodiment where the material of the fin 52 is silicon, the hydrogen radicals can selectively etch the (100) plane rather than the (111) plane or the (110) plane. In some embodiments, the etching rate of the (100) plane can be about 3 times the etching rate of the (111) plane. Due to the etching selectivity of the hydrogen radicals during the second etching process, the etching along the (111) plane or the (110) plane of silicon is slower or even stops.

[0099] As Figure 12BAccordingly, the recess 102 may have a V-shaped lower surface. The angle θ1 between the lower surface of one of the recesses 102 and the line formed on the main surface of the substrate 50 may be about 55° to about 65° (such as about 60°). The distance D1 that the recess 102 extends under the gate spacer 86 may be about 4 nm to about 8 nm, such as about 6 nm. The distance D1 has a maximum value when the depth D2 (below the upper surface of the fin 52) is about 20 nm to about 30 nm (such as about 25 nm). The depth D3 of the recess 102 may be about 40 nm to about 50 nm (such as about 45 nm).

[0100] The recess 102 extends under the gate spacer 86 and has a V-shaped lower surface, which can allow more dopants to diffuse from the subsequently formed epitaxial source / drain regions 82 to the channel region 58. This can reduce the channel resistance R ch . In addition, the recess 102 extending under the gate spacer 86 in the (110) direction can enhance the device, avoid the drain-induced barrier lowering effect, and improve the difference between the on-current and the off-current (such as increasing the on-current and decreasing the off-current).

[0101] Figure 13A and Figure 13B The etching system 200 shown can be used to perform the second etching process. The etching system 200 includes a plasma generation chamber 223, which is connected to the process chamber 203. In one embodiment, the etching system 200 receives a first process gas (such as hydrogen) from a first supply system 205 and / or a second process gas from a second supply system 207. The first supply system 205 and the second supply system 207 can cooperate with each other to supply a variety of different process gases to the process chamber 203 where the substrate 50 is placed. The first supply system 205 and the second supply system 207 may have similar physical components to each other. In other embodiments, fewer or more supply systems may be employed.

[0102] In one embodiment, the first supply system 205 and the second supply system 207 may each include a gas supplier 209 and a gas flow controller 211. The gas supplier 209 may be a container such as a gas storage tank, which may be located near or far from the process chamber 203. In other embodiments, the gas supplier 209 is conducive to independently preparing and supplying the process gas to the gas flow controller 211. Any suitable source can be used as the gas supplier 209 for the process gas, and all these sources are fully included within the scope of the embodiments.

[0103] The gas supplier 209 can supply the required process gas to the gas flow controller 211. The gas flow controller 211 can be used to control the gas flow of the process gas to the gas controller 213 and finally to the plasma generation chamber 223, thereby helping to control the pressure in the plasma generation chamber 223. The gas flow controller 211 can be a proportional valve, a regulating valve, a needle valve, a pressure regulator, a mass flow controller, a combination of the above, or the like. However, any suitable method can be adopted to control and adjust the process gas flow, and these components and methods are fully included in the scope of the embodiments.

[0104] Although the first supply system 205 and the second supply system 207 described herein have the same components, this is only an illustrative example and is not used to limit the embodiments to any mode. Any type of suitable process gas supply system can be used instead, which includes any kind and number of individual components, and can be the same as or different from any other supply system in the etching system 200. These supply systems are fully included in the scope of the embodiments.

[0105] In various embodiments, the process gas can include a mixture of a precursor and a carrier gas. In embodiments where the precursor is stored in a solid or liquid state, the gas supplier 209 can store the carrier gas and can introduce the carrier gas into a precursor tank (not shown) that stores the solid or liquid precursor. Before sending the precursor to the gas controller, the precursor is volatilized or sublimated into a gas portion in the precursor tank, and then the carrier gas is used to propel and carry the precursor. Any suitable combination of methods and units can be used to provide the precursor, and these combinations of units are fully included in the scope of the embodiments. The carrier gas can include nitrogen, helium, argon, xenon, a combination of the above, or the like, but other suitable carrier gases can be used instead.

[0106] The first supply system 205 and the second supply system 207 can supply individual process gases to the gas controller 213. The gas controller 213 is connected to and isolates the first supply system 205 and the second isolation system 207 from the plasma generation chamber 223 to supply the required process gas to the plasma generation chamber 223. The gas controller 213 can include devices such as valves, sensors, and the like to control the supply rate of each process gas, and can receive instructions from the control unit 215 to control the gas controller 213.

[0107] The gas controller 213 can receive instructions from the control unit 215 to open or close the valves, connect one or more of the first supply system 205 or the second supply system 207 to the plasma generation chamber 223, and introduce the required process gas into the plasma generation chamber 223 via the manifold 219.

[0108] In some embodiments, the plasma generation chamber 223 may include a transformer coupled plasma generator and may be a coil. The coil may be attached to a first radio frequency generator 243 used to supply power to the plasma generation chamber 223 to ignite plasma when introducing process gas and / or carrier gas. Although the plasma generation chamber 223 described above includes a transformer coupled plasma generator, the embodiments are not limited to a transformer coupled plasma generator. Instead, any suitable method may be used to generate plasma, such as an inductively coupled plasma system, magnetically assisted reactive ion etching, electron cyclotron resonance, remote plasma generator, or similar methods. All of these methods are fully included within the scope of the embodiments.

[0109] The process chamber 203 further includes a showerhead 231 connected to the plasma generation chamber 223 via a conduit 221. The conduit 221 may transport plasma products (such as hydrogen radicals H· or other plasma products) from the plasma generation chamber 223 into the showerhead 231. The showerhead 231 may be used to disperse the plasma products into the process chamber 203 and may be designed to uniformly disperse the plasma products to minimize unwanted process conditions (resulting from non-uniform dispersion). In one embodiment, the showerhead 231 may include a gas distribution plate 233 that may have a plurality of openings 235 to disperse the plasma products into the process chamber 203.

[0110] Figure 13B An embodiment of the showerhead 231 is shown. Figure 13B The illustrated showerhead 231 may be configured to uniformly distribute plasma products (such as hydrogen radicals) within the process chamber 203. In existing showerheads, the distribution of plasma products that exit the conduit and enter the showerhead remains concentrated near the axis aligned with the conduit. For example, the plasma products are denser near the center of the showerhead. Due to the non-uniform distribution of the plasma products exiting the showerhead, the plasma products may impact the substrate, such as substrate 50, non-uniformly, thus causing non-uniform etching or cleaning during the second etching process. Accordingly, the showerhead 231 is provided to more uniformly distribute the plasma products that impact the substrate 50.

[0111] In Figure 13B it, the gas distribution plate 233 includes openings 235 that contain three sizes of openings 235a, 235b, and 235c. The diameter of the openings 235 gradually increases from the center of the gas distribution plate 233 towards the edge of the gas distribution plate 233, and the opening distribution decreases from the center of the gas distribution plate 233 towards the edge of the gas distribution plate 233. As Figure 13BAs shown, the opening 235a can be located at the center of the gas distribution plate 233 and have a minimum diameter, the opening 235b can surround the opening 235a and have a medium diameter, and the opening 235c can surround the opening 235b and have a maximum diameter. The diameter of the opening 235a is about 5 mm to about 15 mm (such as about 10 mm), the diameter of the opening 235b is about 25 mm to about 35 mm (such as about 30 mm), and the diameter of the opening 235c is about 40 mm to about 60 mm (such as about 50 mm). In addition, the distribution of the opening 235a is greater than that of the opening 235b, and the distribution of the opening 235b is greater than that of the opening 235c. For example, the distribution of the opening 235a can be about 4 openings / cm 2 to about 8 openings / cm 2 The distribution of the opening 235b can be about 2 openings / cm 2 to about 6 openings / cm 2 and the distribution of the opening 235c can be about 1 opening / cm 2 to about 4 openings / cm 2 . In some embodiments, the diameter D4 of the gas distribution plate 233 can be about 100 mm to about 200 mm. The opening 235a can be located in a circle with a maximum diameter of about 20 mm, the opening 235b can be located in an annulus with an inner diameter of about 20 mm to about 50 mm and an outer diameter of about 50 mm to about 80 mm, and the opening 235c can be located in an annulus with an inner diameter of about 80 mm to about 130 mm and an outer diameter of about 130 mm to about 180 mm.

[0112] The relatively large size of the opening 235c near the edge of the gas distribution plate 233 allows the hydrogen radicals in the showerhead 231 to leave the showerhead 231 closer to the edge of the gas distribution plate 233. The relatively small size of the opening 235c near the center of the gas distribution plate 233 allows the plasma products in the showerhead 231 to leave the showerhead 231 with a smaller amount near the center of the gas distribution plate 233. In addition, the distribution of the opening 235a near the center of the gas distribution plate 233 is greater than the distribution of the opening 235c near the edge of the gas distribution plate 233, allowing the amount of plasma products near the center of the gas distribution plate 233 to be greater than the amount of plasma products near the edge of the gas distribution plate 233 when the plasma products leave the showerhead 231. The size and distribution of the openings can together make the plasma products entering the showerhead 231 from the conduit 221 and leaving the showerhead 231 have a more uniform distribution. For example, the plasma product flow rate near the edge of the showerhead 231 (such as within 50 mm of the edge of the showerhead 231) can be 70% of the plasma product flow rate near the center of the showerhead 231 (such as within 20 mm of the center of the showerhead 231). Figure 13BIn the exemplary examples shown, the opening 235 includes openings 235a, 235b, and 235c. Without departing from the scope of the embodiments of the present invention, in other embodiments, the number of openings 235, the configuration of the openings 235, the number of openings 235 of different sizes, the configuration of the openings 235, the relative sizes of the openings 235, and other characteristics of the openings 235 (such as shape, spacing, or distribution, etc.) may be different.

[0113] However, the above description of introducing the plasma products into the process chamber 203 via a single showerhead 231 or a single introduction point is for illustration only and not limiting the embodiments. Any number of separate and independent showerheads 231 or other openings can be used to introduce the plasma products into the process chamber 203. All combinations of showerheads and other introduction points are fully within the scope of the embodiments.

[0114] As Figure 13A shown, the process chamber 203 can receive the plasma products and expose the substrate 50 to the plasma products. The process chamber 203 can be of any desired shape, which can be adapted to disperse the plasma products and bring the plasma products into contact with the substrate 50. The housing 225 can surround the process chamber 203, and the material of the housing 225 is inert to a variety of process materials. Thus, the housing 225 can be any suitable material that can withstand the chemicals and pressures associated with the deposition process. In one embodiment, the housing 225 can be steel, stainless steel, nickel, aluminum, alloys of the above, ceramics, combinations of the above, or the like.

[0115] In the process chamber 203, the substrate 50 can be placed on the mounting platform 237 to position and control the substrate 50 during the deposition process. Although Figure 13A a single mounting platform 237 is shown, the process chamber 203 can additionally include any number of mounting platforms 237. In addition, multiple wafers or substrates 50 can be placed on a single mounting platform 237.

[0116] In some embodiments, the material of the mounting platform 237 is suitable for withstanding the relatively high temperatures of the process. For example, the mounting platform 237 can be made of aluminum nitride material, another metal alloy material, or another suitable material. The mounting platform 237 can be arranged to evenly distribute heat to the wafers or substrates 50 mounted on the mounting platform 237.

[0117] The mounting platform 237 can additionally include a first electrode 239 coupled to a second radio frequency generator 241. During the second etching process or other processes, the second radio frequency generator 241 can electrically bias the first electrode 239 with a radio frequency voltage under the control of the control unit 215.

[0118] The process chamber 203 may also have an exhaust outlet 227, enabling the process chamber 203 to discharge materials. A vacuum pump 229 may be connected to the exhaust outlet 227 of the process chamber 203 to facilitate the extraction of waste materials. Under the control of the control unit 215, the vacuum pump 229 may also be used to reduce and control the pressure in the process chamber 203 to a desired pressure, and may be used to discharge waste materials or reaction by-products from the process chamber 203.

[0119] In Figure 14A and Figure 14B Once the recess 102 is formed, an epitaxial source / drain region 82 is formed in the fin 52 and fills the recess 102 to apply stress to the individual channel regions 58, thereby improving performance. The epitaxial source / drain region 82 is formed in the fin 52 such that each dummy gate 72 is located between an individual pair of adjacent epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain region 82 may extend into the fin 52 and may also pass through the fin 52. In some embodiments, the gate spacer 86 is used to separate the epitaxial source / drain region 82 from the dummy gate 72 by an appropriate lateral distance such that the epitaxial source / drain region 82 does not short-circuit outwardly to the subsequently formed gate of the final fin field effect transistor.

[0120] The epitaxial source / drain region 82 in the region 50N (such as an n-type metal oxide semiconductor region) may be formed by masking the region 50P (such as a p-type metal oxide semiconductor region). Subsequently, the epitaxial source / drain region 82 in the region 50N is grown in the recess 102. The epitaxial source / drain region 82 in the region 50N (such as an n-type metal oxide semiconductor region) may comprise any acceptable material, such as a material suitable for an n-type fin field effect transistor. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the region 50N may comprise a material that applies tensile stress to the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 82 in the region 50N may have a surface that bulges from the individual surfaces of the fin 52 and may have crystal planes.

[0121] The epitaxial source / drain region 82 in the region 50P (e.g., p-type metal oxide semiconductor region) may be formed by masking the region 50N (e.g., n-type metal oxide semiconductor region) and etching the source / drain region of the fin 52 in the region 50P to form a recess 102 in the fin 52. The epitaxial source / drain region 82 in the region 50P is then epitaxially grown in the recess 102. The epitaxial source / drain region 82 in the region 50P (e.g., p-type metal oxide semiconductor region) may include any acceptable material such as a material suitable for a p-type fin field effect transistor. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the region 50P may include a material that applies compressive stress in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. Epitaxial source / drain regions 82 in region 50P may also have surfaces that are raised from respective surfaces of fin 52 and may have crystal planes.

[0122] The epitaxial source / drain regions 82 and / or the fins 52 may be doped to form source / drain regions, followed by annealing. The steps of implanting dopants are similar to the aforementioned process of forming lightly doped source / drain regions. The impurity concentration of the epitaxial source / drain regions 82 may be between about 10 19 cm -3 to about 10 21 cm -3 The n-type and / or p-type impurities used in the epitaxial source / drain regions 82 may be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain regions 82 may be in-situ doped during growth.

[0123] The epitaxial process used to form epitaxial source / drain regions 82 in regions 50N and 50P results in the upper surfaces of the epitaxial source / drain regions having crystal planes that extend laterally outward from the sidewalls of fin 52. In some embodiments, these crystal planes cause adjacent epitaxial source / drain regions 82 of the same fin field effect transistor to merge, such as Figure 14C In other embodiments, after the epitaxial growth process is completed, adjacent epitaxial source / drain regions 82 are kept separated, such as Figure 14D As shown. Figure 14C and Figure 14D In the illustrated embodiment, gate spacers 86 cover the sidewall portions of fin 52 extending over STI 56 to block epitaxial growth. In some embodiments, the spacer etching step used to form gate spacers 86 can be adjusted to remove spacer material and extend the epitaxial growth region to the surface of STI 56.

[0124] exist Figure 15A and Figure 15B In the embodiment, the first interlayer dielectric layer 88 is deposited on Figure 14A and Figure 14BOn the structure shown. The composition of the first interlayer dielectric layer 88 can be a dielectric material, and its deposition method can be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material can include phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like. Other insulating materials formed by any acceptable process can also be used. In some embodiments, a contact etch stop layer is located between the first interlayer dielectric layer 88 and the epitaxial source / drain regions 82, the mask 74, and the gate spacers 86. The contact etch stop layer 87 can include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and its etching rate is different from that of the material on the first interlayer dielectric layer 88.

[0125] In Figure 16A and Figure 16B a planarization process such as chemical mechanical polishing can be performed to make the upper surface of the first interlayer dielectric layer 88 flush with the upper surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 on the dummy gate 72 and portions of the gate seal spacers 80 and the gate spacers 86 along the sidewalls of the mask 74. After the planarization process, the dummy gate 72, the gate seal spacers 80, the gate spacers 86, and the upper surface of the first interlayer dielectric layer 88 are flush. In summary, the upper surface of the dummy gate 72 is exposed via the first interlayer dielectric layer 88. In some embodiments, the mask 74 can be retained, and the planarization process makes the upper surface of the first interlayer dielectric layer 88 flush with the upper surface of the mask 74.

[0126] In Figure 17A and Figure 17B the etching step removes the dummy gate 72 and the mask 74 (if present) to form a recess 90. Portions of the dummy dielectric layer 60 in the recess 90 can also be removed. In some embodiments, only the dummy gate 72 is removed and the dummy dielectric layer 60 is retained, and the recess 90 exposes the dummy dielectric layer 60. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in the first region (such as the core logic region) of the die, but the dummy dielectric layer 60 in the recess 90 in the second region (such as the input / output region) of the die is retained. In some embodiments, the dummy gate 72 can be removed by an anisotropic dry etching process. For example, the etching process can include a dry etching process that uses a reactive gas that can selectively etch the dummy gate 72 without etching the first interlayer dielectric layer 88 or the gate spacers 86. Each recess 90 exposes and / or overlaps the channel region 58 of an individual fin 52. Each channel region 58 is located between a pair of adjacent epitaxial source / drain regions 82. When the dummy gate 72 is etched away, the dummy dielectric layer 60 can act as an etch stop layer. After removing the dummy gate 72, the dummy dielectric layer 60 can be removed as appropriate.

[0127] In Figure 18AWith Figure 18B in, a gate dielectric layer 92 and a gate 94 are formed as a replacement gate. Figure 18C Show Figure 19B a detailed view of region 89. The gate dielectric layer 92 is conformally deposited in the recess 90, such as on the sidewalls and upper surface of the fin 52 and on the sidewalls of the gate seal spacer 80 and / or the gate spacer 86. The gate dielectric layer 92 may also be formed on the upper surface of the first interlayer dielectric layer 88. In some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or a multi-layer of the foregoing. In some embodiments, the gate dielectric layer 92 includes a high-k dielectric material. In these embodiments, the dielectric constant of the gate dielectric layer 92 is greater than about 7.0 and may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or a combination of the foregoing. The method of forming the gate dielectric layer 92 may include molecular beam deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or a similar method. In embodiments where a portion of the dummy dielectric layer 60 remains in the recess 90, the gate dielectric layer 92 includes the material of the dummy dielectric layer 60 such as silicon oxide.

[0128] The gate 94 is deposited on the gate dielectric layer 92 respectively and fills the remaining portion of the recess 90. The gate 94 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination of the foregoing, or a multi-layer of the foregoing. For example, although Figure 18B the gate 94 shown is a single layer, the gate 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and a fill material 94C, as Figure 18C shown. After filling the recess 90, a planarization process such as chemical mechanical polishing may be performed to remove the excess portions of the materials of the gate dielectric layer 92 and the gate 94 on the upper surface of the first interlayer dielectric layer 88. Thus, the remaining portions of the materials of the gate 94 and the gate dielectric layer 92 form the replacement gate of the final fin field effect transistor. The gate 94 and the gate dielectric layer 92 may be collectively referred to as a "gate stack". The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0129] The gate dielectric layer 92 may be formed in regions 50N and 50P simultaneously such that the gate dielectric layer 92 in each region is composed of the same material. The gate 94 may be formed simultaneously such that the gate 94 in each region is composed of the same material. In some embodiments, the gate dielectric layer 92 in each region may be formed by a separate process such that the gate dielectric layer 92 in each region is a different material, and / or the gate 94 in each region may be formed by a separate process such that the gate 94 in each region is a different material. When separate processes are employed, multiple masking steps may be used to mask and expose the appropriate regions.

[0130] In Figure 19A andFigure 19B In this case, the second interlayer dielectric layer 108 is deposited on the first interlayer dielectric layer 88. In some embodiments, the second interlayer dielectric layer 108 is a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, the composition of the second interlayer dielectric layer 108 is a dielectric material such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and the deposition method thereof can be any suitable method such as chemical vapor deposition or plasma-assisted chemical vapor deposition. In some embodiments, before forming the second interlayer dielectric layer 108, the gate stack (including the gate dielectric layer 92 and the corresponding upper gate 94) is recessed to directly form a recess between the upper part of the gate stack and the opposite part of the gate spacer 86, as Figure 19A and Figure 19B shown. The gate mask 96 includes one or more layers of dielectric materials, such as silicon nitride, silicon oxynitride, or the like. After filling the recess, a planarization process can be performed to remove the excess portion of the dielectric material extending above the first interlayer dielectric layer 88. The subsequently formed gate contact 110 (see Figure 20A and Figure 20B ) passes through the gate mask 96 to contact the upper surface of the recessed gate 94.

[0131] In Figure 20A and Figure 20B shown in some embodiments, the gate contact 110 and the source / drain contact 112 are formed through the second interlayer dielectric layer 108, the first interlayer dielectric layer 88, and the gate mask 96. The openings used to form the source / drain contact 112 pass through the first interlayer dielectric layer 88 and the second interlayer dielectric layer 108, and the openings used to form the gate contact 110 pass through the second interlayer dielectric layer and the gate mask 96. The openings can be formed by acceptable photolithography and etching techniques. A liner layer (such as a diffusion barrier layer, an adhesion layer, or the like) and a conductive material can be formed in the openings. The liner layer can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as chemical mechanical polishing can be performed to remove the excess material from the surface of the second interlayer dielectric layer 108. The remaining liner layer and conductive material can form the source / drain contact 112 and the gate contact 110 in the openings. An annealing process can be performed to form a silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is physically and electrically coupled to the gate 94. The source / drain contact 112 and the gate contact 110 can be formed by different processes, or can be formed by the same process. Although the source / drain contact 112 and the gate contact 110 are formed in the same cross-section in the drawings, it should be understood that the above two can be formed in different cross-sections to avoid contact short-circuit.

[0132] As described above, removing the etch residue 104 can reduce device defects and improve device performance. Forming the recess 102 with a V-shaped lower surface (filled with the epitaxial source / drain region 82) can diffuse more dopants from the subsequently formed epitaxial source / drain region into the channel region 58 to reduce the channel resistance R in the channel region 58 ch . In addition, forming the recess 102 (filled with the epitaxial source / drain region 82) that extends under the gate spacer 86 can improve the device, avoid the drain-induced barrier lowering effect, and improve the difference between the on-current and the off-current (e.g., increase the on-current and decrease the off-current). In this way, the device formed by the above method can have improved device performance and reduced device defects.

[0133] In one embodiment, the method includes forming a gate stack on a fin extending from a substrate; forming gate spacers on sidewalls of the gate stack; etching the fin by a first etching process to form a first recess adjacent to the gate spacer, wherein the first etching process is anisotropic; etching the fin by a second etching process to remove the etch residue from the first recess, and the second etching process uses an etchant different from that used in the first etching process; etching a surface of the first recess by a third etching process to form a second recess that extends under the gate spacer in a direction perpendicular to a major surface of the substrate, and the second recess has a V-shaped lower surface, wherein the third etching process is anisotropic along a crystal plane of the substrate and the third etching process uses an etchant different from that used in the first etching process; and epitaxially forming a source / drain region in the second recess. In one embodiment, the etch residue includes native oxide or carbon residue. In one embodiment, the second etching process is an ammonia-based etching process. In one embodiment, the temperature of the second etching process is 100°C to 200°C. In one embodiment, the third etching process is a hydrogen-based plasma etching process. In one embodiment, the first etching process is reactive ion etching. In one embodiment, the etchants used in the second etching process and the third etching process are the same. In one embodiment, the step of etching the surface of the first recess by the third etching process includes flowing out hydrogen radicals via a showerhead, and the opening density near the center of the showerhead is higher than the opening density near the edge of the showerhead.

[0134] In another embodiment, the device includes: fins extending from a substrate; a gate stack located on the fins; gate spacers located on sidewalls of the gate stack; and source / drain regions located in the fins adjacent to the gate spacers, the source / drain regions having a V-shaped lower surface in a (111) crystalline plane, the source / drain regions extending under the gate spacers in a direction parallel to the major surface of the substrate and in a (110) crystalline plane, wherein the source / drain regions extend at least 4 nm to 8 nm under the gate spacers in a depth of 20 nm to 30 nm and in a direction parallel to the major surface of the substrate. In one embodiment, the angle between the V-shaped lower surface of the source / drain regions and a line parallel to the major surface of the substrate is 55° to 65°. In one embodiment, the source / drain regions extend 40 nm to 50 nm under the major surface of the substrate. In one embodiment, the hydrogen concentration adjacent to the source / drain regions in the fins is 5x10 18 atoms / cm 3 to 5x10 19 atoms / cm 3 .

[0135] In yet another embodiment, the method includes: forming fins in a semiconductor substrate; forming a dummy gate stack on the fins; etching the fins adjacent to the dummy gate stack using a first etching process to form a first recess, the first etching process anisotropically etching the fins and the etching direction being perpendicular to the major surface of the semiconductor substrate; after etching the fins using the first etching process, removing the etch residue from the first recess; etching the first recess using a second etching process to form a second recess, the second etching process being anisotropic along the (111) crystal plane and along the (110) crystal plane; forming source / drain regions in the second recess; and replacing the dummy gate with a gate stack. In one embodiment, the second etching process removes the etch residue. In one embodiment, the second etching process includes hydrogen-based plasma etching. In one embodiment, the step of removing the etch residue from the first recess employs an ammonia-based etching process, wherein after removing the etch residue from the first recess, the first recess is etched using the second etching process, and wherein the step of etching the first recess using the second etching process employs a hydrogen-based plasma etching process. In one embodiment, the temperature of the ammonia-based etching process is from 100 °C to 200 °C, and the temperature of the hydrogen-based plasma etching process is from 250 °C to 450 °C. In one embodiment, the method further includes forming gate spacers adjacent to the dummy gate stack, wherein after etching the fins using the first etching process, the sidewalls of the first recess are adjacent to the sidewalls of the gate spacers, and after etching the first recess using the second etching process, the sidewalls of the second recess extend under the gate spacers in a direction perpendicular to the major surface of the semiconductor substrate. In one embodiment, the etch residue includes native oxide or carbon residue. In one embodiment, after etching the fins adjacent to the dummy gate stack using the first etching process and before removing the etch residue from the first recess, the thickness of the etch residue is from 0.1 nm to 1 nm.

[0136] The features of the above embodiments are beneficial for those skilled in the art of the present technology to understand the present invention. Those skilled in the art of the present technology should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art of the present technology should also understand that these equivalent substitutions do not depart from the concept and scope of the present invention, and can be changed, replaced, or varied without departing from the concept and scope of the present invention.

Claims

1. A method of forming a semiconductor device, comprising: Forming a gate stack on a fin extending from a substrate; Forming a gate spacer on sidewalls of the gate stack; Etching the fin by a first etching process to form a first recess adjacent to the gate spacer, wherein the first etching process is anisotropic; Etching the fin by a second etching process to remove an etch residue from the first recess, and the second etching process uses an etchant different from that used in the first etching process; Etching a surface of the first recess by a third etching process to form a second recess, the second recess extending under the gate spacer in a (110) crystal plane in a direction perpendicular to a major surface of the substrate, and the second recess having a V-shaped lower surface, wherein the third etching process is anisotropic along a (100) crystal plane of the substrate, and the third etching process uses an etchant different from that used in the first etching process; And Epitaxially forming a source / drain region in the second recess.

2. The method of forming a semiconductor device according to claim 1, wherein the etch residue includes native oxide or carbon residue.

3. The method of forming a semiconductor device according to claim 1, wherein the second etching process is an ammonia-based etching process.

4. The method of forming a semiconductor device according to claim 3, wherein a temperature of the second etching process is 100 °C to 200 °C.

5. The method of forming a semiconductor device according to claim 1, wherein the third etching process is a hydrogen-based plasma etching process.

6. The method of forming a semiconductor device according to claim 1, wherein the first etching process is reactive ion etching.

7. The method of forming a semiconductor device according to claim 1, wherein the etchants used in the second etching process and the third etching process are the same.

8. The method of forming a semiconductor device according to claim 1, wherein the step of etching the surface of the first recess by the third etching process includes flowing out hydrogen radicals via a shower head, and an opening density near a center of the shower head is higher than an opening density near an edge of the shower head.

9. A semiconductor device, comprising: A fin extending from a substrate; A gate stack located on the fin; A gate spacer located on sidewalls of the gate stack; And A source / drain region located in the fin adjacent to the gate spacer, the source / drain region having a V-shaped lower surface in a (111) crystal plane, the source / drain region extending under the gate spacer in a direction parallel to a major surface of the substrate and in a (110) crystal plane, wherein the source / drain region extends at least 4 nm to 8 nm under the gate spacer in a depth of 20 nm to 30 nm and in a direction parallel to the major surface of the substrate, and the source / drain region has an arcuate sidewall extending from the V-shaped lower surface to a height flush with an upper surface of the fin.

10. The semiconductor device according to claim 9, wherein an angle between the V-shaped lower surface of the source / drain region and a line parallel to the major surface of the substrate is 55° to 65°.

11. The semiconductor device according to claim 9, wherein the source / drain region extends 40 nm to 50 nm below the main surface of the substrate.

12. The semiconductor device according to claim 9, wherein the hydrogen concentration in the fin adjacent to the source / drain region is 5x10 18 atoms / cm 3 to 5x10 19 atoms / cm 3 .

13. A method of forming a semiconductor device, comprising: forming a fin in a semiconductor substrate; forming a dummy gate stack on the fin; etching the fin adjacent to the dummy gate stack using a first etching process to form a first recess, the first etching process anisotropically etching the fin and the etching direction being perpendicular to the main surface of the semiconductor substrate; removing an etch residue from the first recess after etching the fin using the first etching process; etching the first recess using a second etching process to form a second recess, and the second etching process being anisotropic along the (111) crystal plane and along the (110) crystal plane; forming a source / drain region in the second recess, wherein the source / drain region has a V-shaped lower surface in the (111) crystal plane; and replacing the dummy gate with a gate stack.

14. The method of forming a semiconductor device according to claim 13, wherein the second etching process removes the etch residue.

15. The method of forming a semiconductor device according to claim 14, wherein the second etching process comprises hydrogen-based plasma etching.

16. The method of forming a semiconductor device according to claim 13, wherein the step of removing the etch residue from the first recess employs an ammonia-based etching process, wherein the first recess is etched using the second etching process after removing the etch residue from the first recess, and wherein the step of etching the first recess using the second etching process employs a hydrogen-based plasma etching process.

17. The method of forming a semiconductor device according to claim 16, wherein the temperature of the ammonia-based etching process is 100°C to 200°C, and the temperature of the hydrogen-based plasma etching process is 250°C to 450°C.

18. The method of forming a semiconductor device according to claim 13, further comprising forming a plurality of gate spacers adjacent to the dummy gate stack, wherein after etching the fin using the first etching process, the sidewall of the first recess is adjacent to the sidewall of the gate spacer, and after etching the first recess using the second etching process, the sidewall of the second recess extends under the gate spacer in a direction perpendicular to the main surface of the semiconductor substrate.

19. The method of forming a semiconductor device according to claim 13, wherein the etch residue comprises native oxide or carbon residue.

20. The method of forming a semiconductor device according to claim 13, wherein the thickness of the etch residue is 0.1 nm to 1 nm after etching the fin adjacent to the dummy gate stack using the first etching process and before removing the etch residue from the first recess.

21. A method of forming a semiconductor device, comprising: forming a fin extending from a substrate; forming a gate stack on the fin; forming a gate spacer on the sidewalls of the gate stack; Etch the fin by a first etching process to form a first recess adjacent to the gate spacer, wherein the first etching process is anisotropic; Etch the fin by a second etching process to remove an etch residue from the first recess, wherein the second etching process is an ammonia-based etching process; Etch the surface of the first recess by a third etching process to form a second recess that extends under the gate spacer in the (110) crystal plane, wherein the third etching process is a hydrogen-based plasma etching; And Epitaxially form a source / drain region in the second recess, wherein the source / drain region has a V-shaped lower surface in the (111) crystal plane.

22. The method of forming a semiconductor device as claimed in claim 21, wherein the etch residue comprises a carbon residue.

23. The method of forming a semiconductor device as claimed in claim 21, wherein the etch residue comprises a native oxide.

24. The method of forming a semiconductor device as claimed in claim 21, wherein the first etching process comprises reactive ion etching.

25. The method of forming a semiconductor device as claimed in claim 21, wherein the first recess after etching the fin by the first etching process has a U-shaped lower surface, and the second recess after etching the first recess by the third etching process has a V-shaped lower surface.

26. The method of forming a semiconductor device as claimed in claim 21, wherein the third etching process is anisotropic along the (100) crystal plane.

27. The method of forming a semiconductor device as claimed in claim 21, wherein the step of etching the surface of the first recess by the third etching process increases the hydrogen concentration in the fin.

28. A semiconductor device, comprising: A fin extending from a substrate; A gate stack located on the fin; A gate spacer adjacent to the gate stack; A source / drain region located in the fin adjacent to the gate spacer, the source / drain region having a V-shaped lower surface in the (111) crystal plane, the source / drain region extending under the gate spacer in a direction parallel to the major surface of the substrate and in a direction in the (110) crystal plane, wherein the source / drain region has an arcuate sidewall extending from the V-shaped lower surface to a height flush with the upper surface of the fin.

29. The semiconductor device as claimed in claim 28, wherein the source / drain region extends at least 4 nm to 8 nm under the gate spacer in a depth of 20 nm to 30 nm and in a direction parallel to the major surface of the substrate.

30. The semiconductor device as claimed in claim 29, wherein the angle between the sidewall of the V-shaped lower surface of the source / drain region and a line parallel to the major surface of the substrate is 55° to 65°.

31. The semiconductor device as claimed in claim 29, wherein the V-shaped lower surface of the source / drain region extends 40 nm to 50 nm under the upper surface of the fin.

32. The semiconductor device according to claim 29, wherein the hydrogen concentration in the fin adjacent to the source / drain region is 5x10 18 atoms / cm 3 to 5x10 19 atoms / cm 3 .

33. A method of forming a semiconductor device, comprising: Form a fin extending from a semiconductor substrate, Form a dummy gate stack on the fin; An etching process is employed to etch the fin adjacent to the gate stack to form a recess, and the etching process is anisotropic along the (111) crystalline plane and the (110) crystalline plane; A source / drain region is formed in the recess, wherein the source / drain region has a V-shaped lower surface in the (111) crystalline plane; And Replace the dummy gate stack with a gate stack.

34. The method of forming a semiconductor device as claimed in claim 33, further comprising, before etching the fin using the etching process, etching the fin adjacent to the dummy gate stack using a first etching process to form a first recess, wherein the first etching process etches the fin anisotropically in a direction perpendicular to the major surface of the semiconductor substrate.

35. The method of forming a semiconductor device as claimed in claim 34, further comprising removing an etch residue from the first recess after etching the fin using the first etching process and before etching the fin using the etching process.

36. The method of forming a semiconductor device as claimed in claim 35, wherein the step of removing the etch residue from the first recess employs an ammonia-based etching process, and wherein the etching process employs a hydrogen-based plasma etching process.

37. The method of forming a semiconductor device as claimed in claim 36, wherein the temperature of the ammonia-based etching process is from 100°C to 200°C, and the temperature of the hydrogen-based plasma etching process is from 250°C to 450°C.

38. The method of forming a semiconductor device as claimed in claim 33, wherein the etching process comprises hydrogen-based plasma etching.

39. The method of forming a semiconductor device as claimed in claim 33, further comprising forming a plurality of gate spacers adjacent to the dummy gate stack, wherein the sidewalls of the recess extend under the gate spacers in a direction perpendicular to the major surface of the semiconductor substrate.

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