Improved drain and / or gate interconnects and finger structures

Abstract

According to some embodiments of the present invention, a transistor device is provided, which includes: a semiconductor structure; a gate finger extending on the semiconductor structure in a first direction; and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an internal position of the gate interconnect, wherein the gate interconnect is connected to the gate finger at a position offset from the internal position of the gate interconnect.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. application serial No. 16 / 375,398, filed on April 4, 2019, which is a continuation-in-part application of U.S. application serial No. 16 / 032,571, filed on July 11, 2018, and claims priority to U.S. application serial No. 16 / 032,571, the entire contents of each of these U.S. applications are incorporated herein by reference. Technical Field

[0003] The inventive concepts described herein relate to microelectronic devices and, more particularly, to high-power, high-frequency transistors having a unit cell-based structure. Background Art

[0004] In recent years, circuits that require high power handling capabilities while operating at high frequencies such as RF (500 MHz), S-band (3 GHz), and X-band (10 GHz) have become increasingly common. As high-power, high-frequency circuits increase, the need for transistors that can reliably operate at RF and microwave frequencies while still being able to handle higher power loads has increased accordingly.

[0005] In order to provide increased output power, transistors with larger gate peripheries have been developed. One technique for increasing the effective gate periphery of a transistor is to provide multiple transistor cells connected in parallel in a unit cell configuration. For example, as shown in FIG. 1 , a high power transistor may include multiple gate fingers extending in parallel between corresponding elongated source and drain contacts.

[0006] In particular, FIG. 1 shows a metal layout of a conventional semiconductor transistor device 10, which includes a gate pad 12 and a drain pad 32 on a semiconductor substrate 20. FIG. 1 is a plan view of the device (i.e., looking down at the device from above). As shown in FIG. 1, in a conventional semiconductor transistor device 10, the gate pad 12 is connected to a plurality of parallel gate fingers 16 spaced apart from each other along a first direction (e.g., the Y direction shown in FIG. 1) and extending in a second direction (e.g., the X direction shown in FIG. 1) through a gate bus 14. The drain pad 32 is connected to a plurality of drain contacts 36 via a drain bus 34. In addition, a source contact 26 may also be located on the semiconductor transistor device 10. Each gate finger 16 extends along the X direction between a pair of adjacent source contacts 26 and drain contacts 36. The unit cell of the semiconductor transistor device 10 is shown at box 40 and includes a gate finger 16 extending between adjacent source contacts 26 and drain contacts 36. The "gate length" refers to the distance of the gate metallization in the Y direction, while the "gate width" is the distance that the source contact 26 and the drain contact 36 overlap in the X direction. In other words, the "width" of the gate finger 16 refers to the dimension of the gate finger 16 extending parallel to the adjacent source / drain contacts 26, 36 (the distance along the X direction). The gate periphery of the device refers to the sum of the gate widths of each gate finger 16 of the semiconductor transistor device 10.

[0007] In addition to increasing the unit cell, the gate periphery of a multi-cell transistor device can be increased by making the gate fingers wider (i.e., longer in the X direction). However, as the gate fingers of the device become wider, the high frequency performance of the device may be adversely affected. In addition, making the gate fingers wider generally means that the gate fingers must handle increased current levels, which may result in electromigration of the gate finger metallization. Summary of the invention

[0008] According to some embodiments of the present invention, a transistor device is provided, which includes: a semiconductor structure; a gate finger extending on the semiconductor structure in a first direction; and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an internal position of the gate interconnect, wherein the gate interconnect is connected to the gate finger at a position offset from the internal position of the gate interconnect.

[0009] In some embodiments, the gate finger includes edge portions at opposite edges of the gate finger, wherein the center portion is between the edge portions, and wherein the gate interconnect is connected to the edge portions of the gate finger via a plurality of conductive vias.

[0010] In some embodiments, the gate finger has no conductive via connected to a central portion of the gate finger.

[0011] In some embodiments, the edge portion is within one third of a width of the gate finger in the first direction from a corresponding opposing edge of the gate finger.

[0012] In some embodiments, a gate interconnect is connected to the gate finger at a first location on the gate finger adjacent to a first edge of the gate finger and at a second location on the gate finger adjacent to a second edge of the gate finger.

[0013] In some embodiments, the device further includes: a gate runner extending on the semiconductor structure in a first direction, wherein the gate interconnect has a first end and a second end, and wherein the gate interconnect is connected to the gate runner at an interior position of the gate interconnect away from the first end and the second end of the gate interconnect.

[0014] In some embodiments, the gate fingers extend on the semiconductor structure at a first level above the semiconductor structure, the gate interconnects extend on the semiconductor structure at a second level above the semiconductor structure that is higher than the first level, and the gate runners extend on the semiconductor structure at a third level above the semiconductor structure that is equal to or higher than the second level.

[0015] In some embodiments, the gate finger includes a first segment and a second segment with a gap between the first segment and the second segment.

[0016] In some embodiments, the device further includes: a drain finger extending in a first direction on the semiconductor structure; and a drain interconnect extending in the first direction and configured to be coupled to a drain signal at an internal position of the drain interconnect, wherein the drain interconnect is connected to the drain finger through a plurality of conductive vias.

[0017] In some embodiments, the position offset from the inner position of the gate interconnect is offset from the inner position of the gate interconnect by a first offset and from an edge of the gate finger by a second offset, and the first offset is greater than the second offset.

[0018] According to some embodiments of the present invention, a transistor device is provided, which includes: a semiconductor structure; a drain finger extending on the semiconductor structure in a first direction; and a drain interconnect extending in the first direction and configured to be coupled to a drain signal at an internal position of the drain interconnect, wherein the drain interconnect is connected to the drain finger at a position offset from the internal position of the drain interconnect.

[0019] In some embodiments, the drain finger includes edge portions at opposite edges of the drain finger, wherein the center portion is between the edge portions, and the drain interconnect is connected to the edge portions of the drain finger via a plurality of conductive vias.

[0020] In some embodiments, the drain finger has no conductive via connected to the central portion of the drain finger.

[0021] In some embodiments, the edge portion is within one third of a width of the drain finger in the first direction from a corresponding opposing edge of the drain finger.

[0022] In some embodiments, a drain interconnect is connected to the drain finger at a first location on the drain finger adjacent to a first edge of the drain finger and at a second location on the drain finger adjacent to a second edge of the drain finger.

[0023] In some embodiments, the device also includes: a drain channel extending on the semiconductor structure in a first direction, wherein the drain interconnect has a first end and a second end, and the drain interconnect is connected to the drain channel at an internal position of the drain interconnect away from the first end and the second end of the drain interconnect.

[0024] In some embodiments, the drain finger extends on the semiconductor structure at a first level above the semiconductor structure, the drain interconnect extends on the semiconductor structure at a second level above the semiconductor structure that is higher than the first level, and the drain flow path extends on the semiconductor structure at a third level above the semiconductor structure that is equal to or higher than the second level.

[0025] In some embodiments, the device further includes: a gate finger extending in a first direction on the semiconductor structure; and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an internal position of the gate interconnect, wherein the gate interconnect is connected to the gate finger through a plurality of conductive vias.

[0026] In some embodiments, the position offset from the inner position of the drain interconnect is offset from the inner position of the drain interconnect by a first offset amount and from an edge of the drain finger by a second offset amount, and the first offset amount is greater than the second offset amount.

[0027] According to some embodiments of the present invention, a transistor device is provided, the transistor device comprising: a semiconductor structure; and a plurality of gate fingers and a plurality of drain fingers alternately arranged on the semiconductor structure, the plurality of gate fingers and the plurality of drain fingers each extending in a first direction. The gate fingers of the plurality of gate fingers and the drain fingers of the plurality of drain fingers include corresponding edge portions at opposite edges thereof, wherein a center portion is between the corresponding edge portions, one of the gate fingers or the drain fingers has a plurality of conductive vias connected to its corresponding edge portion and has no conductive via connected to the center portion, and the other of the gate fingers or the drain fingers has at least one conductive via connected to its center portion.

[0028] In some embodiments, the corresponding edge portion is within one third of the width of the gate finger or the drain finger in the first direction from the opposite edge of the gate finger or the drain finger.

[0029] In some embodiments, the device further comprises: a plurality of gate interconnects on the semiconductor structure, respective gate interconnects of the plurality of gate interconnects being coupled to respective gate fingers of the plurality of gate fingers; and a plurality of gate runners extending on the semiconductor structure. Each gate interconnect of the plurality of gate interconnects has a first end and a second end, and at least one of the gate interconnects is connected to one of the gate runners at an inner position of at least one of the gate interconnects away from the first end and the second end of the at least one of the gate interconnects.

[0030] In some embodiments, the device also includes a plurality of source regions and a plurality of drain regions alternately arranged on the semiconductor structure, wherein corresponding gate fingers of the plurality of gate fingers extend between adjacent source regions and drain regions, and at least one of the gate channels extends on one of the source regions.

[0031] In some embodiments, at least one of the gate runners extends in a first direction, and a first dimension of at least one of the gate runners in a second direction intersecting the first direction exceeds a second dimension of at least one of the gate interconnects in the second direction.

[0032] According to some embodiments of the present invention, a transistor device is provided, which includes: a semiconductor structure; a plurality of gate fingers extending at a first level above the semiconductor structure; a plurality of drain fingers extending at a second level above the semiconductor; a plurality of gate interconnects on the semiconductor structure at a third level above the semiconductor structure that is higher than the first level, the corresponding gate interconnects being constructed to receive gate signals at their internal positions; and a plurality of drain interconnects on the semiconductor structure at a fourth level above the semiconductor structure that is higher than the first level, the corresponding drain interconnects being constructed to output drain signals at their internal positions, wherein at least one of the gate interconnects is connected to a corresponding gate finger among the plurality of gate fingers at opposite ends of the gate fingers, or at least one of the drain interconnects is connected to a corresponding drain finger among the plurality of drain fingers at opposite ends of the drain fingers.

[0033] According to some embodiments of the present invention, a transistor device is provided, the transistor device comprising: a semiconductor structure; a plurality of gate fingers extending on the semiconductor structure in a first direction; a plurality of gate interconnects, each gate interconnect having a first end and a second end extending on the semiconductor structure in the first direction, wherein each gate interconnect is connected to a corresponding gate finger through a plurality of first conductive vias; and a plurality of gate runners extending on the semiconductor structure in the first direction. At least one of the gate interconnects is connected to one of the gate runners through a second conductive via at an inner position of the at least one gate interconnect away from the first end and the second end of the at least one gate interconnect.

[0034] In some embodiments, respective ones of the gate fingers may be configured to function as gate electrodes of transistor devices.

[0035] In some embodiments, the gate fingers may extend on the semiconductor structure at a first level above the semiconductor structure, the gate interconnects may extend on the semiconductor structure at a second level above the semiconductor structure that is higher than the first level, and the gate runners may extend on the semiconductor structure at a third level above the semiconductor structure that is higher than the second level.

[0036] In some embodiments, the inner position of at least one gate interconnect can be between one third and two thirds of the distance between the first end and the second end of the at least one gate interconnect. In some embodiments, the inner position of at least one gate interconnect can be at a midpoint between the first end and the second end of the at least one gate interconnect.

[0037] In some embodiments, a first gate finger of the gate fingers may include a first segment and a second segment with a gap therebetween. In some embodiments, an inner position of at least one gate interconnect may vertically overlap the gap.

[0038] In some embodiments, the transistor device may further include a gate manifold on the semiconductor structure connected to the gate runner. The gate manifold may extend on the semiconductor structure in a second direction that intersects the first direction.

[0039] In some embodiments, the gate runners may be first gate runners, each first gate runner having a third end and a fourth end, and the internal position may be a first internal position, and the transistor device may further include a plurality of second gate runners extending in a first direction on the semiconductor structure. In such embodiments, at least one second gate runner may be connected to the first gate runner via a third conductive via connected to the first gate runner at a second internal position of the first gate runner that may be away from the third end and the fourth end of the first gate runner. The gate manifold may be connected to the first gate runner via a corresponding second gate runner in the second gate runners.

[0040] In some embodiments, the internal position may be a first internal position, and the transistor device may further include: a plurality of drain fingers extending in a first direction on the semiconductor structure; a plurality of drain interconnects, each drain interconnect having a third end and a fourth end extending in the first direction on the semiconductor structure, wherein each drain interconnect is connected to a corresponding drain finger through a plurality of third conductive vias; and a plurality of drain runners extending in the first direction on the semiconductor structure. A second internal position of at least one drain interconnect away from the third end and the fourth end of at least one drain interconnect may be connected to the drain runner through a fourth conductive via; and a drain manifold may be disposed on the semiconductor structure and connected to the plurality of drain runners.

[0041] According to a further embodiment of the present invention, a transistor device is provided, the transistor device comprising: a semiconductor structure; a plurality of source regions and a plurality of drain regions alternately arranged on the semiconductor structure; a plurality of gate fingers extending at a first level above the semiconductor structure between adjacent source regions and drain regions, respectively; a plurality of gate interconnects on the semiconductor structure at a second level above the semiconductor structure higher than the first level, wherein each gate interconnect is connected to a corresponding gate finger through a plurality of first conductive vias; and a plurality of gate runners on the semiconductor structure at a third level above the semiconductor structure higher than the second level. At least one of the gate runners is connected to at least one of the gate interconnects through a second conductive via, and the second conductive via is connected to at least one of the gate interconnects at a first inner position on at least one of the gate interconnects overlapping with the adjacent source region.

[0042] In some embodiments, the first inner position may be between one third and two thirds of a distance between a first end and a second end of at least one of the gate interconnects.

[0043] In some embodiments, the transistor device may further include a gate manifold on the semiconductor structure and connected to the gate runners, and the plurality of gate runners may be first gate runners, each first gate runner having a third end and a fourth end. In some such embodiments, the transistor device may further include a plurality of second gate runners extending on the semiconductor structure, wherein the second gate runners may be connected to at least one of the first gate runners through a third conductive via, the third conductive via being connected to at least one of the first gate runners at a second inner position of at least one of the first gate runners away from the third end and the fourth end of at least one of the first gate runners. The gate manifold may be connected to the plurality of first gate runners through respective second gate runners of the plurality of second gate runners.

[0044] In some embodiments, a width of at least one of the gate runners may exceed a width of at least one of the gate interconnects.

[0045] In some embodiments, the transistor device may further include: a plurality of drain fingers, respectively on a plurality of drain regions; a plurality of drain interconnects on the semiconductor structure, wherein each of the drain interconnects is connected to a corresponding drain finger through a plurality of third conductive vias; a plurality of drain runners on the semiconductor structure, wherein at least one of the drain runners is connected to at least one of the drain interconnects through a fourth conductive via, the fourth conductive via being connected to at least one of the drain interconnects at a second inner position on at least one of the drain interconnects overlapping an adjacent source region; and a drain manifold on the semiconductor structure and connected to the drain runners. In some embodiments, the gate runner and at least one of the drain runners may be at different levels above the semiconductor structure.

[0046] According to yet a further embodiment of the present invention, a transistor device is provided, which includes: a semiconductor structure; a plurality of gate fingers extending on the semiconductor structure; a plurality of gate interconnects on the semiconductor structure, each of the gate interconnects being electrically coupled to a corresponding gate finger, wherein each gate interconnect has a first end and a second end; and a plurality of gate channels on the semiconductor structure, wherein at least one of the gate channels is connected to at least one of the gate interconnects through a conductive via, wherein a current received at a first end of at least one of the gate interconnects via the conductive via has a phase difference of less than 1 degree compared to a current received at a second end of at least one of the gate interconnects via the conductive via.

[0047] In some embodiments, the gate runners and the gate interconnects may extend in a first direction, and a first dimension of at least one of the gate runners in a second direction intersecting the first direction may exceed a second dimension of at least one of the gate interconnects in the second direction.

[0048] In some embodiments, the conductive via may be connected to an inner position of at least one of the gate interconnects that is between one third and two thirds of a distance between a first end and a second end of at least one of the gate interconnects.

[0049] In some embodiments, a first gate finger of the gate fingers may include a first segment and a second segment with a gap between the first segment and the second segment. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate certain embodiments of the invention. In the drawings:

[0051] FIG. 1 is a plan view of a metal layout of a conventional multi-cell transistor.

[0052] Figure 2A is a plan view showing an embodiment of a multi-cell transistor utilizing gate and drain runners. Figure 2B It is taken along the line A-A' Figure 2A Cross-sectional view of . Figure 2C It is taken along the line B-B' Figure 2A Cross-sectional view of .

[0053] Figure 3A is a cross-sectional view of a unit cell of a conventional laterally diffused metal oxide semiconductor (LDMOS) transistor device. Figure 3B is a cross-sectional view of a unit cell of a conventional LDMOS transistor device utilizing a bottom source terminal. Figure 3C is a cross section of a conventional high electron mobility transistor (HEMT) cell.

[0054] Figure 4 is a plan view showing a transistor device in which the number of gate fingers is increased.

[0055] Figure 5A is a plan view showing a transistor device in which the width of the gate fingers is increased. Figure 5B It is taken along the line A-A' Figure 5A Cross-sectional view of . Figure 5C It is taken along the line B-B' Figure 5A Cross-sectional view of .

[0056] Fig. 6Ais a plan view illustrating a transistor device in which the width of a gate finger is increased according to some embodiments of the present invention. Figure 6B is taken along line A-A' according to some embodiments of the present invention Fig. 6A Cross-sectional view of . Figure 6C is taken along line BB' according to some embodiments of the present invention Fig. 6A Cross-sectional view of .

[0057] Figure 7 and Figure 8 Shown along Fig. 6A Another embodiment of the present invention is taken along line AA'.

[0058] Fig. 9 and Fig.10 A comparison of a conventional gate finger configuration and a gate finger configuration according to an embodiment of the present invention is shown.

[0059] Fig.11 is a cross-sectional view illustrating a transistor device in which multiple gate runners are utilized according to some embodiments of the present invention.

[0060] Fig. 12A is a plan view showing a transistor device in which gate and drain fingers are fed at internal locations without intermediate interconnects. Fig. 12B is taken along line A-A' according to some embodiments of the present invention Fig. 12A Cross-sectional view of . Fig. 12C is taken along line BB' according to some embodiments of the present invention Fig. 12A Cross-sectional view of .

[0061] Fig.13A is a plan view showing a transistor device in which a gate runner extends over a source region. Fig. 13B is taken along line CC' according to some embodiments of the present invention Fig.13A Cross-sectional view of . Fig. 13C Also according to an additional embodiment of the present invention, taken along line CC' Fig.13A Cross-sectional view of .

[0062] Fig.14A It is taken along the line A-A' Fig. 6A 2 is a cross-sectional view showing additional configurations of conductive vias according to some embodiments of the present invention. Fig. 14B is taken along line BB' according to some embodiments of the present invention Fig. 6A Cross-sectional view of . Fig. 14C and 14D Shows Fig.14A Additional examples of embodiments of the present invention.

[0063] Fig.15AIt is taken along the line A-A' Fig. 6A 2 is a cross-sectional view showing additional configurations of conductive vias according to some embodiments of the present invention. Fig. 15B is taken along line BB' according to some embodiments of the present invention Fig. 6A Cross-sectional view of . Fig. 15C and Fig.15D Shows Fig.15A Additional examples of embodiments of the present invention.

[0064] Fig.16A is a plan view showing a transistor device incorporating edge-fed gate fingers in which gate runners extend over source regions. Fig. 16B is taken along line D-D' according to some embodiments of the present invention Fig.16A Cross-sectional view of . Fig. 16C Also according to an additional embodiment of the present invention, taken along line D-D' Fig.16A Cross-sectional view of .

[0065] Fig.17A Embodiments are shown in which both the gate runner and the gate interconnect extend over a region of the semiconductor structure adjacent to the gate fingers. Fig. 17B 2 shows a diagram taken along line D-D' according to an embodiment of the present invention. Fig.17A Cross-sectional view of . DETAILED DESCRIPTION

[0066] Hereinafter, embodiments of the inventive concept are more fully described with reference to the accompanying drawings showing embodiments of the present invention. However, the inventive concept can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Throughout the text, the same reference numerals refer to the same elements.

[0067] Embodiments of the present inventive concept provide a multi-cell transistor device with a large effective gate width. By feeding a gate signal to a gate finger at an internal location of a gate interconnect, such as a midpoint of the gate interconnect, a large phase difference that may occur due to gate signal propagation across the entire length of a long gate finger can be reduced and / or avoided. According to some embodiments, a larger gate width of a multi-cell transistor device can be accommodated by adding a gate runner above the gate interconnect, wherein a conductive via couples the gate runner to an internal location on the gate interconnect. The connection of the gate runner to the internal location of the gate interconnect can be used to divide the gate finger into multiple segments. The gate signal can therefore travel from the internal location of the gate interconnect to the end of the gate interconnect and be provided to the gate finger with minimal or no phase difference in the final propagated gate signal.

[0068] By effectively dividing the gate fingers into multiple segments and distributing the gate signal to each gate finger segment with the aid of gate runners, the gain performance of the transistor can be improved compared to conventional devices.

[0069] According to one aspect of the invention, additional benefits can be obtained when the gate signal is fed to the interior of the gate interconnect and the gate interconnect is coupled to the respective gate finger segments offset from the gate signal being fed to the gate interconnect. In some embodiments, the gate signal is fed to the respective gate finger segments at a location adjacent to or offset a small amount from the edge of the gate finger segments. Feeding the gate signal to the gate finger segments at or near the edge of the gate finger segments can allow the various segments to perform as if they were electrically wired in parallel.

[0070] Depending on the embodiment, the signal provided to the drain finger may continue to be provided at an interior location.As will be discussed herein, providing the gate signal to the edge of the gate finger segment may improve the output signal obtained from the transistor device by improving the phase relationship between the gate and drain signals.

[0071] For example, two parts of a gate finger arranged in series can be fed at two opposite edges to make them behave as if they were arranged in parallel. At the same time, the drain can be fed at an internal position. This configuration can provide the advantage that it allows each long finger of the transistor to operate as a pair of short fingers in parallel, but without doubling the number of fingers. This retains the advantage of lower gate resistance, producing higher gain while producing the same high power. In addition, the configuration of combining edge-fed gate fingers with center-fed drain fingers follows the direction of energy propagation and ensures that the current summing is in phase. This will help maintain the RF performance of the shorter fingers in terms of output power density and efficiency.

[0072] According to one aspect of the present invention, a drain signal is fed to an internal position of a drain interconnect, and the drain interconnect is coupled to a corresponding drain finger segment offset from the drain signal fed to the drain interconnect. In some embodiments, the drain signal is fed to the corresponding drain finger segment at a position adjacent to an edge of the drain finger segment or offset a small amount from the edge. Feeding the drain signal to the drain finger segment at or near the edge of the drain finger segment can allow the individual segments to perform as if they were electrically wired in parallel. In some embodiments, the gate and drain segments are fed from positions offset from the internal position, where the drain and gate interconnects are fed with the drain and gate signals, respectively.

[0073] Therefore, in some embodiments, a transistor is provided, which includes: a semiconductor structure; a plurality of gate fingers extending on the semiconductor structure in a first direction, the respective gate fingers having a first edge and a second edge on an opposite side of the gate finger from the first edge in the first direction; and a plurality of gate interconnects, the respective gate interconnects being connected to the respective gate fingers at a first position adjacent to the first edge of the respective gate fingers and at a second position adjacent to the second edge, the respective gate interconnects being constructed to receive a gate signal at an inner position of a central portion of the gate interconnects.

[0074] In some embodiments, a transistor is provided, comprising: a semiconductor structure; a plurality of gate fingers extending at a first level above the semiconductor structure; a plurality of drain fingers extending at a second level above the semiconductor structure; a plurality of gate interconnects on the semiconductor structure at a third level above the semiconductor structure that is higher than the first level, the respective gate interconnects being constructed to receive gate signals at their internal positions; and a plurality of drain interconnects on the semiconductor structure at a fourth level above the semiconductor structure that is higher than the first level, the respective drain interconnects being constructed to output drain signals at their internal positions, wherein at least one gate interconnect is connected to a respective gate finger among the plurality of gate fingers at opposite ends of the gate fingers, or at least one drain interconnect is connected to a respective drain finger among the plurality of drain fingers at opposite ends of the drain fingers.

[0075] In some embodiments, a transistor is provided, the transistor comprising: a semiconductor structure; and a plurality of gate fingers and a plurality of drain fingers alternately arranged on the semiconductor structure, each gate finger and drain finger extending in a first direction. A gate finger of the plurality of gate fingers and a drain finger of the plurality of drain fingers include respective edge portions at opposite edges thereof, with a center portion between the edge portions, one of the gate fingers or the drain fingers having a plurality of conductive vias connected to the edge portions thereof and having no conductive vias connected to the center portion, and the other of the gate fingers or the drain fingers having at least one conductive via connected to the center portion thereof.

[0076] In some embodiments, a transistor is provided, comprising: a semiconductor structure; a gate finger extending in a first direction on the semiconductor structure; and a gate interconnect extending in the first direction and configured to receive a gate signal at an internal position of the gate interconnect, wherein the gate interconnect is connected to the gate finger at a remote position of the gate interconnect away from the internal position.

[0077] Now refer to Figure 2A-Figure 11 Embodiments of the present invention are described in more detail.

[0078] As discussed in the background section, one technique for increasing the effective gate periphery of a transistor is to provide multiple unit cell transistors connected in parallel. Such multiple unit cell transistors can be used in applications involving high frequency and / or high power. For example, a base station can use an RF power amplifier in the final stage of signal amplification to generate the high output power required for cell coverage. An important element in these RF power amplifiers and similar applications is the unit cell transistor that produces the amplification mechanism.

[0079] Figure 2A is a plan view showing an embodiment of a multi-cell transistor utilizing gate and drain runners. Figure 2B It is taken along the line A-A' Figure 2A Cross-sectional view of . Figure 2C It is taken along the line B-B' Figure 2A Cross-sectional view of .

[0080] First reference Figure 2A , a transistor device 100 including a plurality of transistor cells 200 is shown. The active region of the transistor cell 200 may include a gate finger 210, a drain finger 215, and a source contact 205. During amplification, current flows between the drain finger 215 and the source contact 205, and the amount of current may be modulated by a voltage signal applied to the gate finger 210.

[0081] like Figure 2B As shown in , the gate signal can be provided to the transistor cell 200 via the gate finger 210. The gate finger 210 can be electrically coupled to the gate region of the transistor cell 200. Similarly, as Figure 2C As shown in , the drain signal may be provided to the transistor cell 200 via the drain finger 215 .

[0082] The gate finger 210, drain finger 215, and source 205 may be formed on the semiconductor structure 190 including the embodiment of the transistor. More specifically, the drain finger 215, source contact 205, and gate finger 210 may be coupled to the drain region, source region, and gate region (e.g., channel) of the semiconductor embodiment of the transistor cell 200, respectively. It will be appreciated that the drain finger 215, source contact 205, and gate finger 210 may be connected to the semiconductor embodiment of the transistor cell 200. Figure 2A Multiple embodiments of the semiconductor-based transistor cell 200 are possible with the drain finger 215, source contact 205, and gate finger 210. For example, the drain finger 215, source contact 205, and gate finger 210 may be coupled to LDMOS and / or HEMT transistor embodiments, but the invention is not limited thereto.

[0083] For example, as taken along line C-C' Figure 2A Cross-sectional view of Figure 3A A diagram showing a case where the transistor cell is an LDMOS transistor cell Figure 2A1. The LDMOS field effect transistor (FET) is a three-terminal transistor device having a source region 105 and a drain region 115 formed in a semiconductor structure 190. The semiconductor structure 190 includes a semiconductor substrate 121 (e.g., p-type conductivity) and a drift layer 123 (e.g., n-type conductivity) on the semiconductor substrate 121. The semiconductor substrate may include semiconductor and non-semiconductor substrates, including, for example, sapphire, diamond, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, silicon carbide, GaAs, LGO, ZnO, LAO, InP, etc. The LDMOS transistor cell 200 may include a doped well region providing a source region 105 and a drain region 115. The source region 105, the drain region 115, and the gate region 110 of the LDMOS transistor cell 200 may be coupled to contacts for operation of the LDMOS transistor cell 200. For example, the gate region 110 may be electrically coupled to Figure 2A Similarly, the drain region 115 may be electrically coupled to the gate finger 210 shown in FIG. Figure 2A The drain finger 215 is shown in FIG.

[0084] The gate region 110 is isolated from the conductive channel by an insulator layer 129 (e.g., SiO2). Applying a positive voltage to the gate region 110 relative to the source region 105 can provide current flowing between the drain region 115 and the source region 105 by forming an inversion layer (e.g., a channel) between the source region 105 and the drain region 115. The LDMOS FET can operate in an "enhancement mode", which means that the drain-source current cannot flow until the applied positive gate voltage enhances the channel on the p-well.

[0085] although Figure 3A An LDMOS having contacts connected to the upper surface of the source region 105 of the LDMOS transistor cell 200 is shown, but it will be understood that other embodiments are possible. For example, in some embodiments, vias or other connection regions may be provided to connect the source region 105 to contacts on the bottom surface of the LDMOS device. For example, Figure 3B is a cross-sectional view of a conventional LDMOS transistor cell 200 utilizing a bottom source contact 205. Figure 3B As shown in FIG, a laterally diffused low resistance p+ "sinker" 127 can connect the source region 105 to the substrate 121 and the source contact 205. Figure 3B The LDMOS devices are similar to Figure 2A When used in conjunction with the parallel transistor configuration shown in , source fingers and / or other source contacts may not be needed on the top surface of the device. In some embodiments, source fingers similar to gate fingers 210 and / or drain fingers 215 may be provided.

[0086] As taken along the line C-C' Figure 2A Cross-sectional view of Figure 3C The transistor cell 200 is a HEMT transistor cell. Figure 2A Implementation of the transistor unit 200. Figure 3C As shown in , the HEMT transistor cell 200 may include a semiconductor structure 190, which includes a substrate 122, which may include, for example, 4H-SiC or 6H-SiC. Although silicon carbide may be used as a substrate material, embodiments of the present invention may utilize any suitable substrate, such as sapphire, diamond, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP, etc. An epitaxial structure is formed on the substrate 122. The epitaxial structure may include a channel layer 124 formed on the substrate 122 and a barrier layer 126 formed on the channel layer 124. The channel layer 124 and the barrier layer 126 may include a III-nitride-based material, wherein the material of the barrier layer 126 has a higher band gap than the material of the channel layer 124. For example, the channel layer 124 may include GaN, and the barrier layer 126 may include AlGaN. Although the channel layer 124 and the barrier layer 126 are shown as single layer structures, it will be appreciated that either or both of the channel layer 124 and / or the barrier layer 126 may be implemented as a multi-layer structure. It will also be appreciated that additional layers, such as buffer layers, strain balancing layers, transition layers, etc., may also be included as part of the epitaxial structure provided on the substrate 122.

[0087] Due to the difference in band gap between the barrier layer 126 and the channel layer 124 and the piezoelectric effect at the interface between the barrier layer 126 and the channel layer 124, a two-dimensional electron gas (2DEG) is induced in the channel layer 124 at the junction between the channel layer 124 and the barrier layer 126. The 2DEG serves as a highly conductive layer that allows conduction between the source and drain regions of the device, respectively, under the source contact segment 205 and the drain finger 215. The source contact segment 205 and the drain finger 215 are formed on the barrier layer 126. The gate finger 210 is formed on the barrier layer 126 between the drain finger 215 and the source contact segment 205.

[0088] Figure 3A , Figure 3B and Figure 3C LDMOS and HEMT devices are included as examples of possible configurations of transistor cell 200. However, it will be understood that the present invention may utilize other transistor cell configurations without departing from the scope of the embodiments described herein. For example, any configuration of transistor cell 200 that may use gate fingers and / or drain fingers in combination with other transistor cells may benefit from the embodiments described herein. As such, the present invention is not limited to HEMT and LDMOS transistor cells. As used herein, the term "semiconductor structure" will be used to refer to a structure that may be connected to a semiconductor device. Figure 2A A transistor cell structure having a gate finger 210 and a drain finger 215 (such as, for example, Figure 3A , Figure 3B and Figure 3C LDMOS and HEMT examples shown in ).

[0089] Back to reference Figure 2A , Figure 2B and Figure 2C , the gate fingers 210 may be coupled to the gate runners 225 through a plurality of first conductive gate vias 228. In some embodiments, the gate runners 225 may be at a higher level above the semiconductor substrate than the gate fingers 210. The gate runners 225 may be further connected to the gate pads 221 through second conductive gate vias 227. The gate pads 221 may be further connected to the gate manifold 220. The gate manifold 220 may provide gate signals to the plurality of transistor cells 200.

[0090] The drain fingers 215 may be coupled to the drain runners 235 through a plurality of first conductive drain vias 238. In some embodiments, the drain runners 235 may be at a higher level above the semiconductor structure 190 than the drain fingers 215. The drain runners 235 may be further connected to the drain pads 231 through second conductive drain vias 237. The drain pads 231 may be further connected to the drain manifold 240. The drain manifold 240 may provide a drain signal to the plurality of transistor cells 200.

[0091] For a given fixed drain bias voltage provided to transistor device 100, the amount of output current affects the output power of transistor device 100. The output current is based in part on the total gate periphery, which is Figure 2A-2B The gate finger width (W) shown in FIG. 1 is multiplied by the number of gate fingers 210 .

[0092] A larger gate periphery can be used to generate higher power in the transistor device 100. This higher power output can be achieved by increasing the number of gate fingers 210 and / or by increasing the width of the gate fingers 210 (e.g., extending the gate fingers 210 in the X direction). However, each solution has its limitations.

[0093] For example, increasing the number of gate fingers 210 may increase (eg, in Figure 2A Thus, the physical transistor packaging and / or semiconductor processing equipment may impose constraints on the maximum number of gate fingers 210 that can be included in the device (or alternatively, the maximum extent to which the device can extend in the Y direction). This can be referenced to Figure 4 See, Figure 4 is a plan view of a transistor device 100 having a large number of gate fingers 210. Figure 4 As can be seen in , the size of the physical transistor package 405 may be limited by the size of the substrate 410 on which the transistor device 100 is placed. The physical transistor package 405 may also be affected by the size of the package leads such as the gate lead 415 and / or the drain lead 420.

[0094] Likewise Figure 4 As shown in , another potential disadvantage of using an increased number of gate fingers 210 in the transistor device 100 is the uneven signal phase distribution that may occur along the length of the gate manifold 220. The magnitude of the effect that increasing the number of gate fingers may have on the signal phase distribution and device performance may depend on the design of the transistor device. A given transistor device 100 may have a center portion 450 and an end portion 455. As the length of the gate manifold 220 becomes longer, phase differences may occur in signals transmitted along the length of the gate manifold 220 (e.g., in the Y direction), such as gate signals transmitted to the gate fingers 210. In some embodiments, the gate signal may be received from the gate lead 415 primarily at the center portion 450 of the gate manifold 220 to distribute the gate signal to the end portion 455 of the gate manifold 220. Due to the difference in transmission length, the phase of the gate signal at the end portion 455 may be different from the phase at the center portion 450. Therefore, the drain currents generated at these different regions may also fail to sum in phase at the output terminal (eg, drain lead 420 ), causing the total output current amplitude to decrease, thereby reducing the output power of transistor device 100 .

[0095] In addition to increasing the number of gate fingers within the transistor device 100 , another technique to increase transistor output power may include increasing the width (W) of the gate fingers, and correspondingly increasing the width of the source contacts and drain fingers. Figure 5A is a plan view illustrating an embodiment of a transistor device 500 in which the widths of the gate fingers 510 , source contacts 505 , and drain fingers 515 are increased. Figure 5B It is taken along the line A-A' Figure 5A Cross-sectional view of . Figure 5C It is taken along the line B-B' Figure 5A Cross-sectional view of .

[0096] Figure 5A-5C The transistor device 500 may be very similar to Figure 2A-2C100. However, the widths of the gate fingers 510, source contacts 205, and drain fingers 515 included in the transistor device 500 are increased compared to the widths of the corresponding gate fingers 210, source contacts 205, and drain fingers 215 of the transistor device 100. For example, the width of the gate fingers 510 of the transistor device 500 may be 2W (e.g., twice the gate width of the gate fingers 210 of the transistor device 100). The gate fingers 510, source contacts, and drain fingers 515 with increased widths may be connected to the semiconductor structure 190 to form a transistor cell 590. The widened gate fingers 510 may include a gate pad 221 and a gate runner 525, the structures of which are similar to those described herein with respect to the gate pad 221 and the gate runner 525. Figure 2B The widened drain finger 515 may include a drain pad 231 and a drain channel 535, the structures of which are similar to those described herein with respect to the gate pad 221 and the gate channel 225. Figure 2C The other aspects of the transistor device 500 may be similar to those discussed above with respect to the drain pad 231 and the drain channel 235. Figure 2A-2C In addition, it will be appreciated that the transistor device 500 may include a semiconductor structure 190 that may be similar to the semiconductor structure 190 described above. Figure 3A-3C The transistor device 100 in question is constructed in the same manner as, for example, a HEMT or other types of transistors, such as an LDMOS transistor.

[0097] Unfortunately, increasing the width of the gate finger 510 may introduce performance issues. The first issue is an increase in gate resistance. (See, for example, PHAaen, JAPla, J. Wood, "Modeling and Characterization of RF and Microwave Power FETs", Cambridge University Press, 2007). If the number of gate fingers 510 remains constant and the length of the gate finger 510 is changed, the gate resistance R of the new configuration of the gate finger 510 will increase. new for:

[0098]

[0099] Where R orig and W orig are the original gate finger structures (e.g., Figure 2A The gate resistance and gate finger width of the gate finger 210) and Wne w is the gate finger in the new structure (e.g. Figure 5AAs can be seen from Equation 1, increasing the gate finger width from W to 2W doubles the gate resistance. Increasing the gate resistance may result in lower transistor gain, which is an important specification for amplifiers. For example, if a transistor with a gate finger length of W produces an output power of P, doubling the width of the gate finger 510 to 2W will produce an output power lower than 2P. This nonlinear scaling also poses a challenge to power amplifier designers in selecting the correct transistor die size for a given output power requirement. The increased resistance also reduces the efficiency of the amplifier.

[0100] Another disadvantage associated with gate fingers 510 and / or drain fingers 515 having large widths is the increase in phase differences that occur in the signal along the length of the finger (e.g., from region 550 to region 560 of gate finger 510 and / or from region 555 to region 565 of drain finger 515). The phase differences may be caused by various distribution effects related to the transmission distance along the gate fingers 510 and / or drain fingers 515. These phase differences may reduce the total output current amplitude after summing (combining) at the drain manifold 240. The end result may be that the output power of the transistor device 500 is lower than expected from the increased size. This may also result in a gain reduction phenomenon since the input power is the same.

[0101] In addition, the out-of-phase current combination may affect the time domain output current waveform shape and may affect transistor efficiency, which is another key indicator of power amplifiers. (See, for example, SCCrips' "RF Power Amplifiers for Wireless Communications", Artech House, 2006.) Non-uniform phase phenomena may also exist in Figure 2A-2C The original shorter gate finger 210 is also affected, but to a lesser extent.

[0102] To alleviate these problems when higher output powers are required, Fig. 6A , Figure 6B and 6C The solution shown in . Fig. 6A is a plan view illustrating a transistor device 600 in which the width of a gate finger 610 is increased according to some embodiments of the present invention. Figure 6B is taken along line A-A' according to some embodiments of the present invention Fig. 6A Cross-sectional view of . Figure 6C is taken along line BB' according to some embodiments of the present invention Fig. 6A Cross-sectional view of .

[0103] like Fig. 6A , Figure 6B and Figure 6CAs shown in FIG. 6 , some embodiments of the present invention may provide a plurality of transistor cells 700 repeatedly arranged on a semiconductor structure 690. It will be appreciated that the transistor cells 700 may be composed of, for example, Figure 3A-3C The semiconductor structure 690 shown in FIG. 6 is formed by a plurality of transistor cells 700 (e.g., LDMOS or HEMT transistor cells). The transistor cells 700 can be arranged as part of the transistor device 600 to provide a combined output signal. For example, the respective gate regions, drain regions, and source regions of a plurality of transistor cells 700 can be connected together to provide a plurality of transistors coupled in parallel.

[0104] The transistor cells 700 may be repeatedly arranged in a first direction (e.g., the Y direction). The gate region, drain region, and source region of the corresponding transistor cells 700 may extend in a second direction (e.g., the X direction) intersecting the first direction. The active region of each transistor cell 700 may include a region of the semiconductor structure 690 in which the corresponding gate region, drain region, and source region overlap in the first direction (e.g., the X direction). In some embodiments, the source region of adjacent transistor cells 700 may be a shared source region used as a source region for two different gate regions. Similarly, in some embodiments, the drain region of adjacent transistor cells 700 may be a shared drain region used as a drain region for two different gate regions.

[0105] The transistor device 600 may also include a plurality of gate fingers 610 spaced apart from one another on the semiconductor structure 690 along the semiconductor structure 690 in a first direction (e.g., the Y direction). Each gate finger 610 may have a width of 2W in a second direction (e.g., the X direction), or may have some other width that exceeds the width of a conventional transistor device. In some embodiments, the width 2W may be 800 microns.

[0106] The gate fingers 610 may be disposed on the semiconductor structure 690 to respectively electrically contact the gate regions (eg, channels) of the plurality of transistor cells 700 . The plurality of gate fingers 610 may provide gate signals to the corresponding transistor cells 700 .

[0107] In some embodiments, the transistor device 600 may further include a plurality of drain fingers 615 arranged on the semiconductor structure 690 in a first direction (e.g., Y direction). Each of the plurality of drain fingers 615 may have a width of 2W in a second direction (e.g., X direction), but the present invention is not limited thereto. The plurality of drain fingers 615 may be disposed on the semiconductor structure 690 to electrically contact the drain regions of the plurality of transistor cells 700, respectively. The drain fingers 615 may conduct the drain signals of the corresponding transistor cells 700.

[0108] In some embodiments, the transistor device 600 can also electrically connect each source region of each transistor cell 700 to a common source signal. In some embodiments, the electrical connection for the source region can be on the back side of the semiconductor structure 690 (e.g., the side of the semiconductor structure 690 opposite the gate finger 610 and the drain finger 615). In some embodiments, the plurality of source fingers 605 can also be provided on the same side of the semiconductor structure 690 as the gate finger 610 and the drain finger 615. The plurality of source fingers 605 can have a structure similar to that discussed herein with respect to the gate finger 610 and the drain finger 615.

[0109] Each gate finger 610 may be coupled to a gate interconnect 625 through a plurality of first conductive gate vias 628. In some embodiments, the gate interconnect 625 may be at a higher level (e.g., in the Z direction) than the gate finger 610 above the semiconductor structure 690. In some embodiments, the gate interconnect 625 may have a larger size than the gate finger 610 in a first direction (e.g., in the Y direction). The gate interconnect 625 may be connected to a gate runner 621 through a second conductive gate via 627. In some embodiments, the gate runner 621 may be at a higher level (e.g., in the Y direction) than the gate interconnect 625 above the semiconductor structure 690. In some embodiments, the gate runner 621 may have a larger size in the first direction (e.g., in the Y direction) than the gate interconnect 625. In some embodiments, the gate runner 621 may include a metal or other highly conductive material, including, for example, copper, gold, and / or a composite metal. The gate runner 621 may be further connected to a gate manifold 620. The gate manifold 620 may provide a gate signal to a plurality of transistor cells 700.

[0110] In some embodiments, each second conductive gate via 627 connecting the gate runner 621 to the corresponding gate interconnect 625 may be connected to the gate interconnect 625 at an inner position 629 of the gate interconnect 625. For example, the gate interconnect 625 may have opposing first and second ends 645, 646. In some embodiments, the second conductive gate via 627 may be connected to the gate interconnect 625 at an inner position 629 between the first end 645 and the second end 646 of the gate interconnect 625. In some embodiments, the inner position 629 may be at a midpoint of the first end 645 and the second end 646 of the gate interconnect 625 (e.g., at a midpoint therebetween). In some embodiments, the inner position 629 may be at a distance within ten percent of the length of the gate interconnect 625 from the midpoint of the gate interconnect 625. In some embodiments, the inner position 629 may be at a distance within twenty percent of the length of the gate interconnect 625 from the midpoint of the gate interconnect 625. In some embodiments, the inner location 629 may be at a distance between one third and two thirds of the distance between the first end 645 and the second end 646 of the gate interconnect 625 .

[0111] In some embodiments, each gate finger 610 may be composed of a first segment 610A and a second segment 610B. In some embodiments, the first segment 610A and the second segment 610B may extend collinearly. In some embodiments, the first segment 610A and the second segment 610B may be arranged on opposite sides of the second conductive gate via 627. For example, for a gate finger 610 having a width of 2W, the first segment 610A and the second segment 610B may both have a width of W, but the present invention is not limited thereto. In some embodiments, the first segment 610A and the second segment 610B may be physically separated by a gap, such as Figure 6B For example, additional elements (e.g., an insulating layer) may be provided between the first segment 610A and the second segment 610B. However, the present invention is not limited thereto, and it will be appreciated that in other embodiments, the gate finger 610 may not be divided into separate first and second segments 610A, 610B. For example, Figure 7 An embodiment is shown in which the first section 610A and the second section 610B are integrally connected.

[0112] As described above, in some embodiments, the second conductive gate via 627 can be located at an inner position 629 located at the midpoint of the gate interconnect 625. However, in some embodiments, the second conductive gate via 627 can be located at the inner position 629 offset from the midpoint of the gate interconnect 625. In such embodiments, the first segment 610A can have a different length than the second segment 610B (or vice versa). For example, Figure 8As shown in FIG. 6 , the first segment 610A may have a first length W, and the second segment 610B may have a second length W′ different from the first length W.

[0113] Each drain finger 615 may be coupled to a corresponding drain interconnect 635 through a plurality of first conductive drain vias 638. In some embodiments, the drain interconnect 635 may be at a higher level above the semiconductor structure 690 than the drain fingers 615. In some embodiments, the drain interconnect 635 may be at the same level above the semiconductor structure 690 as the gate interconnect 625. In some embodiments, the drain interconnect 635 may be at a different level above the semiconductor structure 690 than the gate interconnect 625. In some embodiments, the drain interconnect 635 may have a larger size in a first direction (e.g., in the Y direction) than the drain fingers 615.

[0114] Each drain interconnect 635 may be connected to a corresponding drain channel 631 through a corresponding second conductive drain via 637. In some embodiments, the drain channel 631 may be at a higher level than the drain interconnect 635 above the semiconductor structure 690. In some embodiments, the drain channel 631 may be at the same level as the gate channel 621 above the semiconductor structure 690. In some embodiments, the drain channel 631 may be at a different level than the gate channel 621 above the semiconductor structure 690. In some embodiments, the drain channel 631 may have a larger size than the drain interconnect 635 in a first direction (e.g., in the Y direction). In some embodiments, the drain channel 631 may include a metal or other highly conductive material, including, for example, copper, gold, and / or a composite metal. The drain channel 631 may be connected to a drain manifold 640. The drain manifold 640 may provide a drain signal to a plurality of transistor cells 700.

[0115] As with gate runners 621, in some embodiments, a second conductive drain via 637 connecting each drain runner 631 to a corresponding drain interconnect 635 may be connected to drain interconnect 635 at an interior position 639 of drain interconnect 635. Various possibilities for connecting drain runners 631 to drain interconnect 635 are similar to those discussed herein with respect to connecting gate runners 621 to gate interconnect 625, and a repeated description thereof will not be repeated for the sake of brevity.

[0116] The solution described herein can split each gate interconnect 625 into two segments, and can provide symmetrical feeding to the first segment 610A and the second segment 610B of the gate finger 610 by providing feeding from the gate runner 621 to each gate interconnect 625 through a second conductive gate via 627 located, for example, at approximately the center (e.g., the center portion) of each gate interconnect 625. A similar configuration can also be achieved for the drain side (e.g., for the drain interconnect 635 and the drain runner 631). The approach retains the original short gate and drain finger lengths (e.g., separate segments of length W) while achieving the desired higher output power. In some embodiments, the use of a gate runner 621 that can be wider than the gate interconnect 625 and has a lower resistance than the gate interconnect 625 can not significantly increase the gate resistance, and can advantageously reduce the phase difference in the combined signal of the transistor cell 700 that may reduce the output power of the transistor device 600. For example, in an embodiment of the present invention, when a signal (e.g., current) is transmitted to the gate interconnect 625 through the second conductive gate via 627, the signal received at the first end 645 of the gate interconnect 625 may have a phase difference of less than 1 degree from the signal received at the second end 646 of the gate interconnect 625. In some embodiments, the phase difference may be less than 0.5 degrees.

[0117] The present invention increases the finger length of transistor devices in a parallel configuration rather than in a series configuration as used in conventional devices. However, the present invention achieves a total gate periphery that is substantially the same or greater than that of conventional devices. Thus, the embodiments described herein produce the desired higher output power, but retain the original shorter individual gate finger lengths of conventional devices.

[0118] With this technique, the gate resistance of a gate finger (or the drain resistance of a drain finger) is added in parallel rather than in series, reducing the overall resistance and improving transistor gain in high power configurations.

[0119] This technique has a similar effect to doubling the number of gate fingers, but does not cause the die size to be physically too wide to fit in the package. It also mitigates the Figure 4 Phase variation issues associated with wide transistor dies are discussed.

[0120] The embodiments described herein also reduce the Figure 5A-5C The phase variation along the increasing gate and drain finger length (2W) is described, returning to the phase variation relative to Figure 2A-2C The original phase increment described for a shorter gate length (W) but increasing (eg, doubling) the output current.

[0121] Fig. 9 and Fig.103 and 4 are plan views of a conventional transistor device and a transistor device according to an embodiment of the present invention, respectively. Fig.10 The embodiments of the present invention shown in FIG. 1 can be used with Fig. 9 The same gate and drain bonding pad configuration as the prior art die shown in , enables standard wire bonding processes in manufacturing. For example, compared to a conventional transistor device with a gate finger width of W, embodiments of the present invention can maintain the same overall transistor size in a first direction (e.g., Y direction) while, for example, doubling the gate finger width in a second direction (e.g., X direction) to 2W. Therefore, transistor devices according to embodiments of the present invention can allow the use of the same or substantially similar manufacturing processes as conventional transistor devices.

[0122] As in Fig.10 As can be seen in the embodiment of the present invention, the use of the gate / drain flow channels and gate / drain interconnect configurations described herein can improve the performance of existing devices by reducing the phase shift of signals propagating through the device. In some embodiments, Fig.10 The improved configuration shown in can be integrated with existing dies while minimizing modifications to the manufacturing process.

[0123] Fig.11 is a cross-sectional view showing a transistor device utilizing multiple gate runners according to some embodiments of the present invention. In some embodiments, additional conductor layers (eg, gate runners) may be used in a branched form, such as Fig.11 In some embodiments, the branches can be symmetrical. The number of conductor layers can be expanded to allow for more branches, so that shorter fingers can be used while producing the same desired gate periphery. For example, Fig.11 As shown in , the gate finger 1110 can be separated into a plurality of gate finger segments 1110A, 1110B, 1110C, etc. Figure 6B and Figure 7 As discussed, the gate finger segments 1110A, 1110B, 1110C may be separate from one another or may be integrated.

[0124] The gate fingers 1110 may be further coupled to the gate interconnects 1125 through a plurality of first conductive gate vias 1128. In some embodiments, the gate interconnects 1125 may be at a higher level than the gate fingers 1110. In some embodiments, the gate interconnects 1125 may have a larger dimension in a first direction (eg, in the Y direction) than the gate fingers 1110. The gate fingers 1110 may be arranged in a manner similar to Figure 6A-6C The semiconductor structure 690 is connected to the semiconductor structure 1190 in a manner.

[0125] The gate interconnect 1125 may be further connected to the first gate runner 1121_1 through a plurality of second conductive gate vias 1127_1. The first gate runner 1121_1 may be at a higher level than the gate interconnect 1125. In some embodiments, the gate runner 1121_1 may have a larger size than the gate interconnect 1125 in the first direction (e.g., in the Y direction). In some embodiments, the gate interconnect 1125 may be segmented. For example, the gate interconnect 1125 may be separated into a plurality of (e.g., 4) segments that may be physically isolated from each other. Each segment of the gate interconnect 1125 may be connected to the first gate runner 1121_1 through one of the plurality of second conductive gate vias 1127_1 placed at an internal position of the segment of the gate interconnect 1125. In some embodiments, the internal position of the segment of the gate interconnect 1125 may be the midpoint of the segment of the gate interconnect 1125.

[0126] The first gate runner 1121_1 may be further connected to the second gate runner 1121_2 through a plurality of third conductive gate vias 1127_2. The second gate runner 1121_2 may be at a higher level than the first gate runner 1121_1. In some embodiments, the second gate runner 1121_2 may have a larger size than the first gate runner 1121_1 in the first direction (e.g., in the Y direction). The second gate runner 1121_2 may be further connected to the third gate runner 1121_3 through a fourth conductive gate via 1127_3. The third gate runner 1121_3 may be at a higher level than the second gate runner 1121_2. In some embodiments, the third gate runner 1121_3 may have a larger size than the second gate runner 1121_2 in the first direction (e.g., in the Y direction). In this way, a device having three layers of gate runners 1121_1, 1121_2, 1121_3 may be constructed.

[0127] In some embodiments, each gate runner layer can be connected to an adjacent lower layer below the gate runner layer by a conductive via located at an inner position of the adjacent lower layer. For example, the third gate runner 1121_3 can be connected to the second gate runner 1121_2 by a fourth conductive gate via 1127_3 located at an inner position of the second gate runner 1121_2. In some embodiments, the inner position may be the midpoint of the second gate runner 1121_2. In some embodiments, the inner position may be at a distance within ten percent of the length of the gate runner layer from the midpoint of the gate runner layer. In some embodiments, the inner position may be at a distance within twenty percent of the length of the gate runner layer from the midpoint of the gate runner layer. In some embodiments, the inner position may be at a distance between one-third and two-thirds of the distance between the first end and the second end of the gate runner layer.

[0128] like Fig.11 As shown in , some stacked gate runner layers can be segmented. For example, the first gate runner 1121_1 can be separated into two segments that can be physically isolated from each other. Each segment of the first gate runner 1121_1 can be connected to the second gate runner 1121_2 through one of the plurality of third conductive gate vias 1127_2 placed at an inner position of the segment. In some embodiments, the inner position of a segment of the first gate runner 1121_1 is the midpoint of the segment. In some embodiments, the first gate runner 1121_1 can be a single layer. In addition, although Fig.11 Three gate runners 1121_1 , 1121_2 , and 1121_3 are shown, but it will be understood that more or fewer gate runners and / or layers may be provided without exceeding the scope of the present invention.

[0129] The invention described herein is technology independent, which means that it can be applied to LDMOS, GaN and other high power RF transistor technologies. Although embodiments of the present invention are shown with reference to LDMOS and HEMT structures, the inventive concept is not limited to such devices. Therefore, embodiments of the present invention may include other transistor devices having multiple unit cells and control electrodes. Embodiments of the present invention may be applicable to any transistor device where a wider control electrode is desired and there are multiple unit cells of the device. Therefore, for example, embodiments of the present invention may be applicable to various types of devices manufactured using SiC, GaN, GaAs, silicon, etc., such as MESFET, MMIC, SIT, LDMOS, BJT, pHEMT, etc.

[0130] Although the embodiments described herein have included gate interconnects (see, e.g., Figure 6B The gate interconnect 625 and Figure 6C ), but it will be understood that in some embodiments the drain / gate runners may be connected directly to the drain / gate fingers at internal locations. Fig. 12A is a plan view showing a transistor device 1200 in which gate and drain fingers are fed at internal locations without intermediate interconnects. Fig. 12B is taken along line A-A' according to some embodiments of the present invention Fig. 12A Cross-sectional view of . Fig. 12C is taken along line BB' according to some embodiments of the present invention Fig. 12A Similar to those previously described Figure 12A-12C The elements are denoted by like reference numerals, and repeated description thereof may be omitted.

[0131] like Figure 12A-12CAs shown in FIG. 1 , at an internal location without an intermediate interconnect structure, the gate runner 621 can be connected to the gate finger 610 and / or the drain runner 631 can be connected to the drain finger 615. For example, referring to Fig. 12B , the gate runner 621 may extend over the gate finger 610 to connect to an inner position 1229 of the gate finger 610 via the conductive via 627. In some embodiments, the inner position 1229 may be at a midpoint of the gate finger 610. In some embodiments, the inner position 1229 may be at a distance within ten percent of the length of the gate finger 610 from the midpoint of the gate finger 610. In some embodiments, the inner position 1229 may be at a distance within twenty percent of the length of the gate finger 610 from the midpoint of the gate finger 610. In some embodiments, the inner position 1229 may be at a distance between one third and two thirds of the distance between the opposite ends of the gate finger 610.

[0132] In a similar way, Fig. 12C , the drain runner 631 may extend over the drain finger 615 to connect to an inner position 1239 of the drain finger 615 via a conductive via 637. In some embodiments, the inner position 1239 may be at a midpoint of the drain finger 615. In some embodiments, the inner position 1239 may be at a distance within ten percent of the length of the drain finger 615 from the midpoint of the drain finger 615. In some embodiments, the inner position 1239 may be at a distance within twenty percent of the length of the drain finger 615 from the midpoint of the drain finger 615. In some embodiments, the inner position 1239 may be at a distance between one third and two thirds of the distance between opposite ends of the drain finger 615.

[0133] although Fig. 12A The drain fingers 615 and gate fingers 610 are shown as being directly connected to the drain runners 631 and gate runners 621, respectively, without corresponding interconnects, but it will be appreciated that other configurations are possible. For example, in some embodiments, the gate runners 621 may be connected to the gate fingers 610 via internal locations 629 of the gate interconnects 625, e.g. Figure 6B , while the drain runner 631 may be connected to the drain finger 615 at the inner position 1239 without a drain interconnect, e.g. Fig. 12C In some embodiments, the drain channel 631 may be connected to the drain finger 615 via an inner position 639 of the drain interconnect 635, for example, Figure 6C , while the gate runner 621 may be connected to the gate finger 610 at the inner position 1229 without a gate interconnect, e.g. Fig. 12B as shown in .

[0134] The use of interconnects (e.g., gate interconnects and / or drain interconnects) can allow the use of layers having a lower resistance than the intrinsic fingers (e.g., gate fingers and / or drain fingers) of the transistor device. For example, in some embodiments, the interconnects can be formed from a metal layer and / or can have a larger size than the fingers. In some embodiments, the fingers can be made of polysilicon. In some technologies, additional metal layers for use as interconnects may not be available. In some embodiments, additional metal layers can be used when additional space is available. For example, as discussed herein, the source region of the device can be electrically connected through the rear surface of the device rather than the top surface. In such an embodiment, the wiring layer to the gate fingers of the device can extend above the surface of the source region without interfering with the connection to the source region.

[0135] Fig.13A is a plan view showing transistor device 1300 , wherein gate runner 621 extends over source region 605 . Fig. 13B is taken along line CC' according to some embodiments of the present invention Fig.13A Cross-sectional view of . Fig. 13C Also according to an additional embodiment of the present invention, taken along line CC' Fig.13A Similar to those previously described Figure 13A-13C The elements are denoted by like reference numerals, and their repeated descriptions may be omitted.

[0136] like Fig.13A As shown in , in some embodiments, portions of the gate runner 621 and / or gate interconnect 625 may extend over the source region 605 of the transistor device 1300. Portions of the gate runner 621 and / or gate interconnect 625 may be offset from the gate finger 610 (e.g., in the Y direction). Fig.13A and Fig. 13BAs shown in , the gate runner 621 may extend over the source region 605 adjacent to the gate finger 610. The gate runner 621 may be connected to the gate interconnect 625 at an inner position 629 of the gate interconnect 625. The inner position 629 may be between the first end 645 and the second end 646 of the gate interconnect 625. In some embodiments, the inner position 629 may be at a midpoint of the gate finger 610. In some embodiments, the inner position 629 may be at a distance within ten percent of the length of the gate finger 610 from the midpoint of the gate finger 610. In some embodiments, the inner position 629 may be at a distance within twenty percent of the length of the gate finger 610 from the midpoint of the gate finger 610. In some embodiments, the inner position 629 may be at a distance between one-third and two-thirds of the distance between the opposite ends of the gate finger 610. The gate interconnect 625 may be coupled to the gate finger 610 (e.g., the first and second segments 610A, 610B) through a plurality of conductive vias 628.

[0137] The gate runner 621 may be connected to the gate interconnect 625 through the conductive portion 627'. In some embodiments, the conductive portion 627' may extend between the gate runner 621 and the gate interconnect 625 in a direction (e.g., the Y direction) parallel to the surface of the semiconductor structure 690. In some embodiments, the conductive portion 627' may be made of the same or similar material as the gate runner 621.

[0138] The gate runner 621 may be disposed at the same level as the gate interconnect 625, as shown in FIG. Fig. 13B As shown in, but the embodiments described herein are not limited thereto. Fig. 13C As shown in , the gate runner 621 may be disposed at a different level than the gate interconnect 625. In such an embodiment, the conductive portion 627' may also extend in a direction perpendicular to the top surface of the semiconductor structure 690 (eg, the Z direction).

[0139] As discussed herein, in some embodiments, an interconnect (eg, a drain interconnect and / or a gate interconnect) may be formed by a plurality of conductive vias (eg, Figure 6B The conductive vias 628 and / or Figure 6C The conductive via 638 of the gate electrode is connected to the intrinsic finger of the transistor device. In some embodiments, it may be beneficial to have a different configuration of the conductive via to the gate finger than the conductive via to the drain finger.

[0140] For example, when in a Fig. 6A When viewed in plan view in FIG. 6 , it can be seen that the gate signal applied to the gate runner 621 will be transmitted to the gate interconnect 625 at an internal position of the gate interconnect 625. Figure 6A-6CAs shown in , the signal will then flow electrically through the conductive via 628 from the interior location of the gate finger 610 to the exterior / edge of the gate finger 610. Thus, the gate signal is applied to the semiconductor structure 690 from the interior location to the edge.

[0141] On the drain side of the transistor cell, an electrical signal / current received at an inner location of drain finger 615 has the shortest distance to travel to drain flow path 631 to be output by the device, while an electrical signal / current received at an edge portion of drain finger 615 has the longest distance to travel to drain flow path 631 to be output by the device. When viewed as a complete transistor cell, a bias applied to the outermost edge of gate finger 610 that travels the farthest along the gate path can induce a signal on drain finger 615 that also has the farthest travel along the drain path. As the inventors have recognized, this variation can cause current summing problems in the device.

[0142] Fig.14A It is along Fig. 6A The cross-sectional view taken along line AA′ of FIG. 6 illustrates an embodiment of the present invention in which an internally fed gate interconnect 625 is coupled to a gate finger 610 at a location adjacent to an edge of the gate finger 610 . Fig. 14B It is along Fig. 6A , showing an embodiment of the present invention in which an internally fed drain interconnect 635 is coupled to a drain finger 615 via a plurality of conductive vias 638. Fig.14A and Fig. 14B The elements are denoted by like reference numerals, and their repeated descriptions may be omitted.

[0143] According to one aspect of the invention, the gate signal is fed to an inner position 629 of the gate interconnect 625, and the gate interconnect 625 is coupled to the gate finger 610 at positions 647, 648 offset (e.g., offset 1412 and / or offset 1422) from the inner position 629. In some embodiments, the internally fed gate interconnect 625 is coupled to the gate finger 610 at a position adjacent to an edge of the gate finger 610. In some embodiments, Fig.14A The gate interconnect / finger configurations described herein may be combined with the gate interconnect / finger configurations described further herein. Fig. 15B In some embodiments, other gate and / or drain interconnect / finger configurations are possible, such as those described in any other figures. For example, Fig.14A The gate structure can also be Fig.11 Used within the constructs described in or with Fig.11 Used together with the construction described in.

[0144] like Fig.14A, the gate runner 621 may be coupled to the gate finger 610 in a manner similar to that previously described. For example, each gate finger 610 may be coupled to the gate interconnect 625 through a plurality of first conductive gate vias 628. In some embodiments, the gate interconnect 625 may be at a higher level above the semiconductor structure 690 than the gate finger 610 (e.g., in the Z direction). In some embodiments, the gate interconnect 625 may have a larger dimension than the gate finger 610 in a first direction (e.g., in the Y direction). The gate interconnect 625 may be connected to the gate runner 621 through a second conductive gate via 627 at an inner position 629 of the gate interconnect 625. In some embodiments, the gate runner 621 may be at a higher level above the semiconductor structure 690 than the gate interconnect 625. In some embodiments, the inner position 629 may be at a midpoint of the first end 645 and the second end 646 of the gate interconnect 625 (e.g., a midpoint between them). In some embodiments, the inner position 629 may be at a distance within ten percent of the length of the gate interconnect 625 from the midpoint of the gate interconnect 625. In some embodiments, the inner position 629 may be at a distance within twenty percent of the length of the gate interconnect 625 from the midpoint of the gate interconnect 625. In some embodiments, the inner position 629 may be at a distance between one third and two thirds of the distance between the first end 645 and the second end 646 of the gate interconnect 625.

[0145] In some embodiments, the gate runner 621 may have a larger dimension in a first direction (e.g., in the Y direction) than the gate interconnect 625. In some embodiments, the gate runner 621 may include a metal or other highly conductive material, including, for example, copper, gold, and / or composite metals. The gate runner 621 may be further connected to a gate manifold 620. The gate manifold 620 may provide a gate signal to the plurality of transistor cells 700.

[0146] In some embodiments, the gate finger 610 may be composed of a first segment 610A and a second segment 610B, with a gap between the first segment 610A and the second segment 610B, but the present invention is not limited thereto. For example, in some embodiments, the gate finger 610 may be a single segment. In some embodiments, the first segment 610A and the second segment 610B may be arranged in a collinear manner. The length of the first segment 610A (e.g., in the X direction) may be the same as or different from the length of the second segment 610B. The gate finger 610 may have opposing edges 654 and 656. The first opposing edge 654 may be located at the edge of the gate finger 610 that is closest to the gate manifold 620 (see Fig. 6A The second opposing edge 656 may be located at the edge of the gate finger 610 closest to the drain manifold 640 (see Fig. 6A). A first conductive via 628 between the gate interconnect 625 and the gate finger 610 may be connected to the gate finger 610 at a first position 647 offset by a first offset 1410 from the first relative edge 654, and a second conductive via 628 between the gate interconnect 625 and the gate finger 610 may be connected to the gate finger 610 at a second position 648 offset by a second offset 1420 from the second relative edge 656 of the gate finger 610. In other words, the first position 647 may be adjacent to the first relative edge 654, and the second position 648 may be adjacent to the second relative edge 656.

[0147] The first offset 1410 and the second offset 1420 may be configured to position the first and / or second conductive vias 628 adjacent to respective opposing edges 654, 656 of the gate finger 610. In some embodiments, the first and / or second conductive vias 628 may be offset from respective opposing edges 654, 656 of the gate finger 610 by first and second offsets 1410, 1420, the first and second offsets 1410, 1420 being within one-third of the width of the gate finger (e.g., in the X-direction) from the closest opposing edge 654, 656 of the gate finger 610. As used herein, the width of a gate finger 610 (e.g., the width of a gate for an associated transistor cell) is the distance between opposing edges 654, 656 of the gate finger 610 (e.g., in the X-direction) excluding gaps between the gate finger segments 610A, 610B. In some embodiments, the width of the gate finger 610 may be the sum of the width of the first gate finger segment 610A and the width of the second gate finger segment 610B. In some embodiments, the first and / or second conductive vias 628 may be offset from respective opposing edges 654, 656 of the gate finger 610 by first and second offsets 1410, 1420, the first and second offsets 1410, 1420 being within a quarter of the width of the gate finger 610 (e.g., in the X direction) from the closest opposing edge 654, 656 of the gate finger 610. It will be appreciated that the first offset 1410 and the second offset 1420 from the edge 654, 656 may have different values ​​from each other (e.g., one of the offsets may be greater than the other). In some embodiments, the offsets 1412 and / or 1422 between the inner position 629 of the gate interconnect 625 and the position 647 and / or 648 of the gate finger 610 may be greater than the first and / or second offsets 1410, 1420, respectively, between the conductive via 628 and the edge 654, 656 of the gate finger 610.

[0148] In some embodiments, the gate finger 610 may be divided into edge portions E where the first and / or second conductive vias 628 may be connected to the gate finger 610, with a center portion C between the edge portions E. For example, the first conductive via 628 may be connected at a first position 647, and the second conductive via 628 may be connected at a second position 648. The first position 647 of the first conductive via 628 may be offset from an inner position of the gate interconnect 625 by a first offset 1412, and the second position 648 of the second conductive via 628 may be offset from an inner position of the gate interconnect 625 by a second offset 1422.

[0149] In some embodiments, the first position 647 may be located within the first segment 610A of the gate finger 610, that is, within the half of the first segment 610A closest to the gate manifold 620 (see Fig. 6A In some embodiments, the second position 648 may be located within the second segment 610B of the gate finger 610, that is, within the half of the second segment 610B closest to the drain manifold 640 (see Fig. 6A ).

[0150] In some embodiments, the first offset 1410 from the edge 654 and / or the second offset 1420 from the edge 656 may be substantially zero, but the invention is not limited thereto. In other words, the first and / or second conductive vias 628 may be located at or near the respective opposite edges 654, 656 of the gate finger 610. Fig. 14C This embodiment is shown in FIG.

[0151] although Fig.14A and Fig. 14C An embodiment is shown in which each opposing edge 654, 656 of the gate finger 610 has a single conductive via 628 offset from the corresponding edge, but it will be understood that the present invention is not limited thereto. In some embodiments, multiple conductive vias 628 may be located in the edge portion E of the gate finger 610 (e.g., offset from the edge of the gate finger 610). Fig.14D 2 shows an example in which each of the gate finger segments 610A, 610B has a plurality of conductive vias 628 within an edge portion E of the corresponding gate finger segment 610A, 610B.

[0152] In some embodiments, the only connection between the gate interconnect 625 and the gate finger 610 can be within an edge portion E (e.g., offset from a relative edge of the gate finger 610), for example, at a first position 647 and a second position 648, such that a center portion (e.g., center portion C) has no connection to the gate interconnect 625.

[0153] Reference now Fig. 14B, showing that the drain fingers 615 can have different configurations with the conductive vias 638 from the gate fingers 610. Although the gate interconnect 625 can be connected to the gate fingers 610 at or offset from the opposite edges 654, 656 of the gate fingers 610, the drain interconnect 635 can be connected to the drain fingers 615 at multiple locations across the drain fingers 615. In other words, the configuration of the drain fingers can be as previously described with respect to Figure 6C The construct in question.

[0154] The different configurations of the conductive vias between the drain fingers 615 and the gate fingers 610 can follow the direction of energy propagation of the device 600 and allow the transistor device 600 to operate more efficiently than conventional devices.

[0155] although Fig.14A and Fig. 14B 6 shows an embodiment in which the gate finger 610 is connected to the gate interconnect 625 at a location offset from the opposite edge of the gate finger 610 and the drain finger 615 is connected to the drain interconnect 635 across the length of the drain finger 615, but it will be understood that the configuration can be as Fig.15A and Fig. 15B The inversion shown in .

[0156] In some embodiments, drain finger 615 may be connected to drain interconnect 635 at a location offset from an opposite edge of drain finger 615, and gate finger 610 may be connected to gate interconnect 625 across the length of gate finger 610. Fig.15A and Fig. 15B Shown in. Fig.15A It is along Fig. 6A A cross-sectional view taken along line AA' of FIG. 1 shows another embodiment of the present invention in which an internally fed gate interconnect 625 is coupled to a gate finger 610 through a plurality of conductive vias 628. Fig. 15B In, along Fig. 6A In the cross-sectional view taken along line BB′ of FIG. 8 , the internally fed drain interconnect 635 is coupled to the drain finger 615 at a position adjacent to an edge of the drain finger 615 .

[0157] According to one aspect of the present invention, Fig. 15B 639, and the drain interconnect 635 is coupled to at least one drain finger 615 at a first location 657 having an offset of 1512 from the internal location 639 and at a second location 658 having an offset of 1522 from the internal location 639. In some embodiments, the internally fed drain interconnect 635 is coupled to the drain finger 615 at a location adjacent to an edge of the drain finger 615. In some embodiments, the drain interconnect / finger configuration may be similar to Fig.15AIn some embodiments, other drain and / or gate interconnect / finger configurations are possible, such as those described in any of the figures. Fig. 15B The drain structure can also be Fig.11 Used within a structured construct or with Fig.11 Used together with structured constructs.

[0158] refer to Fig. 15B , the drain finger 615 can be composed of a first segment 615A and a second segment 615B, with a gap between the first segment 615A and the second segment 615B, but the present invention is not limited to this. For example, in some embodiments, the drain finger 615 can be a single segment. In some embodiments, the first segment 615A and the second segment 615B can be arranged in a collinear manner. The length of the first segment 615A (for example, in the X direction) can be the same as or different from the length of the second segment 615B. The drain finger 615 can have opposing edges 664 and 665. The first opposing edge 664 can be located at the edge of the drain finger 615 that is closest to the gate manifold 620 (see Fig. 6A The second opposing edge 665 may be located at the edge of the drain finger 615 closest to the drain manifold 640 (see Fig. 6A ). A second conductive via 638 between the drain interconnect 635 and the drain finger 615 may be connected to the drain finger 615 at a first position 657 offset by a first offset amount 1510 from the first relative edge 664, and a second conductive via 638 between the drain interconnect 635 and the drain finger 615 may be connected to the drain finger 615 at a second position 658 offset by a second offset amount 1520 from the second relative edge 665 of the drain finger 615.

[0159] The first offset 1510 and the second offset 1520 can be configured to position the first and / or second conductive vias 638 adjacent to respective opposing edges 664, 665 of the drain finger 615. In some embodiments, the first and / or second conductive vias 638 can be offset from respective opposing edges 664, 665 of the drain finger 615 by first and second offsets 1510, 1520, the first and second offsets 1510, 1520 being within one-third, or in some embodiments, one-quarter, of the width of the drain finger 615 (e.g., in the X direction) from the closest opposing edge 664, 665 of the drain finger 615. As used herein, the width of the drain finger 615 is the distance between the opposing edges 664, 665 of the drain finger 615 (e.g., in the X direction) excluding gaps between the drain finger segments 615A, 615B. In some embodiments, the width of the drain finger 615 may be the sum of the width of the first drain finger segment 615A and the width of the second drain finger segment 615B. In some embodiments, the first and / or second conductive vias 638 may be offset from the respective opposite edges 664, 665 of the drain finger 615 by first and second offsets 1510, 1520, the first and second offsets 1510, 1520 being within one quarter of the width of the drain finger 615 (e.g., in the X direction) from the closest opposite edges 664, 665 of the drain finger 615. It will be appreciated that the first offset 1510 and the second offset 1520 may have different values ​​from each other (e.g., one of the offsets may be greater than the other offset). In some embodiments, the offset 1512 and / or 1522 between the inner position 639 of the drain interconnect 635 and the position 657 and / or 658 of the drain finger 615 can be greater than the first and / or second offset 1510 , 1520 between the conductive via 638 and the edge 664 , 665 of the drain finger 615 .

[0160] In some embodiments, the drain finger 615 can be divided into edge portions E where the first and / or second conductive vias 638 can be connected to the drain finger 615, with a center portion C between the edge portions E. In some embodiments, the first location 657 can be located within the first segment 615A of the drain finger 615, the first location 657 being within the half of the first segment 615A closest to the gate manifold 620 (see Fig. 6A In some embodiments, the second position 658 may be located within the second segment 615B of the drain finger 615, the second position 658 being within the half of the second segment 615B closest to the drain manifold 640 (see Fig. 6A ).

[0161] In some embodiments, the first offset 1510 and / or the second offset 1520 may be substantially zero, but the present invention is not limited thereto. In other words, the first conductive via 638 and / or the second conductive via 638 may be located at or near the respective opposite edges 664, 665 of the drain finger 615. Fig. 15C Shown in.

[0162] although Fig.15A and Fig. 15C An embodiment is shown in which each opposing edge 664, 665 of the drain finger 615 has a single conductive via 638 offset from the corresponding edge, but it will be understood that the present invention is not limited thereto. In some embodiments, multiple conductive vias 638 may be located in the edge portion E of the drain finger 615 (e.g., offset from the edge of the drain finger 615). Fig.15D 6 shows an example in which each of the drain finger segments 615A, 615B has a plurality of conductive vias 638 within an edge portion E of the corresponding drain finger segment 615A, 615B.

[0163] In some embodiments, the only connection between the drain interconnect 635 and the drain finger 615 can be within the edge portion E (e.g., offset from the opposite edge of the drain finger 615, for example, at the first position 657 and the second position 658) so that the center portion (e.g., the center portion C) has no connection to the drain interconnect 635.

[0164] Reference now Fig.15A , showing that the gate finger 610 can have a different configuration than the conductive via 628 of the drain finger 615. While the drain interconnect 635 can be connected to the drain finger 615 at or offset from the opposite edges 664, 665 of the drain finger 615, the gate interconnect 625 can be connected to the gate finger 610 at multiple locations across the gate finger 610. In other words, the configuration of the gate finger can be as previously described with respect to Figure 6B The construct in question.

[0165] As discussed herein with respect to previous embodiments, embodiments of the present invention incorporating edge-fed gates and / or drains may be configured to extend at least a portion of a gate interconnect and / or gate runner over a source region. Fig.16A is a plan view showing a transistor device 1300 ′ incorporating an edge-fed gate finger 610 , wherein a gate runner 621 extends over a source region 605 . Fig. 16B is taken along line D-D' according to some embodiments of the present invention Fig.16A Cross-sectional view of . Fig. 16C Also according to an additional embodiment of the present invention, taken along line D-D' Fig.16ASimilar to those described previously Figure 16A-16C The elements are denoted by like reference numerals, and repeated description thereof may be omitted.

[0166] like Fig.16A As shown in , in some embodiments, portions of gate runner 621 and / or gate interconnect 625 may extend over source region 605 of transistor device 1300'. Portions of gate runner 621 and / or gate interconnect 625 may be offset from gate finger 610 (e.g., in the Y direction). For example, Fig.16A and Fig. 16B , the gate runner 621 may extend over the source region 605 adjacent to the gate finger 610. The gate runner 621 may be connected to the gate interconnect 625 at an inner position 629 of the gate interconnect 625. The inner position 629 may be between the first end 645 and the second end 646 of the gate interconnect 625. In some embodiments, the inner position 629 may be at a midpoint of the gate finger 610. In some embodiments, the inner position 629 may be at a distance within ten percent of the length of the gate finger 610 from the midpoint of the gate finger 610. In some embodiments, the inner position 629 may be at a distance within twenty percent of the length of the gate finger 610 from the midpoint of the gate finger 610. In some embodiments, the inner position 629 may be at a distance between one-third and two-thirds of the distance between the opposing ends of the gate finger 610.

[0167] Gate runner 621 may be connected to gate interconnect 625 through conductive portion 627'. In some embodiments, conductive portion 627' may extend between gate runner 621 and gate interconnect 625 in a direction parallel to a surface of semiconductor structure 690 (eg, the Y direction).

[0168] In some embodiments, the gate finger 610 may be composed of a first gate finger segment 610A and a second gate finger segment 610B, with a gap between the first gate finger segment 610A and the second gate finger segment 610B. In some embodiments, the first gate finger segment 610A and the second gate finger segment 610B may be arranged in a collinear manner. The gate finger 610 may have opposing edges 654 and 656. The first opposing edge 654 may be located at an edge of the gate finger 610 that is closest to the gate manifold 620 (see Fig. 6A The second opposing edge 656 may be located at the edge of the gate finger 610 closest to the drain manifold 640 (see Fig. 6A). A first conductive via 628 between the gate interconnect 625 and the gate finger 610 may be connected to the gate finger 610 at a first position 647 offset from the first opposite edge 654, and a second conductive via 628 between the gate interconnect 625 and the gate interconnect 610 may be connected to the gate finger 610 at a second position 648 offset from the second opposite edge 656 of the gate finger 610. Although Fig.16A The conductive via 628 is shown to be offset from the opposing edges 654, 656 by substantially zero, but it will be understood that the present invention is not limited thereto and the conductive via 628 may be offset from the opposing edges 654, 656 of the gate finger 610 by a non-zero distance. Thus, the connection between the gate interconnect 625 and the gate finger 610 may be substantially similar to that described herein with respect to Fig.14A The connection in question.

[0169] The gate runner 621 may be disposed at the same level as the gate interconnect 625, such as Fig. 16B As shown in, but the embodiments described herein are not limited thereto. Fig. 16C As shown in , the gate runner 621 may be disposed at a different level than the gate interconnect 625. In such an embodiment, the conductive portion 627' may also extend in a direction perpendicular to the top surface of the semiconductor structure 690 (eg, the Z direction).

[0170] although Figure 16A-16C An embodiment is shown in which the gate interconnect 625 extends over the gate finger 610, but it will be understood that the invention is not limited thereto. In some embodiments, a portion of the gate interconnect 625 may extend over a portion of the semiconductor substrate between the gate finger 610 and the adjacent source region. Fig.17A An embodiment of a transistor device 1300" is shown in which a gate runner 621 and a gate interconnect 625 both extend over a region of the semiconductor structure adjacent to a gate finger. Fig. 17B 2 shows a diagram taken along line D-D' according to an embodiment of the present invention. Fig.17A Cross-sectional view of .

[0171] like Fig.17A As shown in , the gate runner 621 may extend partially over the source region 605 adjacent to the gate finger 610. The gate runner 621 may be connected to the gate interconnect 625 via a first conductive portion 627'. In some embodiments, the first conductive portion 627' may extend between the gate runner 621 and the gate interconnect 625 in a direction parallel to the surface of the semiconductor structure 690 (e.g., the Y direction). In some embodiments, the first conductive portion 627' may be made of the same or similar material as the gate runner 621.

[0172] The gate interconnect 625 may also extend over a portion of the semiconductor structure 690 adjacent to the gate finger 610. In some embodiments, the gate interconnect 625 may extend over a portion of the semiconductor structure 690 between the gate finger 610 and the source region 105. In some embodiments, the gate interconnect 625 may extend over a portion of the source region 105.

[0173] The gate interconnect may be partially connected to the gate finger 610 through the second conductive portion 627 ″. The second conductive portion 627 ″ may extend between the gate interconnect 625 and the conductive via 628. Fig. 17B As shown in FIG. 6 , the conductive via 628 may be as described herein, for example, with respect to Fig.14A The ground in question is coupled to an edge portion E of the gate finger 610 .

[0174] The gate runner 621 and the gate interconnect 625 may be disposed at different levels. In some embodiments, at least a portion of the gate runner 621 may overlap a portion of the gate interconnect 625. In some embodiments, both the gate runner 621 and the gate interconnect 625 may include metal, but the present invention is not limited thereto. In some embodiments, the cross-section of the gate runner 621 may have a larger dimension (e.g., in the Y direction) than the cross-section of the gate interconnect 625.

[0175] Embodiments as described herein may allow segmented gate fingers 610 arranged in co-linear fashion to still operate as if they were arranged in parallel, while the drains operate in an internally fed manner. In some embodiments, this configuration may allow each gate finger of a transistor having a width of 2W to operate as a parallel pair of shorter gate fingers each having a width of W, but without doubling the number of fingers. This configuration may retain the benefit of lower gate resistance, producing higher gain while producing the same high power.

[0176] Edge-fed gate fingers and center-fed drain fingers follow the direction of energy propagation of the device and allow the currents to sum in phase. This will help preserve the RF performance of shorter fingers in terms of output power density and efficiency. In some embodiments, similar benefits can be obtained by using center-fed gate fingers and edge-fed drain fingers.

[0177] It will be understood that, although the term first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present invention, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0178] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "one", "an" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this article, the terms "comprise", "comprises", "includes" and / or "comprising" specify that there are specified features, integers, steps, operations, elements and / or components, but do not exclude the presence or increase of one or more other features, integers, steps, operations, elements, components and / or their groups.

[0179] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the present invention belongs. It will be further understood that, unless expressly defined herein, the terms used herein should be interpreted as having a meaning consistent with the meaning in the context of this specification and the relevant field, and will not be interpreted in an idealized or overly formal sense.

[0180] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or extending directly on the other element, or there may also be intervening elements. Conversely, when an element is referred to as being "directly on" or "extending directly on" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0181] Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical", may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0182] Embodiments of the present invention are described herein with reference to cross-sectional views, which are schematic diagrams of ideal embodiments (and intermediate structures) of the present invention. For clarity, the thickness of layers and regions in the drawings may be exaggerated. In addition, variations in the illustrated shapes may be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present invention should not be interpreted as being limited to the specific shapes of the regions shown herein, but should include shape deviations, such as those caused by manufacturing.

[0183] In the drawings and specification, typical embodiments of the invention have been disclosed, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the appended claims.

Claims

1. A transistor device, comprising: Semiconductor structures; a gate finger, wherein the longest edge of the gate finger extends in a first direction on the semiconductor structure; and A gate interconnect extends in the first direction and is configured to be coupled to a gate signal at an inner position of the gate interconnect, wherein the gate interconnect is connected to the gate finger at a position offset from the inner position of the gate interconnect.

2. The transistor device according to claim 1, wherein: The gate finger includes edge portions at opposite edges of the gate finger, wherein a center portion is between the edge portions, and Wherein, the gate interconnect is connected to the edge portion of the gate finger via a plurality of conductive vias.

3. The transistor device according to claim 1 or 2, wherein: The gate finger has no conductive via connected to the central portion of the gate finger.

4. The transistor device according to claim 1 or 2, wherein: The edge portion is within one third of a width of the gate finger in the first direction from a corresponding opposing edge of the gate finger.

5. The transistor device according to claim 1 or 2, wherein: The gate interconnect is connected to the gate finger at a first location on the gate finger adjacent to a first edge of the gate finger and at a second location on the gate finger adjacent to a second edge of the gate finger.

6. The transistor device according to claim 1 or 2, further comprising: a gate channel extending on the semiconductor structure in the first direction, wherein the gate interconnect has a first end and a second end, and Wherein, the gate interconnection is connected to the gate runner at the inner position of the gate interconnection away from the first end and the second end of the gate interconnection.

7. The transistor device according to claim 6, wherein: The gate finger extends on the semiconductor structure at a first level above the semiconductor structure, the gate interconnect extends on the semiconductor structure at a second level above the semiconductor structure that is higher than the first level, and the gate runner extends on the semiconductor structure at a third level above the semiconductor structure that is equal to or higher than the second level.

8. The transistor device according to claim 1 or 2, wherein: The gate finger includes a first segment and a second segment with a gap therebetween.

9. The transistor device according to claim 1 or 2, further comprising: a drain finger extending on the semiconductor structure in the first direction; as well as A drain interconnect extends in the first direction and is configured to be coupled to a drain signal at an inner position of the drain interconnect, wherein the drain interconnect is connected to the drain fingers through a plurality of conductive vias.

10. The transistor device according to claim 1 or 2, wherein: The position offset from an inner position of the gate interconnect is offset from the inner position of the gate interconnect by a first offset amount and from an edge of the gate finger by a second offset amount, and The first offset is greater than the second offset.

11. A transistor device comprising: Semiconductor structures; a drain finger extending on the semiconductor structure in a first direction; as well as A drain interconnect extends in the first direction and is configured to be coupled to a drain signal at an inner position of the drain interconnect, wherein the drain interconnect is connected to the drain finger at a position offset from the inner position of the drain interconnect.

12. The transistor device according to claim 11, wherein: The drain finger includes edge portions at opposite edges of the drain finger, wherein a center portion is between the edge portions, and Wherein, the drain interconnect is connected to the edge portion of the drain finger via a plurality of conductive vias.

13. The transistor device according to claim 11 or 12, wherein: The drain finger has no conductive via connected to the central portion of the drain finger.

14. The transistor device according to claim 11 or 12, wherein: The edge portion is within one third of a width of the drain finger in the first direction from a corresponding opposing edge of the drain finger.

15. The transistor device according to claim 11 or 12, wherein: The drain interconnect is connected to the drain finger at a first location on the drain finger adjacent to a first edge of the drain finger and at a second location on the drain finger adjacent to a second edge of the drain finger.

16. The transistor device according to claim 11 or 12, further comprising: a drain channel extending on the semiconductor structure in the first direction, wherein the drain interconnect has a first end and a second end, and The drain interconnect is connected to the drain channel at the inner position of the drain interconnect away from the first end and the second end of the drain interconnect.

17. The transistor device according to claim 16, wherein: The drain finger extends on the semiconductor structure at a first level above the semiconductor structure, the drain interconnect extends on the semiconductor structure at a second level above the semiconductor structure that is higher than the first level, and the drain channel extends on the semiconductor structure at a third level above the semiconductor structure that is equal to or higher than the second level.

18. The transistor device according to claim 11 or 12, further comprising: a gate finger extending on the semiconductor structure in the first direction; as well as A gate interconnect extends in the first direction and is configured to be coupled to a gate signal at an inner position of the gate interconnect, wherein the gate interconnect is connected to the gate fingers through a plurality of conductive vias.

19. The transistor device according to claim 11 or 12, wherein: The position offset from an inner position of the drain interconnect is offset from the inner position of the drain interconnect by a first offset amount and from an edge of the drain finger by a second offset amount, and The first offset is greater than the second offset.

20. A transistor device comprising: Semiconductor structures; and A plurality of gate fingers and a plurality of drain fingers are alternately arranged on the semiconductor structure, wherein the plurality of gate fingers and the plurality of drain fingers each extend in a first direction, wherein the gate fingers of the plurality of gate fingers and the drain fingers of the plurality of drain fingers include corresponding edge portions at opposite edges thereof, wherein the center portion is between the corresponding edge portions, wherein one of the gate fingers or the drain fingers has a plurality of conductive vias connected to its corresponding edge portion and has no conductive via connected to the central portion, and The other of the gate finger or the drain finger has at least one conductive via connected to a central portion thereof.

21. The transistor device according to claim 20, wherein: The corresponding edge portion is within one third of the width of the gate finger or the drain finger in the first direction from an opposite edge of the gate finger or the drain finger.

22. The transistor device according to claim 20 or 21, further comprising: a plurality of gate interconnects on the semiconductor structure, respective ones of the plurality of gate interconnects coupled to respective ones of the plurality of gate fingers; as well as A plurality of gate channels extending on the semiconductor structure, wherein each of the plurality of gate interconnects has a first end and a second end, and Wherein, at least one of the gate interconnects is connected to one of the gate runners at an inner position of the at least one of the gate interconnects away from the first end and the second end of the at least one of the gate interconnects.

23. The transistor device according to claim 20 or 21, further comprising a plurality of source regions and a plurality of drain regions alternately arranged on the semiconductor structure, in, A corresponding gate finger of the plurality of gate fingers extends between adjacent source and drain regions, and Wherein, at least one of the gate runners extends over one of the source regions.

24. The transistor device according to claim 23, wherein: The at least one of the gate runners extends in the first direction, and Wherein, a first dimension of at least one of the gate runners in a second direction intersecting the first direction exceeds a second dimension of at least one of the gate interconnectors in the second direction.

25. A transistor device comprising: Semiconductor structures; a plurality of gate fingers extending in a first direction on the semiconductor structure; a plurality of gate interconnects, each gate interconnect having a first end and a second end extending on the semiconductor structure in the first direction, wherein each gate interconnect is connected to a corresponding gate finger through a plurality of first conductive vias; and a plurality of gate channels extending on the semiconductor structure in the first direction, At least one of the gate interconnects is connected to one of the gate runners through a second conductive via at an inner position of the at least one gate interconnect away from the first end and the second end of the at least one gate interconnect.

26. The transistor device according to claim 25, wherein: A respective one of the gate fingers is configured to function as a gate electrode of the transistor device.

27. A transistor device according to claim 25 or 26, wherein: The gate finger extends on the semiconductor structure at a first level above the semiconductor structure, the gate interconnect extends on the semiconductor structure at a second level above the semiconductor structure that is higher than the first level, and the gate runner extends on the semiconductor structure at a third level above the semiconductor structure that is higher than the second level.

28. A transistor device according to claim 25 or 26, wherein: The inner position of the at least one gate interconnect is between one third and two thirds of the distance between the first end and the second end of the at least one gate interconnect.

29. The transistor device according to claim 25 or 26, wherein: The inner position of the at least one gate interconnection is at a midpoint between a first end and a second end of the at least one gate interconnection.

30. The transistor device according to claim 25 or 26, wherein: A first gate finger of the gate fingers includes a first segment and a second segment with a gap between the first segment and the second segment.

31. The transistor device according to claim 30, wherein: An inner position of the at least one gate interconnection vertically overlaps the gap.

32. The transistor device of claim 25 or 26, further comprising a gate manifold on the semiconductor structure connected to the gate runner, wherein: The gate manifold extends over the semiconductor structure in a second direction that intersects the first direction.

33. The transistor device according to claim 32, wherein: The gate flow channels are first gate flow channels, each of the first gate flow channels has a third end and a fourth end, wherein the internal position is a first internal position, The transistor device further includes a plurality of second gate channels extending on the semiconductor structure in the first direction. wherein at least one second gate runner is connected to the first gate runner through a third conductive via, the third conductive via being connected to the first gate runner at a second inner position of the first gate runner away from the third end and the fourth end of the first gate runner, and Wherein, the gate manifold is connected to the first gate flow channel through a corresponding second gate flow channel in the second gate flow channels.

34. A transistor device according to claim 25 or 26, wherein: The interior position is a first interior position, and Wherein, the transistor device further comprises: a plurality of drain fingers extending on the semiconductor structure in the first direction; a plurality of drain interconnects, each drain interconnect having a third end and a fourth end extending on the semiconductor structure in the first direction, wherein each drain interconnect is connected to a corresponding drain finger through a plurality of third conductive vias; a plurality of drain channels extending on the semiconductor structure in the first direction, wherein a second inner position of at least one drain interconnect away from the third end and the fourth end of the at least one drain interconnect is connected to the drain flow channel through a fourth conductive via; and A drain manifold is on the semiconductor structure and connected to the plurality of drain runners.

35. A transistor device comprising: Semiconductor structures; a plurality of source regions and a plurality of drain regions alternately arranged on the semiconductor structure; a plurality of gate fingers extending at a first level above the semiconductor structure between adjacent source and drain regions; a plurality of gate interconnects on the semiconductor structure at a second level above the semiconductor structure that is higher than the first level, wherein each gate interconnect is connected to a corresponding gate finger through a plurality of first conductive vias; and A plurality of gate runners are on the semiconductor structure at a third level above the semiconductor structure that is higher than the second level, wherein at least one of the gate runners is connected to at least one of the gate interconnects through a second conductive via connected to the at least one of the gate interconnects at a first internal position on the at least one of the gate interconnects that overlaps an adjacent source region.

36. The transistor device according to claim 35, wherein: The first inner position is between one third and two thirds of a distance between a first end and a second end of the at least one of the gate interconnects.

37. A transistor device according to claim 35 or 36, further comprising a gate manifold on the semiconductor structure and connected to the gate runner, in, The plurality of gate runners are first gate runners, each first gate runner having a third end and a fourth end, Wherein, the transistor device further includes a plurality of second gate channels extending on the semiconductor structure, wherein the second gate runner is connected to at least one of the first gate runners through a third conductive via, the third conductive via being connected to the at least one of the first gate runners at a second inner position of the at least one of the first gate runners away from a third end and a fourth end of the at least one of the first gate runners, and Wherein, the gate manifold is connected to the plurality of first gate runners through corresponding second gate runners among the plurality of second gate runners.

38. A transistor device according to claim 35 or 36, wherein: The width of the at least one of the gate runners exceeds the width of the at least one of the gate interconnects.

39. A transistor device according to claim 35 or 36, wherein: The transistor device further comprises: a plurality of drain fingers, respectively on the plurality of drain regions; a plurality of drain interconnects on the semiconductor structure, wherein each of the drain interconnects is connected to a corresponding drain finger through a plurality of third conductive vias; a plurality of drain flow channels on the semiconductor structure, wherein at least one of the drain flow channels is connected to at least one of the drain interconnects through a fourth conductive via, the fourth conductive via being connected to the at least one of the drain interconnects at a second inner location on the at least one of the drain interconnects that overlaps an adjacent source region; and A drain manifold is on the semiconductor structure and connected to the drain runner.

40. The transistor device of claim 39, wherein: The gate runner and the at least one of the drain runners are at different levels above the semiconductor structure.

41. A transistor device comprising: Semiconductor structures; a plurality of gate fingers extending over the semiconductor structure; a plurality of gate interconnects on the semiconductor structure, each of the gate interconnects being electrically coupled to a respective gate finger, wherein each gate interconnect has a first end and a second end; and A plurality of gate runners on the semiconductor structure, wherein at least one of the gate runners is connected to at least one of the gate interconnects through a conductive via, wherein a current received at a first end of the at least one of the gate interconnects via the conductive via has a phase difference of less than 1 degree compared to a current received at a second end of the at least one of the gate interconnects via the conductive via.

42. The transistor device according to claim 41, wherein The gate runner and the gate interconnect extend in a first direction, Wherein, a first dimension of at least one of the gate runners in a second direction intersecting the first direction exceeds a second dimension of at least one of the gate interconnectors in the second direction.

43. A transistor device according to claim 41 or 42, wherein: The conductive via is connected to an inner position of the at least one of the gate interconnects, the inner position being between one third and two thirds of a distance between the first end and the second end of the at least one of the gate interconnects.

44. A transistor device according to claim 41 or 42, wherein: A first gate finger of the gate fingers includes a first segment and a second segment with a gap between the first segment and the second segment.

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