Non-volatile memory device, operation method thereof, and storage device

Abstract

A nonvolatile memory device, a storage device, and a method for operating the nonvolatile memory device are provided. Each memory block of the nonvolatile memory device includes first memory cells in a first portion of a column and second memory cells in a second portion of the column. When a programming operation is performed based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes a first programming operation for non-adjacent memory cells, among the first and second memory cells, that are not adjacent to a boundary between the first and second portions, and then completes a second programming operation for adjacent memory cells adjacent to the boundary.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0104615, filed on August 26, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concepts described herein relate to semiconductor circuits, and more particularly, to a nonvolatile semiconductor memory, a memory device, and a method of operating the nonvolatile memory device. Background Art

[0004] A nonvolatile memory device is a memory that can retain stored data even when the power is turned off. Examples of nonvolatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase change memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0005] The capacity of a nonvolatile memory device can be increased by arranging the device's memory cells in a three-dimensional stack. However, the reliability of some memory cells in the three-dimensional stack is lower than the reliability of other memory cells in the three-dimensional stack.

[0006] When data is not written in a memory cell with low reliability, the capacity of the nonvolatile memory device is reduced. When data is written in a memory cell with low reliability, the possibility of data loss increases. Summary of the Invention

[0007] At least one example embodiment of the inventive concepts provides a nonvolatile memory device, a storage device, and an operating method of the nonvolatile memory device capable of performing a program operation that increases the reliability of data written in a memory cell having low reliability.

[0008] According to an exemplary embodiment of the present invention, a nonvolatile memory device includes a memory cell array, a row decoder, and a page buffer. The memory cell array is disposed on a substrate. The memory cell array includes memory blocks. The row decoder is connected to the memory cell array via word lines, and the page buffer block is connected to the memory cell array via bit lines. Each memory block includes a pillar having a first portion disposed on the substrate and a second portion stacked on the first portion. The width of the first portion increases with increasing distance from the substrate, and a first conductive material and a first insulating layer surround the first portion and are sequentially stacked on the substrate. The width of the second portion increases with increasing distance from the substrate, and a second conductive material and a second insulating layer surround the second portion and are sequentially stacked on the substrate. A first boundary is located between the first portion and the second portion. The first conductive material and the first portion together form a first memory cell, and the second conductive material and the second portion together form a second memory cell. When a programming operation is performed based on consecutive addresses in a selected memory block, the row decoder and the page buffer are configured to sequentially complete the first programming operation for non-adjacent memory cells of the first and second memory cells that are not adjacent to the first boundary, followed by completing the second programming operation for adjacent memory cells adjacent to the first boundary.

[0009] According to an exemplary embodiment of the present invention, a memory device includes a nonvolatile memory device including a plurality of memory blocks, and a controller that controls a write operation on a selected one of the memory blocks of the nonvolatile memory device. Each memory block includes a first memory cell corresponding to a first portion of a pillar, the first portion extending in a direction perpendicular to a substrate, and a second memory cell corresponding to a second portion of the pillar, the second portion extending in a direction perpendicular to the substrate and disposed on the first portion. The first and second memory cells are classified into at least one first adjacent memory cell adjacent to a first boundary between the first and second portions, and first non-adjacent memory cells that are the remaining memory cells other than the at least one first adjacent memory cell. In a write operation on the selected memory block, the controller controls the nonvolatile memory device so that, upon completion of the programming operation on the first and second memory cells, the number of bits to be written in the at least one first adjacent memory cell is less than the number of bits to be written in the respective first non-adjacent memory cells.

[0010] According to an exemplary embodiment of the present invention, a method for operating a nonvolatile memory device includes memory cells connected in series between a string select transistor and a ground select transistor, the method comprising: performing a first programming operation on a first memory cell among the memory cells; and, after completing the first programming operation on the first memory cell, performing a second programming operation on at least one second memory cell located between the first memory cells. The memory cells are stacked in a direction perpendicular to a substrate based on a first portion of a pillar and a second portion of the pillar, the first portion extending in a direction perpendicular to the substrate, and the second portion extending in a direction perpendicular to the substrate and disposed on the first portion. The at least one second memory cell is adjacent to a boundary between the first portion and the second portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present inventive concept will become apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram illustrating a nonvolatile memory device according to an exemplary embodiment of the inventive concept.

[0013] Figure 2 An example of one memory block according to an exemplary embodiment of the inventive concept is shown.

[0014] Figure 3 is shown with Figure 2 FIG. 1 is a perspective cross-sectional view of an example of a cell string corresponding to a second bit line and a third bit line of a memory block.

[0015] Figure 4 It is schematically shown Figure 3 Cross-sectional view of a memory block.

[0016] Figure 5 An operating method of a nonvolatile memory device according to an exemplary embodiment of the inventive concept is illustrated.

[0017] Figure 6 An example of a scheme in which a nonvolatile memory device performs a program operation is shown.

[0018] Figure 7 An example is shown in which a pillar of a memory block consists of a first portion to a third portion.

[0019] Figure 8 Shown in which the nonvolatile memory device is Figure 7 An example of performing a programming operation on a memory block.

[0020] Figure 9 An operating method of a nonvolatile memory device according to an exemplary embodiment of the inventive concept is illustrated.

[0021] Figure 10 An example of a single-step programming operation is shown.

[0022] Figure 11 An example of a multi-step programming operation is shown.

[0023] Figure 12 and Figure 13 Shown is a nonvolatile memory device according to Figure 9 Examples of how to perform programming operations.

[0024] Figure 14 A storage device including a non-volatile memory device is shown.

[0025] Figure 15 An operating method of a memory device according to an exemplary embodiment of the inventive concept is illustrated.

[0026] Figure 16 A memory device according to an exemplary embodiment of the inventive concept is illustrated. DETAILED DESCRIPTION

[0027] Below, embodiments of the inventive concept are described in detail and clearly to the extent that those skilled in the art can implement the inventive concept.

[0028] Figure 1 1 is a block diagram illustrating a nonvolatile memory device 100 according to an embodiment of the inventive concept. Figure 1 The nonvolatile memory device 100 includes a memory cell array 110, a row decoder block 120 (e.g., a row decoding circuit), a page buffer block 130 (e.g., one or more page buffers), a data input and output block 140 (e.g., an input / output circuit), a buffer block 150 (e.g., one or more buffers), and a control logic block 160 (e.g., a control circuit).

[0029] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells. Each of the memory blocks BLK1 to BLKz can be connected to the row decoder block 120 via at least one ground select line GSL, a word line WL, and at least one string select line SSL. Some word lines WL can be used as dummy word lines. Each memory block can be connected to the page buffer block 130 via a plurality of bit lines BL. The plurality of memory blocks BLK1 to BLKz can be commonly connected to the plurality of bit lines BL.

[0030] In an embodiment, each of the plurality of memory blocks BLK1 to BLKz corresponds to a unit of erase operation. Memory cells belonging to each memory block can be erased simultaneously. In another example, each of the plurality of memory blocks BLK1 to BLKz can be divided into a plurality of sub-blocks. Each of the plurality of sub-blocks can correspond to a unit of erase operation.

[0031] The row decoder block 120 is connected to the memory cell array 110 through the ground selection line GSL, the word line WL, and the string selection line SSL. The row decoder block 120 operates under the control of the control logic block 160.

[0032] The row decoder block 120 may decode the row address RA received from the buffer block 150 and may control voltages to be applied to the string selection line SSL, the word line WL, and the ground selection line GSL based on the decoded row address.

[0033] The page buffer block 130 is connected to the memory cell array 110 through a plurality of bit lines BL. The page buffer block 130 is connected to the data input and output block 140 through a plurality of data lines DL. The page buffer block 130 operates under the control of the control logic block 160.

[0034] During a write operation, the page buffer block 130 may store the data to be written in the memory cell. The page buffer block 130 may apply a voltage to the plurality of bit lines BL based on the stored data. During a read operation or a verification read operation performed during a write operation or an erase operation, the page buffer block 130 may sense the voltage of the bit line BL to generate a sensing result, and may store the sensing result.

[0035] The data input and output block 140 is connected to the page buffer block 130 through a plurality of data lines DL. The data input and output block 140 may receive a column address CA from the buffer block 150. The data input and output block 140 may output data read from the page buffer block 130 to the buffer block 150 according to the column address CA. The data input and output block 140 may provide the data received from the buffer block 150 to the page buffer block 130 based on the column address CA.

[0036] The buffer block 150 may receive a command CMD and an address ADDR from an external device through the first channel CH1 and may exchange data "DATA" with the external device. The buffer block 150 may operate under the control of the control logic block 160. The buffer block 150 may transmit the command CMD to the control logic block 160. The buffer block 150 may transmit the row address RA in the address ADDR to the row decoder block 120 and may transmit the column address CA in the address ADDR to the data input and output block 140. The buffer block 150 may exchange data "DATA" with the data input and output block 140.

[0037] The control logic block 160 may exchange a control signal CTRL from an external device through the second channel CH2 . The control logic block 160 may control the buffer block 150 to route a command CMD, an address ADDR, and data “DATA”.

[0038] The control logic block 160 may decode the command CMD received from the buffer block 150 and may control the nonvolatile memory device 100 according to the decoded command. In an exemplary embodiment of the present inventive concept, the control logic block 160 specifies the order of program operations in which the row decoder block 120 and the page buffer block 130 program memory cells based on differences in structures and different characteristics of the memory cells.

[0039] Figure 2 An example of one memory block BLK1 according to an exemplary embodiment of the inventive concept is shown. Figure 2 , a plurality of cell strings CS are arranged in the first, second, and third directions on a substrate SUB. The plurality of cell strings CS may be commonly connected to a common source line CSL formed on (or in) the substrate SUB. Figure 2 , the position of the substrate SUB is shown to help understand the structure of the memory block BLK1.

[0040] The cell strings of a row can be commonly connected to a ground select line GSL, and the cell strings of each row can be connected to a corresponding one of the first to fourth upper string select lines SSLu1 to SSLu4 and a corresponding one of the first to fourth lower string select lines SSLl1 to SSLl4. The cell strings of each column can be connected to a corresponding one of the first to fourth bit lines BL1 to BL4. For simplified illustration, the cell strings connected to the second and third string select lines SSL21 and SSL2u and SSL31 and SSL3u are depicted as blurred.

[0041] Each cell string may include at least one ground selection transistor GST connected to a ground selection line GSL, a first dummy memory cell DMC1 connected to a first dummy word line DWL1, first to tenth memory cells MC1 to MC10 connected to the first to tenth word lines WL1 to WL10, respectively, a second dummy memory cell DMC2 connected to a second dummy word line DWL2, and a lower string selection transistor SSTl and an upper string selection transistor SSTu connected to corresponding lower string selection lines and upper string selection lines, respectively.

[0042] In each cell string, the ground selection transistor GST, the first dummy memory cell DMC1, the first to tenth memory cells MC1 to MC10, the second dummy memory cell DMC2, the lower string selection transistor SSTl, and the upper string selection transistor SSTu can be connected in series along a third direction perpendicular to the substrate SUB and can be stacked sequentially along the third direction perpendicular to the substrate SUB.

[0043] Memory block BLK1 can be configured as a 3D memory array. The 3D memory array is integrally formed in one or more physical layers of an array of memory cells MC, having active regions disposed above a substrate SUB (e.g., silicon) and circuitry associated with the operation of the memory cells MC. The circuitry associated with the operation of the memory cells MC can be located above or within the substrate SUB. The term "integral" means that the layers of each layer of the array are deposited directly on the layers of the underlying layers of the 3D memory array.

[0044] In an embodiment of the present inventive concept, a 3D memory array includes vertical cell strings CS (or NAND strings) that are vertically oriented such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trap layer. Each cell string may also include at least one select transistor positioned above a memory cell MC. The at least one select transistor may have the same structure as the memory cell MC and may be formed uniformly with the memory cell MC.

[0045] The following patent documents, incorporated herein by reference, describe suitable configurations for three-dimensional memory arrays configured into multiple levels with word lines and / or bit lines shared between levels: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0046] Figure 3 is shown with Figure 2 1 is a perspective cross-sectional view of an example of a cell string CS corresponding to the second bit line BL2 and the third bit line BL3 of the memory block BLK1. Figure 2 and Figure 3 Common source regions CSR extending along the first direction and spaced apart from each other along the second direction are disposed on the substrate SUB.

[0047] The common source regions CSR may be connected together to form a common source line CSL. In an embodiment, the substrate 101 includes a P-type semiconductor material. The common source regions CSR may include an N-type semiconductor material. For example, a conductive material for improving the conductivity of the common source line CSL may be provided on the common source regions CSR.

[0048] The pillars PL are located between the common source regions CSR. In an exemplary embodiment, the pillars PL are perpendicular to the substrate 101 or parallel to the third direction. Each pillar PL includes an inner material 114 , a channel layer 115 , and a first insulating layer 116 .

[0049] The inner material 114 may include an insulating material or an air gap. The channel layer 115 may include a P-type semiconductor material or an intrinsic semiconductor material. The first insulating layer 116 may include one or more insulating layers (eg, different insulating layers) such as a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer.

[0050] Insulating layer 112 and conductive materials CM1 to CM15 may be sequentially stacked along a third direction perpendicular to substrate 101 on substrate 101 to surround pillars PL. In embodiments, insulating layer 112 may include silicon oxide or silicon nitride.

[0051] The second insulating layer 117 may be located between the pillars PL and the conductive materials CM1 to CM15, and between the conductive materials CM1 to CM15 and the insulating layer 112. In each pillar PL, adjacent portions of the first insulating layer 116 and the second insulating layer 117 may be coupled to form an information storage layer. For example, the first insulating layer 116 and the second insulating layer 117 may include oxide-nitride-oxide (ONO) or oxide-nitride-aluminum oxide (ONA). The first insulating layer 116 and the second insulating layer 117 may form a tunneling insulating layer, a charge trap layer, or a blocking insulating layer.

[0052] Drain 118 is disposed on pillar PL. In one embodiment, drain 118 includes an N-type semiconductor material (e.g., silicon). Bit lines BL2 and BL3 extending along the second direction and spaced apart from each other along the first direction are disposed on drain 118. Bit lines BL2 and BL3 are connected to drain 118.

[0053] The pillars PL, together with the first and second insulating layers 116 and 117 and the conductive materials CM1 to CM15, form a cell string CS. Each pillar PL, together with the adjacent first and second insulating layers 116 and 117 and the conductive materials CM1 to CM15, forms a cell string. The first conductive material CM1, together with the adjacent first and second insulating layers 116 and 117 and the channel layer 115, may form a ground select transistor GST. The first conductive material CM1 may extend along a first direction to form a ground select line GSL.

[0054] The second conductive material CM2 may form a first dummy memory cell DMC1 together with the adjacent first and second insulating layers 116 and 117 and the channel layer 115. The second conductive material CM2 may extend along the first direction to form a first dummy word line DWL1.

[0055] The third to twelfth conductive materials CM3 to CM12 may form first to tenth memory cells MC1 to MC10 together with adjacent layers (i.e., the first and second insulating layers 116 and 117 and the channel layer 115). The third to twelfth conductive materials CM3 to CM12 may extend along the first direction to form first to second word lines WL1 to WL10.

[0056] The thirteenth conductive material CM13 may form a second dummy memory cell DMC2 together with adjacent layers, ie, the first and second insulating layers 116 and 117 and the channel layer 115. The thirteenth conductive material CM13 may extend along the first direction to form a second dummy word line DWL2.

[0057] The fourteenth conductive material CM1 and the fifteenth conductive material CM15 may form a lower string selection transistor SST1 and an upper string selection transistor SSTu together with adjacent layers (i.e., the first and second insulating layers 116 and 117 and the channel layer 115). The fourteenth conductive material CM14 and the fifteenth conductive material CM15 may extend along the first direction to form a lower string selection line and an upper string selection line.

[0058] like Figure 3 As shown, each pillar PL may include a first portion adjacent to the substrate 101 and a second portion disposed on the first portion. For example, the first portion is disposed on the substrate, and the second portion is stacked on the first portion. Due to the process of manufacturing a non-volatile memory device (e.g., a flash memory device), the width or cross-sectional area of ​​the pillar PL in the first portion corresponding to the first conductive material CM1 to the seventh conductive material CM7 may become smaller as the distance from the substrate 101 decreases, and may become larger as the distance from the substrate 101 increases. A boundary layer SP may exist between the first portion and the second portion. In an exemplary embodiment, the boundary layer SP includes the same material as the channel layer 115.

[0059] Likewise, in the second portion corresponding to the eighth to fifteenth conductive materials CM8 to CM15, the width or cross-sectional area of ​​the pillar PL may become smaller as the distance from the substrate 101 decreases, and may become larger as the distance from the substrate 101 increases. For example, the outer wall of the pillar PL may include an inclined portion.

[0060] Figure 4 It is schematically shown Figure 3 A cross-sectional view of the memory block BLK1. Figures 1 to 4 , the pillar PL includes a first portion PL1 adjacent to the substrate 101 and a second portion PL2 disposed on the first portion PL1 .

[0061] The fourteenth and fifteenth conductive materials CM14 and CM15 may be separated by the select line cut SC between the second portion PL2 of the pillar PL. The first to fifteenth conductive materials CM1 to CM15 may be separated from different conductive materials by word line cuts WC on opposite sides of the pillar PL.

[0062] The seventh conductive material CM7 and the eighth conductive material CM8 are adjacent to the boundary between the first portion PL1 and the second portion PL2. The seventh conductive material CM7 and the eighth conductive material CM8 located at the boundary between the first portion PL1 and the second portion PL2 may result in reduced reliability. For example, when the distance between the conductive material and the boundary is less than or equal to a certain threshold distance, the conductive material may be considered to be adjacent to the boundary, and when the distance is greater than the threshold distance, the conductive material may be considered not to be adjacent to the boundary. For example, when there is no intermediate second conductive material in a given portion (e.g., PL1, PL2, etc.) between the boundary and the first conductive material, the first conductive material may be considered to be adjacent to the boundary.

[0063] For example, as the cross-sectional area of ​​the pillars PL increases, the programming speed (or efficiency) decreases. Therefore, as the cross-sectional area of ​​the pillars PL increases, the level of the program voltage for programming the same data may increase.

[0064] Therefore, the programming voltage level used to program the memory cell corresponding to the seventh conductive material CM7 (e.g., MC5) can be higher than the programming voltage level used to program a different memory cell. In other words, the programming operation associated with the seventh conductive material CM7 adjacent to the boundary can act as a strong disturbing source that disturbs the data written in the different memory cells adjacent thereto.

[0065] In an exemplary embodiment, the distance between the eighth conductive material CM8 and the first portion PL1 of the pillar PL is smaller than the distance between the remaining conductive material (i.e., the conductive material above the eighth conductive material CM8) and the pillar PL. That is, when a program voltage is applied to the eighth conductive material CM8, the program voltage may have a strong effect on the first portion PL1 of the pillar PL.

[0066] For example, lateral diffusion may occur at the first portion PL1 of the pillar PL. Lateral diffusion refers to a phenomenon in which charges trapped in the first insulating layer 116 of the pillar PL diffuse in a third direction or in a direction opposite to the third direction. In the case where lateral diffusion occurs, the threshold voltage of the memory cell (e.g., MC5) corresponding to the seventh conductive material CM7 may change, thereby reducing data reliability.

[0067] As described above, a program operation of memory cells adjacent to the boundary of the first and second portions PL1 and PL2 of the pillar PL (eg, neighboring memory cells) may reduce the reliability of data written in surrounding memory cells.

[0068] The reliability of the nonvolatile memory device 100 according to an exemplary embodiment of the present inventive concept can be improved by adjusting the order of programming operations for adjacent memory cells and memory cells not adjacent to a boundary (e.g., non-adjacent memory cells). In addition, by considering the reliability of adjacent memory cells with low reliability, the nonvolatile memory device 100 can use adjacent memory cells for data storage and prevent capacity reduction.

[0069] Figure 5 An operating method of the nonvolatile memory device 100 according to an exemplary embodiment of the present inventive concept is shown. Figure 5 , an example is shown in which a program operation is uniformly (or continuously) requested with respect to a specific memory block (e.g., a selected memory block) of the nonvolatile memory device 100. For example, the nonvolatile memory device 100 performs the program operation under the condition that the adjacent memory cells adjacent to the boundary between the first portion PL1 and the second portion PL2 of the pillar PL are distinguished from the non-adjacent memory cells. For example, the nonvolatile memory device 100 may reorder the program operations so that some or all of the program operations for the non-adjacent memory cells are performed or completed before the program operations for the adjacent memory cells are performed.

[0070] Reference Figure 1 、 Figure 4 and Figure 5 In operation S110 , when program operations are continuously requested with respect to a selected memory block, the nonvolatile memory device 100 preferentially performs program (eg, write) operations on non-adjacent memory cells in the selected memory block.

[0071] After completing the programming operation of non-adjacent memory cells in the selected memory block, the nonvolatile memory device 100 performs a programming operation on adjacent memory cells in operation S120. That is, the nonvolatile memory device 100 preferentially programs the non-adjacent memory cells and then programs the adjacent memory cells.

[0072] In an exemplary embodiment, when the first to third memory cells of a given memory block are initially scheduled to be programmed sequentially, the second memory cell is a neighboring memory cell (e.g., closest to the boundary between the portions of the pillars), and the first and third memory cells are non-neighboring memory cells, the control logic 160 controls the nonvolatile memory device 100 to program the first memory cell during a first time, program the third memory cell during a second time after the first time, and program the second memory cell during a third time after the second time. In another embodiment, the control logic 160 is configured to sequentially schedule the programming operations of the first memory cell, the third memory cell, and then the second memory cell based on the proximity of the first to third memory cells to the boundary layer SP.

[0073] Neighboring memory cells may be designated differently depending on whether any one of the influence of a strong disturber and the influence of lateral diffusion is more dominant at the boundary of the pillar PL of the nonvolatile memory device 100 .

[0074] In some embodiments, completion of programming (or programming operation) for a particular memory cell may mean that the nonvolatile memory device has completed writing all data to be stored in the particular memory cell. That is, the nonvolatile memory device 100 may prohibit additional programming operations for the memory cell for which programming has been completed until the memory cell for which programming has been completed is erased.

[0075] Figure 6 An example of a scheme in which the nonvolatile memory device 100 performs a program operation is shown. Figure 1 、 Figure 4 and Figure 6 , the positions of the neighboring memory cells are depicted with dot-filled boxes or hatching. In the first scheme, the memory cell MC5 of the fifth word line WL5 belonging to the first portion PL1 of the pillar PL and closest to the boundary is designated as the neighboring memory cell.

[0076] In operation S211, the nonvolatile memory device 100 first performs a program operation on non-adjacent memory cells MC6 to MC10 of the sixth to fourth word lines WL6 to WL10 of the second portion PL2 of the pillar PL. Thereafter, in operation S212, the nonvolatile memory device 100 performs a program operation on non-adjacent memory cells MC1 to MC4 of the first to fourth word lines WL1 to WL4 of the first portion PL1 of the pillar PL.

[0077] Thereafter, in operation S213 , the nonvolatile memory device 100 performs a program operation on the adjacent memory cell MC5 of the fifth word line WL5 of the first portion PL1 of the pillar PL. In an embodiment, the first scheme is selected in the case where it is determined that the influence of lateral diffusion at the boundary is dominant.

[0078] In the second scheme, the memory cell MC5 of the fifth word line WL5 belonging to the first portion PL1 of the pillar PL and closest to the boundary and the memory cell MC6 of the sixth word line WL6 belonging to the second portion PL2 of the pillar PL and closest to the boundary are designated as adjacent memory cells. In operations S221 and S222, the nonvolatile memory device 100 completes the programming operation of the non-adjacent memory cells.

[0079] Thereafter, in operation S223, the nonvolatile memory device 100 completes the programming operation of the adjacent memory cells. For example, the nonvolatile memory device 100 may perform the programming operation in the order of the memory cell MC5 of the fifth word line WL5 and the memory cell MC6 of the sixth word line WL6, or in the order of the memory cell MC6 of the sixth word line WL6 and the memory cell MC5 of the fifth word line WL5. In an exemplary embodiment, the second scheme is selected in a case where the influence of the strong interference source and the influence of the lateral diffusion are similar.

[0080] In the third scheme, memory cell MC6 of the sixth word line WL6 belonging to the second portion PL2 of the pillar PL and closest to the boundary is designated as an adjacent memory cell. In operations S231 and S232, the nonvolatile memory device 100 completes the program operation of the non-adjacent memory cells.

[0081] Thereafter, in operation S233 , the nonvolatile memory device 100 completes the program operation of the adjacent memory cell MC6 of the sixth word line WL6 . In an exemplary embodiment, the third scheme is selected in a case where the influence of a strong disturber is dominant.

[0082] In an exemplary embodiment of the present inventive concept, the nonvolatile memory device 100 specifies the addresses of memory cells according to the order of programming operations. That is, in the nonvolatile memory device 100, the addresses of adjacent memory cells may follow the addresses of non-adjacent memory cells. For example, during a given programming cycle in which a given memory block is programmed, the row decoder block 120 may receive the addresses of non-adjacent memory cells (e.g., row addresses) from the buffer block 150, and then receive the addresses of adjacent memory cells (e.g., row addresses).

[0083] The nonvolatile memory device 100 may reverse the order of programming operations for non-adjacent memory cells. Figure 6As shown, the nonvolatile memory device 100 may perform a programming operation on non-adjacent memory cells in a direction from the bit lines BL1 to BL4 to the substrate 101; conversely, the nonvolatile memory device 100 may perform a programming operation on non-adjacent memory cells in a direction from the substrate 101 to the bit lines BL1 to BL4.

[0084] Figure 7 An example is shown in which the pillar PL of the memory block is composed of the first part PL1 to the third part PL3. Figure 1 、 Figure 2 and Figure 7 , the pillar PL includes a first portion PL1 disposed on the substrate 101 , a second portion PL2 disposed on the first portion PL1 , and a third portion PL3 disposed on the second portion PL2 .

[0085] A first boundary between the first portion PL1 and the second portion PL2 is located between the fifth conductive material CM5 and the sixth conductive material CM6. A second boundary between the second portion PL2 and the third portion PL3 is located between the tenth conductive material CM10 and the eleventh conductive material CM11. The nonvolatile memory device 100 can specify adjacent memory cells at the first and second boundaries.

[0086] Figure 8 The nonvolatile memory device 100 is shown in FIG. Figure 7 An example of performing a programming operation in a memory block of Figure 1 、 Figure 2 、 Figure 7 and Figure 8 , the nonvolatile memory device 100 may select one of the first to ninth schemes.

[0087] In the fourth scenario, memory cell MC3 of the third word line WL3 belonging to the first portion PL1 of the pillar PL and closest to the first boundary and memory cell MC8 of the eighth word line WL8 belonging to the second portion PL2 of the pillar PL and closest to the second boundary are designated as adjacent memory cells. In operations S311 to S313, the nonvolatile memory device 100 completes the programming operation of the non-adjacent memory cells.

[0088] Then, in operation S314, the nonvolatile memory device 100 performs a program operation on the adjacent memory cell MC8 of the eighth word line WL8 of the second portion PL2 of the pillar PL. Then, in operation S315, the nonvolatile memory device 100 performs a program operation on the adjacent memory cell MC3 of the third word line WL3 of the first portion PL1 of the pillar PL.

[0089] The adjacent memory cells designated in the fifth scheme are the same as those designated in the fourth scheme. In operations S321 and S322, the nonvolatile memory device 100 completes the programming operation for the non-adjacent memory cells belonging to the third and second portions PL3 and PL2 of the pillar PL. Then, in operation S323, the nonvolatile memory device 100 performs a programming operation on the adjacent memory cell MC8 of the eighth word line WL8 of the second portion PL2 of the pillar PL.

[0090] In operation S324, the nonvolatile memory device 100 completes the program operation of non-adjacent memory cells belonging to the first portion PL1 of the pillar PL. Thereafter, in operation S325, the nonvolatile memory device 100 performs a program operation on adjacent memory cells MC3 of the third word line WL3 belonging to the first portion PL1 of the pillar PL.

[0091] That is, in the case of the fourth scheme, after all non-adjacent memory cells are fully programmed, adjacent memory cells are fully programmed. In the case of the fifth scheme, after non-adjacent memory cells around a specific boundary are fully programmed, corresponding adjacent memory cells are fully programmed.

[0092] In the sixth scenario, memory cell MC3 of the third word line WL3 belonging to the first portion PL1 of the pillar PL and closest to the first boundary, memory cell MC4 of the fourth word line WL4 belonging to the second portion PL2 and closest to the first boundary, memory cell MC8 of the eighth word line WL8 belonging to the second portion PL2 and closest to the second boundary, and memory cell MC9 of the ninth word line WL9 belonging to the third portion PL3 and closest to the second boundary are designated as adjacent memory cells. In operations S331 to S333, the nonvolatile memory device 100 completes the programming operation of the non-adjacent memory cells.

[0093] Thereafter, in operation S334, the nonvolatile memory device 100 completes the programming operation of the adjacent memory cells MC8 of the eighth word line WL8 and the adjacent memory cells MC9 of the ninth word line WL9, which are adjacent to the second boundary. The programming operation may be performed in the order of the memory cells MC8 of the eighth word line WL8 and the memory cells MC9 of the ninth word line WL9, or in the order of the memory cells MC9 of the ninth word line WL9 and the memory cells MC8 of the eighth word line WL8.

[0094] Thereafter, in operation S335, the nonvolatile memory device 100 completes the programming operation of the adjacent memory cells MC3 of the third word line WL3 and the adjacent memory cells MC4 of the fourth word line WL4, which are adjacent to the first boundary. The programming operation may be performed in the order of the memory cells MC3 of the third word line WL3 and the memory cells MC4 of the fourth word line WL4, or in the order of the memory cells MC4 of the fourth word line WL4 and the memory cells MC3 of the third word line WL3.

[0095] The adjacent memory cells designated in the seventh scheme are the same as those designated in the sixth scheme. In operations S341 and S342, the nonvolatile memory device 100 completes program operations of non-adjacent memory cells belonging to the third and second portions PL3 and PL2 of the pillar PL.

[0096] Thereafter, in operation S343, the nonvolatile memory device 100 completes the programming operation of the adjacent memory cells MC8 of the eighth word line WL8 and the adjacent memory cells MC9 of the ninth word line WL9, which are adjacent to the second boundary. The programming operation may be performed in the order of the memory cells MC8 of the eighth word line WL8 and the memory cells MC9 of the ninth word line WL9, or in the order of the memory cells MC9 of the ninth word line WL9 and the memory cells MC8 of the eighth word line WL8.

[0097] Thereafter, in operation S344, the nonvolatile memory device 100 completes the programming operation of the non-adjacent memory cells belonging to the first portion PL1 of the pillar PL. Thereafter, in operation S345, the nonvolatile memory device 100 completes the programming operation of the adjacent memory cells MC3 of the third word line WL3 and the adjacent memory cells MC4 of the fourth word line WL4, which are adjacent to the first boundary. The programming operation may be performed in the order of the memory cells MC3 of the third word line WL3 and the memory cells MC4 of the fourth word line WL4, or in the order of the memory cells MC4 of the fourth word line WL4 and the memory cells MC3 of the third word line WL3.

[0098] Operations S351 to S355 of the eighth scheme are the same as operations S311 to S315 of the fourth scheme, except that memory cell MC9 of the ninth word line WL9 with respect to the second boundary is selected as the adjacent memory cell instead of memory cell MC8 of the eighth word line WL8, and memory cell MC4 of the fourth word line WL4 with respect to the first boundary is selected as the adjacent memory cell instead of memory cell MC3 of the third word line WL3.

[0099] Operations S361 to S365 of the ninth scheme are the same as operations S321 to S325 of the fifth scheme, except that memory cell MC9 of the ninth word line WL9 with respect to the second boundary is selected as the adjacent memory cell instead of memory cell MC8 of the eighth word line WL8, and memory cell MC4 of the fourth word line WL4 with respect to the first boundary is selected as the adjacent memory cell instead of memory cell MC3 of the third word line WL3.

[0100] As reference Figure 8 As described, the nonvolatile memory device 100 can designate addresses of memory cells according to a program operation order. In addition, the nonvolatile memory device 100 can reversely change the order of program operations for non-adjacent memory cells.

[0101] The boundary characteristics of the pillar PL may vary depending on the manufacturing process. Therefore, the order of programming operations applied to the boundaries in the same pillar may be changed. For example, the order of programming memory cells of two word lines in operation S334 (or operation S343) may be different from the order of programming memory cells of two word lines in operation S335 (or operation S345).

[0102] For example, with respect to a first boundary, adjacent memory cells of a word line relatively close to the substrate are fully programmed, and then adjacent memory cells of a word line relatively far from the substrate are fully programmed. Conversely, with respect to a second boundary, adjacent memory cells of a word line relatively far from the substrate are fully programmed, and then adjacent memory cells of a word line relatively close to the substrate are fully programmed.

[0103] The locations of adjacent memory cells specified about each boundary and the programming scheme applied about each boundary (e.g., the order of programming operations) can be set by options (e.g., fuse options) after manufacturing the non-volatile memory device 100. For example, the memory device may include one or more fuses or antifuses set during manufacturing to indicate which scheme to use. For example, the control logic block 160 may analyze the setting (e.g., open or closed) of the fuses or antifuses to determine which scheme to implement.

[0104] Figure 9 An operating method of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept is shown. Figure 1 、 Figure 2 and Figure 9 In operation S410, the nonvolatile memory device 100 performs a single-step program operation on non-adjacent memory cells of a selected memory block. In the single-step program operation, the selected memory cells for the program operation are completely programmed through one program operation.

[0105] In operation S420, the nonvolatile memory device 100 performs a multi-step programming operation on adjacent memory cells of the selected memory block. In the multi-step programming operation, the selected memory cells for the programming operation are completely programmed through two or more programming operations. Between the two or more programming operations, a programming operation (e.g., a single-step or multi-step programming operation) may be performed on memory cells of an adjacent word line.

[0106] Figure 10 An example of a single-step programming operation is shown. Figure 10 In the first block B1 and the third block B3, the horizontal axis represents the threshold voltage VTH of the memory cell, and the vertical axis represents the number of memory cells. Figure 10 In the second block B2 of FIG. 1 , the horizontal axis represents time “T” and the vertical axis represents voltage “V” applied to the memory cell through the word line.

[0107] As shown in the first block B1, the memory cell in the erased state has a threshold voltage belonging to one threshold voltage range (eg, state). The programming operation for the memory cell may include two or more programming loops. The second block B2 shows an exemplary programming loop.

[0108] During each programming loop, a program voltage VPGM is applied to a memory cell via a word line. This voltage increases the threshold voltage of the memory cell. Subsequently, a verify voltage VFY is applied to the memory cell. This voltage VFY is used to verify that the threshold voltage of the memory cell has reached the target state.

[0109] For example, when four bits are written to each memory cell, the memory cell that has completed programming may have one of 16 states. In this case, 15 verification voltages VFY may be used. These 15 verification voltages VFY may be used to verify whether the threshold voltage of the memory cell has reached a target state that is one of 15 states (e.g., a programmed state) that is higher than the erased state.

[0110] Figure 11 An example of a multi-step programming operation is shown. Figure 11 In the fourth block B4, the sixth block B6 and the eighth block B8, the horizontal axis represents the threshold voltage VTH of the memory cell, and the vertical axis represents the number of memory cells. Figure 11 In the fifth block B5 and the seventh block B7, the horizontal axis represents time "T" and the vertical axis represents voltage "V" applied to the memory cell through the word line.

[0111] In an exemplary embodiment, the multi-step program operation includes a 1-step program operation and a 2-step program operation. Each of the 1-step program operation and the 2-step program operation may include two or more program loops. The fifth block B5 shows an example of a program loop for the 1-step program operation.

[0112] The program loop may include a program voltage VPGM and a verification voltage VFY. For example, the number of verification voltages VFY may be 7. In the case where a 1-step program operation has been completed, as shown in the fourth block B4 and the sixth block B6, the memory cell may be programmed from the erased state to the erased state and one of the 7 program states.

[0113] The seventh block B7 shows an example of a program loop for a 2-step program operation. The program loop may include a program voltage VPGM and a verification voltage VFY. For example, the number of verification voltages VFY may be 15. In the case where the 2-step program operation has been completed, the memory cells in the 8 states of the sixth block B6 may be programmed to one of the 16 states of the eighth block B8.

[0114] like Figure 11 As shown, a bit may be written in each memory cell through a 1-step programming operation, and additional bits may be further written in the memory cell through a 2-step programming operation. That is, the number of bits stored in each memory cell after the 1-step programming operation is completed may be different from the number of bits stored in each memory cell after the 2-step programming operation is completed.

[0115] For example, bits can be coarsely written into a memory cell through a 1-step programming operation. The coarsely written bits into the memory cell can be finely written through a 2-step programming operation. That is, the number of bits stored in each memory cell after the 1-step programming operation is completed can be the same as the number of bits stored in each memory cell after the 2-step programming operation is completed.

[0116] In an embodiment, Figure 2 The threshold voltages of the dummy memory cells DMC1 and DMC2 shown are different from those of the third and eighth blocks B3 and B8. The dummy memory cells DMC1 and DMC2 may have threshold voltages belonging to a distribution range widely formed between the lowest and highest states of the third and eighth blocks B3 and B8.

[0117] Figure 12 and Figure 13 The nonvolatile memory device 100 is shown in FIG. Figure 9 Examples of how to perform programming operations. Figure 1 、 Figure 2 、 Figure 7 and Figure 12 , the nonvolatile memory device 100 selects one of the tenth to fifteenth schemes.

[0118] In the tenth scheme, memory cell MC8 of the eighth word line WL8 belonging to the second portion PL2 of the pillar PL and closest to the second boundary and memory cell MC3 of the third word line WL3 belonging to the first portion PL1 of the pillar PL and closest to the first boundary are designated as adjacent memory cells.

[0119] Through operations S511 to S515, the nonvolatile memory device 100 can sequentially program memory cells in a direction from the bit lines BL1 to BL4 to the substrate 101. In this case, the nonvolatile memory device 100 completes the programming operation of non-adjacent memory cells and partially performs the programming operation of adjacent memory cells. For example, the nonvolatile memory device 100 only completes a one-step programming operation (operation S512 and operation S514) of the adjacent memory cells.

[0120] Thereafter, the nonvolatile memory device 100 completes the program operation of the adjacent memory cells by completing the 2-step program operation of the adjacent memory cells (operation S516 and operation S517 ).

[0121] The adjacent memory cells designated in the eleventh scheme are the same as the adjacent memory cells designated in the tenth scheme. Through operations S521 to S523, the nonvolatile memory device 100 completes the program operation of non-adjacent memory cells in the direction from the bit lines BL1 to BL4 to the substrate 101, and then completes the 1-step program operation of the adjacent memory cells.

[0122] Then, in operation S524, the nonvolatile memory device 100 completes a 2-step programming operation for adjacent memory cells between the non-adjacent memory cells that have already been programmed. Then, in operations S525 and S526, the nonvolatile memory device 100 completes a 1-step programming operation for the non-adjacent memory cells and a 1-step programming operation for the adjacent memory cells in the same direction.

[0123] Thereafter, in operation S527 , the nonvolatile memory device 100 completes the 2-step program operation of adjacent memory cells between the non-adjacent memory cells for which programming has been completed.

[0124] In an embodiment, the nonvolatile memory device 100 divides operation S523 into parts or sub-operations. For example, the nonvolatile memory device 100 may perform operation S524 after completing the programming operation of the non-adjacent memory cell MC7 closest to the second boundary (e.g., a portion of operation S523). Thereafter, the nonvolatile memory device 100 may perform the remaining portion of operation S523.

[0125] The adjacent memory cells designated in the twelfth scheme are the same as the adjacent memory cells designated in the tenth scheme. Through operations S531 to S534, the nonvolatile memory device 100 completes the program operation of non-adjacent memory cells in the direction from the bit lines BL1 to BL4 to the substrate 101 and completes the 1-step program operation of adjacent memory cells.

[0126] Then, in operation S535, the nonvolatile memory device 100 completes the 2-step programming operation for adjacent memory cells between the non-adjacent memory cells that have already been programmed. Then, in operation S536, the nonvolatile memory device 100 completes the programming operation for the non-adjacent memory cells. Then, in operation S537, the nonvolatile memory device 100 completes the 2-step programming operation for adjacent memory cells between the non-adjacent memory cells that have already been programmed.

[0127] In the thirteenth scheme, the memory cell MC9 of the ninth word line WL9 belonging to the third part PL3 ​​of the column PL and closest to the second boundary, the memory cell MC8 of the eighth word line WL8 belonging to the second part PL2 and closest to the second boundary, the memory cell MC4 of the fourth word line WL4 belonging to the second part PL2 and closest to the first boundary, and the memory cell MC3 of the third word line WL3 belonging to the first part PL1 and closest to the first boundary are designated as adjacent memory cells.

[0128] Through operations S541 to S545, the nonvolatile memory device 100 sequentially programs memory cells in a direction from the bit lines BL1 to BL4 to the substrate 101. In this case, the nonvolatile memory device 100 completes the program operation of non-adjacent memory cells and partially performs the program operation of adjacent memory cells.

[0129] For example, the nonvolatile memory device 100 completes only the 1-step programming operation of the adjacent memory cells (operations S542 and S544). Thereafter, the nonvolatile memory device 100 completes the programming operation of the adjacent memory cells by completing the 2-step programming operation of the adjacent memory cells (operations S546 and S547).

[0130] For example, in two word lines connected to adjacent memory cells, the order of the 1-step program operation or the 2-step program operation may be in a direction from the bit lines BL1 to BL4 to the substrate 101 or in a direction from the substrate 101 to the bit lines BL1 to BL4.

[0131] The adjacent memory cells designated in the fourteenth scheme are the same as the adjacent memory cells designated in the thirteenth scheme. Through operations S551 to S553, the nonvolatile memory device 100 completes the program operation of non-adjacent memory cells in the direction from the bit lines BL1 to BL4 to the substrate 101 and completes the 1-step program operation of the adjacent memory cells.

[0132] Then, in operation S554, the nonvolatile memory device 100 completes the 2-step programming operation for the adjacent memory cells between the non-adjacent memory cells that have completed programming. Then, in operations S555 and S556, the nonvolatile memory device 100 completes the programming operation for the non-adjacent memory cells in the same direction and completes the 1-step programming operation for the adjacent memory cells.

[0133] Thereafter, in operation S557 , the nonvolatile memory device 100 completes the 2-step program operation of adjacent memory cells between the non-adjacent memory cells for which programming has been completed.

[0134] In an embodiment, the nonvolatile memory device 100 divides operation S553 into parts or sub-operations. For example, the nonvolatile memory device 100 may perform operation S554 after completing the programming operation of the non-adjacent memory cell MC7 closest to the second boundary (e.g., a portion of operation S553). Thereafter, the nonvolatile memory device 100 may perform the remaining portion of operation S553.

[0135] In the fifteenth embodiment, adjacent memory cells may be designated as being the same as those designed in the thirteenth embodiment. Through operations S561 to S564, the nonvolatile memory device 100 completes a program operation of non-adjacent memory cells in a direction from the bit lines BL1 to BL4 to the substrate 101 and completes a 1-step program operation of adjacent memory cells.

[0136] Then, in operation S565, the nonvolatile memory device 100 completes the 2-step programming operation for adjacent memory cells between the non-adjacent memory cells that have already been programmed. Then, in operation S566, the nonvolatile memory device 100 completes the programming operation for the non-adjacent memory cells. Then, in operation S567, the nonvolatile memory device 100 completes the 2-step programming operation for adjacent memory cells between the non-adjacent memory cells that have already been programmed.

[0137] Reference Figure 1 、 Figure 2 、 Figure 7 、 Figure 12 and Figure 13, the sixteenth scheme is the same as the tenth scheme, except that the memory cell MC9 of the ninth word line WL9 rather than the memory cell MC8 of the eighth word line WL8 with respect to the second boundary is selected as the adjacent memory cell, and the memory cell MC4 of the fourth word line WL4 rather than the memory cell MC3 of the third word line WL3 with respect to the first boundary is selected as the adjacent memory cell.

[0138] The seventeenth scheme is the same as the eleventh scheme, except that the memory cell MC9 of the ninth word line WL9 with respect to the second boundary is selected as the adjacent memory cell instead of the memory cell MC8 of the eighth word line WL8, and the memory cell MC4 of the fourth word line WL4 with respect to the first boundary is selected as the adjacent memory cell instead of the memory cell MC3 of the third word line WL3.

[0139] The eighteenth scheme is the same as the twelfth scheme, except that the memory cell MC9 of the ninth word line WL9 with respect to the second boundary is selected as the adjacent memory cell instead of the memory cell MC8 of the eighth word line WL8, and the memory cell MC4 of the fourth word line WL4 with respect to the first boundary is selected as the adjacent memory cell instead of the memory cell MC3 of the third word line WL3.

[0140] As reference Figure 12 and Figure 13 As described, the nonvolatile memory device 100 can specify the addresses of the memory cells according to the order of the programming operation. In addition, the nonvolatile memory device 100 can reversely change the order of the programming operation of non-adjacent memory cells. In addition, as shown in FIG. Figure 12 and Figure 13 As described, at different boundaries, adjacent memory cells can be programmed in different orders.

[0141] Positions of adjacent memory cells designated with respect to each boundary and a programming scheme (eg, order of programming operations) applied with respect to each boundary may be set by options (eg, fuse options) after manufacturing the nonvolatile memory device 100 .

[0142] Figure 14 2 shows a memory device 200 including a nonvolatile memory device 210 according to an exemplary embodiment of the inventive concept. Figure 14 , the memory device 200 includes a non-volatile memory device 210 and a controller 220 (eg, a memory controller or control circuit). The non-volatile memory device 210 may be as described with reference to Figures 1 to 13 Configured and operates as described.

[0143] The controller 220 may control read operations, write operations, and erase operations of the nonvolatile memory device 210. The controller 220 may include a host interface block 221 (e.g., a host interface circuit), a main control block 222 (e.g., a control circuit), and a memory manager block 223 (e.g., a memory manager or control circuit).

[0144] The host interface block 221 may transfer a request or command received from an external host device to the main control block 222. The main control block 222 may generate a command CMD and an address ADDR for accessing the nonvolatile memory device 210 according to a request from the external host device or an internal schedule, and may transfer the command CMD and the address ADDR to the memory manager block 223.

[0145] The memory manager block 223 can use the first channel CH1 (refer to Figure 1 ) exchanges a command CMD, an address ADDR, and data “DATA” with the nonvolatile memory device 210. The memory manager block 223 may exchange a control signal CTRL with the nonvolatile memory device 210 through a second channel.

[0146] Figure 15 An example of an operating method of the memory device 200 according to an exemplary embodiment of the inventive concept is shown. Figure 14 and Figure 15 In operation S610, the controller 220 performs a program operation of "n" pages (n is a positive integer of 2 or greater) on non-adjacent memory cells. The controller 220 may control the nonvolatile memory device 210 so that the program operation is completed by writing "n" bits in each non-adjacent memory cell.

[0147] In operation S620, the controller 220 performs a program operation of "m" pages (m and n are positive integers) on adjacent memory cells. The controller 220 may control the nonvolatile memory device 210 so that the program operation is completed by writing "m" bits in each non-adjacent memory cell. In an exemplary embodiment, "m" is less than "n".

[0148] In an exemplary embodiment, even if some or all of the “m” pages are initially scheduled to be programmed before some of the “n” pages, the controller 220 adjusts the programming order so that all of the “n” pages are programmed first, and then all of the “m” pages are programmed after programming of the “n” pages has been completed.

[0149] The memory device 200 can improve the reliability of data written in adjacent memory cells by writing data whose amount is less than the amount of data written in non-adjacent memory cells. Figure 6 、 Figure 8 、 Figure 12 and Figure 13 Designated adjacent memory cells are shown.

[0150] In an exemplary embodiment, during a given programming cycle, a first amount of data is written to non-adjacent memory cells during a first time of the cycle, and a second amount of data is written to adjacent memory cells during a second time of the cycle after the first time, where the second amount is less than the first amount.

[0151] Figure 16 1 shows a memory device 300 according to an exemplary embodiment of the present inventive concept. Figure 1 and Figure 16 , the memory device 300 includes a non-volatile memory device 310 and a controller 320. The controller 320 includes a host interface block 321, a main control block 322, a memory manager block 323, a user cycle count block 324 (e.g., a counting circuit), and an adjacent memory unit manager block 325 (e.g., a memory manager or control circuit).

[0152] The nonvolatile memory device 310, the host interface block 321, the main control block 322 and the memory manager block 323 are connected to the reference Figure 14 Therefore, additional description will be omitted to avoid redundancy.

[0153] The user cycle count block 324 receives operation information OI from the main control block 322. The operation information OI may include information on the operation of the nonvolatile memory device 310. The user cycle count block 324 may count usage cycles of each of the memory blocks BLK1 to BLKz according to the operation information OI.

[0154] For example, the usage cycles of each memory block may include program and erase counts. The usage cycles of each memory block may be calculated by applying weights to various parameters such as program and erase counts, read counts, and remaining time after a program operation.

[0155] The user cycle count block 324 transmits the usage cycle information UC of the memory blocks BLK1 to BLKz to the adjacent memory unit management block 325. The adjacent memory unit management block 325 determines whether the usage cycle of a specific memory block has reached a given threshold. When it is determined that the usage cycle of a specific memory block has reached the given threshold, the adjacent memory unit management block 325 transmits a threshold notification TI to the main control block 322.

[0156] In an exemplary embodiment, the main control block 322 reduces the number of pages to be written in the adjacent memory cells in response to the threshold notification TI. For example, two or more thresholds may be set for each of the memory blocks BLK1 to BLKz. These two or more thresholds may correspond to boundaries of different heights (heights in the third direction) in each memory block. That is, the controller 320 may reduce the number of pages to be written in the adjacent memory cells at the boundaries of different heights at different timings based on different thresholds. For example, if the first memory block is written, erased and / or read too frequently, the reliability of its adjacent memory cells may be lower than the reliability of the adjacent memory cells of the second memory block that is not written, erased or read so frequently. For example, the main control block 322 may initially allow all pages of the adjacent memory cells of a given block to be written, and then, when it is determined that the given memory block has been written, erased and / or read too frequently, may only allow half of the pages to be written in the future.

[0157] The storage device 300 may use adjacent memory cells for storing user data transmitted from an external host device, storing internally generated metadata, or for performance improvement purposes. In the event that the adjacent memory cells are used to store user data and the number of pages to be written in the adjacent memory cells decreases, the storage device 300 may notify the host device of the capacity reduction.

[0158] In the above disclosure, the components of the present inventive concept are described using blocks. These blocks can be implemented using various hardware devices such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs), firmware driven in hardware devices, software such as applications, or a combination of hardware devices and software. In addition, these blocks can include circuits implemented using semiconductor components in integrated circuits or circuits implemented as intellectual property (IP) blocks or cores.

[0159] According to at least one embodiment of the present invention, a program operation for adjacent memory cells is performed after a program operation for non-adjacent memory cells has been completed. Thus, a nonvolatile memory device, a storage device, and a method for operating a nonvolatile memory device are provided that can ensure reliability while preventing data reliability degradation and capacity reduction through a program operation for non-adjacent memory cells.

[0160] While the inventive concepts have been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the inventive concepts.

Claims

1. A nonvolatile memory device comprising: A memory cell array is provided on a substrate, wherein the memory cell array includes a plurality of memory blocks; a row decoder connected to the memory cell array via word lines; and a page buffer connected to the memory cell array through bit lines, wherein each of the plurality of memory blocks includes a pillar including a first portion disposed on the substrate and a second portion disposed on the first portion, The width of the first portion increases as the distance from the substrate increases, and a first conductive material and a first insulating layer surround the first portion and are sequentially stacked on the substrate. The width of the second portion increases as the distance from the substrate increases, and a second conductive material and a second insulating layer surround the second portion and are sequentially stacked on the substrate. wherein the first boundary is located between the first portion and the second portion, wherein the first conductive material and the first portion together form a first memory cell, and the second conductive material and the second portion together form a second memory cell, and Wherein, when a programming operation is performed based on a continuous address in a selected memory block among the multiple memory blocks, the row decoder and the page buffer are configured to complete a second programming operation of adjacent memory cells adjacent to the first boundary after sequentially completing a first programming operation of non-adjacent memory cells that are not adjacent to the first boundary from among the first memory cells and the second memory cells.

2. The nonvolatile memory device according to claim 1, wherein: The neighboring memory cells include a memory cell closest to the first boundary from among the first memory cells.

3. The nonvolatile memory device according to claim 1, wherein: The first programming operation includes a third programming operation of a first non-adjacent memory cell belonging to the first portion from among the non-adjacent memory cells and a fourth programming operation of a second non-adjacent memory cell belonging to the second portion from among the non-adjacent memory cells, Wherein, the second programming operation includes a 1-step programming operation and a 2-step programming operation, and Wherein, the row decoder and the page buffer are further configured as follows: completing one of the third programming operation and the fourth programming operation; Execute the one-step programming operation; completing the other of the third programming operation and the fourth programming operation; The 2-step programming operation is then performed.

4. The nonvolatile memory device according to claim 1, wherein: The neighboring memory cells include a memory cell closest to the first boundary from among the second memory cells.

5. The nonvolatile memory device according to claim 1, wherein: The adjacent memory cells include a memory cell closest to the first boundary from among the first memory cells and a memory cell closest to the first boundary from among the second memory cells. The nonvolatile memory device according to claim 5 , wherein: The first programming operation includes a third programming operation of a first non-adjacent memory cell belonging to the first portion from among the non-adjacent memory cells and a fourth programming operation of a second non-adjacent memory cell belonging to the second portion from among the non-adjacent memory cells, wherein the second programming operation includes a fifth programming operation of a first adjacent memory cell and a sixth programming operation of a second adjacent memory cell, wherein each of the fifth programming operation and the sixth programming operation includes a 1-step programming operation and a 2-step programming operation, and Wherein, the row decoder and the page buffer are further configured as follows: completing one of the third programming operation and the fourth programming operation; performing a 1-step programming operation of each of the fifth programming operation and the sixth programming operation; completing the other of the third programming operation and the fourth programming operation; A 2-step program operation of each of the fifth program operation and the sixth program operation is then performed.

7. The nonvolatile memory device according to claim 1, wherein: The column further includes a third portion stacked on the second portion, The width of the third portion increases as the distance from the substrate increases, and a third conductive material and a third insulating layer surround the third portion and are sequentially stacked on the substrate. wherein the second boundary is located between the second portion and the third portion, and The third conductive material and the third portion together form a third memory cell.

8. The nonvolatile memory device according to claim 7, wherein: The row decoder and the page buffer are further configured to: completing programming of the third memory cell; Then, programming of a fifth memory cell and a seventh memory cell is completed through the first programming operation, wherein the fifth memory cell is a remaining memory cell in the second memory cell except the fourth memory cell closest to the second boundary, and the seventh memory cell is a remaining memory cell in the first memory cell except the sixth memory cell closest to the first boundary; Then completing programming of the fourth memory cell; The programming of the sixth memory cell is then completed through the second programming operation.

9. The nonvolatile memory device according to claim 8, wherein: The second programming operation includes a 1-step programming operation and a 2-step programming operation, and Wherein, the row decoder and the page buffer are further configured as follows: After completing programming of the fifth memory cell, performing a 1-step programming operation of the sixth memory cell; Then completing programming of the seventh memory cell; A 2-step programming operation is then performed on the sixth memory cell.

10. The nonvolatile memory device according to claim 7, wherein: The row decoder and the page buffer are further configured to: completing programming of the third memory cell; Then, completing programming of a fifth memory cell through a portion of the first programming operation, the fifth memory cell being the remaining memory cells among the second memory cells except for the fourth memory cell closest to the second boundary; Then completing programming of the fourth memory cell; Then, completing programming of a seventh memory cell through the remaining portion of the first programming operation, the seventh memory cell being the remaining memory cells in the first memory cells except for the sixth memory cell closest to the first boundary; The programming of the sixth memory cell is then completed through the second programming operation. The nonvolatile memory device according to claim 10 , wherein: The second programming operation includes a 1-step programming operation and a 2-step programming operation, and Wherein, the row decoder and the page buffer are further configured as follows: After completing programming of the fifth memory cell, performing a 1-step programming operation on the sixth memory cell; Then completing programming of the seventh memory cell; A 2-step programming operation is then performed on the sixth memory cell.

12. The nonvolatile memory device according to claim 7, wherein: The row decoder and the page buffer are further configured to: completing programming of a fifth memory cell, the fifth memory cell being the remaining memory cells in the third memory cells except for a fourth memory cell closest to the second boundary; Then, programming of an eighth memory cell is completed through a portion of the first programming operation, the eighth memory cell being the remaining memory cells in the second memory cells except for the sixth memory cell closest to the second boundary and the seventh memory cell closest to the first boundary; Then, completing programming of a tenth memory cell through the remaining portion of the first programming operation, the tenth memory cell being the remaining memory cells of the first memory cells except for the ninth memory cell closest to the first boundary; Then completing programming of the fourth memory cell and the sixth memory cell; Programming of the seventh memory cell and the ninth memory cell is then completed through a third programming operation including the second programming operation.

13. The nonvolatile memory device according to claim 12, wherein: The third programming operation includes a 1-step programming operation and a 2-step programming operation, and Wherein, the row decoder and the page buffer are further configured as follows: After completing programming of the eighth memory cell, performing a one-step programming operation on the seventh memory cell and the ninth memory cell; Then completing programming of the tenth memory cell; A 2-step programming operation is then performed on the seventh memory cell and the ninth memory cell.

14. The nonvolatile memory device according to claim 7, wherein: The row decoder and the page buffer are further configured to: completing programming of a fifth memory cell, the fifth memory cell being the remaining memory cells in the third memory cells except for a fourth memory cell closest to the second boundary; Then, programming of an eighth memory cell is completed through a portion of the first programming operation, the eighth memory cell being the remaining memory cells in the second memory cells except for the sixth memory cell closest to the second boundary and the seventh memory cell closest to the first boundary; Then completing programming of the fourth memory cell and the sixth memory cell; Then, completing programming of a tenth memory cell through the remaining portion of the first programming operation, the tenth memory cell being the remaining memory cells of the first memory cells except for the ninth memory cell closest to the first boundary; Programming of the seventh memory cell and the ninth memory cell is then completed through a third programming operation including the second programming operation.

15. The nonvolatile memory device according to claim 7, wherein: The row decoder and the page buffer are further configured to: completing programming of a fifth memory cell, the fifth memory cell being the remaining memory cells in the third memory cells except for a fourth memory cell closest to the second boundary; Then, programming a seventh memory cell is completed through a portion of the first programming operation, the seventh memory cell being the remaining memory cells in the second memory cell except for the sixth memory cell closest to the first boundary; Then completing programming of the first memory cell through the remaining portion of the first programming operation; Then completing programming of the fourth memory cell; The programming of the sixth memory cell is then completed through the second programming operation.

16. The nonvolatile memory device according to claim 7, wherein: The row decoder and the page buffer are further configured to: completing programming of a fifth memory cell, the fifth memory cell being the remaining memory cells in the third memory cells except for a fourth memory cell closest to the second boundary; Then, programming a seventh memory cell is completed through a portion of the first programming operation, the seventh memory cell being the remaining memory cells in the second memory cell except for the sixth memory cell closest to the first boundary; Then completing programming of the fourth memory cell; Then completing programming of the first memory cell through the remaining portion of the first programming operation; The programming of the sixth memory cell is then completed through the second programming operation.

17. A storage device comprising: a nonvolatile memory device comprising a plurality of memory blocks; as well as a controller configured to control a write operation to a selected memory block of the plurality of memory blocks of the nonvolatile memory device, Wherein, each of the plurality of memory blocks comprises: a first memory cell corresponding to a first portion of the pillar, the first portion extending in a direction perpendicular to the substrate; and a second memory cell corresponding to a second portion of the pillar, the second portion extending in a direction perpendicular to the substrate and disposed on the first portion, wherein the first memory cell and the second memory cell are classified into at least one first adjacent memory cell adjacent to a first boundary between the first portion and the second portion and first non-adjacent memory cells that are remaining memory cells except the at least one first adjacent memory cell, Wherein, in a write operation of a selected memory block, the controller controls the nonvolatile memory device so that when the programming operation of the first memory cell and the second memory cell is completed, the number of bits written in the at least one first adjacent memory cell is less than the number of bits written in each of the first non-adjacent memory cells.

18. The storage device according to claim 17, wherein: The controller reduces the number of bits to be written in the first adjacent memory cell as the usage cycles of the selected memory block increase.

19. The storage device according to claim 17, wherein: Each of the plurality of memory blocks further includes a third memory cell corresponding to a third portion of the pillar, the third portion extending in a direction perpendicular to the substrate and disposed on the second portion, wherein the second memory cell and the third memory cell are classified into at least one second adjacent memory cell adjacent to a second boundary between the second portion and the third portion and second non-adjacent memory cells that are remaining memory cells except the at least one second adjacent memory cell, and The controller controls the number of bits written into the first non-adjacent memory cell and the number of bits written into the second non-adjacent memory cell differently.

20. A method of operating a nonvolatile memory device, the nonvolatile memory device comprising memory cells connected in series between a string selection transistor and a ground selection transistor, the method comprising: completing a first programming operation for a first memory cell among the memory cells; as well as After completing the first programming operation of the first memory cell, completing the second programming operation of at least one second memory cell located between the first memory cells, wherein the memory cell is stacked in a direction perpendicular to the substrate based on a first portion of the pillar and a second portion of the pillar, the first portion extending in a direction perpendicular to the substrate, the second portion extending in a direction perpendicular to the substrate and disposed on the first portion, and The at least one second memory cell is adjacent to a boundary between the first portion and the second portion.

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