Memory Array and Method for Forming a Memory Array Comprising a String of Memory Cells

Abstract

This application relates to a memory array and a method for forming a memory array including memory cell strings. A memory array including memory cell strings includes vertically stacked, laterally spaced-apart memory blocks individually, the vertical stack including alternating insulating and conductive layers. An operative channel material string of memory cells extends through the insulating and conductive layers. An intervening material is laterally between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks. The intervening material includes longitudinally alternating first and second regions each having a vertically elongated seam therein. The vertically elongated seam is longer in the first region than in the second region. Additional embodiments including methods are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to memory arrays and methods for forming memory arrays including strings of memory cells. Background Art

[0002] A memory is an integrated circuit and is used in a computer system to store data. Memories can be fabricated as one or more arrays of individual memory cells. Digital lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines) can be used to write to or read from memory cells. Sense lines can conductively interconnect memory cells along the columns of an array, and access lines can conductively interconnect memory cells along the rows of an array. Each memory cell can be uniquely addressed by a combination of a sense line and an access line.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long period of time without power. Non-volatile memory is conventionally designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is thus refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. In any case, memory cells are configured to retain or store stored content in at least two different selectable states. In a binary system, the states are considered "0" or "1". In other systems, at least some individual memory cells can be configured to store more than two levels or states of information.

[0004] A field effect transistor is an electronic component that can be used in a memory cell. These transistors include a pair of conductive source / drain regions having a semiconductive channel region therebetween. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely blocked. A field effect transistor can also include additional structures, e.g., a reversible programmable charge storage region that is part of the gate structure between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory and is widely used in modern computers and devices. For example, modern personal computers can store the BIOS on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because flash memory enables manufacturers to support new communication protocols as they become standardized and enables manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0006] A NAND can be a basic architecture of an integrated flash memory. A NAND cell device includes at least one select device serially coupled to a serial combination of memory cells (and the serial combination is generally referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement, which includes vertically stacked memory cells, and the vertically stacked memory cells individually include reversibly programmable vertical transistors. Control or other circuitry can be formed under the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells that individually include transistors.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and partial blocks (e.g., sub-blocks), and memory planes, as shown and described in any of U.S. Patent Application Publication Nos. 2015 / 0228659, 2016 / 0267984, and 2017 / 0140833, which are hereby incorporated by reference in their entirety and aspects of which can be used in some embodiments of the invention disclosed herein. Memory blocks can at least partially define the longitudinal profile of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines can occur in a so-called "ladder structure" at the ends or edges of the array of vertically stacked memory cells. The ladder structure includes individual "steps" (alternatively referred to as "tiers" or "ladders"), which define the contact regions of the individual word lines, and vertically extending conductive vias contact thereon to provide electrical access to the word lines. SUMMARY OF THE INVENTION

[0008] Embodiments of the present application provide a memory array including a string of memory cells, which includes: laterally spaced-apart memory blocks, each of which individually includes a vertical stack including alternating insulating layers and conductive layers, and an operative channel material string of memory cells extends through the insulating layers and the conductive layers; and an intervening material that is laterally adjacent to the laterally adjacent memory blocks and longitudinally along the memory blocks, and the intervening material includes longitudinally alternating first and second regions each having a vertically elongated seam, and the vertically elongated seam is longer in the first region than in the second region.

[0009] Another embodiment of the present application provides a memory array including a string of memory cells, which includes: laterally spaced-apart memory blocks, each individually including a vertical stack including alternating insulating layers and conductive layers, and an operative channel material string of memory cells extending through the insulating layers and the conductive layers; and an intervening material that is laterally between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks, the intervening material including longitudinally alternating first and second regions each individually having a vertically elongated seam, the vertically elongated seam having a higher top in the first region than in the second region.

[0010] Another embodiment of the present application provides a memory array including a string of memory cells, which includes: laterally spaced-apart memory blocks, each individually including a vertical stack including alternating insulating layers and conductive layers, and an operative channel material string of memory cells extending through the insulating layers and the conductive layers; an insulating bridge on top of the stack, which extends laterally between laterally adjacent ones of the memory blocks and longitudinally spaced apart along the memory blocks; and an intervening material that is laterally between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks and is directly below the insulating bridge.

[0011] Another embodiment of the present application provides a method for forming a memory array including a string of memory cells, which includes: forming a stack including vertically alternating first and second layers; forming horizontally elongated trenches in the stack to form laterally spaced-apart memory block regions; forming a sacrificial material in the trenches; forming a bridge above the stack and the sacrificial material, the bridge extending across the trenches laterally between laterally adjacent ones of the memory block regions and longitudinally spaced apart along the memory block regions; and replacing the sacrificial material in the trenches with an intervening material between directly below the bridge and longitudinally.

[0012] Another embodiment of the present application provides a method for forming a memory array including a memory cell string, which includes: forming a stack including vertically alternating first and second layers, the first layer including a first sacrificial material; forming a horizontally elongated trench in the stack to form laterally spaced-apart memory block regions; forming a second sacrificial material in the trench; forming a bridge above the stack and the second sacrificial material, the bridge extending across the trench transversely between the laterally adjacent memory block regions and longitudinally spaced apart along the memory block regions; isotropically etching away the second sacrificial material selectively with respect to the bridge and the second layer; isotropically etching away the first sacrificial material in the first layer and replacing it with a conductive material of individual conductive wires; and forming an intervening material in the trench directly below the bridge between the laterally adjacent memory block regions and longitudinally between the bridges. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic cross-sectional view of a portion of a substrate being processed according to an embodiment of the present invention and taken along line 1-1 in Figure 2 therein.

[0014] Figure 2 is a schematic cross-sectional view taken along line 2-2 through Figure 1 therein.

[0015] Figure 3-23 , 30, and 31 are schematic sequential cross-sectional views and / or enlarged views of the construction or portions thereof of Figure 1 and 2 being processed according to some embodiments of the present invention.

[0016] Figures 24-29 , 32, and 33 illustrate alternative example methods and / or structural embodiments of the present invention. DETAILED DESCRIPTION

[0017] Some aspects of the present invention aim to overcome problems associated with so-called "block bending" (where the block stack is laterally tipped / tilted relative to its longitudinal orientation during manufacturing), but the present invention is not limited thereto.

[0018] Embodiments of the present invention encompass methods for forming a memory array, such as an array of NAND or other memory cells having peripheral control circuitry (e.g., CMOS-under-array) below the array. Embodiments of the present invention encompass so-called "post-gate" or "replace-gate" processing, so-called "pre-gate" processing, and other processing independent of the formation time of the transistor gate, whether existing or developed in the future. Embodiments of the present invention also encompass a memory array (e.g., NAND architecture) independent of the manufacturing method. Referring to what can be regarded as a "post-gate" or "replace-gate" process Figures 1-23 to describe a first exemplary method embodiment.

[0019] Figure 1 and 2 shows a structure 10 having an array or array region 12 in which a vertical extension string of transistors and / or memory cells will be formed. The structure 10 includes a substrate 11 having any one or more of conductive / conductor / conduction, semiconductive / semiconductor / semiconduction, or insulating / insulator / insulation (i.e., electrically herein) materials. Various materials are vertically formed on the substrate 11. The materials can be Figure 1 and 2 beside, vertically inside, or vertically outside the materials depicted. For example, other partially or fully fabricated integrated circuit components can be provided above, around, or somewhere inside the substrate 11. Control circuitry and / or other peripheral circuitry for components within a vertical extension string array (e.g., array 12) for operating the memory cells can also be fabricated, and the circuitry can or cannot be fully or partially within the array or sub-array. In addition, multiple sub-arrays can be fabricated and operated independently of each other, sequentially, or otherwise. In this document, a "sub-array" can also be regarded as an array.

[0020] A conductor layer 16 including a conductive material 17 is formed over a substrate 11. The conductor layer 16 may include portions of control circuitry (such as underperipheral array circuitry and / or a common source line or plate) for controlling read and write access to transistors and / or memory cells to be formed within the array 12. A stack 18 including vertically alternating insulating layers 20 and conductive layers 22 is formed over the conductor layer 16. Example thicknesses for each of the layers 20 and 22 are 22 to 60 nanometers. Only a few of the layers 20 and 22 are shown, where the stack 18 is more likely to include dozens, hundreds, or more (etc.) of the layers 20 and 22. Other circuitry, which may or may not be part of the peripheral and / or control circuitry, may be between the conductor layer 16 and the stack 18. For example, multiple vertically alternating layers of conductive and insulating materials of such circuitry may be below the lowest conductive layer 22 and / or above the uppermost conductive layer 22. For example, one or more select gate layers (not shown) may be between the conductor layer 16 and the lowest conductive layer 22, and one or more select gate layers may be above the uppermost conductive layer 22. In any case, the conductive layer 22 (alternatively referred to as the first layer) may not include a conductive material, and the insulating layer 20 (alternatively referred to as the second layer) may not include an insulating material or may be insulating when processed in connection with the "back gate" or "replace gate" example method embodiments initially described herein. Example conductive layer 22 includes a first material 26 (such as silicon nitride) that may be fully or partially sacrificial. Example insulating layer 20 includes a second material 24 (such as silicon dioxide), the composition of which is different from the composition of the first material 26 and which may be fully or partially sacrificial. The uppermost insulating layer 20 may be considered to have a top surface 21.

[0021] A channel opening 25 is formed through the insulating layer 20 and the conductive layer 22 to the conductor layer 16 (e.g., by etching). In some embodiments, the channel opening 25 may partially enter the conductive material 17 of the conductor layer 16 as shown, or may terminate at the top (not shown). Alternatively, by way of example, the channel opening 25 may terminate at or within the top of the lowest insulating layer 20. The reason for the channel opening 25 to extend at least to the conductive material 17 of the conductor layer 16 is to ensure that the subsequently formed channel material (not yet shown) is directly electrically coupled to the conductor layer 16 without using alternative processes and structures to achieve this when such a connection is desired. An etch stop material (not shown) may be within or on top of the conductive material 17 of the conductor layer 16 to assist in stopping the etching of the channel opening 25 relative to the conductor layer 16 when such is desired. Such an etch stop material may be sacrificial or non-sacrificial. By way of example and for simplicity only, the channel openings 25 are shown as being arranged in groups or columns of staggered rows of four and five openings 25 per row, and arranged in laterally spaced memory block regions 58 which will include laterally spaced memory blocks 58 in the finished circuit system configuration. In this document, a "block" generally includes a "sub-block". The memory block regions 58 and the resulting memory blocks 58 (not yet shown) may be considered to be longitudinally elongated and oriented, for example, along the direction 55. The memory block regions 58 may not be discernible at this point in the process. Any alternative existing or future developed arrangements and configurations may be used.

[0022] Transistor channel materials may be formed vertically along the insulating and conductive layers in individual channel openings, thus including individual strings of channel materials that are directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the resulting memory array may include a gate region (e.g., a control gate region) and a memory structure that is laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transfer material. The storage material of an individual memory cell (e.g., a floating gate material such as doped or undoped silicon, or a charge trapping material such as silicon nitride, metal dots, etc.) is vertically along the individual charge blocking regions. The insulating charge transfer material (e.g., a bandgap engineered structure having a nitrogen-containing material [e.g., silicon nitride] sandwiched between two insulator oxides [e.g., silicon dioxide]) is laterally between the channel material and the storage material.

[0023] Figure 3 、 3A, 4, and 4A illustrate an embodiment in which a charge blocking material 30, a storage material 32, and a charge transfer material 34 are vertically formed in individual channel openings 25 along an insulating layer 20 and a conductive layer 22. The transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed, for example, by depositing corresponding thin layers of the transistor materials above the stack 18 and within the individual channel openings 25, and then at least planarizing such backs to the top surface of the stack 18. A channel material 36 is also vertically formed in the channel openings 25 along the insulating layer 20 and the conductive layer 22, thus including individual operative channel material strings 53. Due to scale, the materials 30, 32, 34, and 36 are jointly shown as and only designated as material 37 in Figure 3 and 4 . Example channel materials 36 include suitably doped crystalline semiconductor materials such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness for each of the materials 30, 32, 34, and 36 is 25 to 100 angstroms. As shown, a punch etch can be performed to remove the materials 30, 32, and 34 from the substrate of the channel openings 25 to expose the conductor layer 16 such that the channel material 36 abuts directly against the conductive material 17 of the conductor layer 16. Such a punch etch can occur individually with respect to each of the materials 30, 32, and 34 (as shown), or can occur jointly with respect to all the materials after the deposition of the material 34 (not shown). Alternatively and by way of example only, no punch etch can be performed, and the channel material 36 can be directly electrically coupled to the conductive material 17 of the conductor layer 16 through a separate conductive interconnect (not shown). The channel openings 25 are shown to include a radially centered solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively and by way of example only, the radially centered portion within the channel openings 25 can include a void space (not shown) and / or be free of solid material (not shown). A conductive plug (not shown) can be formed on top of the channel material strings 53 for better electrical connection to an upper circuit system (not shown).

[0024] Referring Figure 5 and 6 , horizontally elongated trenches 40 have been formed in the stack 18 (e.g., by anisotropic etching), thereby forming laterally spaced-apart storage block regions 58. The horizontally elongated trenches 40 can have corresponding bottoms (as shown) that abut directly against the conductive material 17 (e.g., top or interior) of the conductor layer 16, or can have corresponding bottoms that are above the conductive material 17 of the conductor layer 16 (not shown).

[0025] The above processing shows forming and filling the channel openings 25 before forming the trenches 40. This can be reversed. Alternatively, the trenches 40 can be formed between forming and filling the channel openings 25 (not ideal).

[0026] Reference Figure 7 and 8 , a sacrificial material 31 is formed in the trench 40. Example techniques for doing so include: depositing the sacrificial material 31 to overfill the trench 40 and then at least planarizing such back to the top surface 21 of the topmost insulating layer 20. In some embodiments, such a sacrificial material is referred to as a second sacrificial material 31. In one embodiment and as shown, the sacrificial material 31 is formed to have a top surface 19 that is vertically coincident with the top surface 21 of the stack 18. In one embodiment and as shown, the top surfaces 19 and 21 are individually flat and coplanar. Example sacrificial materials include at least one of spin-on carbon, boron- and / or phosphorus-doped silica, silicon nitride, aluminum oxide, and tungsten in elemental form. In one embodiment, the conductive layer 22 includes a first sacrificial material 26, and the sacrificial material 31 includes a second sacrificial material, and in one embodiment, the sacrificial materials have different compositions relative to each other, while in another embodiment, they have the same composition relative to each other.

[0027] Reference Figures 9 to 11 , a bridge 39 is formed over the stack 18 and the sacrificial material 31. The bridge 39 extends across the trench 40 between and longitudinally spaced apart laterally adjacent memory block regions 58. A space 42 is longitudinally between the bridges 39. In one embodiment and as shown, the material 35 of the bridge 39 directly abuts the insulating material 24 of the top insulating layer 20 of the stack 18 and has the same composition as the insulating material 24 (e.g., silica) in one such embodiment. In another embodiment, the bridge material 35 has a composition different from all of the materials (e.g., 24, 26) of the vertically alternating insulating layer 20 and conductive layer 22 (whether directly abutting the top insulating layer 20 of the stack 18 or not), and one example material is carbon-doped silicon nitride. In one embodiment, the bridge material 35 extends across the individual memory block regions 58 at the top and laterally, and in one such embodiment as shown, covers all of the tops (e.g., 21) of the memory block regions 58. Example techniques for forming the patterned bridge material 35 as shown are photolithographic patterning and etching with or without pitch multiplication. In embodiments where the bridge 39 remains in the finished integrated circuit structure, such a bridge is formed to at least insulate its outer material (thus, the bridge 39 formed therefrom is thus insulating).

[0028] The sacrificial material 31 in the trench 40 is replaced by an intervening material directly below and longitudinally between the bridges 39. Reference Figures 12 to 23 Describe examples of such methods. First reference Figures 12 to 14, for example, sacrificial material 31 (not shown) has been removed by selectively and isotropically etching, in one embodiment as shown, relative to the bridging member 39 and the insulating layer 20 and relative to the conductive layer 22. One skilled in the art can select a suitable etching chemical reaction to etch one material selectively relative to other materials.

[0029] Reference Figures 15 to 18 And in one embodiment, material 26 (not shown) of the conductive layer 22 has been removed, for example, by isotropically etching through the space 42 relative to other exposed materials desirably selectively (e.g., using liquid or vapor H3PO4 as the main etchant, where material 26 is silicon nitride and the other materials include one or more oxides or polysilicon). In an exemplary embodiment, material 26 (not shown) in the conductive layer 22 is sacrificial and has been replaced by the conductive material 48 and has thereafter been removed from the space 42 and the trench 40, thus forming individual conductive lines 29 (e.g., word lines) and the vertical extension strings 49 of individual transistors and / or memory cells 56. In one embodiment, during the replacement operation, the material 35 of the bridging member is also at the top and extends laterally across the individual memory block regions 58, and in one such embodiment as shown, during the replacement operation, the material 35 covers all of the tops of the memory block regions 58.

[0030] A thin insulating liner (e.g., Al2O3 and not shown) can be formed before forming the conductive material 48. The approximate locations of the transistors and / or memory cells 56 are Figure 18 indicated by parentheses, while some are Figure 15 and 16 indicated by dashed outlines, where the transistors and / or memory cells 56 are substantially annular or ring-shaped in the depicted example. Alternatively, the transistors and / or memory cells 56 may not completely surround the individual channel openings 25 such that each channel opening 25 can have two or more vertical extension strings 49 (e.g., in an individual conductive layer, multiple transistors and / or memory cells surround an individual channel opening, where there may be multiple word lines per channel opening in an individual conductive layer and not shown). The conductive material 48 can be considered to have ends 50 corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56 ( Figure 18 ). In the depicted embodiment, the control gate region 52 includes individual portions of the individual conductive lines 29. Materials 30, 32, and 34 can be considered as the memory structure 65 that is laterally between the control gate region 52 and the channel material 36. In one embodiment and as shown for the exemplary "back-gate" process, the conductive material 48 of the conductive layer 22 is formed after forming the bridging member 39. Alternatively, for example, relative to a "front-gate" process, the conductive material of the conductive layer can be formed before forming the upper bridging member 39 and / or before forming the trench 40 (not shown).

[0031] A charge blocking region (e.g., charge blocking material 30) is located between the charge storage material 32 and the individual control gate region 52. The charge blocking member may have the following functions in the memory cell: in the program mode, the charge blocking member may prevent charge carriers from transferring from the storage material (e.g., floating gate material, charge trapping material, etc.) to the control gate, and in the erase mode, the charge blocking member may prevent charge carriers from flowing from the control gate into the storage material. Therefore, the charge blocking member can be used to block the charge migration between the control gate region of an individual memory cell and the storage material. The illustrated example charge blocking region includes an insulator material 30. As another example, the charge blocking region may include a lateral (e.g., radial) outer portion of the storage material (e.g., material 32), where such storage material is insulating (e.g., in the case where there is no different composition material between the insulating storage material 32 and the conductive material 48). In any case, as an additional example, the interface between the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any separate composition insulator material 30. In addition, the interface between the conductive material 48 and the material 30 (if present) combined with the insulator material 30 may act as a charge blocking region together, and alternatively or additionally may act as a lateral outer region of the insulating storage material (e.g., silicon nitride material 32). Example materials 30 are one or more of hafnium silicon oxide and silicon dioxide.

[0032] Reference Figures 19 to 23 And in one embodiment, an intervening material 57 is formed directly below the bridging member 39 between laterally adjacent memory block regions 58 and longitudinally in the trench 40 therebetween. For clarity, Figure 22 At a scale Figures 19 to 21 triple the scale of Figure 23 and Figure 22 is a schematic enlarged view of a part of

[0033] The intervening material 57 may provide lateral electrical isolation (insulation) between laterally adjacent memory block regions 58 and the final memory block 58. This may include one or more of insulating, semi-conductive, and conductive materials, and in any case, may facilitate the shorting of the conductive layers 22 relative to each other in the finished circuit system construction. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. In one embodiment, the intervening material 57 includes a laterally outermost insulating material (e.g., silicon nitride and / or silicon dioxide, not shown) and a laterally inner material having a composition different from that of the laterally outermost insulating material (e.g., undoped polysilicon, not shown). In one such embodiment, the laterally inner material is insulating. In one embodiment, the intervening material 57 is insulating everywhere between laterally adjacent memory blocks.In one embodiment, the intervening material 57 includes a vertically elongated seam 61 therein. In one such embodiment and as shown, the vertically elongated seam 61 is longer longitudinally between the bridging members 39 than directly below the bridging members 39. Alternatively or additionally, and as shown, the vertically elongated seam 61 has a seam top 33 ( Figure 22 ), which is higher longitudinally between the bridging members 39 than directly below the bridging members 39. In one embodiment, the vertically elongated seam 61 includes at least one void space, and in one such embodiment and as shown ( Figure 23 ) includes a plurality of vertically spaced void spaces 63. For example, as shown, at least some of the plurality of void spaces 63 may be individually vertically elongated. In another exemplary embodiment, the vertically elongated seam 61a includes only one void space 63a (e.g., extending downward from the top of the intervening material 57 in the trench 40), as shown relative to Figure 24 the structure 10a in. The same numbers from the embodiments described above have been used where appropriate, with the suffix "a" indicating some structural differences. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0034] Reference Figures 25 to 27 shows and describes alternative exemplary methods and resulting structures 10b. The same numbers from the embodiments described above have been used where appropriate, with the suffix "b" or different numbers indicating some structural differences. Figures 25 to 27 shows an exemplary embodiment where the intervening material between memory blocks / block regions is non-uniform. Specifically, the exemplary intervening material 57b is formed to include a lateral outer material 67 and a lateral inner material 68 having a composition different from that of the lateral outer material 67. The vertically elongated seam 61 is in the lateral inner material 68. Merely by way of example, the exemplary lateral outer material 67 includes silicon dioxide, and the exemplary lateral inner material 68 includes undoped polysilicon.

[0035] In one embodiment where the bridging members 39 are isolated / insulated, at least some of the insulating material has the same composition as the intervening material 57 / 57b. In one embodiment where the bridging members 39 are isolated / insulated, at least some of the insulating material has a composition different from that of the intervening material 57 / 57b, and in one embodiment where only some of the insulating material has a composition different from that of the intervening material 57 / 57b.

[0036] Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0037] In one embodiment, all of the material 35 of the bridging members 39 is above the stack 18, e.g., as shown in Figures 19 to 22 Reference Figure 28and 29 Alternative example methods and resulting constructs 10c are shown and described. The same numbers as those of the embodiments described above have been used where appropriate, with the suffix "c" indicating some construction differences. Figure 28 Most closely corresponds to Figure 8 the construct, and an example embodiment is shown in which the sacrificial material 31c is formed to have a top surface 19c that is lower than the top surface 21 of the stack 18. Figure 29 Subsequent processing similar to that described above is shown, most closely corresponding to Figure 16 the construct, and a slightly alternative construct of the bridge 39c is shown, where some material 35 of the bridge is within the vertical stack 18. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0038] In some method embodiments, all bridges 39 / 39c are removed sometime after replacing the sacrificial material in the trenches with interposed material directly under and longitudinally between the bridges. Relative to Figure 30 and 31 Examples of such processing are shown, which are respectively after the processing shown in Figure 20 and 21 The bridges 39 of the construct 10 have been removed (not shown). Alternatively, at least some of the material of the bridges may still extend across the trenches in the final construct of the memory array, such as as shown for the construct 10 in Figures 19 to 23 above, showing that substantially all of the bridge material 35 of the bridge remains. In Figure 32 and 33 (corresponding to Figure 20 and 21 ) respectively, alternative example embodiments are shown for the construct 10d. The same numbers as those of the embodiments described above have been used where appropriate, with the suffix "d" indicating some construction differences. Figure 32 and 33 Show the vertical thickness of the bridge 39d and its material 35d (which has been reduced sometime after the action of forming the bridge material), and for example, at least some of the material of the bridge still extends across the trenches in the final construct of the memory array. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0039] Alternative example constructs may be produced by the method embodiments described above or otherwise. In any case, embodiments of the present invention cover memory arrays that are independent of the manufacturing method. Nevertheless, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0040] Embodiments of the present invention include a memory array (e.g., 12) that includes strings (e.g., 49) of memory cells (e.g., 56). The memory array includes laterally spaced-apart memory blocks (e.g., 58) that each include a vertical stack (e.g., 18) that includes alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). An operative channel material string (e.g., 53) of the memory cells extends through the insulating and conductive layers.

[0041] In one such embodiment, an intervening material (e.g., 57, 57b) is laterally between laterally adjacent memory blocks and longitudinally along the memory blocks. The intervening material includes longitudinally alternating first and second regions (e.g., 60 and 64, respectively, in Figure 22 which) each having a vertically elongated seam (e.g., 61, 61a). The vertically elongated seam is longer in the first region than in the second region. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0042] In one such embodiment, an intervening material (e.g., 57, 57b) is laterally between laterally adjacent memory blocks and longitudinally along the memory blocks. The intervening material includes longitudinally alternating first and second regions (e.g., 60 and 64, respectively, in Figure 22 which) each having a vertically elongated seam (e.g., 61, 61a). The vertically elongated seam has a higher top in the first region than in the second region. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0043] In one such embodiment, insulating bridges (e.g., 39, 39c, 39d) are at the top of the stack and extend across trenches (e.g., 40) that are laterally between laterally adjacent memory block regions and longitudinally spaced therebetween. An intervening material (e.g., 57, 57b) is laterally between laterally adjacent memory blocks and longitudinally along the memory blocks and is directly below the insulating bridges. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0044] The above processing or construction can be considered related to an array of components, which is formed as a single stack or single stack group of such components above a underlying substrate or as part of the underlying substrate or within the single stack or single stack group (but the single stack / group can have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array can also be formed at any location as part of the finished construction and, in some embodiments, can be below the array (e.g., CMOS under the array). In any case, one or more additional such stacks / groups can be provided or fabricated above and / or below the stack / group shown or described above. Also, the arrays of components can be the same or different relative to each other in different stacks / groups, and different stacks / groups can have the same thickness or different thicknesses relative to each other. Intermediate structures can be provided between vertically adjacent stacks / groups (e.g., additional circuitry and / or dielectric layers). Additionally, different stacks / groups can be electrically coupled relative to each other. Multiple stacks / groups can be fabricated individually and sequentially (e.g., one on top of another), or two or more stacks / groups can be fabricated substantially simultaneously.

[0045] The assemblies and structures discussed above can be used in integrated circuits / circuit systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application specific modules and can include multi-layer, multi-chip modules. The electronic system can be any one of a wide range of systems: for example, cameras, wireless devices, displays, chip sets, set-top boxes, gaming, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0046] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "above", "bottom", "beneath", "under", "underneath", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to a general direction along the main substrate surface (i.e., within 10 degrees) and the substrate can be processed relative thereto during manufacturing, while vertical is a direction generally orthogonal thereto. A reference to "exactly horizontal" refers to a direction along the main substrate surface (i.e., not forming a degree with the surface) and the substrate can be processed relative thereto during manufacturing. In addition, as used herein, "vertical" and "horizontal" are directions that are generally perpendicular to each other and are independent of the orientation of the substrate in three-dimensional space. Additionally, "vertically extending" and "extending vertically" refer to a direction that deviates from exactly horizontal by at least 45°. Further, with respect to a field effect transistor, "vertically extending", "vertically extended", "horizontally extending", "horizontally extended", and the like are with reference to the orientation of the channel length of the transistor, along which current flows between the source / drain regions during operation. For a bipolar junction transistor, "vertically extending", "vertically extended", "horizontally extending", "horizontally extended", and the like are with reference to the orientation of the base length, along which current flows between the emitter and the collector during operation. In some embodiments, any component, feature, and / or region that extends vertically extends vertically or within 10° of vertical.

[0047] In addition, "directly above", "directly beneath", and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components relative to each other. Additionally, the use of "above" without "directly" in front only requires that a portion of the stated region / material / component above another stated region / material / component be vertically outside of the other stated region / material / component (i.e., independent of whether there is any lateral overlap between the two stated regions / materials / components). Similarly, the use of "beneath" and "below" without "directly" in front only requires that a portion of the stated region / material / component below another stated region / material / component be vertically inside of the other stated region / material / component (i.e., independent of whether there is any lateral overlap between the two stated regions / materials / components).

[0048] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous and may be continuous or discontinuous over any material over which it is disposed. Where one or more example constituents are provided for any material, the material may include such one or more constituents, consist essentially of such one or more constituents, or consist of such one or more constituents. Additionally, unless otherwise specified, any suitable existing or future developed technique may be used to form each material, where atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation are examples.

[0049] Additionally, "thickness" when used alone (without a directional adjective in front) is defined as the average linear distance perpendicular to the closest surface of an adjacent material or adjacent region having a different composition and passing through a given material or region. Additionally, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If the thickness is variable, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different composition" only requires that those portions of two stated materials or regions that can be directly adjacent to each other be chemically and / or physically different, such as in the case where such materials or regions are heterogeneous. If two stated materials or regions are not directly adjacent to each other, then in the case where such materials or regions are heterogeneous, "different composition" only requires that those portions of the two stated materials or regions that are closest to each other be chemically and / or physically different. In this document, when materials, regions, or structures are in at least some physical contact with each other, the stated materials, regions, or structures are "directly adjacent" to another material, region, or structure. In contrast, "above", "on", "adjacent to", "along", and "against" without a "positive" in front cover both "directly adjacent" and configurations where intervening materials, regions, or structures result in the stated materials, regions, or structures having no physical contact with each other.

[0050] In this document, if, during normal operation, current can flow continuously from one region - material - component to another region - material - component and the flow is primarily through the movement of subatomic positive and / or negative charges when such subatomic positive and / or negative charges are sufficiently generated, then the region - material - components are "electrically coupled" to each other. Another electronic component may be between the region - material - components and electrically coupled to the region - material - components. In contrast, when region - material - components are said to be "directly electrically coupled", there is no intervening electronic component (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) between the directly electrically coupled region - material - components.

[0051] The terms "row" and "column" are used in this document for convenience in distinguishing features of one series or orientation from those of another series or orientation, and components have been or can be formed along said "rows" and "columns". "Row" and "column" are used synonymously with respect to any series of regions, components, and / or features, regardless of function. In any case, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns can be the same. In addition, rows and columns can intersect each other at 90° or at one or more other angles.

[0052] The composition of any of the conductive / conductor / conduction materials herein can be a metallic material and / or a conductively doped semi-conductive / semiconductor / semiconduction material. "Metallic material" is any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0053] In this document, any use of "selective" with respect to etching (etch, etching), removal, deposition, forming, and / or formation is such an action of a stated material with respect to another stated material being acted upon at a volume ratio of at least 2:1. In addition, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming a material relative to another or other stated materials at a volume ratio of at least 2:1 for at least a first 75 angstroms of deposition, growth, or formation.

[0054] Unless otherwise indicated, the use of "or" herein covers either and both.

[0055] Summary

[0056] In some embodiments, a memory array including a string of memory cells includes memory blocks that are individually vertically stacked and laterally spaced apart, the vertical stack including alternating insulating layers and conductive layers. An operative channel material string of the memory cells extends through the insulating layers and the conductive layers. An intervening material is laterally between the laterally adjacent memory blocks and longitudinally along the memory blocks. The intervening material includes longitudinally alternating first and second regions each having a vertically elongated seam. The vertically elongated seam is longer in the first region than in the second region.

[0057] In some embodiments, a memory array including a string of memory cells includes memory blocks that are individually vertically stacked and laterally spaced apart, the vertical stack including alternating insulating and conductive layers. An operative channel material string of the memory cells extends through the insulating and conductive layers. An intervening material is laterally between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks. The intervening material includes longitudinally alternating first and second regions each having a vertically elongated seam. The vertically elongated seam has a higher top in the first region than in the second region.

[0058] In some embodiments, a memory array including a string of memory cells includes memory blocks that are individually vertically stacked and laterally spaced apart, the vertical stack including alternating insulating and conductive layers. An operative channel material string of the memory cells extends through the insulating and conductive layers. Insulating bridges are on top of the stack and extend laterally therebetween and longitudinally spaced apart along laterally adjacent memory blocks. An intervening material is laterally between laterally adjacent memory blocks and longitudinally along the memory blocks and directly under the insulating bridges.

[0059] In some embodiments, a method of forming a memory array including a string of memory cells includes forming a stack including vertically alternating first and second layers. Horizontally elongated trenches are formed in the stack to form laterally spaced-apart memory block regions. Sacrificial material is formed in the trenches. Bridges are formed over the stack and the sacrificial material. The bridges extend laterally between laterally adjacent memory block regions and are longitudinally spaced apart along the memory block regions. The sacrificial material in the trenches is replaced with an intervening material between directly under and longitudinally between the bridges.

[0060] In some embodiments, a method of forming a memory array including a string of memory cells includes forming a stack including vertically alternating first and second layers. The first layer includes a first sacrificial material. Horizontally elongated trenches are formed in the stack to form laterally spaced-apart memory block regions. A second sacrificial material is formed in the trenches. Bridges are formed over the stack and the second sacrificial material. The bridges extend laterally between laterally adjacent memory block regions and are longitudinally spaced apart along the memory block regions. The second sacrificial material is etched away isotropically relative to the bridges and the second layer. The first sacrificial material in the first layer is etched away isotropically and replaced with a conductive material of individual conductive lines. An intervening material is formed in the trenches between directly under and longitudinally between the bridges between laterally adjacent memory block regions.

[0061] As provided, the subject matter disclosed herein has been described in more or less specific language with respect to structural and method features. However, it is to be understood that the claims are not limited to the specific features shown and described, since the components disclosed herein include example embodiments. Accordingly, the claims have the full scope as literally stated and should be construed appropriately in accordance with the doctrine of equivalents.

Claims

1. A memory array including a string of memory cells, comprising: Laterally spaced memory blocks, each individually including a vertical stack comprising alternating insulating and conductive layers, an operative channel material string of memory cells extending through the insulating and conductive layers; And Interstitial material, which is laterally between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks, the interstitial material including longitudinally alternating first and second regions each individually having a vertically elongated seam, the vertically elongated seam being longer in the first region than in the second region, Wherein the vertically elongated seams in the first and second regions each individually include at least one void space; and Wherein the vertically elongated seams in the first and second regions each individually include a plurality of vertically spaced void spaces.

2. The memory array according to claim 1, wherein the vertically elongated seam has a higher top in the first region than in the second region.

3. The memory array according to claim 1, wherein the vertically elongated seams in the first and second regions each individually include only one void space.

4. The memory array according to claim 1, wherein the interstitial material includes a laterally outermost insulating material and a laterally inner material having a composition different from that of the laterally outermost insulating material, the vertically elongated seams in the first and second regions being in the laterally inner material.

5. The memory array according to claim 4, wherein the laterally outermost insulating material includes silicon dioxide, and the laterally inner material includes undoped polysilicon.

6. The memory array according to claim 1, wherein the interstitial material is insulating everywhere between laterally adjacent ones of the memory blocks.

7. A memory array including a string of memory cells, comprising: Laterally spaced memory blocks, each individually including a vertical stack comprising alternating insulating and conductive layers, an operative channel material string of memory cells extending through the insulating and conductive layers; And Interstitial material, which is laterally between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks, the interstitial material including longitudinally alternating first and second regions each individually having a vertically elongated seam, the vertically elongated seam having a higher top in the first region than in the second region, Wherein the vertically elongated seams in the first and second regions each individually include at least one void space; and Wherein the vertically elongated seams in the first and second regions each individually include a plurality of vertically spaced void spaces.

8. The memory array according to claim 7, wherein the vertically elongated seams in the first and second regions each individually include only one void space.

9. A memory array including a string of memory cells, comprising: Horizontally spaced-apart memory blocks, each individually including a vertical stack that includes alternating insulating and conductive layers, with the operative channel material strings of memory cells extending through the insulating and conductive layers; Insulating bridges on top of the stack, extending transversely between the laterally adjacent memory blocks and longitudinally spaced apart along the memory blocks; And Intervening material, which is laterally between the laterally adjacent memory blocks and longitudinally along the memory blocks and directly below the insulating bridges, Wherein the intervening material includes vertically elongated seams therein; and Wherein the vertically elongated seams are longer longitudinally between the bridges than directly below the bridges.

10. The memory array according to claim 9, wherein the insulating material of the bridges directly abuts the insulating material of the top insulating layer of the stack and has the same composition as the insulating material.

11. The memory array according to claim 9, wherein the insulating material of the bridges has a composition different from all the materials of the vertically alternating insulating layers.

12. The memory array according to claim 11, wherein the insulating bridge material comprises carbon-doped silicon nitride.

13. The memory array according to claim 11, wherein all the materials of the bridges are above the vertical stack.

14. The memory array according to claim 11, wherein some of the materials of the bridges are within the vertical stack.

15. The memory array according to claim 9, wherein the intervening material is completely insulating and the insulating material of the bridges has the same composition as the intervening material.

16. The memory array according to claim 9, wherein at least some of the intervening material is insulating and at least some of the insulating material of individual bridges among the bridges has the same composition as the at least some of the insulating intervening material.

17. The memory array according to claim 9, wherein at least some of the intervening material is insulating and at least some of the insulating material of individual bridges among the bridges has a composition different from the composition of the at least some of the insulating intervening material.

18. The memory array according to claim 17, wherein only some of the insulating material of individual bridges among the bridges has a composition different from the composition of the at least some of the insulating intervening material.

19. The memory array according to claim 9, wherein the intervening material includes laterally outermost insulating material and laterally inner material having a composition different from the composition of the laterally outermost insulating material, and the vertically elongated seams in the first and second regions of the intervening material are in the laterally inner material.

20. The memory array according to claim 9, wherein the intervening material is insulating everywhere between the laterally adjacent memory blocks.

21. The memory array according to claim 9, wherein the top of the vertically elongated seams is higher longitudinally between the bridges than directly below the bridges.

22. The memory array according to claim 21, wherein the vertically elongated seam is longer longitudinally between the bridging members than directly beneath the bridging members.

23. A method for forming a memory array including memory cell strings, comprising: forming a stack including vertically alternating first and second layers; forming horizontally elongated trenches in the stack to form laterally spaced-apart memory block regions; forming sacrificial material in the trenches; forming bridging members over the stack and the sacrificial material, the bridging members extending across the trenches laterally between laterally adjacent ones of the memory block regions and longitudinally spaced apart along the memory block regions; and replacing the sacrificial material in the trenches with an intervening material between directly beneath and longitudinally between the bridging members.

24. The method according to claim 23, wherein during the replacement, the material of the bridging members is on top of and extends laterally across individual ones of the memory block regions in the memory block regions.

25. The method according to claim 24, wherein during the replacement, the material of the bridging members covers all the tops of the memory block regions.

26. The method according to claim 23, comprising forming the sacrificial material to have a top surface vertically coincident with the top surface of the stack.

27. The method according to claim 23, comprising forming the sacrificial material to have a top surface lower than the top surface of the stack.

28. The method according to claim 23, comprising forming the sacrificial material and the stack to each have a flat top surface.

29. The method according to claim 28, comprising forming the top surfaces of the sacrificial material and the stack to be coplanar.

30. The method according to claim 23, wherein the material of the bridging members directly abuts the insulating material of the top insulating second layer of the stack and has the same composition as the insulating material.

31. The method according to claim 23, wherein the material of the bridging members has a composition different from all the materials of the vertically alternating first and second layers.

32. The method according to claim 31, wherein the bridging member material comprises carbon-doped silicon nitride.

33. The method according to claim 23, comprising removing all the bridging members after the replacement.

34. The method according to claim 23, wherein in the finished configuration of the memory array, at least some of the material of the bridging members still extends across the trenches.

35. The method according to claim 34, comprising reducing the vertical thickness of the bridging members after the replacement.

36. The method according to claim 23, comprising forming the sacrificial material to include at least one of spin-on carbon, boron- and / or phosphorus-doped silica, alumina, and tungsten in elemental form.

37. The method according to claim 23, comprising forming individual memory cells of the memory cell string to include channel material of an operative channel material string, a gate region that is part of a conductive wire in an individual first layer of the first layer, and a memory structure that is laterally between the gate region and the channel material of the operative channel material string in the individual first layer, the conductive material of the first layer being formed after forming the bridge.

38. The method according to claim 23, comprising forming individual memory cells of the memory cell string to include channel material of an operative channel material string, a gate region that is part of a conductive wire in an individual first layer of the first layer, and a memory structure that is laterally between the gate region and the channel material of the operative channel material string in the individual first layer, the conductive material of the first layer being formed before forming the bridge.

39. A method for forming a memory array including a memory cell string, comprising: forming a stack including vertically alternating first and second layers, the first layer including a first sacrificial material; forming horizontally elongated trenches in the stack to form laterally spaced-apart memory block regions; forming a second sacrificial material in the trenches; forming a bridge over the stack and the second sacrificial material, the bridge extending across the trenches laterally between laterally adjacent memory block regions and longitudinally spaced apart along the memory block regions; isotropically etching away the second sacrificial material selectively with respect to the bridge and the second layer; isotropically etching away the first sacrificial material in the first layer and replacing it with conductive material of individual conductive wires; and forming an intervening material in the trenches directly below the bridge between laterally adjacent memory block regions and longitudinally between the bridges.

40. The method according to claim 39, wherein the first and second sacrificial materials have different compositions relative to each other.

41. The method according to claim 39, wherein the first and second sacrificial materials have the same composition relative to each other.

42. The method according to claim 39, wherein the isotropically etching away the second sacrificial material selectively with respect to the bridge and the second layer is also performed selectively with respect to the first layer.

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