High Speed ​​Low Power Level Shift Clock Buffer

Abstract

A DC coupled buffer is provided with two switching transistors controlled by a delayed version of an output signal for the DC coupled buffer. A first of the switching transistors functions to cut off a current discharged into ground that would otherwise flow when an input signal for the DC coupled buffer is discharged. A remaining second of the switching transistors functions to increase the operating speed of the DC coupled buffer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Non-Provisional Patent Application No. 16 / 516,114, filed on July 18, 2019, and U.S. Provisional Application No. 62 / 701,352, filed on July 20, 2018, the entire contents of which are incorporated herein by reference as if fully set forth below for all applicable purposes. Technical Field

[0003] The present application relates to clock buffers, and more particularly to high speed low power level shifting clock buffers. Background Art

[0004] As transistor sizes have shrunk, the supply voltage for digital cores has decreased. But input / output (I / O) legacy standards typically use higher supply voltages. If a core signal must be transmitted to an external circuit, the signal is typically level-shifted from the internal supply voltage to the I / O supply voltage. An example of such a signal is a clock signal from a voltage-controlled oscillator (VCO) controlled in a phase-locked loop. A clock buffer for a clock signal not only buffers the clock signal, but also level-shifts it from the internal supply voltage to the I / O supply voltage.

[0005] Clock buffering and level shifting can be performed using a variety of alternative architectures. For example, an input clock signal drives an internal node through a capacitor and a resistor in an alternating current (AC) coupled buffer. The resulting passive components in an AC coupled buffer reduce density. In addition, the time constant for the resistor-capacitor (RC) combination limits the frequency range for an AC coupled buffer. To avoid the need for passive devices and the associated frequency limitations of an AC coupled buffer, it is known to use a direct current (DC) coupled buffer. An example DC coupled buffer 100 is shown in FIG. Figure 1 . The DC coupled buffer 100 is located in an input / output (I / O) power domain powered by an I / O power supply voltage VDDH. An inverter for inverting an input clock signal Vin to form a complementary or inverted clock signal Vin_b is located in an internal power domain powered by an internal power supply voltage VDDL lower than the I / O power supply voltage VDDH.

[0006] The inverted clock signal Vin_b drives the gate of a first pull-down NMOS transistor M1 having a source connected to ground. When the input clock signal Vin is low, the drain of the first pull-down transistor M1 will be pulled low as a result. The drain of the first pull-down transistor M1 is connected to a current mirror terminal 120 of a current mirror formed by a diode-connected PMOS transistor P1 and a current mirror PMOS transistor P2. In particular, the drain and gate of the diode-connected PMOS transistor P1 form a current mirror terminal 120, which is also connected to the gate of the current mirror transistor P2. The sources of transistors P1 and P2 are connected to a power rail for the I / O supply voltage VDDH. Therefore, the discharge for the drain of the first pull-down transistor M1 will turn on the diode-connected transistor P1 to conduct the current mirrored by the current mirror transistor P2.

[0007] The drain of the current mirror transistor P2 is connected to the drain of the second pull-down NMOS transistor M2 having a source connected to ground. The input clock signal Vin drives the gate of the second pull-down transistor M2 so that when the inverted input clock signal Vin_b is high (charged to VDDL), the second pull-down transistor M2 will be turned off. Therefore, in response to the falling edge of the input clock signal Vin, the current conducted by the current mirror transistor P2 will charge the internal node 110. The inverter 115 inverts the voltage of the internal node 110 to drive the output clock signal Vout. Therefore, in response to the falling edge of the input clock signal Vin, the output clock signal Vout will be discharged low to ground. In response to the rising edge of the input clock signal Vin, the second pull-down transistor M2 is turned on to pull the node 110 low, so that the inverter 115 charges the output clock signal Vout to be high to VDDH. Although the DC coupled buffer 100 does not require any passive components and does not have the frequency limitations of the AC coupled buffer, when the input clock signal Vin is low, the series combination of the diode connected transistor P1 and the first pull-down transistor M1 discharges the current to ground. In addition, since the current mirror transistor P2 will still be turned on at the rising edge transition of the input clock signal Vin and will slow down the discharge of the internal node 110, the response of the output clock signal Vout to the rising edge of the input clock signal Vin is slowed down by the conflict between the current mirror transistor P2 and the second pull-down transistor M2. Therefore, the DC coupled buffer 100 has relatively high power consumption and reduced operating speed.

[0008] Therefore, there is a need in the art for a DC-coupled level-shifted clock buffer with reduced power consumption and increased operating speed. Summary of the invention

[0009] According to a first aspect of the present disclosure, a level shift buffer is disclosed, which includes: a first transistor, configured to be turned on in response to the assertion of a complementary input signal to discharge a pull-down node coupled to a terminal of the first transistor; a current mirror, configured to charge an internal node in response to the discharge of the current mirror terminal; a first switching transistor, configured to be turned off after the expiration of a delay after the discharge of the output signal, wherein the first switching transistor is coupled between the pull-down node and the current mirror terminal; a second transistor, configured to discharge the internal node in response to the assertion of the input signal to a first power supply voltage, wherein the complementary input signal is a complementary signal of the input signal; and an inverter, configured to invert the voltage of the internal node to form an output signal, wherein the inverter is powered by a second power supply voltage greater than the first power supply voltage.

[0010] According to a second aspect of the present disclosure, a method for level shifting an input signal to form an output signal is disclosed, the method comprising the following actions: conducting an input current for a current mirror in response to assertion of a complementary input signal, wherein the complementary input signal is a complementary signal of the input signal; mirroring the input current through the current mirror to form a mirror current; charging an internal node with the mirror current; discharging the output signal in response to the charging of the internal node; turning off the input current in response to expiration of a delay after the discharge of the output signal; discharging the internal node in response to assertion of the input signal to a first power supply voltage; and asserting the output signal to a second power supply voltage in response to the discharge of the internal node, wherein the second power supply voltage is greater than the first power supply voltage.

[0011] According to a third aspect of the present disclosure, a level shift buffer is disclosed, which includes: a first transistor, which is configured to be turned on in response to the assertion of a complementary input signal to discharge a pull-down node coupled to a terminal of the first transistor; a current mirror, which is configured to charge an internal node in response to the discharge of the current mirror terminal; a second transistor, which is configured to discharge the internal node in response to the assertion of an input signal to a first power supply voltage, wherein the complementary input signal is a complementary signal of the input signal; a first inverter, which is configured to invert the voltage of the internal node to form an output signal, wherein the first inverter is powered by a second power supply voltage greater than the first power supply voltage; and a device for controlling an input current, which is conducted through the first transistor during a delay period, and for shutting off the input current after expiration of the delay period, the delay period starting from the assertion of the complementary input signal.

[0012] These and other advantageous features will be better understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a circuit diagram of a conventional DC-coupled buffer.

[0014] Figure 2 is a circuit diagram of a low power high speed DC coupled buffer according to one aspect of the present disclosure.

[0015] Figure 3 is with Figure 2 Figure 1. A DC-coupled buffer integrated phase-locked loop (PLL).

[0016] Figure 4 is a flow chart of a method for level-shifting an input signal into an output signal according to one aspect of the present disclosure.

[0017] Figure 5 Some example electronic systems each including a DC-coupled buffer according to one aspect of the present disclosure are shown.

[0018] Embodiments of the present disclosure and their advantages will be best understood by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements shown in one or more of the accompanying drawings. DETAILED DESCRIPTION

[0019] A DC coupled buffer is provided, the DC coupled buffer comprising a first pull-down NMOS transistor having a gate driven by an inverted version of an input signal. The input signal and its complementary signal are generated in a first power domain powered by a first power supply voltage, and the DC coupled buffer is generated in a second power domain powered by a second power supply voltage greater than the first power supply voltage. The output signal from the DC coupled buffer will therefore be level shifted relative to the input signal. In order to reduce power consumption and increase operating speed, the drain of the first pull-down transistor is coupled to a current mirror formed by a diode-connected transistor through a first switching transistor, the diode-connected transistor having a gate connected to the gate of the current mirror transistor, so that when both the first pull-down transistor and the first switching transistor are turned on, the current mirror transistor conducts current into an internal node. The inverter inverts the voltage of the internal node to form an output signal.

[0020] The internal node is coupled to ground through a second pull-down transistor having a gate driven by an input signal. After the falling edge of the input signal, when the current mirror charges the internal node, the second pull-down transistor will therefore turn off, causing the inverter to discharge the output signal to ground. A delayed version of the output signal drives the gate of the first switching transistor. Therefore, after the expiration of the delay after the falling edge of the input signal, the first switching transistor will turn off. This prevents the diode-connected transistor from discharging the current after the delay after the falling edge of the input signal, thereby reducing power consumption. In addition, the second switching transistor is connected between the power rail for the second power domain and the gates of the diode-connected transistor and the current mirror transistor. The delayed version of the output signal also drives the gate of the second switching transistor. Therefore, the second switching transistor will be turned on after a delay after the falling edge of the input signal to turn off the current mirror transistor and the diode-connected transistor. Since the current mirror transistor will therefore turn off at the rising edge of the input signal, there will be no conflict with the second pull-down transistor that discharges the internal node, thereby advantageously improving the operating speed of the DC-coupled buffer.

[0021] The following discussion will assume that the DC-coupled buffer is a clock buffer, but it will be appreciated that other types of signals may be buffered and level-shifted by the DC-coupled buffers disclosed herein. The following discussion will also assume that the first supply voltage is the internal supply voltage VDDL and the second supply voltage is the I / O supply voltage VDDH. However, it will be appreciated that the DC-coupled buffers disclosed herein may be used to level-shift between other types of supply voltages. Figure 2 An example DC coupled buffer 200 is shown in FIG. The first pull-down transistor M1, the current mirror terminal 120, the second pull-down transistor M2, the diode-connected transistor P1, the current mirror transistor P2, and the inverters 105 and 115 function as described with respect to the DC coupled buffer 100. After the falling edge for the input clock signal Vin, the complementary input clock signal Vin_b is charged high to VDDL by the inverter 105. The complementary input clock signal Vin_b drives the gate of the first pull-down transistor M1, and the source of the first pull-down transistor M1 is connected to ground. The first pull-down transistor M1 is then turned on to discharge the pull-down node 215 at the drain of the first pull-down transistor M1. The first pull-down transistor M1 may also be referred to herein as simply the first transistor.

[0022] The pull-down node 215 is coupled to the current mirror terminal 120 through the first switch NMOS transistor M3, and the current mirror terminal 120 includes the drain of the transistor P1 connected by a diode in a current mirror configuration with the current mirror transistor P2. The sources of the diode-connected transistor P1 and the current mirror transistor P2 are connected to the power supply node for the I / O power supply voltage VDDH. The delayed version of the output signal (Vout_bb) drives the gate of the first switch transistor M3 so that the first switch transistor M3 will still be turned on at the falling edge of the input clock signal Vin. The discharge of the pull-down node 215 thus discharges the current mirror terminal 120 to cause the diode-connected transistor P1 to conduct the input current of the current mirror to ground through the first switch transistor M3 and the first pull-down transistor M1. Then, the input current for the current mirror is mirrored by the current mirror transistor P2 into a current mirror current, which charges the internal node 110 toward VDDH. The second pull-down transistor M2 is turned off before the rising edge of the input clock signal Vin. The second pull-down transistor M2 is also referred to as the second transistor in this article.

[0023] The charge of the voltage of the internal node 110 is inverted by the inverter 115 to cause the output clock signal Vout to discharge low to ground. The series combination of the inverter 205 and the inverter 210 delays the output clock signal Vout to form a delayed output clock signal Vout_bb. After the expiration of the delay introduced by the series combination of the inverters 205 and 210, the first switch transistor M3 will be turned off after the falling edge of the output signal Vout. In this way, while the input clock signal Vin is low, the input current that continues to discharge to ground through the diode-connected transistor P1 and the first pull-down transistor M1 is cut off. However, due to this delay, there will be a short period after the falling edge of the input clock signal Vin, during which the first pull-down transistor M1 and the first switch transistor are both turned on, so that the current mirror formed by the diode-connected transistor P1 and the current mirror transistor P2 can charge the internal node 110 to force the output clock signal Vout to have a falling edge. Inverters 205 and 210 and first switch transistor M3 may be considered to form means for controlling the input current for the current mirror to be conducted through the first transistor during a delay period and for switching off the input current after expiration of the delay time, the delay period starting from assertion of the complementary input signal.

[0024] The second switch PMOS transistor P3 is connected between the current mirror terminal 120 (the gates of the diode-connected transistor P1 and the current mirror transistor P2) and the power rail for the I / O power supply voltage VDDH. The delayed output clock signal Vout_bb drives the gate of the second switch transistor P3 so that the second switch transistor P3 will be turned on after a delay after the falling edge of the output clock signal Vout. This turning on of the second switch transistor P3 charges the gates of the current mirror transistor P2 and the diode-connected transistor P1 before the rising edge of the input clock signal Vin to turn off the current mirror transistor P2. Therefore, when the second pull-down transistor M2 is turned on in response to the rising edge of the input clock signal Vin, there will be no PMOS transistors that conflict with the second pull-down transistor M2. Therefore, the second pull-down transistor M2 can quickly discharge the internal node 110 to cause a rising edge in the output clock signal Vout. Therefore, the DC-coupled buffer 200 is advantageously low power and high speed.

[0025] The DC-coupled buffer 200 can be used with Figure 3 The phase-locked loop (PLL) 300 shown is integrated. The PLL 300 is located in an internal power domain powered by an internal power supply voltage VDDL. The PLL 300 includes a phase detector 305 that compares the phase of a reference clock signal with a feedback signal from a clock divider 320. Depending on the phase difference between the two signals, the phase detector 305 drives a loop filter 310 that filters the output from the phase detector 305 to drive a voltage controlled oscillator (VCO) 315 with a control voltage signal. The VCO 315 generates an input clock signal Vin that drives the DC-coupled buffer 200. The clock divider 320 divides the input clock signal Vin in frequency to form a feedback signal. The DC-coupled buffer 200 allows the PLL 300 to provide a clock to an external device with an output clock signal Vout in synchronization with the reference clock signal.

[0026] Now about Figure 44 discusses a method of buffering and level shifting an input signal to an output signal. The method includes an action 400 of conducting an input current for a current mirror in response to an assertion of a complementary input signal, wherein the complementary input signal is a complementary signal of the input signal. Conducting an input current through a pull-down transistor M1 in response to a rising edge of the complementary input signal Vin_b is an example of action 400. The method also includes an action of mirroring the input current through a current mirror to form a mirror current. Conducting the mirror current through a current mirror transistor P2 is an example of action 405. In addition, the method includes an action 410 of charging an internal node with a mirror current. The charging of the internal node 110 is an example of action 410. The method also includes an action 415 of discharging the output signal in response to the charging of the internal node. Discharging the output signal Vout in response to the discharge of the internal node 110 is an example of action 415. In addition, the method includes an action 420 of shutting off the input current in response to the expiration of a delay after the discharge of the output signal. Turning off the first switching transistor M3 to stop conducting the input current through the pull-down transistor M1 to ground is an example of action 420. The method also includes an act 425 of discharging the internal node in response to assertion of the input signal to the first supply voltage. Discharging the internal node 110 due to the turning on of the second pull-down transistor M2 is an example of act 425. Finally, the method includes an act 430 of asserting the output signal to a second supply voltage in response to the discharging the internal node, wherein the second supply voltage is greater than the first supply voltage. Charging the output signal Vout to the I / O supply voltage VDDH is an example of act 430.

[0027] The DC-coupled buffers and level shifters disclosed herein may be incorporated into various electronic systems. Figure 5 As shown, a cellular phone 500, a laptop computer 505, and a tablet computer PC 510 may all include memories having a DC-coupled buffer and a level shifter according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers may also be configured with a DC-coupled buffer and a level shifter constructed according to the present disclosure.

[0028] It should be understood that many modifications, substitutions and changes may be made to the materials, devices, configurations and methods of use of the apparatus of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments shown and described herein, as they are only some examples, on the contrary, the scope of the present disclosure should be fully commensurate with the scope of the attached claims and their functional equivalents.

Claims

1. A level shift buffer, comprising: a first transistor configured to turn on in response to assertion of a complementary input signal to discharge a pull-down node coupled to a terminal of the first transistor; a current mirror configured to charge an internal node in response to a discharge of a current mirror terminal; a second transistor configured to discharge the internal node in response to assertion of an input signal to a first supply voltage, wherein the complementary input signal is a complement of the input signal; an inverter configured to invert the voltage of the internal node to form an output signal, wherein the inverter is powered by a second power supply voltage greater than the first power supply voltage; a series of inverters configured to delay the output signal to form a delayed version of the output signal; as well as A first switch transistor is configured to turn off in response to the discharge of the delayed version of the output signal, wherein the first switch transistor is coupled between the pull-down node and the current mirror terminal.

2. The level shift buffer according to claim 1, wherein the current mirror comprises: a diode-connected transistor having a drain and a gate configured to form the current mirror terminal; as well as A current mirror transistor has a gate connected to the current mirror terminal, wherein a drain of the current mirror transistor is coupled to the internal node.

3. The level shift buffer according to claim 2, further comprising: a second switching transistor, wherein the second switching transistor is coupled between a power supply rail and the current mirror terminal, and wherein the second switching transistor is configured to turn on in response to the discharge of the delayed version of the output signal.

4. The level shift buffer of claim 3 , wherein the first transistor, the second transistor, and the first switch transistor are all n-type metal oxide semiconductor (NMOS) transistors, and wherein the diode-connected transistor, the current mirror transistor, and the second switch transistor are all p-type metal oxide semiconductor (PMOS) transistors.

5. The level shift buffer of claim 1, wherein the input signal is an output clock signal from a phase locked loop.

6. The level shift buffer of claim 1, wherein the buffer is incorporated into a cellular telephone.

7. The level shift buffer of claim 1, wherein the input signal is an input clock signal, and wherein the output signal is an output clock signal.

8. A method for level shifting an input signal to form an output signal, comprising: conducting an input current for a current mirror in response to assertion of a complementary input signal, wherein the complementary input signal is a complement of the input signal; mirroring the input current through the current mirror to form a mirror current; charging an internal node with the mirror current; discharging the output signal in response to charging of the internal node; delaying the output signal to form a delayed version of the output signal; shutting off the input current in response to discharging the delayed version of the output signal; discharging the internal node in response to assertion of the input signal to a first supply voltage; as well as In response to the discharge of the internal node, the output signal is asserted to a second supply voltage, wherein the second supply voltage is greater than the first supply voltage.

9. The method according to claim 8, further comprising: The delay is timed by delaying the output signal through a series of inverters to form a delayed output signal.

10. The method according to claim 9, further comprising: A first switching transistor is turned off in response to the discharge of the delayed version of the output signal to turn off the input current.

11. The method according to claim 10, further comprising: A second switching transistor is turned on in response to the discharge of the delayed version of the output signal to shut off the mirror current.

12. The method according to claim 8, further comprising: In a first inverter powered by the first supply voltage, the input signal is inverted to form the complementary input signal.

13. The method according to claim 12, further comprising: In a second inverter powered by the second power supply voltage, the voltage of the internal node is inverted to form the output signal.

14. The method of claim 13, wherein the input signal is an input clock signal, and wherein the output signal is an output clock signal.

15. A level shift buffer, comprising: a first transistor configured to turn on in response to assertion of a complementary input signal to discharge a pull-down node coupled to a terminal of the first transistor; a current mirror configured to charge an internal node in response to a discharge of a current mirror terminal; a second transistor configured to discharge the internal node in response to assertion of an input signal to a first supply voltage, wherein the complementary input signal is a complement of the input signal; a first inverter configured to invert the voltage of the internal node to form an output signal, wherein the first inverter is powered by a second power supply voltage greater than the first power supply voltage; as well as means for controlling an input current for the current mirror to be conducted through the first transistor during a delay period, and for shutting off the input current in response to a discharge of a delayed version of the output signal, wherein the means for controlling the input current comprises a series of inverters configured to delay the output signal by a delay period to form a delayed version of the output signal, the delay period starting from the assertion of the complementary input signal.

16. The level shift buffer of claim 15, wherein the current mirror comprises: a diode-connected transistor having a drain and a gate configured to form the current mirror terminal; as well as A current mirror transistor has a gate connected to the current mirror terminal, wherein a drain of the current mirror transistor is coupled to the internal node.

17. The level shift buffer of claim 15, wherein the apparatus is further configured to charge the current mirror terminal to the second supply voltage in response to the discharge of the delayed version of the output signal.

18. The level shift buffer according to claim 15, further comprising: A second inverter is configured to invert the input signal to form the complementary input signal, wherein the second inverter is powered by the first power supply voltage.

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