Microelectromechanical system device, method for forming the same, and integrated chip

Abstract

Various embodiments of the present disclosure relate to a microelectromechanical system (MEMS) device, a method of forming the same, and an integrated chip. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, wherein the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, wherein opposite sidewalls of the movable mass are disposed between opposite sidewalls of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to a microelectromechanical system device, a method for forming the same, and an integrated chip. Background Art

[0002] A microelectromechanical system (MEMS) device is a microscopic device that integrates mechanical components and electronic components to sense physical quantities and / or act based on the surrounding environment. In recent years, MEMS devices have become increasingly common. For example, the use of MEMS devices as sensing devices (e.g., motion sensing devices, pressure sensing devices, acceleration sensing devices, etc.) has become widespread in many current personal electronic devices (e.g., smart phones, fitness electronic devices, personal computing devices). MEMS devices are also used in other applications, such as vehicle applications (e.g., for accident detection and airbag deployment systems), aerospace applications (e.g., for navigation systems), medical applications (e.g., for patient monitoring), etc. Summary of the Invention

[0003] Embodiments of the present invention provide a microelectromechanical system device, which includes: a first dielectric structure disposed on a first semiconductor substrate, wherein the first dielectric structure at least partially defines a cavity; a second semiconductor substrate disposed on the first dielectric structure and including a movable mass, wherein opposite sidewalls of the movable mass are disposed between opposite sidewalls of the cavity; and a first piezoelectric anti-sticking structure disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-sticking structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.

[0004] Embodiments of the present invention provide an integrated chip, which includes a microelectromechanical system and a biasing circuit system. The biasing circuit system includes: a semiconductor substrate; a movable mass spaced apart from the semiconductor substrate; a cavity at least partially disposed between the semiconductor substrate and the movable mass, wherein opposite sidewalls of the movable mass are disposed between opposite sidewalls of the cavity; and a piezoelectric anti-sticking structure disposed on a surface of the cavity, wherein the piezoelectric anti-sticking structure includes a piezoelectric structure and an electrode. The biasing circuit system is electrically coupled to the electrode, wherein the biasing circuit system is configured to provide a first voltage to the electrode.

[0005] An embodiment of the present invention provides a method for forming a microelectromechanical system device. The method includes: forming a first conductive layer on a lower interlayer dielectric structure, where the lower interlayer dielectric structure is disposed on a semiconductor substrate; forming a second conductive layer on the first conductive layer; forming a piezoelectric layer on the second conductive layer; etching the piezoelectric layer and the second conductive layer to respectively form a piezoelectric structure and an electrode, where the piezoelectric structure is disposed on the electrode; etching the first conductive layer to form a conductive wire; forming an upper interlayer dielectric structure on the lower interlayer dielectric structure, the conductive wire, the electrode, and the piezoelectric structure; forming an opening in the upper interlayer dielectric structure that exposes the piezoelectric structure; and forming a movable mass on the upper interlayer dielectric structure, where the movable mass is formed to have opposing sidewalls disposed between opposing sidewalls of the opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood when read in conjunction with the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views showing some embodiments of a microelectromechanical system (MEMS) device including a piezoelectric anti-stiction structure.

[0008] Figure 2 Showing Figure 1 Cross-sectional views of some other embodiments of the MEMS device shown.

[0009] Figure 3 Showing Figure 1 Cross-sectional views of some other embodiments of the MEMS device shown.

[0010] Figure 4 Showing Figure 1 Cross-sectional views of some other embodiments of the MEMS device shown.

[0011] Figure 5 Showing Figure 1 Cross-sectional views of some more detailed embodiments of the MEMS device shown.

[0012] Figure 6 Showing including Figure 1 Views of some embodiments of a system of some embodiments of the MEMS device shown.

[0013] Figures 7 to 22 Showing for forming Figure 5 Cross-sectional views of a series of some embodiments of the MEMS device shown.

[0014] Figure 23 A flowchart showing some embodiments of a method of forming a MEMS device including a piezoelectric anti - adhesion structure. Detailed Description

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature "on" or "above" a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0017] Many MEMS devices (e.g., accelerometers, gyroscopes, etc.) include a movable mass and a fixed electrode plate. The movable mass has a flat surface that is parallel and spaced apart from the opposing flat surface of the fixed electrode plate. The movable mass is displaced inside a cavity in response to an external stimulus (e.g., pressure, acceleration, gravity, etc.). This displacement changes the distance between the movable mass and the fixed electrode plate. The change in distance can be detected by a change in the capacitive coupling between the movable mass and the fixed electrode and analyzed by an appropriate circuit to derive a measurement of a physical quantity associated with the change in distance, such as acceleration.

[0018] One of the design challenges faced by MEMS devices is to prevent the movable mass from adhering to adjacent components of the MEMS device (an effect known as stiction). As the scale of these devices continues to shrink and the spacing between adjacent surfaces becomes smaller, preventing unintended stiction becomes an increasingly important design consideration. Stiction can occur in several scenarios. During manufacturing, stiction can occur when, for example, the movable mass does not fully detach from its neighboring surface. During normal operation, stiction can also occur when the movable mass deflects to a point where the movable mass contacts an adjacent component (e.g., the surface of a cavity, the surface of a stopper / bump, etc.).

[0019] Various embodiments of the present application relate to a MEMS device having a piezoelectric anti-stiction structure. The MEMS device includes an interlayer dielectric (ILD) structure disposed on a first semiconductor substrate. The upper surface of the ILD structure at least partially defines the bottom of a cavity. A second semiconductor substrate is disposed on the ILD structure and includes a movable mass. The movable mass is configured to be displaced within the cavity in response to an external stimulus. The piezoelectric anti-stiction structure includes a piezoelectric structure and an electrode. In addition, the piezoelectric anti-stiction structure is disposed between the movable mass and the upper surface of the ILD structure. Since the piezoelectric anti-stiction structure is disposed between the movable mass and the upper surface of the ILD structure, the piezoelectric anti-stiction structure can prevent / correct stiction.

[0020] For example, if the movable mass deflects towards the bottom of the cavity beyond a given point, the piezoelectric anti-stiction structure will prevent the movable mass from contacting the bottom of the cavity and potentially adhering to the upper surface of the ILD structure. Thus, if the movable mass adheres to an adjacent component, the movable mass will adhere to the piezoelectric anti-stiction structure. If the movable mass adheres to the piezoelectric anti-stiction structure, a voltage sufficient to deform (or vibrate) the piezoelectric structure can be applied to the electrode, thereby generating a mechanical force that can release the movable mass from its adhered state on the piezoelectric anti-stiction structure.

[0021] Another example of a piezoelectric anti-sticking structure for preventing / correcting adhesion may include a movable mass having a first doping type. In such an embodiment, a first voltage is applied to the electrode, and a second voltage is applied to the movable mass. Accordingly, the voltage across the piezoelectric structure will vary based on the distance of the movable mass from the electrode. Thus, if the movable mass deflects towards the bottom of the cavity beyond a given point (e.g., touches the piezoelectric anti-sticking structure), the distance between the movable mass and the electrode will cause the voltage across the piezoelectric anti-sticking structure to be sufficient to deform the piezoelectric structure, thereby generating a mechanical force that can release the movable mass from its adhered state on the piezoelectric anti-sticking structure.

[0022] Figure 1 A cross-sectional view showing some embodiments of a microelectromechanical system (MEMS) device 100 including a piezoelectric anti-sticking structure is presented. The MEMS device 100 can be, for example, an accelerometer, a gyroscope, or some other MEMS device.

[0023] As Figure 1 shown, the MEMS device 100 includes a first semiconductor substrate 102. The first semiconductor substrate 102 can include any type of semiconductor body (e.g., a single-crystalline silicon / complementary metal-oxide-semiconductor (CMOS) block, silicon-germanium (SiGe), silicon on insulator (SOI), etc.). In some embodiments, one or more semiconductor devices 104 may be provided on / in the first semiconductor substrate 102. In other embodiments, the semiconductor device 104 can be or can include, for example, a metal-oxide-semiconductor (MOS) field-effect transistor (FET), some other MOS device, or some other semiconductor device. In still other embodiments, the first semiconductor substrate 102 can be referred to as a complementary metal-oxide-semiconductor (CMOS) substrate.

[0024] An interlayer dielectric (ILD) structure 106 is disposed over a first semiconductor substrate 102 and a semiconductor device 104. An interconnect structure 108 (e.g., a copper interconnect) is embedded in the ILD structure 106. The interconnect structure 108 includes a plurality of conductive features (e.g., metal lines, metal vias, metal contacts, etc.). In some embodiments, the ILD structure 106 includes one or more stacked ILD layers, which may respectively include a low dielectric constant dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., SiO2), etc. In other embodiments, the ILD structure 106 includes a lower ILD structure 110 and an upper ILD structure 112 disposed over the lower ILD structure 110. In still other embodiments, the plurality of conductive features may include, for example, copper (Cu), aluminum (Al), tungsten (W), titanium nitride (TiN), aluminum-copper (AlCu), some other conductive material, or a combination of the above.

[0025] A second semiconductor substrate 114 is disposed over both the ILD structure 106 and the first semiconductor substrate 102. The second semiconductor substrate 114 may include any type of semiconductor body (e.g., a single crystal silicon / CMOS block, SiGe, SOI, etc.). In some embodiments, the second semiconductor substrate 114 may have a first doping type (e.g., p-type / n-type). In other embodiments, the second semiconductor substrate 114 may be referred to as a MEMS substrate. In still other embodiments, a third semiconductor substrate 116 is disposed over both the second semiconductor substrate 114 and the first semiconductor substrate 102. The third semiconductor substrate 116 may include any type of semiconductor body (e.g., a single crystal silicon / CMOS block, SiGe, SOI, etc.). In still other embodiments, the third semiconductor substrate 116 may be referred to as a cap substrate.

[0026] The ILD structure 106 at least partially defines a cavity 118. In some embodiments, the upper ILD structure 112, the interconnect structure 108, the second semiconductor substrate 114, and the third semiconductor substrate 116 define the cavity 118. In other embodiments, an upper conductive wire 120 of the interconnect structure 108 may at least partially define the cavity 118. For example, the upper conductive wire 120 and the upper surface of the upper ILD structure 112 may define the bottom surface of the cavity 118, and the bottom surface of the third semiconductor substrate 116 may define the upper surface of the cavity 118. In other embodiments, the upper conductive wire 120 of the interconnect structure 108 may be the uppermost conductive wire (e.g., the uppermost metal line) of the interconnect structure 108. In still other embodiments, the third semiconductor substrate 116 at least partially defines an upper portion of the cavity 118, and the upper ILD structure 112 at least partially defines a lower portion of the cavity 118.

[0027] The second semiconductor substrate 114 includes a movable mass 122 (e.g., a proof mass). The movable mass 122 is part of the second semiconductor substrate 114 and is suspended in the cavity 118 by one or more tethers (not shown). In some embodiments, the movable mass 122 has a first doping type (e.g., p-type) or a second doping type (e.g., n-type) opposite to the first doping type. In other embodiments, the movable mass 122 may have a first doping concentration of a first doping type dopant (e.g., p-type dopant) greater than or equal to about 1×10 20 cm -3 or a second doping concentration of a second doping type dopant (e.g., n-type dopant) greater than or equal to about 1×10 20 cm -3 . In still other embodiments, opposite sidewalls of the movable mass 122 are disposed between opposite sidewalls of the upper ILD structure 112.

[0028] A plurality of piezoelectric anti-stiction structures 124 (the first piezoelectric anti-stiction structure 124a, the second piezoelectric anti-stiction structure 124b, the third piezoelectric anti-stiction structure 124c, and the fourth piezoelectric anti-stiction structure 124d in this text are collectively referred to as the piezoelectric anti-stiction structures 124) are disposed in the cavity 118. For example, the first piezoelectric anti-stiction structure 124a and the second piezoelectric anti-stiction structure 124b are disposed in the cavity 118 and the first piezoelectric anti-stiction structure 124a is spaced apart from the second piezoelectric anti-stiction structure 124b. In some embodiments, the piezoelectric anti-stiction structures 124 are disposed between the upper surface of the upper ILD structure 112 and the movable mass 122. It should be understood that in some embodiments, only a single piezoelectric anti-stiction structure may be disposed in the cavity 118.

[0029] For clarity, the features of the piezoelectric anti-stiction structures 124 may be described with reference to only one of the piezoelectric anti-stiction structures 124 (e.g., the first piezoelectric anti-stiction structure 124a), and it should be understood that each of the plurality of piezoelectric anti-stiction structures 124 may also include such features. For example, the first piezoelectric anti-stiction structure 124a includes a first electrode 126a. Thus, it should be understood that the second piezoelectric anti-stiction structure 124b may include a second electrode 126b (and any other piezoelectric anti-stiction structure may also include an electrode).

[0030] The first piezoelectric anti-adhesion structure 124a includes a first piezoelectric structure 128a disposed on the first electrode 126a. In some embodiments, a first conductive structure 130a is disposed on the first piezoelectric structure 128a. In other embodiments, the first electrode 126a is electrically coupled to one or more of the semiconductor devices 104 through the interconnect structure 108. In other embodiments, the first electrode 126a is electrically coupled to the upper conductive line 120.

[0031] The first electrode 126a may include, for example, platinum (Pt), titanium (Ti), copper (Cu), gold (Au), aluminum (Al), zinc (Zn), tin (Sn), some other conductive materials, or a combination of the foregoing. In some embodiments, the first piezoelectric structure 128a may include, for example, lead zirconate titanate (PZT), zinc oxide (ZnO), barium titanate (BaTiO3), potassium niobate (KNbO3), sodium-tungsten-oxide (Na2WO3), barium-sodium-niobium-oxide (Ba2NaNb5O5), lead-potassium-niobium-oxide (Pb2KNb5O 15 )), langasite (La3Ga5SiO 14 )), gallium phosphate (GaPO4), lithium-niobium-oxide (LiNbO3), lithium tantalate (LiTaO3), some other piezoelectric materials, or a combination of the foregoing. The first conductive structure 130a may include, for example, Pt, Ti, Cu, Au, Al, Zn, Sn, some other conductive materials, or a combination of the foregoing. In some embodiments, the first electrode 126a and the first conductive structure 130a include the same material (e.g., Pt). In other embodiments, the first electrode 126a may include a material different from that of the first conductive structure 130a. In other embodiments, the upper conductive line 120 may be a multi-layered structure including a first layer (e.g., TiN), a second layer (e.g., AlCu) disposed on and over the first layer, and a third layer (e.g., TiN) disposed on and over the second layer.

[0032] The first electrode 126a is configured to receive a first voltage. In some embodiments, the first voltage is less than or equal to about 25 volts (V). More specifically, the first voltage can be between about 15 V and about 25 V. In some embodiments, the first conductive structure 130a is configured to be electrically floating (e.g., having a floating voltage). In other embodiments, the first conductive structure 130a is configured to receive a second voltage. In some embodiments, the second voltage can be less than or equal to about 5 V. In still other embodiments, the movable mass 122 is configured to receive a third voltage. The third voltage can be less than or equal to about 5 V.

[0033] Since the piezoelectric anti-stiction structure 124 is disposed between the upper ILD structure 112 and the movable mass 122, the piezoelectric anti-stiction structure 124 can prevent / correct stiction. For example, if the movable mass 122 adheres to the first piezoelectric anti-stiction structure 124a, a first voltage can be provided to the first electrode 126a. By providing the first voltage to the first electrode 126a, the first piezoelectric structure 128a can be deformed (or vibrated) from a first shape to a second shape different from the first shape due to the voltage across the first piezoelectric structure 128a, thereby generating a mechanical force sufficient to correct (or prevent) the seized state (e.g., the movable mass 122 adhering to the first piezoelectric anti-stiction structure 124a).

[0034] Figure 2 Shown Figure 1 A cross-sectional view of some other embodiments of the MEMS device 100 shown.

[0035] As Figure 2 As shown, the piezoelectric anti-stiction structure 124 can include dielectric structures 202 (the first dielectric structure 202a, the second dielectric structure 202b, the third dielectric structure 202c, and the fourth dielectric structure 202d in this text are collectively referred to as the dielectric structure 202) respectively disposed on the piezoelectric structures 128 (the first piezoelectric structure 128a, the second piezoelectric structure 128b, the third piezoelectric structure 128c, and the fourth piezoelectric structure 128d in this text are collectively referred to as the piezoelectric structure 128). For example, the first piezoelectric anti-stiction structure 124a can include the first dielectric structure 202a disposed on the first piezoelectric structure 128a, and the second piezoelectric anti-stiction structure 124b can include the second dielectric structure 202b disposed on the second piezoelectric structure 128b. The first dielectric structure 202a is separated from the upper ILD structure 112 by both the first piezoelectric structure 128a and the first electrode 126a. In some embodiments, the first dielectric structure 202a can comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., silicon nitride (SiN)), an oxynitride (e.g., silicon oxynitride (SiO X N Y), some other dielectric materials, or combinations of the above.

[0036] In embodiments where the piezoelectric anti-stiction structure 124 includes the dielectric structure 202 respectively, the movable mass 122 may have a first doping type and a first doping concentration, or a second doping type and a second doping concentration. In such embodiments, the piezoelectric anti-stiction structure 124 may prevent / correct stiction by applying a third voltage to the movable mass 122 and a first voltage to the first electrode 126a. In some embodiments, the third voltage and the first voltage may be applied regardless of whether the movable mass 122 is in a fixed state (e.g., unable to move freely) or in a movable state (e.g., normal operating state). By applying a first voltage to the first electrode 126a and a third voltage to the movable mass 122, the voltage across the first piezoelectric structure 128a will vary based on the distance between the movable mass 122 and the first electrode 126a. Therefore, if the movable mass 122 deflects towards the first piezoelectric anti-stiction structure 124a beyond a given point (e.g., contacts / adheres to the first dielectric structure 202a), the voltage across the first piezoelectric structure 128a may be sufficient to cause the first piezoelectric structure 128a to deform, thereby generating a mechanical force sufficient to correct (or prevent) the fixed state. In other embodiments, the first doping concentration and / or the second doping concentration may be such that the voltage across the first piezoelectric structure 128a is not sufficient to deform the first piezoelectric structure 128a unless the movable mass 122 contacts / adheres to the first dielectric structure 202a.

[0037] Figure 3 Shown Figure 1 A cross-sectional view of some other embodiments of the MEMS device 100 shown.

[0038] As Figure 3 As shown, the piezoelectric anti-stiction structure 124 may be disposed between the movable mass 122 and the third semiconductor substrate 116. For example, a third piezoelectric anti-stiction structure 124c and a fourth piezoelectric anti-stiction structure 124d are disposed in the cavity 118 and between the bottom surface of the movable mass 122 and the third semiconductor substrate 116. Since the third piezoelectric anti-stiction structure 124c is disposed between the movable mass 122 and the third semiconductor substrate 116, the third piezoelectric anti-stiction structure 124c may prevent / correct the stiction of the movable mass 122 adhering to the surface (e.g., the bottom surface of the third semiconductor substrate 116) disposed above the movable mass 122. In some embodiments, the piezoelectric anti-stiction structure 124 disposed between the movable mass 122 and the third semiconductor substrate 116 may be referred to as a piezoelectric anti-stiction stopper. In other embodiments, the piezoelectric anti-stiction structure 124 disposed between the movable mass 122 and the upper ILD structure 112 may be referred to as a piezoelectric anti-stiction bump.

[0039] In some embodiments, the third piezoelectric anti-sticking structure 124c includes a third dielectric structure 202c disposed on the third piezoelectric structure 128c. The third dielectric structure 202c separates both the third piezoelectric structure 128c and the third electrode 126c from the movable mass 122. In other embodiments, the third electrode 126c can contact both the third semiconductor substrate 116 and the third piezoelectric structure 128c.

[0040] In some embodiments, the piezoelectric anti-sticking structures 124 disposed above the movable mass 122 can be aligned vertically with the piezoelectric anti-sticking structures 124 disposed below the movable mass 122, respectively. For example, the third piezoelectric anti-sticking structure 124c can be aligned vertically with the first piezoelectric anti-sticking structure 124a. In other embodiments, the piezoelectric anti-sticking structures 124 disposed above the movable mass 122 may not be aligned respectively with the piezoelectric anti-sticking structures 124 disposed below the movable mass 122. For example, the third piezoelectric anti-sticking structure 124c can be spaced apart from the sidewall of the upper ILD structure 112 by a first lateral distance, and the first piezoelectric anti-sticking structure 124a can be spaced apart from the sidewall of the upper ILD structure 112 by a second lateral distance different from the first lateral distance.

[0041] Figure 4 Shown Figure 1 A cross-sectional view of some other embodiments of the MEMS device 100 shown.

[0042] As Figure 4 shown, some of the piezoelectric anti-sticking structures 124 in the piezoelectric anti-sticking structures 124 can include dielectric structures 202, and some other piezoelectric anti-sticking structures 124 in the piezoelectric anti-sticking structures 124 can include conductive structures 130 (the first conductive structure 130a, the second conductive structure 130b, the third conductive structure 130c, and the fourth conductive structure 130d herein are collectively referred to as the conductive structure 130). For example, the first piezoelectric anti-sticking structure 124a can include the first conductive structure 130a, and the third piezoelectric anti-sticking structure 124c can include the third dielectric structure 202c.

[0043] In some embodiments, the layout of the first piezoelectric anti-sticking structure 124a may be generally square-shaped, rectangular-shaped, or similar. In some embodiments, the sidewalls of the first piezoelectric anti-sticking structure 124a may be substantially vertical. In other embodiments, the sidewalls of the first piezoelectric anti-sticking structure 124a may form an angle (e.g., angled inward when the sidewalls of the first piezoelectric anti-sticking structure 124a extend from the upper surface of the upper ILD structure 112). In still other embodiments, the sidewalls of the first electrode 126a may be substantially aligned with the sidewalls of the first piezoelectric structure 128a. The sidewalls of the first piezoelectric structure 128a may be substantially aligned with the sidewalls of the first conductive structure 130a. In yet other embodiments, the sidewalls of the third piezoelectric structure 128c may be substantially aligned with the sidewalls of the third dielectric structure 202c.

[0044] The upper surface of the upper ILD structure 112 (e.g., the bottom of the cavity 118) is spaced apart from the uppermost surface of the upper ILD structure 112 by a first distance D1 in the vertical direction. The first piezoelectric anti-sticking structure 124a has a first height H1. In some embodiments, the first height H1 is between about 30% and about 50% of the first distance D1. In other embodiments, the first distance D1 is less than or equal to about 3 micrometers (μm). More specifically, the first distance D1 may be between about 2 μm and 3 μm. In still other embodiments, the first height H1 is less than or equal to about 1.5 μm. More specifically, the first height H1 is about 1 μm.

[0045] The bottom surface of the third semiconductor substrate 116 (e.g., the top of the cavity 118) is spaced apart from the lowermost surface of the third semiconductor substrate 116 by a second distance D2 in the vertical direction. The third piezoelectric anti-sticking structure 124c has a second height H2. In some embodiments, the second height H2 is between about 30% and about 50% of the second distance D2. The second distance D2 may be less than or equal to about 3 μm. More specifically, the second distance D2 may be between about 2 μm and 3 μm. The second height H2 may be less than or equal to about 1.5 μm. More specifically, the second height H2 may be about 1 μm.

[0046] In some embodiments, the first height H1 may be substantially the same as the second height H2. In other embodiments, the first height H1 may be different from the second height H2. In still other embodiments, the first distance D1 may be substantially the same as the second distance D2. In other embodiments, the first distance D1 may be different from the second distance D2.

[0047] In some embodiments, the length (and / or width) of each piezoelectric anti - adhesion structure 124 may be substantially the same. In other embodiments, the length (and / or width) of some of the piezoelectric anti - adhesion structures 124 may be different from the length (and / or width) of some other piezoelectric anti - adhesion structures 124 among the piezoelectric anti - adhesion structures 124. In still other embodiments, the length of the first piezoelectric anti - adhesion structure 124a may be between about 15% and about 50% of the first distance D1. More specifically, the length of the first piezoelectric anti - adhesion structure 124a may be between about 0.5 μm and about 1 μm. In yet other embodiments, the width of the first piezoelectric anti - adhesion structure 124a may be between about 15% and about 50% of the first distance D1. More specifically, the width of the first piezoelectric anti - adhesion structure 124a may be between about 0.5 μm and about 1 μm.

[0048] In some embodiments, the length of the third piezoelectric anti - adhesion structure 124c may be between about 15% and about 50% of the second distance D2. More specifically, the length of the third piezoelectric anti - adhesion structure 124c may be between about 0.5 μm and about 1 μm. In other embodiments, the width of the third piezoelectric anti - adhesion structure 124c may be between about 15% and about 50% of the second distance D2. More specifically, the width of the third piezoelectric anti - adhesion structure 124c may be between about 0.5 μm and about 1 μm.

[0049] Figure 5 Shown Figure 1 A cross - sectional view of some more detailed embodiments of the MEMS device 100 shown.

[0050] As Figure 5 As shown, upper conductive vias 502 (e.g., metal vias) are provided in the upper ILD structure 112. In some embodiments, the upper conductive vias 502 are provided in both the upper ILD structure 112 and the lower ILD structure 110. The upper conductive vias 502 are electrically coupled to the interconnect structure 108 and the second semiconductor substrate 114. In other embodiments, the upper conductive vias 502 may comprise, for example, Cu, Al, W, or the like.

[0051] The first conductive channel 504 is disposed in the second semiconductor substrate 114 and provides an electrical connection between the upper conductive via 502 and the movable mass 122. The first conductive channel 504 is part of the second semiconductor substrate 114 having a first doping type or a second doping type. In some embodiments, a third voltage can be applied to the movable mass 122 through the interconnect structure 108, the upper conductive via 502, and the first conductive channel 504. In other embodiments, since the movable mass 122 has the same doping type as the first conductive channel 504, a third voltage can be applied to the movable mass 122. In other embodiments, the first conductive channel 504 can extend from a fixed portion of the second semiconductor substrate 114 along one or more of the tethers (not shown) to a region of the movable mass 122 having a first doping type or a second doping type. In still other embodiments, the first conductive channel 504 can be referred to as a first doped region.

[0052] In some embodiments, the third semiconductor substrate 116 is bonded to the second semiconductor substrate 114 by a bonding structure 506 (e.g., a eutectic bond structure). The bonding structure 506 can include an upper bonding ring 508 disposed on a lower bonding ring 510. In some embodiments, the bonding structure 506 is conductive. In other embodiments, the lower bonding ring 510 can include, for example, Cu, Al, Au, Sn, Ti, some other bonding material, or a combination thereof. In other embodiments, the upper bonding ring 508 can include, for example, Cu, Al, Au, Sn, Ge, some other bonding material, or a combination thereof. The upper bonding ring 508 can have a top layout with an annular shape that continuously extends around the movable mass 122. In still other embodiments, the lower bonding ring 510 can have a top layout with an annular shape that continuously extends around the movable mass 122.

[0053] Through-substrate vias (TSVs) 512 are disposed in the second semiconductor substrate 114, the upper ILD structure 112, and the lower ILD structure 110. In some embodiments, the TSVs 512 are disposed above the lower ILD structure 110. The TSVs 512 extend completely through the second semiconductor substrate 114 to electrically couple the interconnect structure 108 to the bonding structure 506. In other embodiments, the TSVs 512 extend through an isolation structure 514 (e.g., a shallow trench isolation (STI) structure) disposed in the second semiconductor substrate 114. In still other embodiments, the TSVs 512 can include, for example, Cu, Al, W, or the like.

[0054] The second conductive channel 516 is disposed in the third semiconductor substrate 116 and provides an electrical connection between the bonding structure 506 and the fourth electrode 126d. The second conductive channel 516 is part of the third semiconductor substrate 116 having a first doping type or a second doping type. In some embodiments, a first voltage can be applied to the fourth electrode 126d through the interconnect structure 108, the TSV 512, the bonding structure 506, and the second conductive channel 516. In other embodiments, the second conductive channel 516 can be referred to as a second doped region.

[0055] The third conductive channel 518 is disposed in the third semiconductor substrate 116 and provides an electrical connection between the bonding structure 506 and the third electrode 126c. The third conductive channel 518 is part of the third semiconductor substrate 116 having a first doping type or a second doping type. In some embodiments, a first voltage can be applied to the third electrode 126c through the interconnect structure 108, the TSV 512 (or another TSV), the bonding structure 506, and the third conductive channel 518. In other embodiments, the third conductive channel 518 can be referred to as a third doped region.

[0056] Figure 6 Shows including Figure 1 Views of some embodiments of a system 600 of some embodiments of the illustrated MEMS device 100.

[0057] As Figure 6 As shown, the system 600 includes a MEMS device 100 and a biasing circuitry 602. The biasing circuitry 602 is electrically coupled to the MEMS device 100. The biasing circuitry 602 is configured to provide one or more biasing signals 606 (the first biasing signal 606a and the second biasing signal 606b herein are collectively referred to as biasing signals 606) to the MEMS device 100 to prevent / correct stiction of the movable mass 122 of the MEMS device 100 (see, for example, Figure 5 ). For example, the biasing circuitry 602 can provide a first biasing signal 606a having a first voltage to the electrodes 126 of the piezoelectric anti-stiction structure 124, and the biasing circuitry 602 can provide a second biasing signal 606b having a third voltage to the movable mass 122.

[0058] In some embodiments, during operation of the MEMS device 100, the biasing circuitry 602 may continuously provide the one or more biasing signals 606 to the MEMS device 100. In other embodiments, the biasing circuitry 602 may selectively provide the one or more biasing signals 606 to the MEMS device 100. In yet other embodiments, the biasing circuitry 602 may selectively provide the one or more biasing signals 606 to the electrodes 126 of the piezoelectric anti-stiction structure 124. For example, in some embodiments, the biasing circuitry 602 may provide only the first biasing signal 606a to the first electrode 126a.

[0059] In some embodiments, the system 600 includes measurement circuitry 604 electrically coupled to the MEMS device 100. In yet other embodiments, the measurement circuitry 604 is electrically coupled to the biasing circuitry 602. The measurement circuitry 604 is configured to determine whether the MEMS device 100 is in a movable state (e.g., the movable mass 122 is free to move around the cavity 118) or a fixed state (e.g., the movable mass 122 is not free to move around the cavity 118). For example, the measurement circuitry 604 may provide one or more analysis signals 608 (the first analysis signal 608a and the second analysis signal 608b herein are collectively referred to as the analysis signals 608) to the MEMS device 100. The measurement circuitry 604 receives one or more response signals 610 (the first response signal 610a and the second response signal 610b herein are collectively referred to as the response signals 610) corresponding to the one or more analysis signals 608. For example, the measurement circuitry 604 may provide the first analysis signal 608a and the second analysis signal 608b and receive the first response signal 610a and the second response signal 610b, respectively. The measurement circuitry analyzes the one or more response signals 610 to determine whether the movable mass 122 is in a movable state or a fixed state (e.g., analyzes the voltage to determine the position of the movable mass 122 relative to one or more fixed electrodes in the cavity 118).

[0060] The measurement circuitry 604 can determine whether the MEMS device 100 is in a first fixed state or a second fixed state. The first fixed state can be referred to as a touch-down state and occurs when the movable mass 122 contacts / attaches to the first piezoelectric anti-stiction structure 124a and the second piezoelectric anti-stiction structure 124b. The second fixed state can be referred to as a tilt state and occurs when the movable mass 122 contacts / attaches to the first piezoelectric anti-stiction structure 124a but does not contact / attach to the second piezoelectric anti-stiction structure 124b, or vice versa. In some embodiments, when both the first response signal 610a and the second response signal 610b indicate that the movable mass 122 is attached to both the first piezoelectric anti-stiction structure 124a and the second piezoelectric anti-stiction structure 124b, the measurement circuitry 604 can determine that the movable mass 122 is in the first fixed state. In other embodiments, when the first response signal 610a indicates that the movable mass 122 is attached to the first piezoelectric anti-stiction structure 124a and the second response signal 610b indicates that the movable mass 122 is not attached to the second piezoelectric anti-stiction structure 124b, the measurement circuitry 604 can determine that the movable mass 122 is in the second fixed state.

[0061] In some embodiments, the measurement circuitry 604 can provide one or more status indication signals 612 (the first status indication signal 612a and the second status indication signal 612b herein are collectively referred to as the status indication signals 612) based on the state of the MEMS device 100 to the bias circuitry 602. Based on the one or more status indication signals 612, the bias circuitry 602 can (or may not) provide the one or more bias signals 606 to the MEMS device 100. For example, the measurement circuitry 604 can provide one or more status indication signals 612 indicating that the MEMS device is in a movable state, and the bias circuitry 602 may not provide any of the one or more bias signals 606 to the MEMS device 100. In other embodiments, during operation of the MEMS device 100, the bias circuitry 602 continuously provides the one or more bias signals 606 to the MEMS device 100.

[0062] In some embodiments, the measurement circuitry 604 may provide a first status indication signal 612a and a second status indication signal 612b to the biasing circuitry 602 to indicate that the MEMS device 100 is in a first fixed state, and the biasing circuitry 602 may provide the one or more biasing signals 606 to the MEMS device 100. In such an embodiment, the one or more biasing signals 606 may be provided to one or more of the electrodes 126 of the piezoelectric anti-stiction structure 124. In other embodiments, the measurement circuitry 604 may provide a first status indication signal 612a and a second status indication signal 612b to the biasing circuitry 602 to indicate that the MEMS device 100 is in a second fixed state. For example, the first status indication signal 612a may indicate that the movable mass 122 is adhered to the first piezoelectric anti-stiction structure 124a, and the second status indication signal 612b may indicate that the movable mass 122 is not adhered to the second piezoelectric anti-stiction structure 124b. In such an embodiment, the biasing circuitry 602 may provide corresponding one or more biasing signals 606 to the MEMS device 100. For example, the biasing circuitry 602 may provide a first biasing signal 606a to the first electrode 126a to deform the first piezoelectric structure 128a. In other such embodiments, the biasing circuitry 602 may provide the one or more biasing signals 606 to the MEMS device 100. For example, the biasing circuitry 602 may provide a first biasing signal 606a to the first electrode 126a to deform the first piezoelectric structure 128a, and a second biasing signal 606b to the second electrode 126b to deform the second piezoelectric structure 128b.

[0063] In some embodiments, an integrated chip (IC) includes the system 600. In other embodiments, a first integrated chip may include the MEMS device 100, and a second integrated chip different from the first integrated chip may include the biasing circuitry 602 and / or the measurement circuitry 604. In still other embodiments, a first integrated chip may include the MEMS device 100, a second integrated chip may include the biasing circuitry 602, and a third integrated chip different from the first integrated chip and the second integrated chip may include the measurement circuitry 604. In some embodiments, the biasing circuitry 602 includes one or more of the one or more semiconductor devices 104 (see, e.g., Figure 5 ). In other embodiments, the measurement circuitry 604 includes one or more of the one or more semiconductor devices 104. In still other embodiments, the biasing circuitry 602 and the measurement circuitry 604 may be disposed on / above the same semiconductor substrate (e.g., the first semiconductor substrate 102).

[0064] Figures 7 to 22 Shown for formingFigure 5 A series of cross-sectional views of some embodiments of the MEMS device 100 shown.

[0065] As Figure 7 shown, a portion of the interconnect structure 108 is disposed in the lower ILD structure 110 and above the first semiconductor substrate 102. In addition, one or more semiconductor devices 104 are disposed on / in the first semiconductor substrate 102. In some embodiments, the method of forming the structure shown in Figure 7 includes forming the one or more semiconductor devices 104 by the following processes: forming pairs of source / drain regions in the first semiconductor substrate 102 (e.g., formed by ion implantation); thereafter, forming a gate dielectric and a gate electrode above the first semiconductor substrate and between the pairs of source / drain regions (e.g., formed by deposition / growth processes and etching processes). Then a first ILD layer is formed above the one or more semiconductor devices 104, and contact openings are formed in the first ILD layer. Conductive material (e.g., W) is formed on the first ILD layer and in the contact openings. Thereafter, a planarization process (e.g., chemical-mechanical polishing (CMP)) is performed on the conductive material to form conductive contacts (e.g., metal contacts) in the first ILD layer.

[0066] Next, a second ILD layer is formed over the first ILD layer and the conductive contact, and a first conductive wire trench is formed in the second ILD layer. A conductive material (e.g., Cu) is formed over the second ILD layer and in the first conductive wire trench. Thereafter, a planarization process (e.g., CMP) is performed on the conductive material to form a conductive wire (e.g., a metal wire) in the second ILD layer. Next, a third ILD layer is formed over the second ILD layer and the conductive wire, and a conductive via opening is formed in the third ILD layer. A conductive material (e.g., Cu) is formed over the third ILD layer and in the conductive via opening. Thereafter, a planarization process (e.g., CMP) is performed on the conductive material to form a conductive via (e.g., a metal via) in the third ILD layer. The above processes for forming the conductive wire and the conductive via can be repeated any number of times. In some embodiments, the above layers and / or structures can be formed using, for example, the following deposition or growth processes: such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, sputtering, electrochemical plating, electroless plating, some other deposition or growth processes, or a combination of the above.

[0067] As Figure 8 shown, a first conductive layer 802 is formed over the lower ILD structure 110 and the portion of the interconnect structure 108. In some embodiments, the process of forming the first conductive layer 802 includes depositing the first conductive layer 802 over the lower ILD structure 110 and the portion of the interconnect structure 108. The first conductive layer 802 can be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition processes, or a combination of the above. In other embodiments, the first conductive layer 802 can include, for example, Cu, Al, TiN, AlCu, some other conductive materials, or a combination of the above.

[0068] In some embodiments, the first conductive layer 802 includes multiple layers. For example, the first conductive layer can include a first layer (e.g., TiN), a second layer (e.g., AlCu) disposed over and on the first layer, and a third layer (e.g., TiN) disposed over and on the second layer. In such embodiments, the process of forming the first conductive layer 802 can include depositing the first layer over the lower ILD structure 110 and the portion of the interconnect structure 108, depositing the second layer on the first layer, and depositing the third layer on the second layer.

[0069] As shown Figure 9 in Figure 9 , a second conductive layer 902 is formed over the first conductive layer 802. In some embodiments, the process of forming the second conductive layer 902 includes depositing the second conductive layer 902 over the first conductive layer 802. The second conductive layer 902 can be deposited by, for example, CVD, PVD, ALD, sputtering, electroplating, electroless plating, some other deposition process, or a combination of the above. In other embodiments, the second conductive layer 902 can include, for example, Pt, Ti, Cu, Au, Al, Zn, Sn, Ru, some other conductive material, or a combination of the above.

[0070] Figure 9 Also shown in

[0070] , a first piezoelectric layer 904 is formed over the second conductive layer 902. In some embodiments, the process of forming the first piezoelectric layer 904 includes depositing the first piezoelectric layer 904 over the second conductive layer 902. The first piezoelectric layer 904 can be deposited or grown by, for example, sputtering, spin-on process, CVD, PVD, ALD, molecular-beam epitaxy, some other deposition or growth process, or a combination of the above. In other embodiments, the first piezoelectric layer 904 can include, for example, PZT, ZnO, BaTiO3, KNbO3, Na2WO3, Ba2NaNb5O5, Pb2KNb5O 15 , La3Ga5SiO 14 , GaPO4, LiNbO3, LiTaO3, some other piezoelectric material, or a combination of the above.

[0071] Figure 9 Also shown in

[0071] , a third conductive layer 906 is formed over the first piezoelectric layer 904. In some embodiments, the process of forming the third conductive layer 906 includes depositing the third conductive layer 906 over the first piezoelectric layer 904. The third conductive layer 906 can be deposited by, for example, CVD, PVD, ALD, sputtering, electroplating, electroless plating, some other deposition process, or a combination of the above. In other embodiments, the third conductive layer 906 can include, for example, Pt, Ti, Cu, Au, Al, Zn, Sn, Ru, some other conductive material, or a combination of the above. In embodiments where the dielectric structure 202 is disposed over the piezoelectric structure 128 respectively, the third conductive layer 906 may not be formed over the first piezoelectric layer 904.

[0072] As shown Figure 10 in

[0072] , a first plurality of piezoelectric anti-sticking structures 124 are formed over the first conductive layer 802. In some embodiments, the process of forming the piezoelectric anti-sticking structures 124 includes depositing over the third conductive layer 906 (see, for example, Figure 9) A mask layer (not shown) (e.g., positive / negative photoresist) is formed thereon. Thereafter, the third conductive layer 906, the first piezoelectric layer 904, and the second conductive layer 902 (see, for example Figure 9 ) are exposed to an etchant (e.g., wet / dry etchant). The etchant removes the unmasked portions of the third conductive layer 906, thereby forming a plurality of conductive structures 130 on the first piezoelectric layer 904; the etchant removes the unmasked portions of the first piezoelectric layer 904, thereby forming a plurality of piezoelectric structures 128 on the second conductive layer 902; and the etchant removes the unmasked portions of the second conductive layer 902, thereby forming a plurality of electrodes 126 on the first conductive layer 802. Subsequently, the mask layer can be stripped. It should be understood that one or more etchants and / or mask layers can be utilized to form the piezoelectric anti-sticking structure 124.

[0073] As Figure 11 shown, an upper conductive wire 120 of the interconnect structure 108 is formed. In some embodiments, the process of forming the upper conductive wire 120 includes forming a mask layer (not shown) on the first conductive layer 802, and the mask layer covers the piezoelectric anti-sticking structure 124 (see, for example Figure 10 ). Thereafter, the first conductive layer 802 is exposed to an etchant. The etchant removes the unmasked portions of the first conductive layer 802, thereby forming the upper conductive wire 120. Subsequently, the mask layer can be stripped.

[0074] As Figure 12 shown, an upper ILD layer 1202 is formed above the upper conductive wire 120 and above the piezoelectric anti-sticking structure 124. The upper ILD layer 1202 can be formed with a substantially flat upper surface. In some embodiments, the process of forming the upper ILD layer 1202 includes depositing the upper ILD layer 1202 on the upper conductive wire 120 and the piezoelectric anti-sticking structure 124. The upper ILD layer 1202 can be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the above. In other embodiments, a planarization process (e.g., CMP) can be performed on the upper ILD layer 1202 to planarize the upper surface of the upper ILD layer 1202. The upper ILD layer 1202 can include a low dielectric constant dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., SiO2), etc. It should be understood that in some embodiments, the upper ILD layer 1202 can include one or more stacked ILD layers, and the one or more stacked ILD layers can respectively include a low dielectric constant dielectric, an oxide, etc.

[0075] Figure 12It is also shown that an upper conductive via 502 is formed in the upper ILD layer 1202. The upper conductive via 502 is formed to extend through the upper ILD layer 1202 to the upper conductive line 120. In some embodiments, the process of forming the upper conductive via 502 includes forming a mask layer (not shown) on the upper ILD layer 1202. Thereafter, the upper ILD layer 1202 is exposed to an etchant to remove the unmasked portions of the upper ILD layer 1202, thereby forming an opening (not shown) in the upper ILD layer 1202. Then a conductive layer (not shown) is deposited on the upper ILD layer 1202 and in the opening. In some embodiments, the conductive layer includes, for example, Cu, Al, W, etc. In other embodiments, the conductive layer can be deposited by, for example, CVD, PVD, ALD, sputtering, electroplating, electroless plating, some other deposition process, or a combination of the above. Thereafter, a planarization process (e.g., CMP) is performed on the conductive layer, thereby forming the upper conductive via 502.

[0076] As Figure 13 As shown, an upper ILD structure 112 is formed on top of the lower ILD structure 110. In some embodiments, the process of forming the upper ILD structure 112 includes forming a first opening 1302 in the upper ILD layer 1202 that exposes the piezoelectric anti-sticking structure 124. In some embodiments, the process of forming the first opening 1302 includes forming a mask layer (not shown) on the upper ILD layer 1202 and the upper conductive via 502. Thereafter, the upper ILD layer 1202 is exposed to an etchant to remove the unmasked portions of the upper ILD layer 1202, thereby forming the first opening 1302. In other embodiments, the formation of the upper ILD structure 112 completes the formation of the ILD structure 106.

[0077] In embodiments where the dielectric structure 202 is disposed on the piezoelectric structure 128 respectively, the dielectric structure 202 can be formed during or after the formation of the upper ILD structure 112. For example, the dielectric structure 202 can be formed during the formation of the upper ILD structure 112 by selectively forming the first opening 1302 (e.g., formed by multiple mask layers and etching processes) such that some portions of the upper ILD layer 1202 are respectively retained on the piezoelectric structure 128 as the dielectric structure 202. In another example, the dielectric structure 202 can be formed after the formation of the upper ILD structure 112 by depositing a dielectric layer on the exposed piezoelectric structure 128 and selectively etching the dielectric layer to form the dielectric structure 202 on the piezoelectric structure 128 respectively.

[0078] As Figure 14As shown, the second semiconductor substrate 114 is bonded to the upper ILD structure 112. In some embodiments, bonding the second semiconductor substrate 114 to the upper ILD structure 112 forms a first lower portion of the cavity 118. In other embodiments, the second semiconductor substrate 114 can be bonded to the upper ILD structure 112 by, for example, direct bonding, hybrid bonding, eutectic bonding, or some other bonding process. In still other embodiments, after bonding the second semiconductor substrate 114 to the upper ILD structure 112, the second semiconductor substrate 114 can be thinned by removing (e.g., by grinding or CMP) an upper portion of the second semiconductor substrate 114.

[0079] As Figure 15 As shown, the through-substrate vias (TSVs) 512 are formed to extend through the second semiconductor substrate 114 to the interconnect structure 108. In some embodiments, the TSVs 512 are formed to extend through at least a portion of the second semiconductor substrate 114, the upper ILD structure 112, and the lower ILD structure 110. The TSVs 512 can be formed to extend through the isolation structure 514 disposed in the second semiconductor substrate 114. In some embodiments, the isolation structure 514 is formed before forming the TSVs 512. In other embodiments, the isolation structure 514 can be formed by forming trenches in the second semiconductor substrate 114 and then filling the trenches with a dielectric material. In still other embodiments, a planarization process (e.g., CMP) can be performed on the dielectric material.

[0080] In some embodiments, the process of forming the TSVs 512 includes forming a mask layer (not shown) on the second semiconductor substrate 114. Thereafter, the second semiconductor substrate 114 is exposed to an etchant that removes the unmasked portion of the second semiconductor substrate 114 and the underlying portions of the upper ILD structure 112 and the lower ILD structure 110, thereby forming TSV openings that extend through the second semiconductor substrate 114 to the interconnect structure 108. After forming the TSV openings, a conductive layer (not shown) is deposited on the second semiconductor substrate 114 and in the TSV openings. In some embodiments, the conductive layer includes, for example, Cu, Al, W, etc. In other embodiments, the conductive layer can be deposited by, for example, CVD, PVD, ALD, sputtering, electroplating, electroless plating, some other deposition process, or a combination of the above. Thereafter, a planarization process (e.g., CMP) is performed on the conductive layer, thereby forming the TSVs 512. It should be understood that in some embodiments, the TSV 512 can be one of a plurality of TSVs formed by the above process.

[0081] As Figure 16As shown, a lower bonding ring 510 is formed on the second semiconductor substrate 114 and the TSV 512. In some embodiments, the process of forming the lower bonding ring 510 includes forming a mask layer (not shown) over the second semiconductor substrate 114 and the TSV 512. The mask layer includes a plurality of openings that expose some portions of the second semiconductor substrate 114 and the TSV 512. Then, a conductive layer (not shown) is deposited over the mask layer and in the plurality of openings. In some embodiments, the conductive layer includes, for example, Cu, Al, Au, Sn, some other bonding materials, or a combination of the foregoing. In other embodiments, the conductive layer can be deposited by, for example, CVD, PVD, ALD, sputtering, electroplating, electroless plating, some other deposition processes, or a combination of the foregoing. Thereafter, a planarization process (e.g., CMP) is performed on the conductive layer to form the lower bonding ring 510. Subsequently, in some embodiments, the mask layer is removed.

[0082] As Figure 17 shown, a movable mass 122 is formed in the second semiconductor substrate 114. In some embodiments, the process of forming the movable mass 122 includes forming a mask layer (not shown) over the second semiconductor substrate 114 and the lower bonding ring 510. Thereafter, the second semiconductor substrate 114 is exposed to an etchant. The etchant removes the unmasked portions of the second semiconductor substrate 114 to form the movable mass 122. Subsequently, in some embodiments, the mask layer is removed.

[0083] As Figure 18 shown, an upper bonding ring 508 is formed on the third semiconductor substrate 116. In some embodiments, the upper bonding ring 508 is formed to have a layout corresponding to that of the lower bonding ring 510. In some embodiments, the process of forming the upper bonding ring 508 includes forming a mask layer (not shown) over the third semiconductor substrate 116. The mask layer includes a plurality of openings that expose some portions of the third semiconductor substrate 116. Then, a conductive layer (not shown) is deposited over the mask layer and in the plurality of openings. In some embodiments, the conductive layer includes, for example, Cu, Al, Au, Sn, some other bonding materials, or a combination of the foregoing. In other embodiments, the conductive layer can be deposited by, for example, CVD, PVD, ALD, sputtering, electroplating, electroless plating, some other deposition processes, or a combination of the foregoing. Thereafter, a planarization process is performed on the conductive layer to form the upper bonding ring 508. Subsequently, in some embodiments, the mask layer is removed. In still other embodiments, one or more doped regions (e.g., formed by ion implantation) can be formed in the third semiconductor substrate 116 before forming the upper bonding ring 508.

[0084] As Figure 19As shown, a second opening 1902 is formed in the third semiconductor substrate 116. In some embodiments, the process of forming the second opening 1902 includes depositing a first mask layer 1904 (e.g., negative / positive photoresist) on the third semiconductor substrate 116, and the first mask layer 1904 covers the upper bonding ring 508. Then, the third semiconductor substrate 116 is exposed to an etchant. The etchant removes the unmasked portion of the third semiconductor substrate 116, thereby forming the second opening 1902. In some embodiments, the first mask layer 1904 can be stripped off.

[0085] As Figure 20 shown, a fourth conductive layer 2002 is formed over the third semiconductor substrate 116, the upper bonding ring 508, and the first mask layer 1904. In some embodiments, the fourth conductive layer 2002 lines the second opening 1902 (see, for example Figure 19 ). In other embodiments, the process of forming the fourth conductive layer 2002 includes depositing the fourth conductive layer 2002 on the third semiconductor substrate 116 and the first mask layer 1904. The fourth conductive layer 2002 can be deposited by, for example, CVD, PVD, ALD, sputtering, electroplating, electroless plating, some other deposition process, or a combination of the above. In still other embodiments, the fourth conductive layer 2002 can include, for example, Pt, Ti, Cu, Au, Al, Zn, Sn, some other conductive material, or a combination of the above.

[0086] Figure 20 Also shown is that a second piezoelectric layer 2004 is formed over the fourth conductive layer 2002. In some embodiments, the process of forming the second piezoelectric layer 2004 includes depositing the second piezoelectric layer 2004 on the fourth conductive layer 2002. The second piezoelectric layer 2004 can be deposited or grown by, for example, sputtering, spin coating process, CVD, PVD, ALD, molecular beam epitaxy, some other deposition or growth process, or a combination of the above. In other embodiments, the second piezoelectric layer 2004 can include, for example, PZT, ZnO, BaTiO3, KNbO3, Na2WO3, Ba2NaNb5O5, Pb2KNb5O 15 , La3Ga5SiO 14 , GaPO4, LiNbO3, LiTaO3, some other piezoelectric material, or a combination of the above.

[0087] Figure 20Also shown is that a fifth conductive layer 2006 is formed over the second piezoelectric layer 2004. In some embodiments, the process of forming the fifth conductive layer 2006 includes depositing the fifth conductive layer 2006 on the second piezoelectric layer 2004. The fifth conductive layer 2006 can be deposited by, for example, CVD, PVD, ALD, sputtering, electroplating, electroless plating, some other deposition process, or a combination of the above. In some other embodiments, the fifth conductive layer 2006 can include, for example, Pt, Ti, Cu, Au, Al, Zn, Sn, some other conductive material, or a combination of the above. In embodiments where the dielectric structure 202 is disposed on the piezoelectric structure 128 respectively, the fifth conductive layer 2006 may not be formed over the second piezoelectric layer 2004.

[0088] As Figure 21 shown, a second plurality of piezoelectric anti-sticking structures 124 are formed over the third semiconductor substrate 116. In some embodiments, the piezoelectric anti-sticking structures 124 are formed within a second opening 1902 (see, for example, Figure 19 ). In some embodiments, the process of forming the piezoelectric anti-sticking structures 124 includes forming a second mask layer (not shown) over the fifth conductive layer 2006 (see, for example, Figure 20 ). Thereafter, the fifth conductive layer 2006, the second piezoelectric layer 2004, and the fourth conductive layer 2002 (see, for example, Figure 20 ) are exposed to an etchant. The etchant removes the unmasked portions of the fifth conductive layer 2006, thereby forming a plurality of conductive structures 130 on the second piezoelectric layer 2004; the etchant removes the unmasked portions of the second piezoelectric layer 2004, thereby forming a plurality of piezoelectric structures 128 on the fourth conductive layer 2002; and the etchant removes the unmasked portions of the fourth conductive layer 2002, thereby forming a plurality of electrodes 126 on the third semiconductor substrate 116.

[0089] As Figure 22 shown, the third semiconductor substrate 116 is bonded to the second semiconductor substrate 114, thereby forming an upper portion of the cavity 118. In some embodiments, the cavity 118 is formed as a sealed cavity. In some other embodiments, the process of bonding the third semiconductor substrate 116 to the second semiconductor substrate 114 includes bonding an upper bonding ring 508 to a lower bonding ring 510. The upper bonding ring 508 can be bonded to the lower bonding ring 510 by, for example, eutectic bonding. It should be understood that the third semiconductor substrate 116 can be bonded to the second semiconductor substrate 114 by other bonding processes (e.g., direct bonding, hybrid bonding, etc.). In still some other embodiments, after bonding the third semiconductor substrate 116 to the second semiconductor substrate 114, the formation of the MEMS device 100 is completed.

[0090] Figure 23Flowchart 2300 showing some embodiments of a method of forming a MEMS device including a piezoelectric anti-stiction structure. Although the flowchart 2300 shown herein is illustrated and described as a series of acts or events, it should be understood that the illustrated order of such acts or events should not be construed in a limiting sense. For example, some acts may occur in a different order and / or occur synchronously with other acts or events other than those shown and / or described herein. In addition, not all of the acts shown may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be implemented in one or more separate acts and / or phases. Figure 23 Although the flowchart 2300 shown herein is illustrated and described as a series of acts or events, it should be understood that the illustrated order of such acts or events should not be construed in a limiting sense. For example, some acts may occur in a different order and / or occur synchronously with other acts or events other than those shown and / or described herein. In addition, not all of the acts shown may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be implemented in one or more separate acts and / or phases.

[0091] At act 2302, a first semiconductor substrate having a lower interlayer dielectric (ILD) structure disposed on a first semiconductor substrate is provided. Figure 7 A cross-sectional view showing some embodiments corresponding to act 2302 is shown.

[0092] At act 2304, a plurality of piezoelectric anti-stiction structures are formed over the lower ILD structure and the first semiconductor substrate. Figures 8 to 10 A series of cross-sectional views showing some embodiments corresponding to act 2304 are shown.

[0093] At act 2306, an upper ILD structure is formed over the lower ILD structure and the first semiconductor substrate, wherein the piezoelectric anti-stiction structures are disposed in openings of the upper ILD structure. Figures 11 to 13 A series of cross-sectional views showing some embodiments corresponding to act 2306 are shown.

[0094] At act 2308, a second semiconductor substrate is bonded to the upper ILD structure, wherein the second semiconductor substrate extends through the opening to form a cavity, and wherein the piezoelectric anti-stiction structures are disposed in the cavity. Figure 14 A cross-sectional view showing some embodiments corresponding to act 2308 is shown.

[0095] At act 2310, a movable mass is formed in the second semiconductor substrate and on the piezoelectric anti-stiction structures. Figures 15 to 17 A series of cross-sectional views showing some embodiments corresponding to act 2310 are shown.

[0096] At act 2312, a third semiconductor substrate is bonded to the second semiconductor substrate. Figures 18 to 22 A series of cross-sectional views showing some embodiments corresponding to act 2312 are shown.

[0097] In some embodiments, the present application provides a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, wherein the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, wherein opposite sidewalls of the movable mass are disposed between opposite sidewalls of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.

[0098] In some embodiments, in the above-mentioned MEMS device, the first piezoelectric anti-stiction structure includes: a first conductive structure disposed on the first piezoelectric structure, wherein the first piezoelectric structure separates the first electrode from the first conductive structure.

[0099] In some embodiments, in the above-mentioned MEMS device, the first electrode and the first conductive structure have the same chemical composition.

[0100] In some embodiments, in the above-mentioned MEMS device, the first piezoelectric anti-stiction structure includes: a second dielectric structure disposed on the first piezoelectric structure, wherein the first piezoelectric structure separates the first electrode from the second dielectric structure.

[0101] In some embodiments, in the above-mentioned MEMS device, the movable mass has a dopant concentration greater than about 1×10 20 cm -3 .

[0102] In some embodiments, in the above-mentioned MEMS device, wherein the second dielectric structure includes an oxide.

[0103] In some embodiments, in the above-mentioned MEMS device, an upper surface of the first dielectric structure at least partially defines a bottom surface of the cavity; the upper surface of the first dielectric structure is spaced apart from a topmost surface of the first dielectric structure by a distance; and a height of the first piezoelectric anti-stiction structure is between about 30% and about 50% of the distance.

[0104] In some embodiments, in the above-mentioned MEMS device, the distance is between about 2 micrometers and about 3 micrometers.

[0105] In some embodiments, in the above-mentioned MEMS device, further includes: a third semiconductor substrate disposed over both the first semiconductor substrate and the second semiconductor substrate, wherein the third semiconductor substrate defines an upper portion of the cavity.

[0106] In some embodiments, in the above-mentioned microelectromechanical system device, it further includes: a second piezoelectric anti-sticking structure disposed between the movable mass and the bottom surface of the third semiconductor substrate, wherein the second piezoelectric anti-sticking structure includes a second piezoelectric structure and a second electrode disposed between the second piezoelectric structure and the bottom surface of the third semiconductor substrate, and wherein the bottom surface of the third semiconductor substrate at least partially defines the upper surface of the cavity.

[0107] In some embodiments, in the above-mentioned microelectromechanical system device, the second piezoelectric anti-sticking structure includes: a second conductive structure disposed on the second piezoelectric structure, wherein the second piezoelectric structure separates the second electrode from the second conductive structure.

[0108] In some embodiments, in the above-mentioned microelectromechanical system device, the second piezoelectric anti-sticking structure includes: a third dielectric structure disposed on the second piezoelectric structure, wherein the second piezoelectric structure separates the second electrode from the third dielectric structure.

[0109] In some embodiments, in the above-mentioned microelectromechanical system device, it further includes: an interconnect structure disposed in the first dielectric structure, wherein the conductive features of the interconnect structure at least partially define the cavity, and wherein the first electrode is electrically coupled to the conductive features of the interconnect structure.

[0110] In some embodiments, in the above-mentioned microelectromechanical system device, the conductive features of the interconnect structure are the uppermost metal lines of the interconnect structure.

[0111] In some embodiments, the present application provides an integrated circuit (IC). The integrated circuit includes a microelectromechanical system (MEMS). The MEMS includes: a semiconductor substrate; a movable mass spaced apart from the semiconductor substrate; a cavity at least partially disposed between the semiconductor substrate and the movable mass, wherein opposite sidewalls of the movable mass are disposed between opposite sidewalls of the cavity; and a piezoelectric anti-sticking structure disposed on the surface of the cavity, wherein the piezoelectric anti-sticking structure includes a piezoelectric structure and an electrode. A bias circuit system is electrically coupled to the electrode, wherein the bias circuit system is configured to provide a first voltage to the electrode.

[0112] In some embodiments, in the above-mentioned integrated circuit, it further includes: a doped region disposed in the movable mass, wherein the bias circuit system is electrically coupled to the doped region and is configured to provide a second voltage different from the first voltage to the doped region.

[0113] In some embodiments, in the above integrated chip, the piezoelectric anti-sticking structure: has a first shape when the movable mass is spaced apart from the piezoelectric anti-sticking structure; and has a second shape different from the first shape when the movable mass contacts the piezoelectric anti-sticking structure.

[0114] In some embodiments, in the above integrated chip, it further includes: a measurement circuit system configured to determine whether the movable mass is in a movable state or a fixed state, where: when the movable mass is in the fixed state, the bias circuit system provides the first voltage to the electrode; and when the movable mass is in the movable state, the bias circuit system does not provide the first voltage to the electrode.

[0115] In some embodiments, the present application provides a method for forming a microelectromechanical system (MEMS) device. The method includes forming a first conductive layer on a lower interlayer dielectric (ILD) structure, where the lower ILD structure is disposed on a semiconductor substrate. Forming a first conductive layer on the lower ILD structure. Forming a second conductive layer on the first conductive layer. Forming a piezoelectric layer on the second conductive layer. Etching the first piezoelectric layer and the second conductive layer to respectively form a piezoelectric structure and an electrode, where the piezoelectric structure is disposed on the electrode. Etching the first conductive layer to form a conductive wire. Forming an upper ILD structure on the lower ILD structure, the conductive wire, the electrode, and the piezoelectric structure. Forming an opening in the upper ILD structure that exposes the piezoelectric structure. Forming a movable mass on the upper ILD structure, where the movable mass is formed to have opposite sidewalls disposed between opposite sidewalls of the opening.

[0116] In some embodiments, in the above method, it further includes: forming a third conductive layer on the piezoelectric layer before etching the piezoelectric layer or the second conductive layer; and etching the third conductive layer to form a conductive structure, where the conductive structure is disposed on the piezoelectric structure and is spaced apart from the electrode through the piezoelectric structure.

[0117] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. A microelectromechanical system device, comprising: A first dielectric structure disposed over a first semiconductor substrate, wherein the first dielectric structure at least partially defines a cavity; A second semiconductor substrate disposed over the first dielectric structure and including a movable mass, wherein opposite sidewalls of the movable mass are disposed between opposite sidewalls of the cavity; A first piezoelectric anti-stiction structure disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure; An interconnect structure disposed within the first dielectric structure; and A conductive via disposed within the first dielectric structure, wherein the conductive via extends vertically from a first conductive feature of the interconnect structure to the second semiconductor substrate, and wherein the conductive via is electrically coupled to the movable mass via a conductive channel that extends within the second semiconductor substrate.

2. The microelectromechanical system device according to claim 1, wherein the first piezoelectric anti-stiction structure includes: A first conductive structure disposed on the first piezoelectric structure, wherein the first piezoelectric structure separates the first electrode from the first conductive structure.

3. The microelectromechanical system device according to claim 2, wherein the first electrode and the first conductive structure comprise the same chemical composition.

4. The microelectromechanical system device according to claim 1, wherein the first piezoelectric anti-stiction structure includes: A second dielectric structure disposed on the first piezoelectric structure, wherein the first piezoelectric structure separates the first electrode from the second dielectric structure.

5. The microelectromechanical system device according to claim 4, wherein the second dielectric structure comprises an oxide.

6. The microelectromechanical system device according to claim 1, wherein: An upper surface of the first dielectric structure at least partially defines a bottom surface of the cavity; The upper surface of the first dielectric structure is spaced apart from a topmost surface of the first dielectric structure by a distance; and A height of the first piezoelectric anti-stiction structure is between 30% and 50% of the distance.

7. The microelectromechanical system device according to claim 6, wherein the distance is between 2 micrometers and 3 micrometers.

8. The microelectromechanical system device according to claim 1, further comprising: A third semiconductor substrate disposed over both the first semiconductor substrate and the second semiconductor substrate, wherein the third semiconductor substrate defines an upper portion of the cavity.

9. The microelectromechanical system device according to claim 8, further comprising: A second piezoelectric anti-stiction structure disposed between the movable mass and a bottom surface of the third semiconductor substrate, wherein the second piezoelectric anti-stiction structure includes a second piezoelectric structure and a second electrode disposed between the second piezoelectric structure and the bottom surface of the third semiconductor substrate, and wherein the bottom surface of the third semiconductor substrate at least partially defines an upper surface of the cavity.

10. The MEMS device according to claim 9, wherein the second piezoelectric anti-sticking structure comprises: A second conductive structure disposed on the second piezoelectric structure, wherein the second piezoelectric structure separates the second electrode from the second conductive structure.

11. The MEMS device according to claim 9, wherein the second piezoelectric anti-sticking structure comprises: A third dielectric structure disposed on the second piezoelectric structure, wherein the second piezoelectric structure separates the second electrode from the third dielectric structure.

12. The MEMS device according to claim 1, wherein the conductive feature of the interconnect structure locally defines the cavity, and wherein the first electrode is electrically coupled to the conductive feature of the interconnect structure.

13. The MEMS device according to claim 12, wherein the conductive feature of the interconnect structure is the uppermost metal line of the interconnect structure.

14. An integrated chip, comprising: A MEMS, comprising: A semiconductor substrate; A movable mass spaced apart from the semiconductor substrate; A cavity at least partially disposed between the semiconductor substrate and the movable mass, wherein opposite sidewalls of the movable mass are disposed between opposite sidewalls of the cavity; An interlayer dielectric structure disposed between the semiconductor substrate and the movable mass; An interconnect structure disposed within the interlayer dielectric structure; A conductive via extending perpendicularly from the interlayer dielectric structure towards the movable mass, wherein the conductive via at least partially defines a conductive path that electrically couples the movable mass to the interconnect structure; A piezoelectric anti-sticking structure disposed on a surface of the cavity, wherein the piezoelectric anti-sticking structure comprises a piezoelectric structure and an electrode, wherein the electrode is disposed between the piezoelectric structure and a bottom surface of the cavity, and wherein the piezoelectric structure is configured to change shape based on a potential difference between the electrode and the movable mass; and A bias circuit system electrically coupled to the electrode, wherein the bias circuit system is configured to provide a first voltage to the electrode.

15. The integrated chip according to claim 14, further comprising: A doped region disposed in the movable mass, wherein the bias circuit system is electrically coupled to the doped region and is configured to provide a second voltage different from the first voltage to the doped region.

16. The integrated chip according to claim 15, wherein the piezoelectric anti-sticking structure: Has a first shape when the movable mass is spaced apart from the piezoelectric anti-sticking structure; and Has a second shape different from the first shape when the movable mass contacts the piezoelectric anti-sticking structure.

17. The integrated chip according to claim 14, further comprising: A measurement circuit system configured to determine whether the movable mass is in a movable state or a fixed state, wherein: When the movable mass is in the fixed state, the bias circuit system provides the first voltage to the electrode; and When the movable mass is in the movable state, the biasing circuit system does not supply the first voltage to the electrode.

18. A method of forming a microelectromechanical system device, the method comprising: Forming a first conductive layer on a lower interlayer dielectric structure, wherein the lower interlayer dielectric structure is disposed on a semiconductor substrate; Forming a second conductive layer on the first conductive layer; Forming a piezoelectric layer on the second conductive layer; Etching the piezoelectric layer and the second conductive layer to form a piezoelectric structure and an electrode, respectively, wherein the piezoelectric structure is disposed on the electrode; Etching the first conductive layer to form a conductive wire; Forming an upper interlayer dielectric structure over the lower interlayer dielectric structure, the conductive wire, the electrode, and the piezoelectric structure; Forming an opening in the upper interlayer dielectric structure that exposes the piezoelectric structure; And Forming a movable mass over the upper interlayer dielectric structure, wherein the movable mass is formed to have opposing sidewalls disposed between opposing sidewalls of the opening, The method further comprises: Forming an interconnect structure within the lower interlayer dielectric structure; And Forming a conductive via within the lower interlayer dielectric structure such that the conductive via extends vertically from the interlayer dielectric structure towards the movable mass, wherein the conductive via at least partially defines a conduction path that electrically couples the movable mass to the interconnect structure.

19. The method of forming a microelectromechanical system device according to claim 18, further comprising: Forming a third conductive layer on the piezoelectric layer before etching the piezoelectric layer or the second conductive layer; And Etching the third conductive layer to form a conductive structure, wherein the conductive structure is disposed on the piezoelectric structure and is spaced apart from the electrode by the piezoelectric structure.

20. An integrated chip, comprising: A semiconductor substrate; A movable mass spaced apart from the semiconductor substrate; A cavity at least partially disposed between the semiconductor substrate and the movable mass, wherein opposing sidewalls of the movable mass are disposed between opposing sidewalls of the cavity; An interlayer dielectric structure disposed between the semiconductor substrate and the movable mass; An interconnect structure disposed within the interlayer dielectric structure; A conductive via extending vertically from the interlayer dielectric structure towards the movable mass, wherein the conductive via at least partially defines a conduction path that electrically couples the movable mass to the interconnect structure; A first piezoelectric anti-stiction structure disposed on a first surface of the cavity, wherein the first piezoelectric anti-stiction structure comprises a first piezoelectric structure and a first electrode, wherein the first electrode is disposed between the first piezoelectric structure and a bottom surface of the cavity, and wherein the piezoelectric structure is configured to change shape based on a potential difference between the electrode and the movable mass.

21. The integrated chip according to claim 20, further comprising: A doped region is provided in the movable mass, wherein the doped region has a dopant concentration greater than 1×10 20 cm -3 .

22. The integrated chip according to claim 21, wherein the first piezoelectric anti-stiction structure: having a first shape when the movable mass is spaced apart from the first piezoelectric anti - adhesion structure; and having a second shape different from the first shape when the movable mass contacts the first piezoelectric anti - adhesion structure.

23. The integrated chip according to claim 20, wherein the first piezoelectric anti - adhesion structure further comprises a first conductive structure, and the outer sidewalls of the first electrodes are respectively aligned with the outer sidewalls of the first piezoelectric structure; and the outer sidewalls of the first piezoelectric structure are respectively aligned with the outer sidewalls of the first conductive structure.

24. The integrated chip according to claim 20, further comprising: a second piezoelectric anti - adhesion structure disposed on the first surface of the cavity, wherein the second piezoelectric anti - adhesion structure is laterally spaced apart from the first piezoelectric anti - adhesion structure, wherein the second piezoelectric anti - adhesion structure comprises a second piezoelectric structure, a second electrode, and a second conductive structure, and wherein the second piezoelectric structure is disposed between the second electrode and the second conductive structure.

25. The integrated chip according to claim 24, further comprising: a third piezoelectric anti - adhesion structure disposed on the second surface of the cavity, wherein: the second surface of the cavity is vertically spaced apart from the first surface of the cavity; the movable mass is vertically disposed between the third piezoelectric anti - adhesion structure and the second piezoelectric anti - adhesion structure; the third piezoelectric anti - adhesion structure comprises a third piezoelectric structure, a third electrode, and a third conductive structure; the third piezoelectric structure is disposed between the third electrode and the third conductive structure; and the vertical distance between the second piezoelectric structure and the third piezoelectric structure is greater than the vertical distance between the second conductive structure and the third conductive structure.

26. An integrated chip, comprising: an inter - layer dielectric structure disposed on a first semiconductor substrate; a second semiconductor substrate disposed on the inter - layer dielectric structure; a third semiconductor substrate disposed on both the first semiconductor substrate and the second semiconductor substrate, wherein the third semiconductor substrate and the inter - layer dielectric structure partially define a cavity, and wherein the second semiconductor substrate comprises a movable mass disposed within the cavity; a piezoelectric anti - adhesion structure disposed on the bottom surface of the third semiconductor substrate, wherein the piezoelectric anti - adhesion structure comprises a piezoelectric structure and an electrode, and wherein the electrode is disposed between the bottom surface of the third semiconductor substrate and the piezoelectric anti - adhesion structure; an interconnect structure disposed within the inter - layer dielectric structure; and a conductive via disposed within the inter - layer dielectric structure, wherein the conductive via extends vertically from a first conductive feature of the interconnect structure to the second semiconductor substrate, and wherein the conductive via is electrically coupled to the movable mass via a conductive channel that extends within the second semiconductor substrate; and a substrate via disposed within the inter - layer dielectric structure and the second semiconductor substrate, wherein the substrate via is electrically coupled to the electrode of the piezoelectric anti - adhesion structure.

27. The integrated chip according to claim 26, further comprising: A bonding structure is disposed between the second semiconductor substrate and the third semiconductor substrate, wherein the substrate vias vertically extend through the interlayer dielectric structure and the second semiconductor substrate and extend to the bonding structure, and wherein the bonding structure electrically couples the substrate vias to a first conductive channel, and the first conductive channel is disposed in the third semiconductor substrate and extends from the electrode to the bonding structure.

28. The integrated chip according to claim 27, further comprising: An upper conductive via is disposed in the interlayer dielectric structure, wherein the upper conductive via vertically extends through the interlayer dielectric structure and extends to the second semiconductor substrate, and wherein a second conductive channel extends from the upper conductive via to the movable mass body such that the movable mass body is electrically coupled to the upper conductive via.

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