Chip packaging structure and forming method thereof

Abstract

A chip packaging structure and a method for forming the same are provided. The method includes providing a wiring substrate. The method includes sequentially forming a nickel-containing layer and a gold-containing layer above a first pad. The method includes forming a conductive protective layer to cover the gold-containing layer above the nickel-containing layer. The method includes bonding the chip to the wiring substrate via a conductive bump and a solder flux layer surrounding the conductive bump. The conductive bump is between the second pad and the chip. The method includes removing the solder flux layer while the conductive protective layer covers the nickel-containing layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor manufacturing technology, and in particular to a chip packaging structure and a method for forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning these different material layers using photolithography and etching processes to form circuit components and elements on the semiconductor substrate.

[0003] Many integrated circuits are typically manufactured on semiconductor wafers. The dies of the wafer can be processed and packaged at the wafer level, and various technologies have been developed for wafer-level packaging. Summary of the invention

[0004] According to some embodiments, a method for forming a chip packaging structure is provided. The method includes providing a wiring substrate. The wiring substrate includes a substrate, a first pad, a second pad and an insulating layer. The first pad and the second pad are respectively above the first surface and the second surface of the substrate. The insulating layer is above the first surface and partially covers the first pad, and the first pad is wider than the second pad. The method includes sequentially forming a nickel-containing layer and a gold-containing layer above the first pad. The method includes forming a conductive protective layer to cover the gold-containing layer above the nickel-containing layer. The conductive protective layer, the gold-containing layer and the nickel-containing layer are made of different materials, and the first distance between the first top surface of the insulating layer and the second top surface of the first pad is greater than the second distance between the third top surface of the conductive protective layer and the second top surface. The method includes bonding the chip to the wiring substrate via a first conductive bump and a first soldering flux layer surrounding the first conductive bump. The first conductive bump is between the second pad and the chip and connects the second pad and the chip. The method includes removing the first soldering flux layer while the conductive protective layer covers the nickel-containing layer.

[0005] According to other embodiments, a method for forming a chip packaging structure is provided. The method includes providing a wiring substrate. The wiring substrate includes a substrate, a first pad, a second pad and an insulating layer, the first pad and the second pad are respectively above the first surface and the second surface of the substrate, and the insulating layer is above the first surface and the first pad and has an opening, and the opening partially exposes the first pad. The method includes sequentially forming a nickel-containing layer and a gold-containing layer in the opening. The method includes forming a conductive protective layer above the gold-containing layer, wherein the first porosity of the conductive protective layer is less than the second porosity of the gold-containing layer. The method includes bonding the chip to the second pad of the wiring substrate via a first conductive bump after the conductive protective layer is formed above the gold-containing layer. The method includes forming a conductive structure above the conductive protective layer after bonding the chip to the second pad. The method includes reflowing the conductive structure and the conductive protective layer to melt and mix the conductive structure and the conductive protective layer together, thereby forming a second conductive bump.

[0006] According to some other embodiments, a chip packaging structure is provided. This chip packaging structure includes a first wiring substrate, the first wiring substrate includes a substrate, a first pad, a second pad and an insulating layer, the first pad and the second pad are respectively located above the first surface and the second surface of the substrate, the insulating layer is above the first surface and partially covers the first pad, and the first pad is wider than the second pad. This chip packaging structure includes a nickel-containing layer above the first pad. This chip packaging structure includes a conductive protective layer above the nickel-containing layer. The conductive protective layer includes tin, and the conductive protective layer and the insulating layer above the first pad surround the groove. This chip packaging structure includes a chip above the second surface of the substrate. This chip packaging structure includes a conductive bump between the second pad and the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description in conjunction with the accompanying drawings of the specification can better understand the content of the embodiments of the present invention. It should be emphasized that, according to standard practices in the industry, many components are not drawn to scale. In fact, in order to clearly discuss, the sizes of various components may be arbitrarily increased or reduced.

[0008] Figure 1A to Figure 1M is a cross-sectional schematic diagram of various stages of a process for forming a chip package structure according to some embodiments.

[0009] Figure 2A to Figure 2B is a cross-sectional schematic diagram of various stages of a process for forming a chip package structure according to some embodiments.

[0010] Figure 3 is a schematic cross-sectional view of a chip packaging structure according to some embodiments.

[0011] Figure 4A to Figure 4His a cross-sectional schematic diagram of various stages of a process for forming a chip package structure according to some embodiments.

[0012] Figure 5A to Figure 5B is a cross-sectional schematic diagram of various stages of a process for forming a chip package structure according to some embodiments.

[0013] Figure 6 is a schematic cross-sectional view of a chip packaging structure according to some embodiments.

[0014] Figure 7 is a schematic cross-sectional view of a chip packaging structure according to some embodiments.

[0015] Figure 8 is a schematic cross-sectional view of a chip packaging structure according to some embodiments.

[0016] Fig. 9 is a schematic cross-sectional view of a chip packaging structure according to some embodiments.

[0017] Description of reference numerals:

[0018] 100,200,270,290,300,400,490,510,520,600,700,800,900: Chip packaging structure

[0019] 110,280,280a: Wiring substrate

[0020] 111: Base

[0021] 111a, 111b, 178a: Surface

[0022] 112: Through-substrate vias

[0023] 113a,113b,114a,114b,284: wiring layer

[0024] 115a,115b,288: Solder pad

[0025] 115b1,118a1,118b1,122a,132,262: Top surface

[0026] 116a, 116b, 286: Conductive vias

[0027] 117a,117b,118a,118b,282: Insulation layer

[0028] 122: Nickel-containing layer

[0029] 124: Palladium-containing layer

[0030] 126: Gold-bearing layer

[0031] 130: Conductive protective layer

[0032] 134: Curved top surface

[0033] 140,450: Carrier substrate

[0034] 150: Conductive layer

[0035] 160,190: Flux material layer

[0036] 170: Chip

[0037] 172: Semiconductor substrate

[0038] 172a: front surface

[0039] 172b: rear surface

[0040] 174: Dielectric layer

[0041] 176: Conductive pad

[0042] 178: Interconnect Layer

[0043] 180,210,260,410,480: Conductive bumps

[0044] 220,420,460: Flux layer

[0045] 230,G: Carrier substrate

[0046] 240: Bottom filling layer

[0047] 250,440: Molding layer

[0048] 260a: Conductive structure

[0049] 289: Elastic contact structure

[0050] 430,470: Device

[0051] 610,710,730: Adhesive layer

[0052] 620: Heat sink cover

[0053] 720: Heat sink

[0054] 740: Heat sink

[0055] A: Cutting line

[0056] C: Intermetallic compound layer

[0057] D1,D2,D3,D4: distance

[0058] E: Slot

[0059] F: Desoldering solution

[0060] P1, P2: Open

[0061] R1: Groove

[0062] T1, T2, T3, T3', T4, T5: thickness

[0063] W1, W2, W3, W4: Width DETAILED DESCRIPTION

[0064] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first component is formed on or above a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the embodiments of the present invention may reuse reference numerals and / or letters in different examples. This repetition is for the purpose of simplicity and clarity and does not represent a specific relationship between the different embodiments and / or configurations discussed.

[0065] In addition, spatially relative terms may be used herein, such as "below," "under," "down," "above," "upper," and similar terms, which are intended to facilitate description of the relationship between one element or component and another element or component as shown. These spatially relative terms are used to cover different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used herein will also be interpreted based on the orientation after the turn. It should be understood that additional operations may be provided before, during, and after the method, and that some of the operations described may be replaced or eliminated for other embodiments of the method.

[0066] Some embodiments of the present invention are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the stages described may be replaced or eliminated for different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described below may be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a specific order, these operations may be performed in other logical orders.

[0067] Figure 1A to Figure 1M is a cross-sectional schematic diagram of various stages of a process for forming a chip packaging structure according to some embodiments. Figure 1AAs shown, a wiring substrate 110 is provided. According to some embodiments, the wiring substrate 110 includes a substrate 111, through-substrate vias (or plated through holes (PTH)) 112, wiring layers 113a, 113b, 114a, and 114b, pads 115a and 115b, conductive vias 116a and 116b, and insulating layers 117a, 117b, 118a, and 118b.

[0068] According to some embodiments, the substrate 111 has surfaces 111a and 111b. According to some embodiments, the surface 111a is opposite to the surface 111b. In some embodiments, the substrate 111 is made of an insulating material, such as a fiber material, a polymer material, or a glass material. For example, the fiber material includes a glass fiber material.

[0069] In some other embodiments, according to some embodiments, the substrate 111 is made of a semiconductor material or a conductive material. For example, the semiconductor material includes silicon or germanium. For example, the conductive material includes a metal material.

[0070] According to some embodiments, through-substrate vias 112 penetrate substrate 111. According to some embodiments, wiring layers 113a and 113b are formed over surfaces 111a and 111b, respectively. According to some embodiments, through-substrate vias 112 electrically connect wiring layer 113a to wiring layer 113b.

[0071] According to some embodiments, if the substrate 111 is made of a semiconductor material or a conductive material, an insulating layer (not shown) is formed between the substrate 111 and the through-substrate via 112 and between the substrate 111 and the wiring layers 113 a and 113 b to electrically insulate the substrate 111 from the through-substrate via 112 and the wiring layers 113 a and 113 b.

[0072] According to some embodiments, wiring layer 114a, pad 115a, conductive via 116a, and insulating layers 117a and 118a are formed over surface 111a. According to some embodiments, wiring layer 114a and conductive via 116a are in insulating layer 117a. According to some embodiments, pad 115a is over insulating layer 117a. According to some embodiments, conductive via 116a electrically connects between wiring layers 113a and 114a and between wiring layer 114a and pad 115a.

[0073] According to some embodiments, an insulating layer 118a is formed over the insulating layer 117a and the pad 115a. According to some embodiments, the insulating layer 118a has an opening P1. According to some embodiments, the plurality of openings P1 respectively expose the plurality of pads 115a thereunder. According to some embodiments, the insulating layer 118a partially covers the pad 115a.

[0074] According to some embodiments, wiring layer 114b, pad 115b, conductive via 116b, and insulating layers 117b and 118b are formed over surface 111b. According to some embodiments, wiring layer 114b and conductive via 116b are in insulating layer 117b. According to some embodiments, pad 115b is over insulating layer 117b. According to some embodiments, conductive via 116b electrically connects between wiring layers 113b and 114b and between wiring layer 114b and pad 115b.

[0075] According to some embodiments, an insulating layer 118b is formed over the insulating layer 117b and the pad 115b. According to some embodiments, the insulating layer 118b has an opening P2. According to some embodiments, the plurality of openings P2 expose the plurality of pads 115b, respectively. According to some embodiments, the insulating layer 118b partially covers the pad 115b.

[0076] In some embodiments, the pad 115b is wider than the pad 115a. That is, according to some embodiments, the width W1 of the pad 115b is greater than the width W2 of the pad 115a. According to some embodiments, the pad 115b is used to bond with a wiring substrate (e.g., a printed circuit board). According to some embodiments, the pad 115a is used to bond with a chip. According to some embodiments, the width W1 is in the range of about 200 μm to about 600 μm. According to some embodiments, the width W2 is in the range of about 20 μm to about 110 μm. In some embodiments, the (maximum) width W3 of the opening P2 is greater than the (maximum) width W4 of the opening P1.

[0077] According to some embodiments, through substrate via 112, wiring layers 113a, 113b, 114a and 114b, pads 115a and 115b, and conductive vias 116a and 116b are made of conductive materials, such as metal materials or alloys thereof. The metal materials include aluminum, copper, or tungsten.

[0078] According to some embodiments, Figure 1B As shown, a nickel-containing layer 122 is formed over the top surface 115b1 of the pad 115b. According to some embodiments, the nickel-containing layer 122 covers the entire exposed portion of the top surface 115b1, which is exposed by the opening P2. According to some embodiments, the nickel-containing layer 122 is in the opening P2. According to some embodiments, the nickel-containing layer 122 is made of nickel or its alloy. According to some embodiments, the formation of the nickel-containing layer 122 uses a plating process, such as an electroless plating process.

[0079] According to some embodiments, Figure 1BAs shown, a palladium-containing layer 124 is formed over the nickel-containing layer 122. According to some embodiments, the palladium-containing layer 124 is in the opening P2. According to some embodiments, the palladium-containing layer 124 has a thickness T1 in a range of about 0.02 μm to about 0.1 μm. According to some embodiments, the palladium-containing layer 124 is made of palladium or its alloy. According to some embodiments, the formation of the palladium-containing layer 124 uses a plating process, such as an electroless plating process.

[0080] According to some embodiments, Figure 1B As shown, a gold-containing layer 126 is formed over the palladium-containing layer 124. According to some embodiments, the gold-containing layer 126 is in the opening P2. According to some embodiments, the gold-containing layer 126 has a thickness T2 in the range of about 0.02 μm to about 0.1 μm. According to some embodiments, the gold-containing layer 126 is made of gold or its alloy. According to some embodiments, the formation of the gold-containing layer 126 uses a plating process, such as an immersion plating process.

[0081] According to some embodiments, Figure 1B As shown, a conductive protective layer 130 is formed over the gold-containing layer 126. In some embodiments, the porosity of the conductive protective layer 130 is lower than the porosity of the palladium-containing layer 124 and lower than the porosity of the gold-containing layer 126. That is, according to some embodiments, the conductive protective layer 130 has a denser structure than the palladium-containing layer 124 and the gold-containing layer 126.

[0082] In some embodiments, the thickness T3 of the conductive protection layer 130 is greater than the sum of the thickness T1 of the palladium-containing layer 124 and the thickness T2 of the gold-containing layer 126. In some embodiments, the conductive protection layer 130 is thinner than the insulating layer 118b above the pad 115b.

[0083] According to some embodiments, the thickness T3 is in a range of about 1 μm to about 25 μm. According to some embodiments, the thickness T3 is in a range of about 1 μm to about 10 μm. According to some embodiments, the conductive protection layer 130 covers the entire top surface 122 a of the nickel-containing layer 122 .

[0084] If the conductive protective layer 130 is not formed, the nickel atoms in the nickel-containing layer 122 may be affected by the deflux solution used in the subsequent deflux process, and may migrate through the palladium-containing layer 124 and the gold-containing layer 126 and be oxidized. Since the conductive protective layer 130 is denser and thicker than the palladium-containing layer 124 and the gold-containing layer 126, the conductive protective layer 130 can separate the nickel-containing layer 122 from the deflux solution. Therefore, the conductive protective layer 130 can improve the adhesion between the pad 115b and the conductive bump, which is subsequently formed and connected between the pad 115b and the chip. The formation of the conductive protective layer 130 can enhance the conductive bump.

[0085] Since the conductive protection layer 130 can provide stronger protection for the nickel-containing layer 122, a flux removal solution having stronger removal capability for the flux layer can be used to more thoroughly remove the flux layer, thereby improving the yield of the flux layer removal process.

[0086] In some embodiments, a distance D1 between the top surface 118b1 of the insulating layer 118b and the top surface 115b1 of the pad 115b is greater than a distance D2 between the top surface 132 of the conductive protection layer 130 and the top surface 115b1 of the pad 115b. That is, according to some embodiments, the top surface 132 is lower than the top surface 118b1.

[0087] According to some embodiments, the conductive protection layer 130, the gold-containing layer 126, the palladium-containing layer 124, and the nickel-containing layer 122 are made of different materials. According to some embodiments, the conductive protection layer 130 is made of a metal material (e.g., tin) or an alloy thereof (e.g., a tin alloy). According to some embodiments, the conductive protection layer 130 is formed using a printing process or an electroless plating process.

[0088] According to some embodiments, Figure 1C As shown, a reflow process is performed on the conductive protective layer 130. During the reflow process, the gold-containing layer 126 and the palladium-containing layer 124 are dissolved in the conductive protective layer 130, and an intermetallic compound layer C is formed between the conductive protective layer 130 and the nickel-containing layer 122. According to some embodiments, the intermetallic compound layer C can improve the adhesion between the conductive protective layer 130 and the nickel-containing layer 122.

[0089] According to some embodiments, the intermetallic compound layer C is structurally denser than the conductive protection layer 130, the gold-containing layer 126, and the palladium-containing layer 124. In some embodiments, the thickness T4 of the intermetallic compound layer C is greater than the sum of the thickness T1 of the palladium-containing layer 124 and the thickness T2 of the gold-containing layer 126 (e.g., Figure 1B ). Therefore, according to some embodiments, the intermetallic compound layer C provides stronger protection for the nickel-containing layer 122 than the palladium-containing layer 124 and the gold-containing layer 126. As a result, the intermetallic compound layer C and the conductive protection layer 130 can together protect the nickel-containing layer 122 from being damaged during subsequent processes.

[0090] According to some embodiments, the intermetallic compound layer C is made of the materials of the conductive protection layer 130 and the nickel-containing layer 122. According to some embodiments, the intermetallic compound layer C includes a compound material. For example, the compound material includes tin and nickel, such as Ni3Sn4.

[0091] According to some embodiments, after the reflow process, the conductive protection layer 130 has a (maximum) thickness T3'. According to some embodiments, the thickness T3' is greater than the sum of the thickness T1 of the palladium-containing layer 124 and the thickness T2 of the gold-containing layer 126 (eg, Figure 1B According to some embodiments, the thickness T3' is greater than the thickness T3 (as shown in FIG. Figure 1B shown).

[0092] According to some embodiments, thickness T3' ranges from about 1 μm to about 25 μm. According to some embodiments, thickness T3' ranges from about 1 μm to about 10 μm. In some embodiments, (reflowed) conductive protection layer 130 is thinner than insulating layer 118b over pad 115b.

[0093] According to some embodiments, conductive protection layer 130 has curved top surface 134. In some embodiments, distance D1 between top surface 118b1 of insulating layer 118b and top surface 115b1 of pad 115b is greater than (maximum) distance D3 between curved top surface 134 and top surface 115b1.

[0094] In some embodiments, the conductive protection layer 130 and the insulating layer 118b above the pad 115b surround the groove R1. According to some embodiments, the entire conductive protection layer 130 above one of the pads 115b is in the corresponding opening P2. That is, according to some embodiments, the conductive protection layer 130 does not extend beyond the corresponding opening P2, which prevents the conductive protection layer 130 from contacting the carrier substrate in subsequent processes.

[0095] The design for preventing the conductive protection layer 130 from contacting the carrier substrate in the subsequent process includes the conductive protection layer 130 being thinner than the insulating layer 118b above the pad 115b (eg, Figure 1B As shown), the top surface 132 is lower than the top surface 118b1 (as shown Figure 1B ), and the distance D1 between the top surface 118b1 of the insulating layer 118b and the top surface 115b1 of the pad 115b is greater than the (maximum) distance D3 between the curved top surface 134 and the top surface 115b1 (as shown in Figure 1C In some other embodiments (not shown), according to design requirements, the curved top surface 134 (or top surface 132) is higher than the top surface 118b1.

[0096] According to some embodiments, Figure 1D As shown, the wiring substrate 110 is turned upside down and placed on the carrier substrate 140. According to some embodiments, the carrier substrate 140 is configured to provide temporary mechanical and structural support during subsequent process steps. According to some embodiments, the carrier substrate 140 includes glass, silicon oxide, aluminum oxide, metal, a combination of the foregoing, or similar materials. According to some embodiments, the carrier substrate 140 includes a metal frame.

[0097] According to some embodiments, Figure 1DAs shown, a conductive layer 150 is formed over the pad 115a. According to some embodiments, the conductive layer 150 includes a solder ball. According to some embodiments, the conductive layer 150 is made of a conductive material, such as a metal (e.g., tin) or an alloy thereof (e.g., a tin alloy). According to some embodiments, the formation of the conductive layer 150 includes forming a solder material layer (not shown) over the pad 115a; and reflowing the solder material layer to form the conductive layer 150.

[0098] According to some embodiments, Figure 1E As shown, a thermal compression process is performed on the conductive layer 150 to flatten the top surface 152 of the conductive layer 150. According to some embodiments, as Figure 1F As shown, a flux material layer 160 is formed over the conductive layer 150 and the top surface 118a1 of the insulating layer 118a. The flux material layer 160 is used to ensure bonding between the conductive layer 150 and the conductive bumps over the chip in the subsequent chip bonding process, thereby improving the yield of the chip bonding process.

[0099] In some embodiments, the flux material layer 160 includes tartaric acid, a resin, an amine and / or a solvent. In some embodiments, the amine is an alkyl substituted amine, ethanolamine, ethoxylated amine, or propoxylated amine. In some embodiments, a surfactant, sometimes referred to as a flow modifier, is used. The specific surfactant depends on the compatibility with the flux material layer 160. In some embodiments, the surfactant is anionic, such as a long chain alkyl carboxylic acid, such as lauric acids, stearic acids, or similar materials. According to some embodiments, the flux material layer 160 is formed using a dipping process or a jetting process.

[0100] According to some embodiments, Figure 1G As shown, a chip 170 is provided. According to some embodiments, the chip 170 includes a semiconductor substrate 172, a dielectric layer 174, a conductive pad 176, and an interconnect layer 178.

[0101] According to some embodiments, the semiconductor substrate 172 has a front surface 172a and a rear surface 172b opposite to the front surface 172a. In some embodiments, active elements (e.g., transistors, diodes, or similar elements) and / or passive elements (e.g., resistors, capacitors, inductors, or similar elements) are formed in the semiconductor substrate 172 above or adjacent to the front surface 172a.

[0102] In some embodiments, the semiconductor substrate 172 is made of at least an elemental semiconductor material, including silicon or germanium in a single crystal, polycrystalline or amorphous structure. In some other embodiments, the semiconductor substrate 172 is made of a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide), an alloy semiconductor (e.g., SiGe or GaAsP), or a combination thereof. The semiconductor substrate 172 may also include a multilayer semiconductor, a semiconductor on insulator (SOI) (e.g., silicon on insulator or germanium on insulator), or a combination thereof.

[0103] According to some embodiments, a dielectric layer 174 is formed over the front surface 172a. The dielectric layer 174 is made of a polymer material, such as polyphenylene sulfide. A polybenzoxazole (PBO) layer, a polyimide (polyimide) layer, a benzocyclobutene (BCB) layer, an epoxy resin (epoxy) layer, a photosensitive material layer or other suitable materials.

[0104] According to some embodiments, conductive pad 176 is formed in dielectric layer 174. According to some embodiments, conductive pad 176 is electrically connected to a device (not shown) formed in / over semiconductor substrate 172. According to some embodiments, conductive pad 176 is made of a conductive material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), or tantalum alloy.

[0105] According to some embodiments, interconnect layer 178 is formed over dielectric layer 174. According to some embodiments, interconnect layer 178 includes a dielectric layer (not shown) and a conductive interconnect structure (not shown) in the dielectric layer.

[0106] According to some embodiments, Figure 1G As shown, conductive bumps 180 are formed over interconnect layer 178. The conductive interconnect structure of interconnect layer 178 is electrically connected to conductive bumps 180 and conductive pads 176 in accordance with some embodiments.

[0107] According to some embodiments, the conductive bump 180 is made of a conductive material, such as tin (Sn) or an alloy thereof. In some other embodiments, the conductive bump 180 is made of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy.

[0108] According to some embodiments, Figure 1GAs shown, a flux material layer 190 is formed over the conductive bump 180 and the surface 178a of the interconnect layer 178. The flux material layer 190 is used to ensure the bonding between the conductive bump 180 and the conductive layer 150 in the subsequent chip bonding process (eg, Figure 1F As shown), the yield of the chip bonding process is improved.

[0109] In some embodiments, the flux material layer 190 comprises tartaric acid, a resin, an amine and / or a solvent. In some embodiments, the amine is an alkyl-substituted amine, an ethanolamine, an ethoxylated amine, or a propoxylated amine. In some embodiments, a surfactant, sometimes referred to as a flow modifier, is used. The specific surfactant depends on the compatibility with the flux material layer 190. In some embodiments, the surfactant is anionic, such as a long-chain alkyl carboxylic acid, such as lauric acid, stearic acid, or a similar material. According to some embodiments, the flux material layer 190 is formed using a dipping process or a spraying process.

[0110] According to some embodiments, Figure 1H As shown, the chip 170 is bonded to the wiring substrate 110 via the conductive bumps 210 and the flux layer 220. According to some embodiments, the flux layer 220 surrounds the conductive bumps 210.

[0111] According to some embodiments, conductive bump 210 is between and connects pad 115a and chip 170. According to some embodiments, conductive bump 210 is formed of conductive layer 150 and conductive bump 180. According to some embodiments, flux layer 220 is formed of flux material layers 160 and 190.

[0112] According to some embodiments, the conductive protection layer 130 is thinner than the conductive bump 210 . That is, according to some embodiments, the (maximum) thickness T3 ′ of the conductive protection layer 130 is smaller than the thickness T5 of the conductive bump 210 .

[0113] According to some embodiments, Fig. 1I As shown, the flux layer 220 is removed. According to some embodiments, the process of removing the flux layer 220 includes a dipping process or a spraying process. For example, according to some embodiments, in the dipping process, the wiring substrate 110 is dipped into the desoldering solution F contained in the tank E. According to some embodiments, the flux layer 220 can be dissolved in the desoldering solution F.

[0114] According to some embodiments, the conductive protection layer 130 and the intermetallic compound layer C separate the nickel-containing layer 122 from the desoldering solution F. According to some embodiments, the conductive protection layer 130 directly contacts the desoldering solution F.

[0115] According to some embodiments, the desoldering solution F includes an aqueous liquid (eg, deionized water) and a solvent, such as hydrofluorocarbons (HFC's), hydrochlorofluorocarbons (HCFC's), chlorofluorocarbons, alcohols, terpenes, and combinations thereof.

[0116] According to some embodiments, Figure 1J As shown, the wiring substrate 110 is disposed above the carrier substrate 230. According to some embodiments, the carrier substrate 230 is configured to provide temporary mechanical and structural support during subsequent process steps. According to some embodiments, the carrier substrate 230 comprises glass, silicon oxide, aluminum oxide, metal, combinations thereof, etc. According to some embodiments, the carrier substrate 230 comprises a metal frame.

[0117] According to some embodiments, Figure 1J As shown, an underfill layer 240 is formed between the chip 170 and the wiring substrate 110. According to some embodiments, the underfill layer 240 includes an insulating material, such as a polymer material.

[0118] According to some embodiments, Figure 1J As shown, a molding layer 250 is formed over the wiring substrate 110, the chip 170, and the underfill layer 240. According to some embodiments, the molding layer 250 encapsulates the chip 170. According to some embodiments, the molding layer 250 surrounds the chip 170, the conductive bumps 210, and the underfill layer 240. According to some embodiments, the molding layer 250 is made of an insulating material, such as a polymer material.

[0119] According to some embodiments, Figure 1K As shown, the wiring substrate 110 is turned upside down and placed on the carrier substrate G. According to some embodiments, the carrier substrate G is configured to provide temporary mechanical and structural support during subsequent process steps. According to some embodiments, the carrier substrate G comprises glass, silicon oxide, aluminum oxide, metal, a combination of the foregoing, or similar materials. According to some embodiments, the carrier substrate G comprises a metal frame.

[0120] According to some embodiments, Figure 1K As shown, a conductive structure 260a is formed above the conductive protection layer 130. According to some embodiments, the conductive structure 260a is made of a conductive material, such as a metal (such as Sn) or the aforementioned alloy. In some embodiments, the conductive structure 260a and the conductive protection layer 130 are made of the same conductive material, such as tin or a tin alloy.

[0121] According to some embodiments, Figure 1K and Figure 1L As shown, a reflow process is performed on the conductive structure 260 a and the conductive protection layer 130 to melt and mix the conductive structure 260 a and the conductive protection layer 130 together to form a conductive bump 260 .

[0122] In some embodiments, a distance D4 between a top surface 262 of the conductive bump 260 and a top surface 115b1 of the pad 115b is greater than a distance D1 between a top surface 118b1 of the insulating layer 118b and the top surface 115b1. According to some embodiments, the conductive bump 260 is wider and thicker than the conductive bump 210. Therefore, according to some embodiments, in a subsequent process, the conductive bump 260 can be bonded to a wiring substrate having a pad larger than that of the chip 170.

[0123] According to some embodiments, Figure 1L As shown, a cutting process is performed along a cutting line A over the wiring substrate 110 to cut through the wiring substrate 110 and the molding layer 250 to form a chip package structure 270 .

[0124] According to some embodiments, Figure 1M As shown, the chip package structure 270 is bonded to a wiring substrate 280 via conductive bumps 260. The wiring substrate 280 includes a printed circuit board or other suitable wiring substrates. According to some embodiments, the wiring substrate 280 includes an insulating layer 282, a wiring layer 284, conductive vias 286, and pads 288.

[0125] According to some embodiments, wiring layers 284 and conductive vias 286 are in insulating layer 282. According to some embodiments, pads 288 are over insulating layer 282. According to some embodiments, conductive vias 286 electrically connect between wiring layers 284 and between wiring layers 284 and pads 288.

[0126] According to some embodiments, the wiring layer 284, the conductive via 286 and the pad 288 are made of a conductive material, such as a metal material or an alloy thereof, wherein the metal material includes aluminum, copper or tungsten.

[0127] According to some embodiments, in this step, a chip package structure (or board-level package structure) 100 is substantially formed. According to some embodiments, the chip package structure 100 includes a chip package structure 270, a conductive bump 260, and a wiring substrate 280. According to some embodiments, the chip package structure 100 is a ball grid array (BGA) package structure.

[0128] FIG. 2A to FIG. 2B is a cross-sectional schematic diagram of various stages of a process for forming a chip packaging structure according to some embodiments. Figure 2AAs shown, in Figure 1J After the step of , a cutting process is performed along the cutting line A over the wiring substrate 110 to cut through the wiring substrate 110 and the mold layer 250 to form a chip package structure 290 .

[0129] According to some embodiments, Figure 2B As shown, a wiring substrate 280a is provided. According to some embodiments, the wiring substrate 280a is similar to Figure 1M The wiring substrate 280 of FIG. 280a further includes an elastic contact structure 289. According to some embodiments, the elastic contact structure 289 is mounted to the pad 288.

[0130] According to some embodiments, Figure 2B As shown, the chip package structure 290 is bonded to the wiring substrate 280a via the conductive protection layer 130 and the elastic contact structure 289. According to some embodiments, the elastic contact structure 289 directly contacts the conductive protection layer 130. According to some embodiments, the elastic contact structure 289 is an elastic metal strip.

[0131] According to some embodiments, in this step, a chip packaging structure (or board-level packaging structure) 200 is substantially formed. According to some embodiments, the chip packaging structure 200 includes a chip packaging structure 290 and a wiring substrate 280a. According to some embodiments, the chip packaging structure 200 is a land grid array (LGA) packaging structure.

[0132] Figure 3 3 is a schematic cross-sectional view of a chip packaging structure (or board-level packaging structure) 300 according to some embodiments. Figure 3 As shown, the chip packaging structure 300 is similar to Figure 2B The chip package structure 200 is shown in FIG. 1 , except that the elastic contact structure 289 of the chip package structure 300 penetrates the conductive protection layer 130. The conductive protection layer 130 can fix the elastic contact structure 289 to the pad 115b to improve the yield of the chip package structure 300. According to some embodiments, the chip package structure 300 is a land grid array (LGA) package structure.

[0133] Figure 4A to Figure 4H is a cross-sectional schematic diagram of various stages of a process for forming a chip packaging structure according to some embodiments. Figure 4A As shown, in Fig. 1I After the step of , the wiring substrate 110 is disposed on the carrier substrate 230. According to some embodiments, as Figure 4A As shown, a portion of the conductive layer 150 is not bonded to the chip 170 .

[0134] According to some embodiments, Figure 4A As shown, an underfill layer 240 is formed between the chip 170 and the wiring substrate 110. According to some embodiments, as Figure 4A As shown, a flux layer 420 is formed over a portion of the conductive layer 150 and the top surface 118a1 of the insulating layer 118a.

[0135] In some embodiments, the flux layer 420 comprises tartaric acid, a resin, an amine and / or a solvent. In some embodiments, the amine is an alkyl-substituted amine, an ethanolamine, an ethoxylated amine, or a propoxylated amine. In some embodiments, a surfactant, sometimes referred to as a flow modifier, is used. The specific surfactant depends on the compatibility with the flux layer 420. In some embodiments, the surfactant is anionic, such as a long chain alkyl carboxylic acid, such as lauric acid, stearic acid, or a similar material. According to some embodiments, the flux layer 420 is formed using a dipping process or a spraying process.

[0136] According to some embodiments, Figure 4B As shown, device 430 is bonded to wiring substrate 110 via conductive bump 410. According to some embodiments, conductive bump 410 is partially formed by a portion of conductive layer 150. According to some embodiments, device 430 includes an active device or a passive device such as a resistor, capacitor, or inductor.

[0137] According to some embodiments, Figure 4C As shown, a desoldering process is used to remove the flux layer 420. According to some embodiments, as Figure 4C As shown, a molding layer 440 is formed over the wiring substrate 110, the chip 170, the underfill layer 240, the device 430, and the conductive bumps 410. The molding layer 440 encapsulates the chip 170 and the device 430 according to some embodiments.

[0138] According to some embodiments, the mold layer 440 surrounds the chip 170, the conductive bumps 210, the underfill layer 240, the device 430, and the conductive bumps 410. According to some embodiments, the mold layer 440 is made of an insulating material, such as a polymer material.

[0139] According to some embodiments, Figure 4D As shown, the wiring substrate 110 is turned upside down and placed on the carrier substrate 450. According to some embodiments, the carrier substrate 450 is configured to provide temporary mechanical and structural support during subsequent process steps. According to some embodiments, the carrier substrate 450 includes glass, silicon oxide, aluminum oxide, metal, a combination of the foregoing, or a similar material. According to some embodiments, the carrier substrate 450 includes a metal frame.

[0140] According to some embodiments, Figure 4DAs shown, a solder flux layer 460 is formed over a portion of the conductive protective layer 130. In some embodiments, the solder flux layer 460 comprises tartaric acid, resin, amine and / or solvent. In some embodiments, the amine is an alkyl-substituted amine, ethanolamine, ethoxylated amine or propoxylated amine.

[0141] In some embodiments, a surfactant, sometimes referred to as a flow modifier, is used. The specific surfactant depends on the compatibility with the flux layer 460. In some embodiments, the surfactant is anionic, such as a long chain alkyl carboxylic acid, such as lauric acid, stearic acid, or similar materials. According to some embodiments, a dipping process or a spraying process is used to form the flux layer 460.

[0142] According to some embodiments, Figure 4E As shown, device 470 is bonded to wiring substrate 110 via conductive bump 480. According to some embodiments, conductive bump 480 is partially formed by a portion of conductive protection layer 130. According to some embodiments, device 470 includes an active device or a passive device such as a resistor, capacitor, or inductor.

[0143] According to some embodiments, Figure 4F As shown, a desoldering process is used to remove the flux layer 460. According to some embodiments, as Figure 4G As shown, Figure 1K to Figure 1L The steps of forming the conductive bump 260 and forming a chip packaging structure (or a board-level packaging structure) 400 are performed. According to some embodiments, as Figure 4H As shown, Figure 1M The chip package structure 400 is bonded to the wiring substrate 280 via the conductive bumps 260 .

[0144] According to some embodiments, in this step, a chip package structure 490 is substantially formed. According to some embodiments, the chip package structure 490 includes the chip package structure 400, the conductive bumps 260 and the wiring substrate 280. According to some embodiments, the chip package structure 490 is a ball grid array (BGA) package structure.

[0145] Figure 5A to Figure 5B is a cross-sectional schematic diagram of various stages of a process for forming a chip packaging structure according to some embodiments. Figure 5A As shown, in Figure 4F After the step of , a cutting process is performed along the cutting line A over the wiring substrate 110 to cut through the wiring substrate 110 and the molding layer 440 to form a chip package structure 510 .

[0146] According to some embodiments, Figure 5BAs shown, the chip package structure 510 is bonded to the wiring substrate 280a via the conductive protection layer 130 and the elastic contact structure 289. According to some embodiments, the elastic contact structure 289 directly contacts the conductive protection layer 130. According to some embodiments, the elastic contact structure 289 is an elastic metal strip. According to some embodiments, the elastic contact structure 289 penetrates the conductive protection layer 130.

[0147] According to some embodiments, in the step, a chip package structure (or board-level package structure) 520 is generally formed. According to some embodiments, the chip package structure 520 includes a chip package structure 510 and a wiring substrate 280a. According to some embodiments, the chip package structure 520 is a land grid array (LGA) package structure.

[0148] Figure 6 is a schematic cross-sectional view of a chip packaging structure 600 according to some embodiments. Figure 6 As shown, the chip packaging structure 600 is similar to Figure 1M The chip package structure 100 of the embodiment of the present invention further includes an adhesive layer 610 and a heat dissipation cover 620 in addition to the chip package structure 600. According to some embodiments, the chip package structure 600 does not include the mold layer 250 of the chip package structure 100.

[0149] According to some embodiments, the adhesive layer 610 is formed over the wiring substrate 110. According to some embodiments, the adhesive layer 610 surrounds the chip 170 and the underfill layer 240. According to some embodiments, the adhesive layer 610 has a ring shape. According to some embodiments, the heat dissipation cover 620 is disposed over the chip 170 and the adhesive layer 610.

[0150] According to some embodiments, the adhesive layer 610 is made of a polymer, such as epoxy or silicone. According to some embodiments, a dispensing process is used to form the adhesive layer 610. According to some embodiments, the heat dissipation cover 620 is made of a material with high thermal conductivity, such as a metal material (aluminum or copper), an alloy material (such as stainless steel), or aluminum silicon carbide (AlSiC).

[0151] Figure 7 is a schematic cross-sectional view of a chip packaging structure 700 according to some embodiments. Figure 7 As shown, the chip packaging structure 700 is similar to Figure 1M The chip package structure 100 of the embodiment of the present invention further includes an adhesive layer 710, a heat ring 720, an adhesive layer 730 and a heat dissipation plate 740 in addition to the chip package structure 700. According to some embodiments, the chip package structure 700 does not have the mold layer 250 of the chip package structure 100.

[0152] According to some embodiments, the adhesive layer 710 is formed over the wiring substrate 110. According to some embodiments, the adhesive layer 710 surrounds the chip 170 and the underfill layer 240. According to some embodiments, the adhesive layer 710 has a ring shape. According to some embodiments, the heat ring 720 is disposed on the adhesive layer 710.

[0153] According to some embodiments, the adhesive layer 730 is formed on the heat ring 720. According to some embodiments, the adhesive layer 730 has a ring shape. According to some embodiments, the heat plate 740 is disposed above the adhesive layer 730 and the chip 170.

[0154] According to some embodiments, the adhesive layers 710 and 730 are made of a polymer, such as epoxy or silicone. According to some embodiments, the adhesive layers 710 and 730 are formed using a dispensing process.

[0155] According to some embodiments, the heat dissipation ring 720 and the heat dissipation plate 740 are made of a material with high thermal conductivity, such as a metal material (aluminum or copper), an alloy material (such as stainless steel), or aluminum silicon carbide (AlSiC).

[0156] Figure 8 is a cross-sectional view of a chip packaging structure 800 according to some embodiments. Figure 8 As shown, the chip packaging structure 800 is similar to Figure 3 The chip package structure 300 further includes an adhesive layer 610 and a heat dissipation cover 620 in addition to the chip package structure 800 .

[0157] According to some embodiments, the chip package structure 800 does not have the mold layer 250 of the chip package structure 300. According to some embodiments, the elastic contact structure 289 passes through the conductive protection layer 130. According to some embodiments, the elastic contact structure 289 directly contacts the intermetallic compound layer C.

[0158] According to some embodiments, the adhesive layer 610 is formed over the wiring substrate 110. According to some embodiments, the adhesive layer 610 surrounds the chip 170 and the underfill layer 240. According to some embodiments, the adhesive layer 610 has a ring shape. According to some embodiments, the heat dissipation cover 620 is disposed over the chip 170 and the adhesive layer 610.

[0159] According to some embodiments, the adhesive layer 610 is made of a polymer, such as epoxy or polysilicon. According to some embodiments, a dispensing process is used to form the adhesive layer 610. According to some embodiments, the heat dissipation cover 620 is made of a material with high thermal conductivity, such as a metal material (aluminum or copper), an alloy material (such as stainless steel), or aluminum silicon carbide (AlSiC).

[0160] Fig. 9is a schematic cross-sectional view of a chip package structure 900 according to some embodiments. Fig. 9 As shown, the chip packaging structure 900 is similar to Figure 3 The chip package structure 300 of the embodiment of the present invention further includes an adhesive layer 710 , a heat dissipation ring 720 , an adhesive layer 730 and a heat dissipation plate 740 in addition to the chip package structure 900 . According to some embodiments, the chip package structure 900 does not include the mold layer 250 of the chip package structure 300 .

[0161] According to some embodiments, the adhesive layer 710 is formed over the wiring substrate 110. According to some embodiments, the adhesive layer 710 surrounds the chip 170 and the underfill layer 240. According to some embodiments, the adhesive layer 710 has a ring shape. According to some embodiments, the heat ring 720 is disposed over the adhesive layer 710.

[0162] According to some embodiments, the adhesive layer 730 is formed over the heat ring 720 . According to some embodiments, the adhesive layer 730 has a ring shape. According to some embodiments, the heat plate 740 is disposed over the adhesive layer 730 and the chip 170 .

[0163] According to some embodiments, the adhesive layers 710 and 730 are made of a polymer, such as epoxy or silicone. According to some embodiments, the adhesive layers 710 and 730 are formed using a dispensing process.

[0164] According to some embodiments, the heat dissipation ring 720 and the heat dissipation plate 740 are made of a material with high thermal conductivity, such as a metal material (aluminum or copper), an alloy material (such as stainless steel), or aluminum silicon carbide (AlSiC).

[0165] The processes and materials used to form the chip package structures 200 , 300 , 490 , 520 , 600 , 700 , 800 , and 900 may be similar or identical to those described above for forming the chip package structure 100 .

[0166] According to some embodiments, a chip packaging structure and a method for forming the same are provided. The method (for forming the chip packaging structure) forms a conductive protective layer above the nickel-containing layer above the solder pad before the reflow process to protect the nickel-containing layer from being oxidized during the reflow process. Therefore, the adhesion between the solder pad and the conductive bump subsequently formed between the solder pad and the chip is improved. As a result, the yield of the chip packaging structure is improved.

[0167] According to some embodiments, a method for forming a chip packaging structure is provided. The method includes providing a wiring substrate. The wiring substrate includes a substrate, a first pad, a second pad and an insulating layer. The first pad and the second pad are respectively above the first surface and the second surface of the substrate. The insulating layer is above the first surface and partially covers the first pad, and the first pad is wider than the second pad. The method includes sequentially forming a nickel-containing layer and a gold-containing layer above the first pad. The method includes forming a conductive protective layer to cover the gold-containing layer above the nickel-containing layer. The conductive protective layer, the gold-containing layer and the nickel-containing layer are made of different materials, and the first distance between the first top surface of the insulating layer and the second top surface of the first pad is greater than the second distance between the third top surface of the conductive protective layer and the second top surface of the first pad. The method includes bonding the chip to the wiring substrate via a conductive bump and a solder flux layer surrounding the conductive bump. The conductive bump is between the second pad and the chip. The method includes removing the solder flux layer while the conductive protective layer covers the nickel-containing layer.

[0168] In some embodiments, the method further comprises: before bonding the chip to the wiring substrate, reflowing the conductive protection layer, wherein the gold-containing layer is dissolved in the conductive protection layer and an intermetallic compound layer is formed between the conductive protection layer and the nickel-containing layer.

[0169] In some embodiments, after the conductive protection layer is reflowed, the conductive protection layer has a curved top surface.

[0170] In some embodiments, the conductive protection layer covers the entire fourth top surface of the nickel-containing layer.

[0171] In some embodiments, the method further includes: before forming the gold-containing layer over the first bonding pad, forming a palladium-containing layer over the nickel-containing layer, wherein the gold-containing layer is formed over the palladium-containing layer.

[0172] In some embodiments, the insulating layer has an opening exposing a portion of the first pad, the nickel-containing layer, the palladium-containing layer, and the gold-containing layer are in the opening and cover the portion, and the conductive protection layer is entirely in the opening.

[0173] In some embodiments, the method further includes: before bonding the chip to the wiring substrate, forming a conductive layer over the second pad, wherein a portion of the first conductive bump is formed by the conductive layer.

[0174] In some embodiments, the wiring substrate further includes a third pad above the first surface, and a nickel-containing layer, a gold-containing layer, and a conductive protective layer are further formed above the third pad. The method further includes: after removing the first flux layer, joining the device to the third pad via a second conductive bump and a second flux layer surrounding the second conductive bump, wherein the second conductive bump is partially formed by the conductive protective layer above the third pad; and removing the second flux layer.

[0175] In some embodiments, the removing of the first flux layer includes using a desoldering solution to remove the first flux layer, and the conductive protective layer separates the nickel-containing layer from the desoldering solution.

[0176] In some embodiments, the conductive protective layer is denser than the gold containing layer.

[0177] According to some embodiments, a method for forming a chip packaging structure is provided. The method includes providing a wiring substrate. The wiring substrate includes a substrate, a first pad, a second pad and an insulating layer, the first pad and the second pad are respectively above the first surface and the second surface of the substrate, and the insulating layer is above the first surface and the first pad and has an opening, and the opening partially exposes the first pad. The method includes sequentially forming a nickel-containing layer and a gold-containing layer in the opening. The method includes forming a conductive protective layer above the gold-containing layer, wherein the first porosity of the conductive protective layer is less than the second porosity of the gold-containing layer, and the conductive protective layer is thinner than the insulating layer above the first pad. The method includes bonding the chip to the second pad of the wiring substrate via a first conductive bump after the conductive protective layer is formed above the gold-containing layer. The method includes forming a conductive structure above the conductive protective layer after bonding the chip to the second pad. The method includes reflowing the conductive structure and the conductive protective layer to melt and mix the conductive structure and the conductive protective layer together, thereby forming a second conductive bump.

[0178] In some embodiments, the conductive protection layer is thinner than the insulating layer over the first pad.

[0179] In some embodiments, the conductive structure and the conductive protection layer are made of the same material.

[0180] In some embodiments, the conductive protective layer is thicker than the gold containing layer.

[0181] In some embodiments, the first pad is wider than the second pad, and the second conductive bump is wider and thicker than the first conductive bump.

[0182] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a first wiring substrate, the first wiring substrate includes a substrate, a first pad, a second pad and an insulating layer, the first pad and the second pad are respectively located above the first surface and the second surface of the substrate, the insulating layer is above the first surface and partially covers the first pad, and the first pad is wider than the second pad. The chip packaging structure includes a nickel-containing layer above the first pad. The chip packaging structure includes a conductive protective layer above the nickel-containing layer. The conductive protective layer includes tin, and the conductive protective layer and the insulating layer above the first pad surround the groove. The chip packaging structure includes a chip above the second surface of the substrate. The chip packaging structure includes a conductive bump between the second pad and the chip.

[0183] In some embodiments, the chip packaging structure further includes: a second wiring substrate, wherein the first wiring substrate is above the second wiring substrate, the second wiring substrate includes a second substrate and an elastic contact structure mounted to the second substrate, and the elastic contact structure directly contacts the conductive protection layer.

[0184] In some embodiments, the resilient contact structure is a resilient metal strip.

[0185] In some embodiments, the elastic contact structure penetrates the conductive protection layer.

[0186] In some embodiments, the chip package structure further comprises: an intermetallic compound layer between the conductive protection layer and the nickel-containing layer, wherein the intermetallic compound layer comprises tin and nickel.

[0187] The above summarizes the components of several embodiments so that those skilled in the art can better understand the aspects of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the concept and scope of the embodiments of the present invention, and they can make various changes, substitutions and adjustments without violating the concept and scope of the embodiments of the present invention.

Claims

1. A method for forming a chip packaging structure, comprising: A wiring substrate is provided, comprising a substrate, a first pad, a second pad and an insulating layer, wherein the first pad and the second pad are respectively above a first surface and a second surface of the substrate, the insulating layer is above the first surface and partially covers the first pad, and the first pad is wider than the second pad; Sequentially forming a nickel-containing layer and a gold-containing layer above the first pad; Forming a conductive protective layer to cover the gold-containing layer above the nickel-containing layer, wherein the conductive protective layer, the gold-containing layer and the nickel-containing layer are made of different materials, and a first distance between a first top surface of the insulating layer and a second top surface of the first pad is greater than a second distance between a third top surface of the conductive protective layer and the second top surface; bonding a chip to the wiring substrate via a first conductive bump and a first solder flux layer surrounding the first conductive bump, wherein the first conductive bump is between the second pad and the chip and connects the second pad and the chip; and The first soldering flux layer is removed while the conductive protection layer covers the nickel-containing layer.

2. The method for forming a chip package structure according to claim 1, further comprising: Before bonding the chip to the wiring substrate, the conductive protection layer is reflowed, wherein the gold-containing layer is dissolved in the conductive protection layer and an intermetallic compound layer is formed between the conductive protection layer and the nickel-containing layer. 3 . The method for forming a chip package structure according to claim 2 , wherein after the conductive protection layer is reflowed, the conductive protection layer has a curved top surface. 4 . The method for forming a chip package structure according to claim 1 , wherein the conductive protection layer covers an entire fourth top surface of the nickel-containing layer.

5. The method for forming a chip package structure according to claim 1, further comprising: Before forming the gold-containing layer on the first pad, a palladium-containing layer is formed on the nickel-containing layer, wherein the gold-containing layer is formed on the palladium-containing layer.

6. The method for forming a chip packaging structure as claimed in claim 5, wherein the insulating layer has an opening exposing a portion of the first pad, the nickel-containing layer, the palladium-containing layer and the gold-containing layer are in the opening and cover the portion, and the conductive protection layer is entirely in the opening.

7. The method for forming a chip package structure according to claim 1, further comprising: Before bonding the chip to the wiring substrate, a conductive layer is formed above the second bonding pad, wherein a portion of the first conductive bump is formed by the conductive layer.

8. The method for forming a chip package structure according to claim 1, wherein the wiring substrate further comprises a third pad above the first surface, the nickel-containing layer, the gold-containing layer and the conductive protection layer are further formed above the third pad, and the method further comprises: After removing the first flux layer, bonding a device to the third pad via a second conductive bump and a second flux layer surrounding the second conductive bump, wherein the second conductive bump is partially formed by the conductive protection layer over the third pad; and The second flux layer is removed. 9 . The method for forming a chip package structure according to claim 1 , wherein removing the first flux layer comprises using a flux removal solution to remove the first flux layer, and the conductive protection layer separates the nickel-containing layer from the flux removal solution. 10 . The method for forming a chip package structure according to claim 1 , wherein the conductive protection layer is denser than the gold-containing layer.

11. A method for forming a chip packaging structure, comprising: A wiring substrate is provided, comprising a substrate, a first pad, a second pad and an insulating layer, wherein the first pad and the second pad are respectively above a first surface and a second surface of the substrate, and the insulating layer is above the first surface and the first pad and has an opening to partially expose the first pad; forming a nickel-containing layer and a gold-containing layer in the opening in sequence; forming a conductive protective layer on the gold-containing layer, wherein a first porosity of the conductive protective layer is less than a second porosity of the gold-containing layer; After the conductive protection layer is formed on the gold-containing layer, a chip is bonded to the second pad of the wiring substrate via a first conductive bump; After bonding the chip to the second pad, forming a conductive structure over the conductive protection layer; and The conductive structure and the conductive protection layer are reflowed to melt and mix the conductive structure and the conductive protection layer together, thereby forming a second conductive bump. 12 . The method for forming a chip package structure according to claim 11 , wherein the conductive protection layer is thinner than the insulating layer above the first bonding pad. 13 . The method for forming a chip package structure according to claim 11 , wherein the conductive structure and the conductive protection layer are made of the same material. 14 . The method for forming a chip package structure according to claim 11 , wherein the conductive protection layer is thicker than the gold-containing layer. 15 . The method for forming a chip package structure according to claim 11 , wherein the first bonding pad is wider than the second bonding pad, and the second conductive bump is wider and thicker than the first conductive bump.

16. A chip packaging structure, comprising: A first wiring substrate, comprising a substrate, a first pad, a second pad and an insulating layer, wherein the first pad and the second pad are respectively located above a first surface and a second surface of the substrate, the insulating layer is above the first surface and partially covers the first pad, and the first pad is wider than the second pad; a nickel-containing layer over the first pad; a conductive protection layer over the nickel-containing layer, wherein the conductive protection layer comprises tin, and the conductive protection layer and the insulating layer over the first pad surround a groove; a chip on the second surface of the substrate; as well as A conductive bump is between the second pad and the chip.

17. The chip packaging structure according to claim 16, further comprising: A second wiring substrate, wherein the first wiring substrate is above the second wiring substrate, the second wiring substrate comprises a second substrate and an elastic contact structure mounted to the second substrate, and the elastic contact structure directly contacts the conductive protection layer. The chip package structure according to claim 17 , wherein the elastic contact structure is an elastic metal strip.

19. The chip package structure according to claim 17, wherein the elastic contact structure penetrates into the conductive protection layer.

20. The chip packaging structure according to claim 16, further comprising: An intermetallic compound layer is between the conductive protection layer and the nickel-containing layer, wherein the intermetallic compound layer includes tin and nickel.

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