Chamfer etching apparatus and semiconductor device manufacturing method

Abstract

The present disclosure provides a bevel etch apparatus and a semiconductor device manufacturing method. A bevel etch apparatus includes a chuck plate configured to receive a substrate, a lower plasma exclusion zone (PEZ) ring around a perimeter of the chuck plate, a cover plate on the chuck plate, and an upper PEZ ring around a perimeter of the cover plate. The lower PEZ ring includes a ring base and a protrusion extending upward from an edge of the ring base and around a lower portion of a sidewall of the substrate.

Description

Technical Field

[0001] The present invention relates to apparatus and methods for manufacturing semiconductor devices, and more specifically, to an apparatus for bevel etching a substrate edge and a method for manufacturing semiconductor devices using the apparatus. Background Technology

[0002] The growing demand for high capacity, thinness, and compact size in semiconductor devices and electronic products using them has led to the development of various new packaging technologies. For example, semiconductor devices can include application processors, memory devices, and image sensors. Packaging technologies can integrate application processors, memory devices, and image sensors into a single chip. Summary of the Invention

[0003] Some exemplary embodiments of the present invention provide a bevel etching apparatus that can reduce or prevent plasma-induced damage to the bottom surface of a substrate.

[0004] Some exemplary embodiments of the present invention provide a method for manufacturing a semiconductor device that can reduce defects at the substrate edge.

[0005] According to some exemplary embodiments of the present invention, a chamfering etching apparatus may include: a chuck plate configured to receive a substrate; a lower plasma isolation zone (PEZ) ring surrounding the periphery of the chuck plate; a cover plate on the chuck plate; and an upper PEZ ring surrounding the periphery of the cover plate. The lower PEZ ring may include: a ring base; and a protrusion extending upward from the edge of the ring base to surround the lower portion of the sidewall of the substrate.

[0006] According to some exemplary embodiments of the present invention, a chamfering etching apparatus may include: a chamber; a chuck plate in the chamber configured to receive a substrate; a lower PEZ ring surrounding the periphery of the chuck plate, the lower PEZ ring including an outer wall surrounding a lower portion of a side surface of the substrate; a cover plate on the chuck plate; an upper PEZ ring surrounding the periphery of the cover plate and on the lower PEZ ring; and a bias electrode adjacent to the upper PEZ ring and the lower PEZ ring.

[0007] According to some exemplary embodiments of the present invention, a method for manufacturing a semiconductor device may include: forming a first semiconductor device on a first substrate; forming a second semiconductor device on a second substrate; etching an upper corner of the second substrate to form a stepped groove, the upper corner being radially spaced from the second semiconductor device; and bonding the second semiconductor device to the first semiconductor device. Attached Figure Description

[0008] Figure 1 A flowchart is shown, illustrating an example of a semiconductor device manufacturing method conceived according to the present invention.

[0009] Figures 2 to 7 A sectional view is shown, which shows Figure 1 Semiconductor device manufacturing methods.

[0010] Figure 8 A cross-sectional view is shown, which illustrates the etching. Figure 3 The chamfering etching apparatus for the upper corner of the second substrate is shown.

[0011] Figure 9 A sectional view is shown, which shows Figure 8 Examples of chuck plates, lower plasma isolation zone (PEZ) rings, cover plates, and upper PEZ rings are shown.

[0012] Figure 10 A perspective view is shown, which shows Figure 9 The example shown is a lower PEZ ring. Detailed Implementation

[0013] Figure 1 An example of a semiconductor device manufacturing method according to the present invention is shown. Figures 2 to 7 A sectional view is shown, which shows Figure 1 Semiconductor device manufacturing methods.

[0014] Reference Figure 1 and Figure 2 The first manufacturing apparatus can form a first semiconductor device 102 on a first substrate W1 (S10). The first manufacturing apparatus may include a film deposition apparatus, a photolithography apparatus, and an etching apparatus, but the inventive concept is not limited thereto. For example, the first substrate W1 may include a silicon wafer. The first substrate W1 may have a first diameter D1 of approximately 300 mm, but the inventive concept is not limited thereto. The first semiconductor device 102 may be formed on the top surface of the first substrate W1. For example, the first semiconductor device 102 may be a memory device. The first semiconductor device 102 may include, for example, a DRAM device or a NAND flash memory device. Alternatively, the first semiconductor device 102 may include an application processor, but the inventive concept is not limited thereto.

[0015] Reference Figure 1 and Figure 3The second manufacturing apparatus can form the second semiconductor device 112 on the second substrate W2 (S20). The second manufacturing apparatus can be the same as the first manufacturing apparatus. Furthermore, the second substrate W2 can be the same as the first substrate W1. For example, the second substrate W2 can include a silicon wafer. The second substrate W2 can have a second diameter D2 of approximately 300 mm. The second semiconductor device 112 can be formed on the top surface of the second substrate W2. For example, the second semiconductor device 112 can include an image sensor.

[0016] Figure 8 Etching shown Figure 3 An example of a chamfering etching apparatus 100 for the upper corner of the second substrate W2 is shown. As used herein, the term "upper corner" may refer to a portion or region defined by the edge of the top surface of the second substrate W2 and the upper portion of the sidewall or side surface of the second substrate W2. The upper corner may extend around the entire perimeter of the second substrate W2.

[0017] Reference Figure 1 , Figure 4 and Figure 8 The chamfering etching apparatus 100 can etch or trim the upper corner of the second substrate W2 to form a stepped groove 114 (S30). The chamfering etching apparatus 100 can locally provide plasma P to the upper corner of the second substrate W2 to form the stepped groove 114. The stepped groove 114 can be formed to have an L-shape or an L-shaped cross-section. For example, the stepped groove 114 can have a first width WD1 of about 0.5 mm to about 3 mm and a first height H1 of about 3 μm to about 30 μm.

[0018] Reference Figure 8 The chamfering etching apparatus 100 may include a chamber 10, a chuck plate 20, a lower plasma isolation zone (PEZ) ring 30, a bias electrode 40, a cover plate 50, and an upper PEZ ring 60.

[0019] The chamber 10 can provide a hermetically sealed or open space to the second substrate W2. The chamber 10 can have a vacuum pressure lower than atmospheric pressure.

[0020] A chuck plate 20 may be disposed within the chamber 10. The chuck plate 20 may receive a second substrate W2. The chuck plate 20 may support the center of the second substrate W2. For example, the chuck plate 20 may include a chuck base 22 and a dielectric layer 24. The chuck base 22 may include an aluminum alloy. The dielectric layer 24 may be disposed on the chuck base 22. The dielectric layer 24 may include aluminum oxide (Al2O3), but the inventive concept is not limited thereto.

[0021] A power source 26 can be provided outside the chamber 10. The power source 26 can be connected to the chuck base 22 to provide a power source 28. The chuck base 22 can use the power source 28 to generate plasma P at the edge of the second substrate W2. For example, the power source 28 can have a frequency of approximately 13.56 MHz.

[0022] Figure 9 Show Figure 8 The illustration shows an example of the chuck plate 20, lower PEZ ring 30, cover plate 50, and upper PEZ ring 60. For ease of illustration, Figure 8 Some of the components shown are not in Figure 9 As shown in the image.

[0023] Reference Figure 9 The chuck plate 20, lower PEZ ring 30, cover plate 50, and upper PEZ ring 60 can restrictively and / or selectively expose the upper corner of the second substrate W2 to plasma P. The lower PEZ ring 30 can be disposed around or surrounding the side of the chuck plate 20 and can support the edge of the second substrate W2 or the edge of the bottom surface of the second substrate W2. The cover plate 50 can cover the center of the second substrate W2. The upper PEZ ring 60 can be disposed around or surrounding the cover plate 50 and can partially cover the edge of the second substrate W2 or be disposed above the edge of the second substrate W2.

[0024] The PEZ ring 30, cover plate 50 and upper PEZ ring 60 will be described in detail below.

[0025] The lower PEZ ring 30 may be disposed on or around the sidewall or side of the chuck plate 20, and / or on the periphery of the chuck plate 20. The lower PEZ ring 30 may comprise ceramics such as Al2O3 and / or Y2O3. The lower PEZ ring 30 may have an L-shape or an L-shaped cross-section. The lower PEZ ring 30 may surround the lower corner of the second substrate W2. For example, the lower PEZ ring 30 may surround the edge of the bottom surface of the second substrate W2 and the lower portion of the sidewall or side surface of the second substrate W2. The lower PEZ ring 30 may prevent plasma P from contacting the edge of the bottom surface of the second substrate W2 and the lower corner of the second substrate W2.

[0026] Figure 10 Show Figure 9 The example shown is the lower PEZ ring 30.

[0027] Reference Figure 9 and Figure 10 The lower PEZ ring 30 may include a ring base 32 and a protrusion or outer wall 34.

[0028] The ring base 32 can support the edge of the second substrate W2. The ring base 32 can have a top surface or upper surface that is coplanar with the top surface or upper surface of the dielectric layer 24 of the chuck plate 20. The ring base 32 can have a second width WD2 of about 10 mm to about 50 mm.

[0029] The protrusion 34 may be disposed on the edge (e.g., the outermost edge) of the ring base 32 and may extend upward from the ring base 32 (e.g., perpendicular to the top surface of the ring base 32). The protrusion 34 may extend in the direction of the sidewall of the upper PEZ ring 60 (e.g., parallel to the side or sidewall of the upper PEZ ring 60). The protrusion 34 may surround the lower portion of the sidewall of the second substrate W2 and / or the lower corner of the second substrate W2, and may expose the upper corner of the second substrate W2 or the upper portion of the sidewall of the second substrate W2 to the plasma P. The protrusion 34 may prevent the bottom surface and lower corner of the second substrate W2 from being damaged by the plasma P. The protrusion 34 may have the same inner diameter ID as the second diameter D2 of the second substrate W2. When the second diameter D2 of the second substrate W2 is about 300 mm, the inner diameter ID of the protrusion 34 may be about 300 mm. When the second substrate W2 has a thickness of approximately 775 μm, the protrusion 34 may have a second height H2 of approximately 745 μm to approximately 772 μm from the top surface of the ring base 32. The protrusion 34 may expose the upper corner of the second substrate W2 or the upper portion of the sidewall of the second substrate W2 to the plasma P along a first height H1 of approximately 3 μm to approximately 30 μm. The plasma P may partially etch the upper corner of the second substrate W2 to form a stepped groove 114. The plasma P may also etch the edge of the top surface of the second substrate W2 and the upper portion of the sidewall of the second substrate W2 to form the stepped groove 114.

[0030] Reference Figure 8 and Figure 10 The bias electrode 40 can be disposed outside the lower PEZ ring 30 and the upper PEZ ring 60 within the chamber 10, or configured to be radially away from the lower PEZ ring 30 and the upper PEZ ring 60. For example, the bias electrode 40 can be configured to be adjacent to a corner of the lower PEZ ring 30 and / or the upper PEZ ring 60. The bias electrode 40 can have an annular or ring-shaped form. The bias electrode 40 can concentrate the plasma P at the upper corner of the second substrate W2. The bias electrode 40 may include, for example, a lower electrode 42 and an upper electrode 44.

[0031] The lower electrode 42 can be disposed below the lower PEZ ring 30. Plasma P can be contained between the lower electrode 42 and the upper electrode 44. The lower electrode 42 can be connected to a bias power supply 46. The bias power supply 46 can supply bias power 48 to the lower electrode 42. The lower electrode 42 can use the bias power 48 to concentrate plasma P at the upper corner of the second substrate W2. The bias power 48 can have a frequency of about 2 MHz to about 60 MHz. Alternatively, the lower electrode 42 can be electrically grounded, but the inventive concept is not limited thereto.

[0032] The upper electrode 44 can be positioned above the lower electrode 42. The upper electrode 44 can also be positioned above the upper PEZ ring 60. When the lower electrode 42 is connected to the bias power supply 46, the upper electrode 44 can be electrically grounded. Alternatively, when the lower electrode 42 is electrically grounded, the upper electrode 44 can be connected to the bias power supply 46. The upper electrode 44 can use the bias power 48 to concentrate the plasma P at the upper corner of the second substrate W2.

[0033] Reference Figures 8 to 10 The cover plate 50 may be disposed on or above the chuck plate 20 within the chamber 10. The cover plate 50 may overlap with the chuck plate 20. The cover plate 50 and the chuck plate 20 may have the same diameter or substantially the same diameter. For example, the cover plate 50 may comprise quartz. In another example, the cover plate 50 may comprise ceramic of Al2O3 and / or Y2O3, but the inventive concept is not limited thereto.

[0034] A gas supply 52 can be connected to a cover plate 50. The gas supply 52 can supply a reactive gas 54 to the cover plate 50. For example, the cover plate 50 may have an aperture or channel 51 defined therein. The reactive gas 54 can be supplied to the top surface of the second substrate W2 through the aperture 51. The reactive gas 54 can flow along the top surface of the second substrate W2 and can be supplied to the plasma P outside the upper PEZ ring 60. For example, the cover plate 50 may be spaced from the second substrate W2 by about 1 mm or less. Since the bottom surface of the cover plate 50 and the top surface of the second substrate W2 are spaced apart by a distance smaller than the sheath width of the plasma P, no plasma P may be generated between the cover plate 50 and the second substrate W2. The reactive gas 54 can activate an etching reaction at the upper corner of the second substrate W2. The reactive gas 54 can be an etching gas. For example, the reactive gas 54 may include SF6, CF4, HF, and / or NF3.

[0035] The upper PEZ ring 60 may be disposed on the lateral or side surface of the cover plate 50 and / or on the periphery of the cover plate 50. The upper PEZ ring 60 may have a bottom surface coplanar with the bottom surface of the cover plate 50. The upper PEZ ring 60 may comprise ceramics such as Al2O3 and / or Y2O3. The upper PEZ ring 60 may cover the edge of the second substrate W2 or be disposed above the edge of the second substrate W2. Since the bottom surface of the upper PEZ ring 60 and the top surface of the second substrate W2 are spaced apart by a spacing smaller than the sheath width of the plasma P, no plasma P may be generated between the upper PEZ ring 60 and the second substrate W2.

[0036] The upper PEZ ring 60 may be thicker than the lower PEZ ring 30. The upper PEZ ring 60 may have a third width WD3 smaller than the second width WD2 of the lower PEZ ring 30. The upper PEZ ring 60 may have an outer diameter OD smaller than the inner diameter ID of the protrusion 34. For example, the protrusion 34 may have an inner diameter ID larger than the outer diameter OD of the upper PEZ ring 60. The outer diameter OD of the upper PEZ ring 60 may, for example, be in the range of about 294 mm to about 299 mm. The upper PEZ ring 60 may expose the upper corner of the second substrate W2 to the plasma P. The exposed upper corner of the second substrate W2 may have a first width WD1 of about 0.5 mm to about 3 mm. The upper PEZ ring 60 may expose the edge of the top surface of the second substrate W2.

[0037] Return to reference Figure 1 and Figure 5 The bonding apparatus can bond the second semiconductor device 112 to the first semiconductor device 102 (S40). For example, step S40 of bonding the second semiconductor device 112 to the first semiconductor device 102 may include a wafer-to-wafer bonding method. The top surface of the second substrate W2 can be bonded to the top surface of the first substrate W1. Although not shown, the pads of the first semiconductor device 102 can be bonded to the pads of the second semiconductor device 112.

[0038] Reference Figure 1 and Figure 6The polishing apparatus can polish the bottom surface of the second substrate W2 to expose the stepped groove 114 (S50). For example, the bottom surface of the stepped groove 114 can be removed to expose the sidewalls or vertical sidewalls of the stepped groove 114. The step S50 of polishing the bottom surface of the second substrate W2 can be, for example, a back lap process or a back grind process for the second substrate W2. The second substrate W2 can be polished to have a first height H1 of about 3 μm to about 30 μm. When the stepped groove 114 is exposed, the second substrate W2 can have a third diameter D3 of about 294 mm to about 299 mm. The stepped groove 114 can reduce crack fragments or particle defects in the second substrate W2 generated during the polishing process of the bottom surface of the second substrate W2. When the stepped groove 114 is not present, crack fragments or particles may be generated at the upper corners of the second substrate W2 during the polishing process.

[0039] Reference Figure 1 and Figure 7 The cutting device 120 can cut the first substrate W1 and the second substrate W2 along or adjacent to the first semiconductor device 102 and the second semiconductor device 112, resulting in the semiconductor chip C being separated from the first substrate W1 and the second substrate W2 (S60). The cutting device 120 may include a sawing device and / or a laser cutting device. The semiconductor chip C may have a bonding structure or a stacked structure of the first semiconductor device 102 and the second semiconductor device 112.

[0040] As described above, the chamfering etching apparatus of some exemplary embodiments of the present invention can use a lower PEZ ring with a protrusion around the lower corner of the substrate, thus preventing damage to the bottom surface of the substrate. Furthermore, the semiconductor device manufacturing method of some exemplary embodiments of the present invention can etch the upper corner of the substrate to form a stepped groove, and the stepped groove can be used to reduce edge defects of the substrate when the bottom surface of the substrate is polished.

[0041] Although the inventive concept has been described in conjunction with embodiments illustrated in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the scope of the inventive concept. Therefore, it will be understood that the above embodiments are illustrative in all respects only and not restrictive. The inventive concept is defined by the appended claims, and equivalents of the claims will be included therein.

[0042] This application claims priority to Korean Patent Application No. 10-2019-0104939, filed on August 27, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A beveling etching apparatus, comprising: A chuck plate, configured as a receiving substrate; A lower plasma isolation zone (PEZ) ring surrounds the periphery of the chuck plate; Cover plate, on the chuck plate; as well as The upper PEZ ring surrounds the periphery of the cover plate. The lower PEZ ring includes: The ring base is configured to support the edge of the bottom surface of the substrate; and A protrusion extends upward from the edge of the ring base to surround the lower portion of the sidewall of the substrate. The protrusion has an inner diameter larger than the outer diameter of the upper PEZ ring. The protrusion has a height of 745 μm to 772 μm from the top surface of the ring base. The upper surface of the upper PEZ ring is coplanar with the upper surface of the cover plate. The lower surface of the lower PEZ ring is coplanar with the lower surface of the chuck plate. The chamfering etching apparatus further includes a bias electrode, which comprises a lower electrode and an upper electrode above the lower electrode. The upper surface of the lower electrode is below the lower surface of the chuck plate and the lower surface of the lower PEZ ring, and is spaced apart from the lower PEZ ring. The lower surface of the upper electrode is above the upper surface of the cover plate and the upper surface of the upper PEZ ring, and is spaced apart from the upper PEZ ring.

2. The chamfering etching apparatus according to claim 1, wherein The inner diameter of the protrusion is 300 mm, and The outer diameter of the upper PEZ ring is 294 mm to 299 mm.

3. The chamfering etching apparatus according to claim 1, wherein the top surface of the ring base is coplanar with the top surface of the chuck plate.

4. The chamfering etching apparatus according to claim 1, wherein the cover plate is above the chuck plate and the cover plate has the same diameter as the chuck plate.

5. The chamfering etching apparatus according to claim 4, wherein the ring base has a width greater than the width of the upper PEZ ring.

6. The chamfering etching apparatus according to claim 1, wherein the upper PEZ ring is thicker than the lower PEZ ring.

7. The chamfering etching apparatus according to claim 1, wherein the bottom surface of the upper PEZ ring is coplanar with the bottom surface of the cover plate.

8. The chamfering etching apparatus of claim 1, wherein the upper PEZ ring and the lower PEZ ring expose the upper corner of the substrate.

9. A beveling etching apparatus, comprising: Chamber; A chuck plate in the chamber, the chuck plate being configured to receive a substrate; A lower plasma isolation zone (PEZ) ring surrounding the periphery of the chuck plate; The cover plate on the chuck plate; An upper PEZ ring surrounding the periphery of the cover plate and on the lower PEZ ring; as well as The bias electrode adjacent to the upper PEZ ring and the lower PEZ ring, The lower PEZ ring includes: The ring base is configured to support the edge of the bottom surface of the substrate; and A protrusion extends upward from the edge of the ring base to surround the lower portion of the sidewall of the substrate. The protrusion has an inner diameter larger than the outer diameter of the upper PEZ ring. The protrusion has a height of 745 μm to 772 μm from the top surface of the ring base. The upper surface of the upper PEZ ring is coplanar with the upper surface of the cover plate. The lower surface of the lower PEZ ring is coplanar with the lower surface of the chuck plate. The bias electrode includes a lower electrode and an upper electrode above the lower electrode. The upper surface of the lower electrode is below the lower surface of the chuck plate and the lower surface of the lower PEZ ring, and is spaced apart from the lower PEZ ring. The lower surface of the upper electrode is above the upper surface of the cover plate and the upper surface of the upper PEZ ring, and is spaced apart from the upper PEZ ring.

10. The chamfering etching apparatus of claim 9, further comprising a bias power supply connected to the lower electrode and configured to supply bias power to the lower electrode.

11. The chamfering etching apparatus according to claim 9, wherein the chuck plate comprises: Chuck base; and The dielectric layer on the base of the chuck.

12. The chamfering etching apparatus of claim 11 further includes a power source connected to the chuck base and configured to supply power to the chuck base.

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