Multi-chip package

Abstract

The package comprises a package body having a package top side, a package footprint side, and package side walls; a plurality of power semiconductor chips electrically connected in parallel to each other, each power semiconductor chip having a first load terminal and a second load terminal and being configured to block a blocking voltage applied between the load terminals and to conduct a chip load current between the load terminals; a leadframe structure for electrically and mechanically coupling the package to a carrier, the package footprint side facing the carrier, the leadframe structure comprising a plurality of first external terminals. Each first external terminal extends out of the package body to establish an interface connection with the carrier. Each first load terminal of the plurality of power semiconductor chips is electrically connected to at least two of the plurality of first external terminals by at least one package body internal connection member. The package further comprises a horizontally extending conductive layer at the package top side or at the package footprint side, wherein the conductive layer is electrically connected to each second load terminal of the plurality of power semiconductor chips.

Description

TECHNICAL FIELD

[0001] The present specification relates to embodiments of a package enclosing a plurality of power semiconductor chips, and to embodiments of a system for providing a load current to a load, the system comprising a package enclosing a plurality of power semiconductor chips. In particular, the present specification relates to embodiments of a surface mount device (SMD) package with top side cooling, the package enclosing a plurality of power semiconductor chips, and to embodiments of a system comprising such a package. BACKGROUND

[0002] Many functions of modern devices, such as converting electrical energy and driving electric motors or machines, rely on power semiconductor devices in automotive, consumer and industrial applications.

[0003] For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs) and diodes, to name just a few, have been used in various applications, including but not limited to switching in power supplies and power converters.

[0004] Power semiconductor devices typically comprise one or more power semiconductor chips, each power semiconductor chip being configured to conduct a load current along a load current path between two load terminals of the respective chip. Moreover, the load current path can be controlled, for example, by means of an insulating electrode, sometimes referred to as a gate electrode. For example, upon receiving a corresponding control signal from, for example, a driver, the control electrode can set the power semiconductor chip into one of a conducting state and a blocking state.

[0005] After the power semiconductor chips have been manufactured, the power semiconductor chips are typically mounted in a package in a manner that allows the package with the chips to be arranged within an application, for example, in a power converter or power supply system, such that the chips can be coupled to a carrier, for example, a printed circuit board (PCB), as part of the package.

[0006] To this end, a technology commonly referred to as surface mount technology (SMT) is known, wherein the concept can generally refer to the production of electronic circuits in which components are mounted or placed directly onto the surface of a PCB. Accordingly, such components are referred to as surface mount device (SMD) components.

[0007] Another mounting configuration is the so-called through-hole technology, for example, a configuration method in which components with leads are fitted into holes in a circuit board.

[0008] Generally, SMD components can be smaller than their through-hole counterparts. Nonetheless, both technologies are still in use today.

[0009] The packages can have various styles of short pins or leads, flat contacts (also referred to as "terminal pads"), a matrix of solder balls (e.g. so-called ball grid array, BGA) and / or end portions on the package body of the component.

[0010] Exemplary configurations of SMD packages are known from documents DE 10 2015 101 674 A1 and DE 10 2015 120 396 A1.

[0011] Each of these known SMD packages encloses a power semiconductor chip and has a package body with a package top side, a package footprint side and package side walls, wherein the package side walls extend from the package footprint side to the package top side. The chip has a first load terminal and a second load terminal and is configured to block a blocking voltage applied between the load terminals.

[0012] Each of the known SMD packages identified above further comprises a leadframe structure for electrically and mechanically coupling the package to a support and the package footprint side faces the support. The leadframe structure comprises external terminals which extend out of the package side walls and are electrically connected with the first load terminal of the chip. Furthermore, each package comprises a top layer arranged at the package top side and electrically connected with the second load terminal of the chip.

[0013] Thus, each of these SMD packages known from documents DE 10 2015 101 674 A1 and DE 10 2015 120 396 A1 can exhibit a package top side facing away from the support and equipped with a top layer on which a heat dissipating device, e.g. a heat sink, can be mounted. Thus, heat can be removed from the package enclosing the chip. Such a package can therefore be referred to as SMD top side cooling (SMD-TSC) package.

[0014] The main function of a component implementing heat dissipation is to remove heat from the package body. For this purpose, it is known, for example, to couple a heat sink to the top layer, e.g. by means of an intermediate component, e.g. a heat sink. The heat sink can be electrically insulated from the top layer.

[0015] Of course, the size and / or configuration of the means for dissipating heat of the package is related to the heat generated by the chip(s) operating within the package, i.e. to the losses generated by the chip during operation. Such losses occur, for example, during switching events (so-called switching losses) and during conduction of a load current (so-called on-state losses or static losses). Losses that can occur during a constant off-state (blocking state) of the chip are much lower than switching losses and on-state losses.

[0016] The construction of a package (and / or of a heat sink coupled thereto) is generally related to the amount of power dissipation generated within the package body, i.e. to the amount of power dissipation generated by one or more chips comprised therein. The higher the dissipation, the larger / more complex the package (and / or the heat sink coupled thereto) has to be designed.

[0017] A low on-state dissipation or static dissipation can be achieved by connecting and operating several power semiconductor chips in parallel, since the total on-state resistance of the chips connected in parallel is reduced compared to the individual on-state resistance of one chip. SUMMARY

[0018] Certain aspects of the present specification relate to embodiments of a package comprising at least two separate power semiconductor chips connected in parallel to each other, thereby obtaining a package having a relatively small total on-state resistance (R on ), and accordingly a relatively small static dissipation.

[0019] Exemplary embodiments of the package disclosed herein are surface mount device (SMD) packages, e.g. SMD-TSC packages. Other embodiments of the package are configured according to a through-hole technology, e.g. the package according to other embodiments is based on a SIP (single in line package) or DIP (dual in line package) or DIPP (dual in line pin package) technology. Other exemplary embodiments of the package disclosed herein are leadless packages.

[0020] According to a first embodiment, a package comprises a package body having a package top side, a package footprint side, and a package sidewall extending from the package footprint side to the package top side, a plurality of power semiconductor chips electrically connected in parallel to each other, each power semiconductor chip having a first load terminal and a second load terminal and being configured to block a blocking voltage applied between said load terminals and to conduct a chip load current between said load terminals, a leadframe structure for electrically and mechanically coupling the package to a carrier and the package footprint side facing the carrier, the leadframe structure comprising a plurality of first external terminals. Each first external terminal extends out of the package body to establish an interface connection with the carrier. Each first load terminal of the plurality of power semiconductor chips is electrically connected to at least two of the plurality of first external terminals at least by means of one package body internal connection member. The package further comprises a horizontally extending conductive layer at the package top side or at the package footprint side, wherein the conductive layer is electrically connected to each second load terminal of the plurality of power semiconductor chips.

[0021] According to a second embodiment, a system for providing a load current to a load is presented. The system comprises a power supply, a power supply path for coupling the power supply to the load; and a system main switch in the power supply path, wherein the system main switch comprises one or more packages according to the first embodiment, wherein the one or more packages are configured to conduct the load current.

[0022] According to another embodiment, a method of processing a package is provided. The method comprises:

[0023] providing a package body having a package top side, a package footprint side, and a package sidewall extending from the package footprint side to the package top side;

[0024] arranging a plurality of power semiconductor chips in the package body and electrically connecting the chips in parallel to each other, each power semiconductor chip having a first load terminal and a second load terminal and being configured to block a blocking voltage applied between said load terminals and to conduct a chip load current between said load terminals;

[0025] providing a leadframe structure for electrically and mechanically coupling the package to a carrier with the package footprint side facing the carrier, the leadframe structure comprising a plurality of first external terminals, wherein

[0026] each first external terminal extends out of the package body for establishing an interface connection with the carrier;

[0027] each first load terminal of the plurality of power semiconductor chips is electrically connected to at least two of the plurality of first external terminals at least by means of one package body internal connection member; and

[0028] providing a horizontally extending conductive layer at the package top side or the package footprint side, wherein the conductive layer is electrically connected to each second load terminal of the plurality of power semiconductor chips.

[0029] Features of optional further embodiments are defined in dependent claims. These features can be combined with each other to form further embodiments, if not explicitly stated otherwise. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figures 1A-1B both schematically and exemplarily showing a part of a perspective projection of a package according to one or more embodiments;

[0031] Figure 2 both schematically and exemplarily showing a part of a perspective projection of a power semiconductor chip according to one or more embodiments;

[0032] Figure 3 both schematically and exemplarily showing a part of a perspective projection of a package according to one or more embodiments;

[0033] Figure 4 A portion of a horizontal projection of a package is schematically and exemplarily shown in accordance with one or more embodiments;

[0034] Figure 5 A portion of a horizontal projection of a package is schematically and exemplarily shown in accordance with one or more embodiments; and

[0035] Figure 6 A portion of a circuit diagram of a system is schematically and exemplarily shown in accordance with one or more embodiments. DETAILED DESCRIPTION

[0036] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the application can be practiced.

[0037] In this respect, directional terms such as "top," "bottom," "up," "down," "front," "back," "leading," "trailing," "above," and the like can be used with reference to the orientation of the described drawings. Because embodiments can be positioned in a number of different orientations, the directional terms are used for purposes of illustration and are in no way limiting. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present application. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the application is defined by the appended claims.

[0038] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation of the application and is not meant as a limitation of the application. For example, features illustrated or described as part of one embodiment can be used with another embodiment to yield still a further embodiment. It is intended that the present application include such modifications and variations. Specific language is used to describe examples, but the use of such specific language is not meant to limit the scope of the claims. The figures are not drawn to scale and are used solely for purposes of illustration. For the purposes of clarity, not every component is called out in the figures, if not specifically stated. The drawings are only intended to facilitate an understanding of the present application.

[0039] The term "horizontal" as used in this specification is intended to describe an orientation that is substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. For example, this can be a surface of a semiconductor wafer or chip. For example, the (first) lateral direction X and the (second) lateral direction Y mentioned below can both be horizontal directions, wherein the first lateral direction X and the second lateral direction Y can be perpendicular to each other.

[0040] The term "vertical" as used in the present specification is intended to describe an orientation which is arranged substantially perpendicular to a horizontal surface, i.e. parallel to a normal direction of a surface of a semiconductor wafer / chip. For example, the extension direction Z mentioned below can be an extension direction which is perpendicular to both the first lateral direction X and the second lateral direction Y.

[0041] In the context of the present specification, the terms "ohmic contact", "electrical contact", "ohmic connection" and "electrical connection" are intended to describe the presence of a low-ohmic electrical connection or low-ohmic current path between two regions, segments, zones, parts or portions of a device as described herein. Furthermore, in the context of the present specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of a respective semiconductor device; for example, the transition between two elements which are in contact with each other can not include further intermediate elements, etc.

[0042] Furthermore, in the context of the present specification, the term "electrically insulated" is used in the context of its general effective understanding and thus the term "electrically insulated" is intended to describe that two or more components are positioned apart from each other and that no ohmic connection connecting those components is present. However, components which are electrically insulated from each other can still be coupled to each other, e.g. mechanically and / or capacitively and / or inductively. As an example, two electrodes of a capacitor can be electrically insulated from each other and at the same time be mechanically and capacitively coupled to each other, e.g. by an insulation, e.g. a dielectric.

[0043] The specific embodiments described in the present specification relate to, but are not limited to, power semiconductor chips, e.g. power semiconductor chips which can be used within a power converter or a power supply. Thus, in embodiments, such chips can be configured to carry a load current which is to be fed to a load and / or provided by a power supply, respectively. For example, the chips can comprise one or more active power semiconductor cells, e.g. monolithically integrated diode cells, and / or monolithically integrated transistor cells, and / or monolithically integrated IGBT cells, and / or monolithically integrated RC-IGBT cells, and / or monolithically integrated MOS gate diode (MGD) cells, and / or monolithically integrated MOSFET cells and / or derivatives thereof. A plurality of such diode cells and / or such transistor cells can be integrated in a chip.

[0044] The term "power semiconductor chip" as used in the present specification is intended to describe a single chip which has a high voltage blocking and / or a high current carrying capability. In other words, such power semiconductor chips are intended for high currents and / or voltages, the currents typically being in the range of amperes, e.g. up to 5 or 100 amperes or even up to 1000 A and more, the voltages typically being higher than 15 V, more typically up to 40 V and more, e.g. up to at least 500 V or more than 500 V, e.g. at least 600 V, or even up to 2000 V and more.

[0045] For example, the power semiconductor chip described below can be a chip configured to be used as a power component in low, medium and / or high voltage applications.

[0046] For example, the term "power semiconductor chip" used in the present specification is not directed to a logic semiconductor device for storing data, computing data and / or other types of semiconductor-based data processing, for example.

[0047] Figure 2 A part of a perspective projection of a power semiconductor chip 100 according to one or more embodiments is schematically and exemplarily shown.

[0048] The power semiconductor chip 100 has a first load terminal 101 and a second load terminal 102. The power semiconductor chip 100 is configured to block a blocking voltage applied between the load terminals 101, 102 and to conduct a chip load current between the load terminals 101, 102.

[0049] The power semiconductor chip 100 can be processed within a semiconductor wafer together with other power semiconductor chips, which semiconductor wafer is cut into individual power semiconductor chips after wafer processing is completed.

[0050] For example, during such wafer processing, the first load terminal 101 is formed for each designated chip, for example by depositing a conductive material, for example a metal, on the front side of the wafer. Forming the first load terminal 101 on the front side of the wafer can include the use of a mask. The first load terminal 101 is typically formed after completion of the construction of the semiconductor body 10.

[0051] The second terminal 102 is typically formed on the back side of the wafer, for example without a mask, but substantially uniformly along the entire back side. For example, the second load terminal 102 can include a backside metallization.

[0052] The chip 100 can thus have a vertical construction according to which the first load terminal 101 is arranged at the chip front side and the second load terminal 102 is arranged at the chip back side. In lateral directions, for example in lateral directions X and Y and linear combinations thereof, the chip can be terminated by chip edges, for example side surfaces extending in the vertical direction Z.

[0053] The semiconductor body 10 is coupled between a first load terminal 101 and a second load terminal 102. For example, if a voltage applied between the first load terminal 101 and the second load terminal 102 is positive (e.g. the potential of the second load terminal 102 is greater than the potential of the first load terminal 101), the semiconductor body 10 conducts (forward) a load current between the load terminals 101 and 102. If the voltage is negative, the semiconductor body 10 can be configured to block such a voltage and to suppress the flow of a load current between the load terminals 101, 102; i.e. the chip 100 can have a reverse blocking configuration. In another embodiment, the chip 100 has a reverse conducting (RC) configuration.

[0054] For example, the power semiconductor chip 100 can be a diode, wherein, for example, the first load terminal 101 can be a cathode terminal and the second load terminal 102 can be an anode terminal.

[0055] In another embodiment, the power semiconductor chip 100 can be a controllable power semiconductor chip, for example a transistor or a gated diode or a thyristor or a derivative of one of the above mentioned variants. For example, the power semiconductor chip 100 can comprise a control terminal 103, which is also typically arranged at the front side of the power semiconductor chip 100. In embodiments, the first load terminal 101 can thus be a source / emitter terminal and the second load terminal 102 can be a drain / collector terminal.

[0056] Possible basic configurations of power semiconductor chips 100 (transistors (e.g. MOSFETs, IGBTs etc.), diodes and thyristors) are known to the person skilled in the art and are thus avoided to be explained in more detail. The embodiments described herein are not limited to a specific type of power semiconductor chip. For example, the chips can also be designed as monolithic bidirectional blocking and conducting power semiconductor chips. For example, each chip can be a Si-MOSFET, a SiC-MOSFET or a GaN-HEMT (high electron mobility transistor).

[0057] Further, it is noted that the first load terminal 101 can also be arranged at the back side of the power semiconductor chip 100 and the second load terminal 102 can also be arranged at the front side of the power semiconductor chip 100.

[0058] For example, the chips 100 comprised in the package 200 (described below) all have the same MOSFET configuration.

[0059] Before being able to be used in an application, the power semiconductor chip 100 is typically comprised in a package, which can allow the chip to be mechanically mounted and electrically connected in the application, for example also for thermal distribution purposes. Such a package can environmentally seal the comprised power semiconductor chip 100.

[0060] Figures 1A-1B both schematically and exemplarily illustrate a portion of a perspective projection of a package 200 according to one or more embodiments. Reference will now be made to Figure 1A and Figure 1B both.

[0061] The package 200 comprises a package body 20 having a package top side 201, a package footprint side 202, and a package sidewall 203 extending from the package footprint side 202 to the package top side 201.

[0062] The package body 20 can be made of or respectively comprise a molding block. For example, the package body 20 exhibits a flat configuration according to which: each of the package top side 201 and the package footprint side 202 extends substantially horizontally along first and second lateral directions X and Y; the package sidewall 203 extends substantially perpendicularly along a vertical direction Z; and a maximum horizontal extension of the package footprint side 202 amounts to at least twice a maximum vertical extension of the package sidewall 203.

[0063] The leadframe structure of the package 100 is configured to electrically and mechanically couple the package 200 to a carrier 300, and the package footprint side 202 faces the carrier 300.

[0064] The carrier 300 can be a printed circuit board (PCB) or can be a component of a PCB. In another embodiment, the carrier 300 can be a direct copper bonding (DCB) substrate, e.g. a ceramic circuit board, or can be a component of a DCB substrate. In yet another embodiment, the carrier 300 can also be based on an insulated metal substrate (IMS). The carrier 300 can be made of an electrically insulating material, e.g. made of a polymer, a PCB laminate, a ceramic, a flame retardant (FR) material, e.g. FR4, a composite epoxy material (CEM), e.g. CEM1 or CEM3, a bismaleimide-triazine resin (BT) material, an imide, a polyimide, ABF, or a combination of the above exemplary materials.

[0065] In an embodiment, the package 200 is coupled to the carrier via the leadframe structure of the package 200.

[0066] The package 200 encloses a plurality of power semiconductor chips 100 electrically connected in parallel to each other, each power semiconductor chip 100 having a first load terminal 101 and a second load terminal 102, and being configured to block a blocking voltage applied between said load terminals 101, 102 and to conduct a chip load current between said load terminals 101, 102.

[0067] The above with respect to Figure 2The explanations presented for the power semiconductor chip 100 can equally apply to each power semiconductor chip 100 comprised in the package 200.

[0068] In embodiments, the chips 100 comprised in the package 200 are identically configured. For example, each chip 100 exhibits the same MOSFET configuration.

[0069] For example, the chips 100 are sandwiched between the package top side 201 and the package footprint side 202. The package body 20 can completely surround the chips 100 and seal the chips 200 against the environment. Further aspects of the arrangement of the chips 100 will be described below.

[0070] The leadframe structure of the package 200 can serve as an electrically conductive interface between the first load terminal 101 of the chips 100 (and, if present, one or more other terminals of the chips (control and / or sensing terminals)) and other components (not shown) fixed at the carrier 300. For example, the carrier 300 can comprise or be provided with other components (not shown; e.g., one or more other packages comprising one or more other chips, and / or controllers, sensors, passive components, loads, etc.), the terminals of the chips 100 being coupled with these other components via the leadframe structure. The connection between the leadframe structure and the terminals of the chips 100 (e.g., the first load terminal 101) can be realized by means of internal package connections, and in order to connect the chips with other components outside of the package 200, the leadframe structure can comprise one or more external terminals, as will now be explained in more detail in the following.

[0071] As used herein, the expression “electrically connected in parallel with each other” shall mean that all first load terminals 101 of the chips 100 enclosed in the package 200 exhibit substantially the same first electrical potential, and that all second load terminals 102 of the enclosed chips 100 exhibit substantially the same second electrical potential. For example, the total load current of the package is conducted by the plurality of chips 100 jointly and simultaneously. The expression is thus not intended to also cover so-called anti-parallel connections (e.g., two anti-parallel connected diodes do not conduct the load current simultaneously).

[0072] For example, each chip 100 exhibits the same on-resistance (Ron) and, thus, the total on-resistance of the package 200 amounts to approximately Ron divided by the total number of chips 100. on on For example, each chip 100 exhibits the same on-resistance (Ron) and, thus, the total on-resistance of the package 200 amounts to approximately Ron divided by the total number of chips 100.

[0073] Reference is now made to both Figures 1A-1B and Figure 3 The leadframe structure 21 comprises a plurality of first external terminals 2111. Each first external terminal 2111 extends out of the package body 20 to establish an interface connection with the carrier 300. ​

[0074] Each first load terminal 101 of the plurality of power semiconductor chips 100 is electrically connected to at least two of the plurality of first external terminals 2111 at least by means of one package-internal connection member 270.

[0075] For example, with reference to Figure 3 , the package 200 integrates eight chips 100, which are arranged substantially in two rows parallel to each other. The leadframe structure 21 comprises eight package-internal connection members 270.

[0076] In embodiments, each package-internal connection member 270 is terminated by at least two first external terminals 2111, and each package-internal connection member 270 is electrically connected to first load terminals 101 of at least two chips (in the shown example, to four chips 100). For example, each end of a respective connection member 270 is terminated in at least one first external terminal 2111.

[0077] For example, as Figure 3 illustrated, each package-internal connection member 270 can be joined at each of its ends to a respective first load terminal leg 211 of the leadframe structure 21, which establishes an interface connection with the plurality of first external terminals 2111.

[0078] Further, in embodiments, each first external terminal 2111 extends out of a first one of the package side walls 203 of the package body 20, or out of a second one of the package side walls 203 of the package body 20, the first and second package side walls being arranged opposite to each other. Further, for each first load terminal 101 of the plurality of power semiconductor chips 100, at least one of the at least two first external terminals 2111 provided for the respective first load terminal 101 extends out of the first package side wall, and at least another one of the at least two first external terminals 2111 provided for the respective first load terminal 101 extends out of the second package side wall.

[0079] For example, still with reference to Figure 3 As an example, each package-internal connection member 270 can extend substantially laterally from a first package side wall 203 (e.g., the right one of the package side walls 203 in Figure 3 ) to an opposite second package side wall 203 (e.g., the left one of the package side walls 203 in Figure 3 ), and establish electrical contact with at least one first load terminal 101 of at least one chip 100 along its laterally extending course. Each package-internal connection member 270 establishes electrical contact with first load terminals 101 of at least two chips 100 along its laterally extending course.

[0080] Thus, according to embodiments, more generally, the at least two first external terminals 2111 provided for each first load terminal 101 are electrically connected to each other by the at least one package body internal connection member 270 within the package body 20.

[0081] For example, each package body internal connection member 270 is implemented as a wire bond, as a clip or as a ribbon bond.

[0082] The package body internal connection members 270 provide an electrically conductive path between the first load terminals 101 of the chip 100 and the first external terminals 2111. As mentioned above, at each package side wall 203, a subset of the first external terminals 2111 can be bonded into a respective first load terminal bar 211. Each first load terminal bar 211 can extend substantially parallel to the package side wall 203 and provide an interface between the subset of first external terminals 2111 and one or more package internal connection members 270.

[0083] The control terminals 103 (not shown in Figure 3 ) can be connected in a similar way. For example, the package 200 comprises a plurality of third external terminals 2131. For example, at each of the first and second package side walls opposite to each other, the package 200 comprises at least one control terminal bar 213 extending substantially parallel to the respective package side wall 203. At each side wall 203, a third external terminal 2131 is bonded into a control terminal 213. Within the package body 20, a plurality of package internal control terminal connection members 275 are provided extending from the control terminal bar 213 to the respective control terminal 103 of the package integrated chip 100. For example, the package 200 comprises at least one package internal control terminal connection member 275 for each chip 100. Further, as Figure 3 shown, for example, the third external terminals 2131 extend out of the central portion of the first and second package side walls (center with respect to the second lateral direction Y) and the subset of first external terminals 2111 extends out of the first and second package side walls on either side of the third external terminals 2131 in the second lateral direction Y. That is, in the example shown in Figure 3 , the package comprises pins that are symmetric with respect to the third external terminals 2131 arranged in the middle of the package and the first external terminals 2111 arranged on either side thereof. For comparison, the example shown in Figure 4 has pins that are symmetric with respect to the first external terminals 2111 arranged in the middle and the third external terminals 2131 arranged on either side thereof. Needless to say, Figure 3 the arrangement shown can also be used for top side cooling as shown in Figure 1A and bottom side cooling as shown in Figure 1B .

[0084] For example, the internal control terminal connection member 275 of each package body is implemented as wire bonding, as a jig, or as strip bonding.

[0085] Furthermore, as described above, each control terminal bar 213 may provide an interface between a subset of the third external terminals 2131 and a subset of the control terminal connection members 275 inside the package body. Similarly, as described above, each first load terminal bar 211 may provide an interface between a subset of the first external terminals 2111 and a subset of the connection members 270 inside the package body.

[0086] Now refer to it again Figures 1A-1B Package 200 is on the top side of package 201 (e.g.) Figure 1A (as shown) or on the package occupied area side 202 (as shown) Figure 1B As shown, a horizontally extending conductive layer 22 is included, wherein the conductive layer 22 is electrically connected to each of the second load terminals 102 of the plurality of power semiconductor chips 100 integrated in the package 200. Horizontally extending conductive layers may also be provided at both the top side 201 of the package and the package occupied area side 202.

[0087] For example, package 200 can therefore exhibit a TSC construction, such as Figure 1A As shown in the image. Alternatively, package 200 can exhibit a BSC (bottom-side cooling or plate-side cooling) configuration, as shown in the image. Figure 1B As shown in the image.

[0088] In both variants, the conductive layer 22 may be monolithic and may, for example, laterally overlap with each power semiconductor chip 100 in the first and second transverse X and Y directions.

[0089] For example, such as Figure 1A As best illustrated, the conductive layer 22 is arranged to be substantially coplanar with the top side 201 of the package; for example, the conductive layer 22 does not substantially protrude from the top side 201 of the package. The horizontal surface area of ​​the conductive layer 22 may total at least 50%, at least 60%, or even greater than 80% or even greater than 95% (but less than 100%) of the total surface area of ​​the top side 201 of the package. This surface area may be exposed to the environment of the package body 20, i.e., the surface area of ​​the conductive layer 22 is not enclosed within the package body 20, but forms part of the outer surface. This can be similarly applied to BSC constructions (see [link to BSC configuration]). Figure 1B ).

[0090] The conductive layer 22 can be monolithic and continuously extending, i.e., as a continuous conductive surface, so as to fully (laterally / horizontally) overlap with each chip 100 integrated in the package 200. For example, each chip 100 is arranged within the vertical projection of the horizontal surface of the conductive layer 22. Figure 3The exemplary construction of the conductive layer 22 can also be correct for the embodiments shown (where the conductive layer 22 is not shown).

[0091] In another embodiment, as shown in Figure 1B the conductive layer 22 is arranged at the package footprint side 202, and thus, the package 200 can then exhibit the bottom side cooling (BSC) construction.

[0092] In an embodiment, as shown in Figures 1A-1B and Figure 3 each of the plurality of first external terminals 2111 extends out of the package body 20 at a respective one of the package sidewalls 203. For example, the first external terminals 2111 are arranged at two sidewalls 203 opposite to each other, while the first external terminals 2111 are not arranged at the remaining two sidewalls 203.

[0093] Further, as shown in Figures 1A-1B and Figure 3 each first external terminal 2111 can be arranged at a vertically central position of the respective sidewall 203. For example, this can advantageously allow using the same package 200 for BSC or TSC packages, depending on the orientation of the external terminals 2111; thus, they can be oriented towards the conductive layer 22 (corresponding to the BSC construction), or towards the package top / bottom side 201 / 202 where no conductive layer 22 is provided, resulting in the TSC construction.

[0094] According to embodiments and as exemplarily shown in Figures 1A-1B and Figure 3 the explanations of the optional arrangement of the first external terminals 2111 in the preceding paragraph can equally apply to the arrangement of the third external terminals 2131.

[0095] In an embodiment, irrespective of the horizontally extending conductive layer 22, the leadframe structure 21 does not comprise external terminals extending out of the package body 20 and electrically connected with one or more second load terminals 102 of the power semiconductor chips 100. For example, all chips 100 integrated in the package 200 are electrically contacted by the package external entity by means of the first external terminals 2111 for the first load terminals 101, and by means of the horizontally extending conductive layer 22 for the second load terminals 102, and by means of the third external terminals 2131 for the control terminals 103 (if any) of all chips 100 integrated in the package 200 by the package external entity. In contrast, no external terminals (like terminals 2111, 2131) are provided for the second load terminals 102.

[0096] In embodiments, each power semiconductor chip 100 is arranged at the same vertical level within the package body 20. Further, each chip 100 can be arranged in the package body 20 such that its second load terminal 102 faces the package footprint side 202 and its first load terminal 101 and its control terminal 103 face the package top side 201.

[0097] For example, the package top side 201 has a total horizontal surface area of at least 4 cm 2 For example, each package side wall 203 can exhibit a total lateral extension of at least 1 cm, at least 2 cm or at least 3 cm. An exemplary package size is 3.72 cm x 4.716 cm.

[0098] Further, the package top side 201 can be exposed to the environment of the package body (20) such that the horizontal surface area of the conduction layer 22 is not enclosed within the package body 20 but forms part of the outer surface. This can similarly apply to the BSC configuration (see Figure 1B ).

[0099] In embodiments, each power semiconductor chip 100 integrated in the package 200 is configured to block a blocking voltage of at least 500 V. Further, a static ohmic resistance measured between the horizontally extending conduction layer 22 and the plurality of first external terminals 2111 is less than 5 mOhm or even less than 1.5 mOhm during conduction of a chip load current. This relatively low resistance is achieved at least by means of a parallel connection of the plurality of chips 100.

[0100] In the following, reference is made to Figure 4 which schematically and exemplarily shows a part of a horizontal projection of the package 200 according to one or more embodiments. Figure 4 A package portion close to one (e.g., first) package side wall 203 is shown. The package portion close to the second (opposite) package side wall 203 can be identically configured such that the package exhibits a symmetrical design.

[0101] As mentioned above, the leadframe structure can comprise a first load terminal bar 211 and a plurality of first external terminals 2111 extending out of the package body 20 to establish an interface connection with the carrier 300 and to electrically connect the first load terminals 101 of at least some of the plurality of power semiconductor chips 100 by means of the first load terminal bar 211 and the package internal connection member 270. For example, at least one or at least two first external terminals 2111 are provided for each power semiconductor chip 100.

[0102] If present, for the electrical connection of control terminal 103, package 200 may include at least one third external terminal 2131, which extends out of package body 20 to establish an interface connection with carrier 300 and be electrically connected to at least one of the control terminals 103 of a plurality of power semiconductor chips 100. Figures 1A-1B , Figure 3 and Figure 4 As shown, there can certainly be more than one third external terminal 2131; for example, two third external terminals 2131. However, since controlling the power semiconductor chip 100 by providing control signals to the control terminal 103 generally does not require high current, a few third external terminals 2131 may be sufficient. For example, as described above, at least within the package body 20, one or two third external terminals 2131 are connected to the control terminal 103 of the enclosed power semiconductor chip 100, for example, within the housing body 20, at least by means of the internal package control terminal connection member 275.

[0103] As described above, the first external terminal 2111 is electrically insulated from the conductive layer 22. If present, one or more third external terminals 2131 are electrically insulated from both the first external terminal 2111 and the conductive layer 22.

[0104] One or more of external terminals 2111 and 2131, or each of the external terminals, may be configured to be electrically and mechanically coupled to the carrier 300, for example, by soldering. Within this specification, the term "external" may mean that external terminals 2111 and 2131 may be configured to be electrically contacted by means of a component (body) outside the package body 20.

[0105] In addition, external terminals 2111 and 2131 can be designed as pins, such as Figures 1A-1B and Figure 3 As best illustrated in the figure. In another embodiment, for example, to form a so-called leadless package, the external terminals 2111 and 2131 of package 200 are flat planar external terminals. For example, within this specification, the term "flat planar" may mean that both external terminals 2111 and 2131 exhibit a corresponding substantially planar bottom surface, the dimensions of which have a horizontal dimension (e.g., along each of a first lateral direction X and a second lateral direction Y) at least as large as the vertical dimension (e.g., along the vertical direction Z) of the corresponding external terminal, said planar bottom surface laterally overlapping the package occupied area side 202. Thus, package 200 may be a leadless package, such as an SMD leadless package. In another embodiment, external terminals 2111 and 2131 are configured as contact pins (as shown) or contact balls.

[0106] In the package body 20, the plurality of power semiconductor chips 100 are arranged horizontally next to each other along the first lateral direction X. For example, each chip 100 has the same position with respect to the vertical direction Z. For example, each power semiconductor chip 100 is arranged at the same vertical level within the package body 20. The chips 100 can be arranged equidistantly, for example, with a distance along the first lateral direction X between each pair of adjacent chips 100 being in the range of 0.5 mm to 5.0 mm.

[0107] The first load terminal bars 211 of the leadframe structure 21 can also extend along the first lateral direction X in order to allow for a subsequent establishment of an electrical contact to the first load terminals 101 of the power semiconductor chips 100 by means of the package internal connection means 270.

[0108] The first load terminal bars 211 can be spatially displaced from the plurality of chips 100 along the second lateral direction Y Figure 4 ) or the first lateral direction X Figure 3 , for example, by a distance in the range of 0.5 mm to 5.0 mm.

[0109] In an embodiment, the first external terminals 2111 extend away from the first load terminal bars 211 (within the package body 20) along the first or second lateral direction X, Y to penetrate the package side wall 203 and to reach outside of the package 200, where the first external terminals 2111 can establish an interface connection with the carrier 300, as shown in Figures 1A-1B , Figure 3 and Figure 4 .

[0110] Hence, the implementation of a parallel connection of the plurality of chips 100 can be at least partially achieved by means of the first load terminal bars 211 and the package internal connection means 270.

[0111] For example, the total lateral extension of each first load terminal bar 211 can be at least as large as the total lateral extension of the array of one or more chips 100.

[0112] As mentioned above, the package internal control terminal connection means 275 (e.g. wire bonds) connect the control terminals 103 of the power semiconductor chips 100 with the control terminal bars 213. The control terminal bars 213 can each be spatially displaced from the plurality of chips 100 along the first or second lateral direction X, Y, for example, by a distance in the range of 0.5 mm to 5.0 mm.

[0113] In embodiments, the third external terminals 2131 extend away from the respective control terminal bars 213 (within the package body 20) along the first or second lateral direction X, Y to penetrate the package side walls 203 and to reach outside of the package 200, where the third external terminals 2131 can establish an interface connection with the carrier 300, as Figures 1A-1B , Figure 3 and Figure 4 indicated.

[0114] As indicated in Figure 4 , the first load terminal bars 211 and the control terminal bars 213 can be arranged next to each other along the second lateral direction Y. For example, due to the higher number of first external terminals 2111 (compared to the number of third external terminals 2131), it can be appropriate to position the control terminal bars 213 relative to the second lateral direction Y between the array of chips 100 and the first load terminal bars 211. For example, the package internal connection means 275 extend below or above (relative to the vertical direction Z) the control terminal bars 213 to connect to the first load terminal bars 211.

[0115] In embodiments, as indicated in Figure 4 , the first load terminal bars 211 are positioned relative to the first lateral direction X between two third external terminals 2131.

[0116] In contrast, Figure 3 shows a different way according to which, at each of the two opposite package side walls, the control terminal bars 213 are arranged between two first load terminal bars 211.

[0117] As mentioned above, the second load terminals 102 are electrically connected to the conductive layer 22. For example, the second load terminals 102 are electrically connected to the conductive layer 22 only and no external terminals (like terminals 2111 and 2131) are provided.

[0118] Figure 5 A part of a horizontal projection of the package 200 according to one or more further embodiments is schematically and exemplarily shown. Reference is also made to Figure 3 , for example, the plurality of power semiconductor chips 100 comprises a first subset consisting of N > 2 power semiconductor chips 100 and a second subset consisting of N power semiconductor chips 100. For example, N is equal to two, three, four, five, six, seven, eight, nine or ten. N can even be larger than ten, for example equal to or larger than 12, 14, and so on. Thus, the total number of chips 100 comprised in the package 200 can be equal to 2 x N.

[0119] Figure 3 and Figure 5 show an embodiment with N = 4.

[0120] In an embodiment, the N power semiconductor chips 100 of the first subset are arranged along a first path 100-A, e.g. extending in a first lateral direction X. Further, the N power semiconductor chips 100 of the second subset are arranged along a second path 100-B parallel to the first path 100-A and horizontally displaced from the first path 100-A, e.g. along a second lateral direction Y. Likewise, the N chips 100 of the second subset can be arranged in the same way relative to the vertical direction Z as the N chips 100 of the first subset. Figure 4 Each of the 2xN chips of the first and second subset can have the same position relative to the vertical direction Z.

[0121] The leadframe structure 21 of the package 200 can comprise at least one first load terminal bar 211 for both arrays of chips 100-A and 100-B, as shown in Figure 3 (with two first load terminal bars 211 provided for each path 100-A, 100-B) and Figure 5 (with one first load terminal bar 211 provided for each path 100-A, 100-B).

[0122] The first load terminal bars 211 for the first array of N chips 100-A extend parallel to the package side wall 203, e.g. to allow for a subsequent routing of package internal connection members 275, e.g. relative to Figure 3 and Figure 4 in the manner already explained, electrical contact is established with the first load terminals 101 of the N power semiconductor chips 100 of the first subset.

[0123] The further first load terminal bars 211 of the N chips 100 of the second subset in the second array 100-B also extend parallel to the package side wall 203, e.g. to allow for a subsequent routing of package internal connection members 275, e.g. relative to Figure 3 and Figure 4 in the manner already explained, electrical contact is established with the first load terminals 101 of the power semiconductor chips 100 of the second subset.

[0124] For example, the first load terminal bars 211 for the N chips 100 of the first array 100-A are arranged within the package body 20 and between the first array 100-A and a first one of the package side walls 203 or, respectively, an opposite second one of the package side walls 203. As shown, the further first load terminal bars 211 for the N chips 100 of the second array 100-B can also be arranged between the second array 100-B and the first one of the package side walls 203 or, respectively, the opposite second one of the package side walls 203.

[0125] For example, as described above, the conductive layer 22 is used to provide an electrical connection to the second load terminal 102 of each of the 2xN power semiconductor chips 100, e.g. at the package top side 201. Thus, an external contact can be coupled to the conductive layer 22 and, within the package body 20, the conductive layer 22 is electrically connected to the second load terminal 102 of each of the 2xN power semiconductor chips 100.

[0126] According to Figures 1A-1B , Figure 3 , Figure 4 and Figure 5 embodiments, a parallel connection of all 2xN power semiconductor chips 100 can be established by electrically connecting each of the first external terminals 2111 to each other, wherein this electrical connection can also occur outside of the package body 20. Further, a parallel connection of all 2xN power semiconductor chips 100 can be established by electrically connecting each of the third external terminals 2131 to each other, wherein this electrical connection can also occur outside of the package body 20.

[0127] According to Figure 5 embodiments, the package 200 further comprises a horizontally extending conductive layer 22 at the package top side 201. If arranged at the package top side, the horizontally extending conductive layer 22 can be a top side cooling layer. Thus, Figure 5 the package 200 can exhibit a TSC configuration. The horizontally extending conductive layer 22 can overlap some or all of the power semiconductor chips 100 comprised in the package 200 (as shown) laterally along the first and second lateral directions X and Y.

[0128] With regard to all embodiments described herein, the power semiconductor chips 100 in the package 200 can be configured to be commonly set into a respective conduction state, e.g. by means of providing a corresponding control signal at the third external terminals 2131, wherein the first external terminals 2111 and the conductive layer 22 are configured to conduct at least a sum of the chip load currents during the conduction state. For example, in the conduction state, the total load current is evenly distributed among the power semiconductor chips 100 comprised in the package 200; e.g. if 2xN power semiconductor chips 100 are comprised in the package 200, each chip 100 conducts a share of the total load current I 总 amounting to approximately I 总 / (2xN) in the conduction state, which is referred to herein as chip load current.

[0129] The parallel connection of the chips 100 included in the package 200 allows achieving a lower on-state resistance of the chips 100 integrated within the package 200. For example, the total on-state resistance of the chips 100 and the package 200, i.e. the total on-state resistance of the package 200 integrating the chips 100 connected in parallel to each other, can be equal to or less than 5 mOhm, or less than 2 mOhm, or less than 1 mOhm.

[0130] Furthermore, with respect to all embodiments described herein, the package 200 can comprise not only the first external terminals 2111 but can optionally comprise one or more third external terminals 2131. The total number of third external terminals 2131 can be limited, for example, to eight, four, three or two. In addition, the package 200 can comprise a further external terminal (not shown), for example, a sense external terminal electrically connected to one or more sense terminals in one or more of the enclosed chips 100, for example, in order to be able to measure an operating parameter, for example, a temperature, a voltage and / or an actual load current. However, again, it is emphasized that, in accordance with one or more embodiments, no other externally accessible electrically conductive member exists in addition to the conductive layer 22, in particular, no external terminal similar to the terminals 2111 and 2131 is connected to the second load terminals 102.

[0131] As described above, the leadframe structure 21 of the package 200 comprises at least the first load terminal bars 211 and the first external terminals 2111. The leadframe structure 21 is configured to mechanically and electrically couple the package body 20 to a carrier 300, for example, a printed circuit board (PCB).

[0132] In an embodiment, the leadframe structure 21 is a metal frame structure. Thus, the leadframe structure can constitute a metal carrier which is arranged partly inside and partly outside the package body 20.

[0133] According to another embodiment, a method of processing a package is provided. The method comprises:

[0134] - providing a package body having a package top side, a package footprint side and a package side wall, the package side wall extending from the package footprint side to the package top side;

[0135] - arranging a plurality of power semiconductor chips in the package body and electrically connecting the chips in parallel to each other after each power semiconductor chip has a first load terminal and a second load terminal and is configured to block a blocking voltage applied between the load terminals and to conduct a chip load current between the load terminals;

[0136] - A leadframe structure is provided for electrically and mechanically coupling a package to a carrier, wherein the package occupies a side portion facing the carrier, and the leadframe structure includes a plurality of first external terminals, wherein

[0137] Each first external terminal extends out of the package body to establish an interface connection with the carrier;

[0138] Each first load terminal of a plurality of power semiconductor chips is electrically connected to at least two of a plurality of first external terminals by means of an internal connection member of a package body; and

[0139] - A horizontally extending conductive layer is provided on the top side of the package or on the side of the package occupied area, wherein the conductive layer is electrically connected to each of the second load terminals of a plurality of power semiconductor chips.

[0140] An exemplary embodiment of the processing method corresponds to the above reference. Figures 1A-1B to Figure 5 An embodiment of package 200 is described. For example, the processing method may include ensuring that each power semiconductor chip is arranged at the same vertical level within the package body. Therefore, the total thickness of the package (e.g., the distance between the top side of the package and the package occupied area side) does not depend on the total number of chips included in the package.

[0141] For example, even if the processed package could therefore include multiple chips electrically connected in parallel, existing packaging processing platforms can be used. For instance, existing die / wire bonding platforms can be used to form the above reference. Figures 1A-1B to Figure 5 An embodiment of the package 200 is described.

[0142] In the following text, reference will be made to Figure 6 The diagram schematically and exemplaryly shows a portion of a circuit diagram of a system 1000 according to one or more embodiments.

[0143] System 1000 is configured to provide load current to load 500. Load 500 may be constituted by, for example, the electrical system of a vehicle. For example, the load may include an electric drive of the vehicle, such as an electric brake for driving the vehicle itself or one or more other electrical components.

[0144] System 1000 includes a power supply 400 that provides power signals at power terminals 401, 402. The power supply 400 may be, for example, a DC power supply, such as a battery that provides a DC voltage between power terminals 401, 402. The power supply 400 may alternatively or additionally include (not shown) a power semiconductor converter circuit (not shown) that provides power signals at power terminals 401, 402, for example, a DC voltage of at least 100V.

[0145] The system 1000 further comprises a power source path 600 for coupling the power source 400 to the load 500. The power source path 600 can comprise one or more of the following: one or more cables, one or more wires, one or more connectors, one or more copper lines, etc.

[0146] A system main switch 700 is arranged in the power source path 600. The system main switch 700 can be configured to selectively set the power source path 600 into a blocking state (i.e. such that the power source path 600 is interrupted and no load current can be provided from the power source 400 to the load 500) and a conducting state during which the power source path 600 is conductive and can provide the load current generated by the power source 400 to the load 500. Thus, if the system main switch 700 is closed (i.e. conductive), the system main switch conducts the load current currently consumed by the load 500.

[0147] For example, the system main switch 700 can be a battery main switch. For example, the system main switch 700 operates at a relatively low switching frequency, e.g. less than 1 Hz. Main switches are typically not operated continuously at a constant switching frequency, but irregularly, e.g. only a few times per day (e.g. in case of use as a battery main switch in a vehicle).

[0148] According to one or more of the above-described embodiments, the system main switch 700 comprises one or more packages 200. The one or more packages 200 are configured to conduct the load current provided to the load 500.

[0149] Thus, a beneficial application of the above-described embodiments of the package 200 can be its use within a main switch such as a battery main switch. Such switches typically require very low static losses due to the long time of the conductive state that can occur (e.g. for several hours or even days). In contrast, such applications typically do not require very low switching losses since switching events occur rarely. Thus, the above-described embodiments of the package 200 can be used to replace conventional main switches such as relays, contactors, etc.

[0150] For ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for explaining the orientation of one element relative to another element as illustrated in the drawings. Such terms are intended to encompass different orientations of the respective devices in addition to the orientation depicted in the drawings. Further, terms such as "first", "second", and the like, can be used herein for describing various elements, regions, parts, sections and the like and are also not intended to be limiting. Like terms refer to like elements throughout the description.

[0151] As used herein, the terms "have," "comprise," "include," "contain," "display," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features.

[0152] With the above variations and applications in view, it should be understood that the application is not limited to the foregoing description, but is only limited by the scope of the appended claims and the equivalents thereof.

Claims

1. A package (200) comprising: - a package body (20) having a package top side (201), a package footprint side (202), and a package sidewall (203) extending from the package footprint side (202) to the package top side (201); - a plurality of power semiconductor chips (100) electrically connected in parallel to each other, each power semiconductor chip (100) having a first load terminal (101) and a second load terminal (102) and being configured to block a blocking voltage applied between the first load terminal (101) and the second load terminal (102) and to conduct a chip load current between the first load terminal (101) and the second load terminal (102); - a leadframe structure (21) for electrically and mechanically coupling the package (200) to a carrier (300) with the package footprint side (202) facing the carrier (300), the leadframe structure (21) comprising a plurality of first external terminals (2111), wherein each first external terminal (2111) extends out of the package body (20) to establish an interface connection with the carrier (300), each first load terminal (101) of the plurality of power semiconductor chips (100) being electrically connected to at least two first external terminals (2111) of the plurality of first external terminals (2111) by means of at least one package body internal connection member (270); - a horizontally extending conductive layer (22) at the package top side (201) or at the package footprint side (202), wherein the conductive layer (22) is electrically connected with each second load terminal (102) of the plurality of power semiconductor chips (100).

2. The package (200) of claim 1, wherein, The conductive layer (22) is monolithic and horizontally overlaps each power semiconductor chip (100).

3. The package (200) according to claim 1 or 2, wherein Each of the plurality of power semiconductor chips (100) is controllable and comprises a respective control terminal (103).

4. The package (200) of claim 3, wherein, The leadframe structure (21) comprises a plurality of control external terminals (2131) for establishing an interface connection with the carrier (300), wherein each of the plurality of control external terminals (2131) is electrically connected with a control terminal (103) of at least one of the plurality of power semiconductor chips (100).

5. The package (200) of claim 1 or 2, wherein, Each power semiconductor chip (100) is arranged at a same vertical level within the package body (20).

6. The package (200) of claim 1 or 2, wherein, The leadframe structure (21) does not comprise an external terminal extending out of the package body (20) and being electrically connected with one or more second load terminals (102) of the power semiconductor chips (100), irrespective of the horizontally extending conductive layer (22).

7. The package (200) according to claim 1 or 2, wherein, - each of the first external terminals (2111) extends out of a first one of the package side walls (203) of the package body (20) or out of a second one of the package side walls (203) of the package body (20), the first and the second package side wall being arranged opposite to each other; - for each first load terminal (101) of the plurality of power semiconductor chips (100), at least one of the at least two first external terminals (2111) provided for the respective first load terminal (101) extends out of the first package side wall and at least one other of the at least two first external terminals (2111) provided for the respective first load terminal (101) extends out of the second package side wall.

8. The package (200) of claim 7, wherein, The at least two first external terminals (2111) provided for each first load terminal (101) are electrically connected to each other by means of the at least one package body internal connection member (270) within the package body (20).

9. The package (200) of claim 1 or 2, wherein, The package top side (201) has a total horizontal surface area of: - at least 4 cm 2 ; and / or - is exposed to an environment of the package body (20) such that the horizontal surface area of the conductive layer (22) is not enclosed within the package body (20) but forms part of an outer surface.

10. The package (200) of claim 1 or 2, wherein, The horizontally extending conductive layer (22) - is monolithic; and / or - laterally overlaps each of the power semiconductor chips (100); and / or - is arranged substantially coplanar to the package top side (201); and / or - does not laterally protrude from the package top side (201); and / or - has a horizontal surface area which amounts to at least 50%, at least 60%, or even more than 80%, but less than 100% of the total horizontal surface area of the package top side (201).

11. The package (200) of claim 1 or 2, wherein, Each power semiconductor chip (100) is configured to block a blocking voltage of at least 500 V.

12. The package (200) of claim 1 or 2, wherein, A static ohmic resistance measured between the horizontally extending conductive layer (22) and the plurality of first external terminals (2111) is less than 5 mOhm during conduction of the chip load current.

13. The package (200) of claim 3, wherein, Each power semiconductor chip (100) has a vertical configuration according to which a first load terminal (101) of each power semiconductor chip (100) and a control terminal (103) of each power semiconductor chip (100) are arranged at a chip front side and a second load terminal (102) of each power semiconductor chip (100) is arranged at a chip back side, and wherein each power semiconductor chip (100) is arranged in the package (200) such that the chip front side of each power semiconductor chip (100) faces the package top side (201).

14. The package (200) of claim 1 or 2, wherein, The plurality of power semiconductor chips (100) comprises a first subset of N>2 power semiconductor chips (100) and a second subset of N power semiconductor chips (100), wherein the power semiconductor chips (100) of the first subset are arranged along a first path (100-A), and wherein the power semiconductor chips (100) of the second subset are arranged along a second path (100-B), which is parallel to the first path (100-A) and horizontally shifted with respect to the first path (100-A).

15. The package (200) of claim 1 or 2, wherein, Each of the plurality of first external terminals (2111) extends out of the package body (20) at a respective one of the package side walls (203).

16. The package (200) of claim 15, wherein, Each first external terminal (2111) is arranged at a vertically centered position of the respective package side wall (203).

17. A system (1000) for providing a load current to a load (500), the system (1000) comprising: - a power supply (400); - a power supply path (600) for coupling the power supply (400) to the load (500); - a system switch (700) in the power supply path (600), wherein the system switch (700) comprises one or more packages (200) according to any one of claims 1 to 16, wherein one or more of the packages (200) are configured to conduct the load current at least partially.

Images