Semiconductor device

Abstract

Aspects of the present disclosure relate to a semiconductor device, the semiconductor device including: a crystalline substrate having a first surface and a second surface facing away from each other in a vertical direction; and an insulating layer disposed on the first surface of the crystalline substrate. The semiconductor device may further include: an etch stop layer interposed between the crystalline substrate and the insulating layer and contacting the crystalline substrate and the insulating layer; and a conductive via structure penetrating the crystalline substrate and the insulating layer. The semiconductor device may further include an insulating separation layer disposed horizontally adjacent to the conductive via structure and having an inner wall and an outer wall. The insulating separation layer may include a first portion disposed between the conductive via structure and the crystalline substrate and a second portion disposed between the conductive via structure and the etch stop layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0109641, filed on Sep. 4, 2019, with the Korean Intellectual Property Office (KIPO), the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a through-silicon via and a method of manufacturing the same. Background Art

[0003] A semiconductor device may be electrically connected to another semiconductor device or a printed circuit board through a via. The via may be used in three-dimensional chip mounting and may transfer a transfer speed faster than that of a conventional solder ball or solder bump. As semiconductor devices become highly integrated, there is a need to develop physically and electrically reliable vias. Summary of the Invention

[0004] A semiconductor device according to an exemplary embodiment of the inventive concept is provided. An aspect of the present disclosure relates to a semiconductor device including a crystalline substrate having a first surface and a second surface facing each other in a vertical direction. The semiconductor device may further include an insulating layer disposed on the first surface of the crystalline substrate. The semiconductor device may further include an etch stop layer interposed between the crystalline substrate and the insulating layer and contacting the crystalline substrate and the insulating layer. The semiconductor device may further include a conductive via structure penetrating the crystalline substrate and the insulating layer. The semiconductor device may further include an insulating partition layer disposed adjacent to the conductive via structure in a horizontal direction and having an inner wall and an outer wall facing away from the inner wall, the inner wall contacting the conductive via structure. The insulating partition layer may include a first portion disposed between the conductive via structure and the crystalline substrate and a second portion disposed between the conductive via structure and the etch stop layer. The outer wall of the second portion may protrude in a horizontal direction from the outer wall of the first portion with respect to the conductive via structure.

[0005] An additional aspect of the present disclosure relates to a semiconductor device including a crystalline semiconductor substrate. The semiconductor device may further include an etch stop layer disposed on the first surface of the crystalline semiconductor substrate. The semiconductor device may further include a conductive via structure penetrating the crystalline semiconductor substrate and the etch stop layer. The semiconductor device may further include an insulating partition layer disposed between the conductive via structure and the crystalline semiconductor substrate. A lower portion of the insulating partition layer may contact a portion of the etch stop layer.

[0006] Additional aspects of the present disclosure relate to a semiconductor device. The semiconductor device may include a substrate. The semiconductor device may further include a first semiconductor device disposed on the substrate. The semiconductor device may further include a second semiconductor device disposed on the first semiconductor device. The first semiconductor device may include: a first crystalline semiconductor substrate; a first etch stop layer disposed on a first surface of the first crystalline semiconductor substrate. The first semiconductor device may further include: a first conductive via structure penetrating the first crystalline semiconductor substrate and the first etch stop layer and having a height of 10 μm to 100 μm; and a first insulating spacer layer disposed between the first conductive via structure and the first crystalline semiconductor substrate. A lower portion of the first insulating spacer layer may contact a portion of the first etch stop layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Some example embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0008] Figure 1 is a cross-sectional view showing a semiconductor device according to an example embodiment.

[0009] Figure 2A is a cross-sectional view showing a semiconductor device according to an example embodiment.

[0010] Figure 2B is Figure 2A an enlarged view of region B of

[0011] Figure 2C is a cross-sectional view showing a via structure and a wiring pattern according to an example embodiment.

[0012] Figure 3A , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3H , Figure 3I and Figure 3J are cross-sectional views for describing a method of manufacturing a semiconductor device according to an example embodiment.

[0013] Figure 3B is Figure 3A an enlarged view of region B of

[0014] Figure 3G is Figure 3F an enlarged view of region B of

[0015] Figure 4A , Figure 4B and Figure 4D are cross-sectional views for describing a method of manufacturing a semiconductor device according to an example embodiment.

[0016] Figure 4C isFigure 4B An enlarged view of region B.

[0017] Figure 4E is Figure 4D An enlarged view of region B.

[0018] Figure 5A is a cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0019] Figure 5B is Figure 5A An enlarged view of region B.

[0020] Figures 6A to 6E is a cross-sectional view for describing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0021] Figure 7 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment. Detailed Description of the Invention

[0022] Hereinafter, some embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used for like components, and their repeated description will be omitted.

[0023] Figure 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0024] Referring to Figure 1 , the semiconductor device may include a semiconductor substrate 100, a wiring layer 200, an etch stop layer 300, a separation layer 400, and a via structure 500. The semiconductor device may be a semiconductor chip including a memory chip, a logic chip, or a combination thereof. The semiconductor substrate 100 may be a wafer-level substrate or a chip-level substrate. The semiconductor substrate 100 may be a crystalline semiconductor substrate. For example, the semiconductor substrate 100 may be in a single crystal state. The semiconductor substrate 100 may be formed of silicon, germanium, or silicon-germanium. The semiconductor substrate 100 may have a first surface 101 and a second surface 102 facing each other. The first surface 101 of the semiconductor substrate 100 may be a front surface, and the second surface 102 may be a back surface. The second surface 102 of the semiconductor substrate 100 may be parallel to the first surface 101.

[0025] The etch stop layer 300 and the wiring layer 200 may be provided on the first surface 101 of the semiconductor substrate 100. That is, the layers 200 and 300 may be provided below the first surface 101 and / or in contact with the first surface 101 in the vertical direction. It should be understood that the term "on" as used throughout this disclosure will be broadly interpreted to have the meaning understood from the context of this disclosure and the exemplary illustrations. For example, "on" should include the meaning of "on" something from above and the meaning of "on" something from below, and does not require the specified items to be directly adjacent to each other. The etch stop layer 300 may be interposed between the semiconductor substrate 100 and the wiring layer 200. As another example, the wiring layer 200 may include a plurality of insulating layers, and the etch stop layer 300 may be interposed between the insulating layers.

[0026] The via structure 500 may be formed in the semiconductor substrate 100 and may penetrate at least a part of the wiring layer 200 and the etch stop layer 300. The via structure 500 may be a conductive via structure. The spacer layer 400 may be interposed between the via structure 500 and the semiconductor substrate 100. The spacer layer 400 may be an insulating spacer layer. The connection terminal 610 may be provided on the bottom surface of the wiring layer 200. The connection terminal 610 may include solder balls. The connection terminal 610 may include a conductive material, for example, a metal. The connection terminal 610 may include, for example, tin, silver, bismuth, and / or their alloys. The connection terminal 610 may be electrically connected to the via structure 500. In this disclosure, "electrically connected / electrically contacted" may mean direct connection / direct contact or indirect connection / indirect contact via other conductive components. However, the term "contact" and "in contact with" used in a physical sense mean direct connection (e.g., touching). The via structure 500 and the connection terminal 610 may transmit electrical signals to or from the semiconductor device. In this disclosure, being electrically connected to the semiconductor device may mean being electrically connected to at least one integrated circuit in the integrated circuit of the semiconductor device. Hereinafter, the semiconductor device according to the exemplary embodiment will be described in more detail.

[0027] Figure 2A is a cross-sectional view showing a semiconductor device according to an exemplary embodiment and is Figure 1 an enlarged view of region A of Figure 2B is Figure 2A an enlarged view of region B of Figure 2C is a cross-sectional view for describing a via structure and a wiring pattern according to an exemplary embodiment and corresponds to Figure 2A an enlarged view of region B of . Hereinafter, descriptions repeating the above will be omitted.

[0028] Referring to Figure 1 、 Figure 2A and Figure 2B, The semiconductor device includes a crystalline semiconductor substrate 100, an integrated circuit 150, a wiring layer 200, an etch stop layer 300, a separation layer 400, and a via structure 500. The wiring layer 200 is disposed on the first surface 101 of the semiconductor substrate 100. For example, the wiring layer 200 may be disposed under the first surface 101. The wiring layer 200 may also be disposed in the vertical direction between the first surface 101 and the connection terminal 610. The wiring layer 200 may include a first insulating layer 211, a second insulating layer 212, and a wiring structure 250. The integrated circuit 150 may be disposed in the semiconductor substrate 100 or on the first surface 101 of the semiconductor substrate 100. For example, the integrated circuit 150 may include transistors. The integrated circuit 150 may include a doped region 105, and the doped region 105 may be used as a source / drain region of the transistor. The first insulating layer 211 may cover the etch stop layer 300 and the integrated circuit 150. The first insulating layer 211 may contact the bottom surface of the first surface 101 and / or be disposed on the bottom surface of the first surface 101. The first insulating layer 211 may include a semiconductor oxide such as silicon oxide, silicon oxynitride, or silicon carbonitride. The first insulating layer 211 may be amorphous. The first insulating layer 211 may be a multi-layer. The second insulating layer 212 may be disposed on the bottom surface of the first insulating layer 211. The second insulating layer 212 may include a plurality of stacked second insulating layers 212. The (one or more) second insulating layer 212 may be amorphous. The (one or more) second insulating layer 212 may include a semiconductor oxide such as silicon oxide, silicon oxynitride, or silicon carbonitride.

[0029] The wiring structure 250 is disposed on the first surface 101 of the semiconductor substrate 100, and may be disposed in the first insulating layer 211 and the second insulating layer 212 or between the insulating layers 211 and 212. For example, a part of the wiring structure 250 may be disposed under the first surface 101 and may contact the first surface 101. The wiring structure 250 may include a contact plug 251, a metal via 252, and a wiring pattern 253. The wiring structure 250 may include a conductive material, for example, copper or tungsten. The contact plug 251 passes through the first insulating layer 211 and may be connected to the integrated circuit 150. The wiring pattern 253 may be disposed between the insulating layers 211 and 212. At least one of the wiring patterns 253 may be electrically connected to the contact plug 251. The metal via 252 passes through at least one of the second insulating layers 212 and may be connected to a corresponding one of the wiring patterns 253.

[0030] An etch stop layer 300 is provided on a first surface 101 of a semiconductor substrate 100. The etch stop layer 300 may be in physical contact with the first surface 101 of the semiconductor substrate 100. The etch stop layer 300 may be provided between any one of the wiring patterns 253 in the wiring pattern 253 and the semiconductor substrate 100. The etch stop layer 300 may be interposed between the semiconductor substrate 100 and the first insulating layer 211. The etch stop layer 300 may include a material different from the semiconductor substrate 100 and the first insulating layer 211. The etch stop layer 300 may include a material having an etch selectivity with respect to the semiconductor substrate 100 and the first insulating layer 211. The etch stop layer 300 may include aluminum (Al), silicon (Si), carbon (C), oxygen (O), nitrogen (N), and / or hydrogen (H). For example, the etch stop layer 300 may include silicon nitride (SiN x ), silicon carbonitride (SiC x N y ), and / or aluminum oxide (AlO x ), where x and y are each independently a positive real number.

[0031] A via structure 500 is provided in the semiconductor substrate 100, the etch stop layer 300, and the first insulating layer 211. For example, a via 490 penetrates the semiconductor substrate 100, the etch stop layer 300, and the first insulating layer 211, and the via structure 500 is provided in the via 490. The via structure 500 may be connected to the wiring structure 250. For example, the via structure 500 may contact one of the wiring patterns 253 in the wiring pattern 253. The height H of the via structure 500 may be relatively much greater than the height of the metal via 252 and the height of the contact plug 251. For example, the height H of the via structure 500 may be about 10 μm to about 100 μm.

[0032] The via structure 500 may include a barrier pattern 510, a seed pattern 520, and a conductive via 530. The barrier pattern 510 may be provided along a sidewall 500c and a bottom surface 500b of the via structure 500. The barrier pattern 510 may be formed between the conductive via 530 and the substrate 100, between the conductive via 530 and the etch stop layer 300, between the conductive via 530 and the first insulating layer 211, and between the conductive via 530 and one of the wiring patterns 253 in the wiring pattern 253. The barrier pattern 510 may be interposed between the conductive via 530 and any one of the wiring patterns 253. The barrier pattern 510 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium, cobalt, and their alloys.

[0033] The seed pattern 520 can extend along the blocking pattern 510 on the blocking pattern 510. The seed pattern 520 can be interposed between the blocking pattern 510 and the conductive via 530. The seed pattern 520 can include a conductive material such as a metal. The seed pattern 520 can include, for example, copper, tungsten, manganese, titanium, or an alloy thereof.

[0034] The conductive via 530 is disposed on the seed pattern 520 and fills the through hole 490. The conductive via 530 can include a metal such as copper or tungsten. The top surface of the conductive via 530 can be disposed at substantially the same level as the top surface of the seed pattern 520, the top surface of the blocking pattern 510, and the top surface of the spacer layer 400. It should be understood that the terms described as "substantially the same", "substantially equal", and "substantially planar" can be exactly the same, exactly equal, exactly planar, or at the same level, or these terms can be the same, equal, planar, or at the same level within acceptable variations that may occur, for example, due to manufacturing processes.

[0035] As Figure 2B and Figure 2C As shown in [relevant figure], the wiring pattern 253 can include a blocking metal film 256, a seed metal film 255, and a metal pattern 254. The metal pattern 254 can have a first surface 254a and a second surface 254b facing away from each other, for example, an upper surface and a lower surface. The first surface 254a of the metal pattern 254 can face the first surface 101 of the semiconductor substrate 100. The metal pattern 254 can include copper or tungsten. The blocking metal film 256 and the seed metal film 255 can be interposed between the metal pattern 254 and the first insulating layer 211. For example, the blocking metal film 256 can be interposed between the first surface 254a of the metal pattern 254 and the first insulating layer 211, and between the metal pattern 254 and the via structure 500. The via structure 500 can physically contact the blocking metal film 256. For example, the blocking pattern 510 (blocking layer) can physically contact the blocking metal film 256. The blocking metal film 256 can further extend on the side surface 254c of the metal pattern 254 to be interposed between the metal pattern 254 and a corresponding one of the second insulating layers 212 in the second insulating layer 212. The blocking metal film 256 can include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The seed metal film 255 can be disposed between the metal pattern 254 and the blocking metal film 256. In one embodiment, the seed metal film 255 covers the first surface 254a (uppermost surface) and the side surface 254c of the metal pattern 254, but does not cover the second surface 254b (lowermost surface) of the metal pattern 254. The seed metal film 255 can include, for example, copper, manganese, titanium, or an alloy thereof.

[0036] As Figure 2BAs shown, the bottom surface 500b of the through-hole structure 500 may be rounded or chamfered. The bottom surface 500b of the through-hole structure 500 may correspond to the bottom surface of the barrier pattern 510 (barrier layer). The bottom surface 500b of the through-hole structure 500 may bulge downward. The bottom surface 500b of the through-hole structure 500 may have a central portion and an edge portion. In a plan view, the edge portion may be interposed between the central portion and the side wall 500c of the through-hole structure 500. The central portion may be disposed at a level lower than the edge portion. Since the bottom surface 500b of the through-hole structure 500 is rounded, the contact area between the through-hole structure 500 and the wiring pattern 253 may be increased. Accordingly, the through-hole structure 500 and the wiring pattern 253 may be electrically connected. For example, the through-hole structure 500 may further extend into the seed metal film 255 such that the barrier pattern 510 contacts the seed metal film 255. As another example, the bottom surface 500b of the through-hole structure 500 may be disposed in the barrier metal film 256, and the through-hole structure 500 may not extend all the way to contact the seed metal film 255.

[0037] As Figure 2C shown, the bottom surface 500b of the through-hole structure 500 may be substantially flat, substantially smooth or substantially planar. The central portion of the bottom surface 500b of the through-hole structure 500 may be disposed at substantially the same level as the edge portion of the bottom surface 500b. As shown in the present embodiment, the through-hole structure 500 contacts the barrier metal film 256 without contacting the seed metal film 255 or the metal pattern 254.

[0038] As Figure 2A shown, the wiring pattern 253 may include a plurality of wiring patterns 253. For simplicity, in Figure 2B , Figure 2C , Figure 3B , Figure 3G , Figure 4C , Figure 4E and Figure 5B the metal pattern 254, the seed metal film 255 and the barrier metal film 256 are shown in detail. However, each of the wiring patterns 253 may include the metal pattern 254, the seed metal film 255 and the barrier metal film 256 as shown in Figure 2B and Figure 2C shown. In each of the wiring patterns 253, the barrier metal film 256 may be disposed on the first surface 254a of the metal pattern 254. For simplicity, a single wiring pattern 253, the barrier metal film 256 and the seed metal film 255 will be described below.

[0039] The separation layer 400 can surround the sidewall 500c of the through-hole structure 500. The separation layer 400 can be arranged adjacent to the through-hole structure 500. The separation layer 400 arranged adjacent to the through-hole structure 500 can be in physical contact with the through-hole structure 500. The separation layer 400 can include a first portion 410 and a second portion 420. The first portion 410 can be arranged between the through-hole structure 500 and the semiconductor substrate 100. The second portion 420 can be arranged between the through-hole structure 500 and the etch stop layer 300, can be electrically connected to the first portion 410, and can protrude toward the side surface of the etch stop layer 300. The second portion 420 of the separation layer 400 can include the same material as that of the first portion 410 and can be connected to the first portion 410 without any interface. As Figure 2B shown, the second portion 420 of the separation layer 400 can be interposed between the first surface 101 and the first insulating layer 211. The separation layer 400 can not be arranged in the first insulating layer 211. For example, the bottom surface of the separation layer 400 can be arranged at substantially the same level as the bottom surface of the etch stop layer 300.

[0040] The separation layer 400 can have an inner wall facing the through-hole structure 500 and an outer wall facing away from the inner wall. As Figure 2B shown, the inner wall of the separation layer 400 can include a first inner wall 410c of the first portion 410 and a second inner wall 420c of the second portion 420. The outer wall of the separation layer 400 can include a first outer wall 410d of the first portion 410 and a second outer wall 420d of the second portion 420. The first inner wall 410c and the second inner wall 420c of the separation layer 400 can be in physical contact with the barrier pattern 510. The second inner wall 420c of the separation layer 400 can be connected to the first inner wall 410c. The second outer wall 420d of the second portion 420 of the separation layer 400 can not be aligned with the first outer wall 410d of the first portion 410. The second portion 420 of the separation layer 400 can protrude toward the etch stop layer 300. For example, the second outer wall 420d can protrude laterally outward relative to the first outer wall 410d of the first portion 410. The second gap D2 between the second outer wall 420d and the sidewall 500c can be larger than the first gap D1 between the first outer wall 410d and the sidewall 500c of the through-hole structure 500. The separation layer 400 can contact a part of the etch stop layer 300. For example, the lower part of the separation layer 400 can contact a part of the etch stop layer 300, and the lower part of the separation layer 400 can correspond to the second portion 420.

[0041] The through-hole structure 500 can include a first sidewall and a second sidewall opposite to the first sidewall. As Figure 2BAs shown, the separation layer 400 may include a first insulating separation pattern 401 and a second insulating separation pattern 402 facing the first insulating separation pattern 401. The first insulating separation pattern 401 (also described as the first insulating isolation pattern) may be provided on the first sidewall of the through-hole structure 500. The second insulating separation pattern 402 (also described as the second insulating isolation pattern) may be provided on the second sidewall of the through-hole structure 500. Each of the first insulating separation pattern 401 and the second insulating separation pattern 402 may include a first portion 410 and a second portion 420.

[0042] The separation layer 400 may electrically separate the semiconductor substrate 100 from the through-hole structure 500. Leakage current of the through-hole structure 500 may be prevented and / or suppressed by the separation layer 400. The separation layer 400 may include an insulating material such as silicon oxide or silicon oxynitride.

[0043] The through-hole structure 500 may be spaced apart from the integrated circuit 150 by a predetermined distance. For example, the through-hole structure 500 may be horizontally spaced apart from the doped region 105. In the present disclosure, "horizontal" may indicate a direction parallel to the first surface 101 of the semiconductor substrate 100.

[0044] As Figure 2A shown, a third insulating layer 910 may be further provided on the second surface 102 of the semiconductor substrate 100 to cover the second surface 102 of the semiconductor substrate 100. The through-hole structure 500 may be provided in the third insulating layer 910. The third insulating layer 910 may expose the top surface of the through-hole structure 500. The third insulating layer 910 may include a carbon-containing material such as a spin on carbon (SOC) hard mask material. The carbon-containing material may be amorphous. As another example, the third insulating layer 910 may be omitted.

[0045] As Figure 2A shown, a conductive pad (also referred to as a "bond pad" or "pad") 620 may be provided on the second surface 102 of the semiconductor substrate 100 and may cover the top surface of the through-hole structure 500 and the top surface of the third insulating layer 910. The conductive pad 620 may be electrically connected to the through-hole structure 500. The conductive pad 620 may be electrically connected to the integrated circuit 150 through the through-hole structure 500 and the wiring structure 250. The conductive pad 620 may be used as a terminal for electrically connecting to an external device. The external device may be, for example, a semiconductor chip, a passive device, a substrate, or a board. The conductive pad 620 may include a metal such as copper, aluminum, titanium, and / or an alloy thereof.

[0046] The terminal pad 260 may be provided on the bottom surface of the wiring layer 200. The terminal pad 260 may be electrically connected to the integrated circuit 150 or the through-hole structure 500 through the wiring structure 250. The terminal pad 260 may include a metal material such as copper, titanium, or aluminum. A connection terminal 610 may be further provided on the terminal pad 260. The connection terminal 610 may be electrically connected to the terminal pad 260.

[0047] A protective layer 700 may be further provided on the bottom surface of the wiring layer 200. The protective layer 700 may have a terminal opening exposing the terminal pad 260. The protective layer 700 may include an insulating material, for example, an insulating polymer.

[0048] Figure 3A 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F 、 Figure 3H 、 Figure 3I and Figure 3J is a cross-sectional view for describing a method of manufacturing a semiconductor device according to example embodiments. Figure 3B yes Figure 3A Magnified view of area B. Figure 3G yes Figure 3F Hereinafter, the description repeating the above description will be omitted. Figure 3A When, refer to Figure 3A Describes the top surface, bottom surface, lowermost part and uppermost part, Figure 3A The top surface, bottom surface, lowermost portion and uppermost portion described in Figures 2A to 2B and Figures 3C to 3J The top surface, bottom surface, lowermost portion, and uppermost portion shown in FIG are oriented differently. For example, Figure 3A The wiring layer 200 is shown as being located on top of the first surface 101 in the vertical direction, while Figure 2A The wiring layer 200 is shown as being located on the bottom of the first surface 101 in the vertical direction.

[0049] Reference Figure 3A and Figure 3B An etch stop layer 300 and a wiring layer 200 are formed on the first surface 101 (upper surface) of the semiconductor substrate 100. In an exemplary embodiment, a semiconductor substrate 100 having a crystalline structure is prepared. Doped regions 105 may be formed by implanting conductive impurities into the first surface 101 of the semiconductor substrate 100. An integrated circuit 150 may be formed on the first surface 101 of the semiconductor substrate 100 or in the semiconductor substrate 100. Formation of the integrated circuit 150 may include forming the doped regions 105.

[0050] An etch stop layer 300 is formed on a first surface 101 of a semiconductor substrate 100 to cover the first surface 101 of the semiconductor substrate 100. The etch stop layer 300 may be in physical contact with the first surface 101 of the semiconductor substrate 100.

[0051] A first insulating layer 211 is formed on the etch stop layer 300 to cover the integrated circuit 150. The first insulating layer 211 may include a plurality of insulating layers. A contact plug 251 may pass through the first insulating layer 211 and may be connected to the integrated circuit 150. The contact plug 251 may also pass through the etch stop layer 300. A second insulating layer 212 may be formed on the first insulating layer 211.

[0052] As Figure 3B shown, a trench 213 may be formed in the second insulating layer 212 to expose the first insulating layer 211. A barrier metal film 256 may be formed in the trench 213 to conformally cover the bottom and sidewalls of the trench 213. A seed metal film 255 may be formed on the barrier metal film 256. By performing an electroplating process using the seed metal film 255 (e.g., a seed metal layer) as an electrode, a metal pattern 254 may be formed on the seed metal film 255 (seed metal layer). Thereafter, a patterning process of the barrier metal film 256, the seed metal film 255, and the metal pattern 254 may be further performed. The patterning process may include removing the barrier metal film 256, the seed metal film 255, and the metal pattern 254 located on the top surface of the second insulating layer 212. Accordingly, the barrier metal film 256, the seed metal film 255, and the metal pattern 254 may be disposed in the trench 213. Accordingly, the formation of the wiring pattern 253 may be completed.

[0053] The formation of the second insulating layer 212 and the formation of the wiring pattern 253 may be repeatedly performed. Accordingly, a plurality of stacked second insulating layers 212 may be formed as Figure 3A shown, and the wiring pattern 253 may be formed between the second insulating layers 212. Although not shown in Figure 3A each of the wiring patterns 253 may include a barrier metal film 256, a seed metal film 255, and a metal pattern 254. In each of the wiring patterns 253, the barrier metal film 256 may be interposed between the semiconductor substrate 100 and the metal pattern 254. A metal via 252 may be formed to penetrate at least one of the second insulating layers 212. The wiring pattern 253 and the metal via 252 may be formed by, for example, a damascene process, but are not limited thereto. Hereinafter, a single wiring pattern 253 will be described.

[0054] A terminal pad 260 may be formed on the uppermost second insulating layer 212 to connect the terminal pad 260 to the wiring structure 250. A protective layer 700 may be further formed on the wiring layer 200. The protective layer 700 may expose at least a portion of the terminal pad 260.

[0055] Referring Figure 3C , the semiconductor substrate 100 is turned upside down such that the second surface 102 of the semiconductor substrate 100 faces upward, i.e., the semiconductor substrate 100 may be oriented such that the second surface 102 is the upper surface. Thereafter, a portion of the semiconductor substrate 100 may be removed to thin the semiconductor substrate 100. Thinning of the semiconductor substrate 100 may include performing a planarization process on the second surface 102 of the semiconductor substrate 100. The planarization process may be, for example, a chemical mechanical polishing process.

[0056] Referring Figure 3D , a first mask pattern 911 and a second mask pattern 920 are formed on the second surface 102 of the thinned semiconductor substrate 100. The first mask pattern 911 may cover the second surface 102 of the semiconductor substrate 100. The first mask pattern 911 may be a hard mask layer. For example, the first mask pattern 911 may include a carbon-containing material, such as a spin-on carbon (SOC) hard mask material as an example. The second mask pattern 920 may be formed on the first mask pattern 911. For example, the second mask pattern 920 may be formed by coating a photoresist material on the first mask pattern 911 to form a mask layer and performing a patterning process on the mask layer to form the second mask pattern 920. The patterning process may include an exposure process and a development process. The second mask pattern 920 may have a guiding opening 929. The first opening 919 may be formed in the first mask pattern 911 by an etching process using the second mask pattern 920. The first opening 919 may be aligned with the guiding opening 929 and may expose the second surface 102 of the semiconductor substrate 100.

[0057] Referring Figure 3E , a through hole 490 is formed in the semiconductor substrate 100 to expose the etch stop layer 300. In an exemplary embodiment, a first etching process may be performed on the second surface 102 of the semiconductor substrate 100 exposed by the first opening 919 to form the through hole 490. For example, the first etching process may be an anisotropic etching process. The first etching process may include, for example, a dry etching process using a fluorine-containing gas. In the dry etching process, the etch stop layer 300 may have an etching selectivity with respect to the semiconductor substrate 100. For example, the etch stop layer 300 may have a very low etching rate or may not be etched. Therefore, after the first etching process is completed, the through hole 490 may expose the top surface of the etch stop layer 300.

[0058] In the first etching process, interface defects may be formed on the sidewalls of the through-hole 490. For example, interface defects may be formed on the sidewall 100c of the semiconductor substrate 100 exposed by the through-hole 490.

[0059] The through-hole 490 may be spaced apart from the integrated circuit 150 by a predetermined distance. Thus, damage to the integrated circuit 150 due to the first etching process can be prevented.

[0060] Refer to Figure 3F and Figure 3G and, the etch stop layer 300 is removed to extend the through-hole 490 into the etch stop layer 300. In an exemplary embodiment, a second etching process may be performed on the etch stop layer 300 in the through-hole 490. The second etching process may include a wet etching process. For example, an ammonium-containing material may be used as an etchant during the second etching process. The etch stop layer 300 can be removed by the second etching process. Thus, the through-hole 490 can extend into the etch stop layer 300. In the second etching process, the semiconductor substrate 100 and the first insulating layer 211 may have an etching selectivity with respect to the etch stop layer 300. For example, the semiconductor substrate 100 and the first insulating layer 211 may have a very low etching rate or may not be etched during the second etching process. The through-hole 490 may expose the top surface of the first insulating layer 211.

[0061] The second etching process may be an isotropic etching process. The etch stop layer 300 exposed to the through-hole 490 may be further removed horizontally to form a recessed portion 495. The recessed portion 495 may be connected to the through-hole 490. The recessed portion 495 may be recessed from the sidewall 100c of the semiconductor substrate 100 toward the etch stop layer 300. The recessed portion 495 may expose the inner surface 300c of the etch stop layer 300. The recessed portion 495 may be formed between the first surface 101 and the first insulating layer 211.

[0062] Refer to Figure 3H and, a separation layer 400 is formed in the through-hole 490 and the recessed portion 495. The separation layer 400 may be formed by a deposition process such as an atomic layer deposition process. The separation layer 400 may conformally cover the bottom surface and the sidewalls of the through-hole 490. For example, the separation layer 400 may conformally cover the exposed sidewall 100c of the semiconductor substrate 100, the top surface of the first insulating layer 211, and the top surface of the second mask pattern 920. The separation layer 400 may be disposed in the recessed portion 495. The separation layer 400 may fill the recessed portion 495. For example, the separation layer 400 may cover the inner surface 300c of the etch stop layer 300 and the exposed first surface 101 of the semiconductor substrate 100.

[0063] The spacer layer 400 may include a first portion 410, a second portion 420, and a third portion 430. The first portion 410 may be disposed on the sidewall 100c of the semiconductor substrate 100. The second portion 420 may be disposed in the recessed portion 495. The third portion 430 may be disposed on the top surface of the first insulating layer 211 and may not extend into the recessed portion 495. In a plan view, the third portion 430 may be surrounded by the first portion 410.

[0064] Referring Figure 3H and Figure 3I , a portion of the first insulating layer 211 and the third portion 430 are removed to extend the through hole 490 into the first insulating layer 211. In an exemplary embodiment, a third etching process may be performed on the spacer layer 400 in the through hole 490. The third etching process may be, for example, an anisotropic etching process. For example, the third etching process may be performed by a dry etching process using a fluorine-containing gas. The third portion 430 of the spacer layer 400 and the said portion of the first insulating layer 211 may be removed by the third etching process. The removed portion of the first insulating layer 211 may be the portion interposed between the third portion 430 and one of the wiring patterns 253 in the wiring pattern 253. The through hole 490 may extend into the first insulating layer 211 due to the third etching process, and the wiring pattern 253 may be exposed. Unless otherwise stated in the following description, the wiring pattern 253 may represent one of the wiring patterns 253 among the plurality of wiring patterns 253 that is connected to the through hole structure 500 or the contact through hole structure 500.

[0065] During the third etching process, the upper portion of the wiring pattern 253 may be partially etched. Accordingly, the upper surface 253a of the wiring pattern 253 exposed in the through hole 490 may be recessed. The upper surface 253a of the wiring pattern 253 exposed in the through hole 490 may be disposed at a level lower than the upper surface 253a of the wiring pattern 253 covered by the first insulating layer 211. The recessed upper surface 253a of the wiring pattern 253 may be rounded or curved. For example, the recessed upper surface 253a of the wiring pattern 253 may bulge downward. In another exemplary embodiment, the upper surface 253a of the wiring pattern 253 exposed in the through hole 490 may be substantially flat.

[0066] The spacer layer 400 on the second mask pattern 920 may be further removed by the third etching process to expose the second mask pattern 920. After the third etching process is completed, the first portion 410 and the second portion 420 of the spacer layer 400 may remain.

[0067] When the etch stop layer 300 is omitted and the via hole 490 is formed in the semiconductor substrate 100 and the first insulating layer 211 by a single etching process, it may be difficult to control the etching process. For example, the wiring pattern 253 may be damaged during the etching process. Or, in the etching process of the separation layer 400, the separation layer 400 may be damaged. In the exemplary embodiment, an etch stop layer 300 may be formed between the semiconductor substrate 100 and the wiring pattern 253, and an etch stop layer 300 may be formed between the semiconductor substrate 100 and the first insulating layer 211. The etch stop layer 300 may have different etching selectivities with respect to the semiconductor substrate 100 and the first insulating layer 211. Therefore, the via hole 490 may be formed by a first etching process, a second etching process, and a third etching process to expose the wiring pattern 253. Since the formation of the via hole 490 is performed by multiple etching processes, the etching of the via hole 490 can be controlled more precisely. Therefore, the undesired etching of the wiring pattern 253 or the separation layer can be reduced, suppressed, or prevented.

[0068] Referring to Figure 3J , a barrier layer 511, a seed layer 521, and a via layer 531 are formed in the via hole 490 and on the second surface 102 of the semiconductor substrate 100. In the exemplary embodiment, the barrier layer 511 may be formed by a deposition process to conformally cover the inner sidewall and the bottom surface of the via hole 490. For example, the barrier layer 511 may be formed on the upper surface 253a of the wiring pattern 253, the inner sidewall of the first insulating layer 211, the first inner wall of the first portion 410, and the second inner wall of the second portion. The barrier layer 511 may be horizontally spaced apart from the etch stop layer 300 by the second portion 420 of the separation layer 400. The barrier layer 511 may be horizontally spaced apart from the semiconductor substrate 100 by the first portion 410 of the separation layer 400. The barrier layer 511 may further extend on the second surface 102 of the semiconductor substrate 100 to cover the second mask pattern 920. The seed layer 521 may be formed on the barrier layer 511. The seed layer 521 may conformally cover the barrier layer 511 in the via hole 490 and on the second surface 102 of the semiconductor substrate 100.

[0069] The via layer 531 may be formed on the seed layer 521 to fill the via hole 490. The formation of the via layer 531 may include performing an electroplating process using the seed layer 521 as an electrode. The via layer 531 may extend on the second surface 102 of the semiconductor substrate 100 to cover the seed layer 521.

[0070] Returning to the reference Figure 2A and Figure 2B, a planarization process can be performed on the via layer 531 to form a via structure 500. The via structure 500 may include a barrier pattern 510, a seed pattern 520, and a conductive via 530. According to an embodiment, the planarization process may include a chemical mechanical polishing (CMP) process. The barrier layer 511, the seed layer 521, and the via layer 531 may be planarized to form the barrier pattern 510, the seed pattern 520, and the conductive via 530, respectively. The barrier layer 511, the seed layer 521, the via layer 531, and the spacer layer 400 on the second surface 102 of the semiconductor substrate 100 may be removed by the planarization process. The via structure 500 may be disposed in the via 490.

[0071] The top of the spacer layer 400, the top of the first mask pattern 911, and the second mask pattern 920 may be removed by the planarization process. As a result of the planarization process, the remaining first mask pattern 911 may form the third insulating layer 910. The top surface of the via structure 500 may be disposed at substantially the same level as the top surface of the third insulating layer 910. In another exemplary embodiment, the planarization process may be performed until the semiconductor substrate 100 is exposed.

[0072] As described above, when the etch stop layer 300 is omitted and the via 490 is formed by a single etching process, the contact resistance may increase due to damage to the wiring pattern 253. Alternatively, it may be difficult to sufficiently fill the inside of the via 490 to adequately form the via structure 500. When the spacer layer 400 is over-etched, at least a portion of the via structure 500 may contact the semiconductor substrate 100. Therefore, the electrical separation between the via structure 500 and the semiconductor substrate 100 may be insufficient.

[0073] According to some exemplary embodiments, the via 490 may be formed by a first etching process to a third etching process to prevent undesired etching of the wiring pattern 253 and the spacer layer 400. Thus, the inside of the via 490 may be satisfactorily filled with the via structure 500, and the contact resistance between the via structure 500 and the wiring pattern 253 may be improved. The via structure 500 may be spaced apart from the semiconductor substrate 100 by the spacer layer 400 and may be electrically separated from the semiconductor substrate 100. The reliability of the semiconductor device may be improved.

[0074] The via structure 500 may be formed by a via last process. For example, after the processes of forming the integrated circuit 150 and the wiring layer 200 and the process of thinning the semiconductor substrate 100, the via structure 500 may be formed.

[0075] A conductive pad 620 may be formed on the top surface of the through-hole structure 500 and on the third insulating layer 910 to electrically connect the conductive pad 620 to the through-hole structure 500. Although not shown, an upper passivation layer may be further formed on the third insulating layer 910. A connection terminal 610 may be formed on the bottom surface of the terminal pad 260. As described above, the manufacture of the semiconductor device may be completed.

[0076] Figure 4A 、 Figure 4B and Figure 4D is a cross-sectional view for describing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept, and is Figure 1 corresponds to the enlarged view of area A. Figure 4C yes Figure 4B Magnified view of area B. Figure 4E yes Figure 4D Hereinafter, descriptions repeating the above descriptions will be omitted.

[0077] Reference Figures 3A to 3H , an etch stop layer 300 and a wiring layer 200 may be formed on the first surface 101 of the semiconductor substrate 100. A first mask pattern 911 and a second mask pattern 920 may be formed on the second surface 102 of the semiconductor substrate 100. A through hole 490 may be formed in the semiconductor substrate 100 through the first etching process. The through hole 490 may be extended into the etch stop layer 300 through the second etching process, and a recessed portion 495 may be formed. A separation layer 400 may be formed on the bottom and inner wall of the through hole 490 and in the recessed portion 495. The separation layer 400 may extend on the sidewalls and top surface of the second mask pattern 920.

[0078] Reference Figure 4A , a capping pattern 930 may be formed on the top surface and sidewalls of the second mask pattern 920 to cover the separation layer 400. The capping pattern 930 may block a portion of the guide opening 929. The capping pattern 930 may have a second opening 939, which may be connected to the through-hole 490. The width W20 of the second opening 939 may be narrower than the width W10 of the through-hole 490 on the second surface 102 of the semiconductor substrate 100. The second opening 939 may overlap with the central area of the through-hole 490 in a plan view.

[0079] The capping pattern 930 may include a material having an etch selectivity with respect to the separation layer 400. The capping pattern 930 may include a nitrogen-containing material. The capping pattern 930 may include, for example, silicon nitride, silicon carbonitride, and / or silicon oxynitride.

[0080] Reference Figure 4B and Figure 4C, a third etching process may be performed on the spacer layer 400 exposed by the second opening 939. The third etching process may be, for example, an isotropic dry etching process. The third part 430 of the spacer layer 400 and a part of the first insulating layer 211 may be removed by the third etching process, and the top surface of the wiring pattern 253 may be exposed. In this case, the third part 430 and the said part of the first insulating layer 211 may be vertically stacked with the second opening 939. The second opening 939 may not be vertically stacked with the spacer layer 400 on the sidewall 100c of the semiconductor substrate 100. The cover pattern 930 may prevent the first part 410 of the spacer layer 400 from being etched during the third etching process. As used herein, unless otherwise clearly indicated, "vertical" may represent a direction substantially parallel to the direction perpendicular to the first surface 101 of the semiconductor substrate 100. The through hole 490 may extend into the first insulating layer 211 by the third etching process.

[0081] Since the second opening 939 has a width W20 narrower than the width of the through hole 490, the width of the through hole 490 in the first insulating layer 211 may be smaller than the width of the through hole 490 in the semiconductor substrate 100. For example, as Figure 4C shown, the maximum width W12 of the through hole 490 in the first insulating layer 211 may be smaller than the minimum width W11 of the through hole 490 in the semiconductor substrate 100.

[0082] As described in the example of the conductive pad 620 referred to Figure 3I , the upper surface of the wiring pattern 253 exposed by the third etching process may be further recessed. In another exemplary embodiment, the top surface of the wiring pattern 253 exposed by the through hole 490 may be substantially flat.

[0083] Referring to Figure 4D and Figure 4E , the cover pattern 930 (see Figure 4B ) may be removed, and a through hole structure 500 may be formed in the through hole 490. The formation of the through hole structure 500 may be similar to the steps described in reference to Figure 2A , Figure 2B and Figure 3J . As described in reference to Figure 3J [[ID=X]] ​

[0084] According to an embodiment, the through-hole structure 500 may have a shape corresponding to the through-hole 490. As Figure 4E shown, the maximum width W22 of the through-hole structure 500 in the first insulating layer 211 may be smaller than the minimum width W21 of the through-hole structure 500 in the semiconductor substrate 100. The bottom surface 500b of the through-hole structure 500 may bulge downward. The upper surface of the wiring pattern 253 may include a first upper surface that contacts the through-hole structure 500 and a second upper surface that contacts the first insulating layer 211. The first upper surface of the wiring pattern 253 may be disposed at a level lower than the second upper surface of the wiring pattern 253. Through the examples described so far, a semiconductor device can be manufactured.

[0085] Figure 5A is a cross-sectional view showing a semiconductor device according to an exemplary embodiment and corresponds to Figure 1 an enlarged view of region A of. Figure 5B shows Figure 5A an enlarged view of region B of. In the following, descriptions that repeat the above description will be omitted.

[0086] Referring to Figure 5A and Figure 5B , the semiconductor device may include a semiconductor substrate 100, a wiring layer 200, an etch stop layer 300, a separation layer 400, and a through-hole structure 500. The semiconductor substrate 100, the wiring layer 200, and the through-hole structure 500 may be the same as or similar to the semiconductor substrate 100, the wiring layer 200, and the through-hole structure 500 described in reference to Figures 2A to 2C . The wiring layer 200 may include a first insulating layer 211, a second insulating layer 212, and a wiring structure 250. The wiring structure 250 may include a contact plug 251, a metal via 252, and a wiring pattern 253. The wiring pattern 253 may include a barrier metal film 256, a seed metal film 255, and a metal pattern 254 as Figure 5B shown.

[0087] In addition, the etch stop layer 300 may be disposed between the first insulating layer 211 and the uppermost second insulating layer 212 and between the first insulating layer 211 and the wiring pattern 253. The etch stop layer 300 may physically contact the top surface of the wiring pattern 253. For example, as Figure 5B shown, the etch stop layer 300 may physically contact the barrier metal film 256 (barrier metal layer).

[0088] The through-hole structure 500 may be disposed in the semiconductor substrate 100, the first insulating layer 211, and the etch stop layer 300. The through-hole structure 500 may be horizontally spaced apart from the integrated circuit 150. The through-hole structure 500 may include a barrier pattern 510, a seed pattern 520, and a conductive via 530. As Figure 5BAs shown, the bottom surface 500b of the through-hole structure 500 can be substantially flat. The bottom surface 500b of the through-hole structure 500 can contact the barrier metal film 256 (barrier metal layer). The through-hole structure 500 may not contact the seed metal film 255 (seed metal layer).

[0089] The spacer layer 400 can surround the sidewall of the through-hole structure 500. The spacer layer 400 can be interposed between the semiconductor substrate 100 and the through-hole structure 500, and between the first insulating layer 211 and the through-hole structure 500. The spacer layer 400 may not extend into the etch stop layer 300. As Figure 5B shown, the lowermost surface 400b of the spacer layer 400 can be set at a level substantially the same as or higher than the level of the upper surface of the etch stop layer 300. The spacer layer 400 can expose the inner surface 300c of the etch stop layer 300. The inner wall 400c of the spacer layer 400 and the inner surface 300c of the etch stop layer 300 can be in physical contact with the through-hole structure 500. The spacer layer 400 can contact a part of the etch stop layer 300. For example, the lower part of the spacer layer 400 can contact a part of the etch stop layer 300, and the lower part of the spacer layer 400 can be the part including the lowermost surface 400b.

[0090] Figures 6A to 6E is a cross-sectional view for describing a method of manufacturing a semiconductor device according to an exemplary embodiment. Hereinafter, descriptions that repeat the above description will be omitted.

[0091] Referring to Figure 6A , a wiring layer 200 and an etch stop layer 300 can be formed on the first surface 101 of the semiconductor substrate 100. The formation of the wiring layer 200 can be performed by a method similar to the method described above with reference to Figure 2A . However, the etch stop layer 300 can be formed between the first insulating layer 211 and the wiring pattern 253, and between the first insulating layer 211 and the second insulating layer 212. A thinning process can be performed on the second surface 102 of the semiconductor substrate 100 to remove a part of the semiconductor substrate 100. A first mask pattern 911 and a second mask pattern 920 can be formed on the second surface 102 of the thinned semiconductor substrate 100.

[0092] Referring to Figure 6B, a first etching process can be performed on the semiconductor substrate 100 so that through-holes 490 can be formed in the semiconductor substrate 100 and the first insulating layer 211. In the first etching process, the mask patterns 911 and 920 can be used as etching masks. In the first etching process, the etch stop layer 300 can have an etching selectivity with respect to the semiconductor substrate 100 and the first insulating layer 211. After the first etching process is completed, the through-holes 490 can expose the top surface of the etch stop layer 300.

[0093] Referring to Figure 6C , a spacer layer 400 can be formed in the through-holes 490 to cover the bottom surface and sidewalls of the through-holes 490. For example, the spacer layer 400 can conformally cover the exposed sidewalls 100c of the semiconductor substrate 100, the sidewalls of the first insulating layer 211, and the top surface of the etch stop layer 300. The spacer layer 400 can extend on the top surface of the second mask pattern 920.

[0094] Referring to Figure 6D , a third etching process can be performed to remove a part of the spacer layer 400. The removed part of the spacer layer 400 can include the part of the spacer layer 400 located on the top surface of the etch stop layer 300 and the part of the spacer layer 400 located on the second mask pattern 920. In an exemplary embodiment, the third etching process can include an anisotropic dry etching process and can be performed under conditions similar to those of the Figure 3I example of the third etching process described above. In the third etching process, the etch stop layer 300 can have an etching selectivity with respect to the spacer layer 400. After the third etching process, the through-holes 490 can expose the top surface of the etch stop layer 300. The spacer layer 400 can remain on the sidewalls 100c of the semiconductor substrate 100 and the sidewalls of the first insulating layer 211.

[0095] Referring to Figure 6E , a second etching process can be performed to remove the exposed etch stop layer 300. The second etching process can include a wet etching process. Thus, the through-holes 490 can extend into the etch stop layer 300. The inner surface 300c of the etch stop layer 300 can be exposed to the through-holes 490.

[0096] In the second etching process, the wiring pattern 253 can not be etched. After the second etching process, the through-holes 490 can expose the top surface 253a of the wiring pattern 253. The exposed top surface 253a of the wiring pattern 253 can be substantially flat or substantially planar.

[0097] Returning to Figure 5A and Figure 5B , a via structure 500 can be formed in the through-holes 490. It can be formed in the same manner as referring to Figure 2A ,Figure 2B and Figure 3J The formation of the through-hole structure 500 is performed in substantially the same manner as described. As referred to Figure 3J above, the through-hole structure 500 can be formed by forming a barrier layer 511 (barrier film), a seed layer 521 (seed film), and a through-hole layer 531 (through-hole film), and then planarizing the barrier layer 511 (barrier film), the seed layer 521 (seed film), and the through-hole layer 531 to form a barrier pattern 510, a seed pattern 520, and a conductive via 530, respectively. In the planarization process, the upper portion of the first mask pattern 911, the upper portion of the spacer layer 400, and the second mask pattern 920 can be removed. After the planarization process, the remaining first mask pattern 911 can form the third insulating layer 910. Thereafter, a conductive pad 620 and a connection terminal 610 can be formed. Through the exemplary embodiments described so far, a semiconductor device can be manufactured.

[0098] Figure 7 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment. Hereinafter, descriptions repeating the above description will be omitted.

[0099] Referring to Figure 7 , the semiconductor package 1 includes a package substrate 1000, may include first to fourth semiconductor devices 11, 12, 13, and 14, and includes a molding film 5000. The package substrate 1000 may include a printed circuit board or a redistribution layer. External terminals 1600 may be provided on the bottom surface of the package substrate 1000. Metal pads 1700 may be provided on the top surface of the package substrate 1000. The metal pads 1700 may be electrically connected to the external terminals 1600 through internal wirings 1800.

[0100] Each of the first to third semiconductor devices 11, 12, and 13 may be the same as or similar to Figure 1 the semiconductor device. At least one of the first to third semiconductor devices 11, 12, and 13 may be the same as the semiconductor device referred to Figures 2A to 2C described, Figure 4D and Figure 4E the semiconductor device of Figure 5A and Figure 5Bis the same as or similar to the semiconductor device. The first semiconductor device 11 may include a first semiconductor substrate 1100, a first wiring layer 1200, a first etch stop layer 1300, a first separation layer 1400, and a first via structure 1500. The second semiconductor device 12 may include a second semiconductor substrate 2100, a second wiring layer 2200, a second etch stop layer 2300, a second separation layer 2400, and a second via structure 2500. The third semiconductor device 13 may include a third semiconductor substrate 3100, a third wiring layer 3200, a third etch stop layer 3300, a third separation layer 3400, and a third via structure 3500.

[0101] The first semiconductor substrate 1100, the second semiconductor substrate 2100, the third semiconductor substrate 3100, and the fourth semiconductor substrate 4100 may be substantially the same as or similar to Figure 1 an example of, Figures 2A to 2C an example of, Figure 4D and Figure 4E an example of or Figure 5A and Figure 5B the semiconductor substrate 100 described in an example of. The first wiring layer 1200, the second wiring layer 2200, the third wiring layer 3200, and the fourth wiring layer 4200 may be substantially the same as or similar to Figure 1 an example of, Figures 2A to 2C an example of, Figure 4D and Figure 4E an example of or Figure 5A and Figure 5B the wiring layer 200 described in an example of. The first etch stop layer 1300, the second etch stop layer 2300, and the third etch stop layer 3300 may be substantially the same as or similar to the etch stop layer 300 described by referring to Figure 1 an example of, Figures 2A to 2C an example of, Figure 4D and Figure 4E an example of or Figure 5A and Figure 5B an example of. The first separation layer 1400, the second separation layer 2400, and the third separation layer 3400 may be substantially the same as or similar to the above separation layer 400. The first via structure 1500, the second via structure 2500, and the third via structure 3500 may be substantially the same as or similar to Figure 1 an example of, Figures 2A to 2C an example of, Figure 4D and Figure 4E an example of or Figure 5A and Figure 5B the via structure 500 described in an example of.

[0102] The first semiconductor device 11 can be mounted on a package substrate 1000. For example, the first connection terminal 1610 can be connected to a metal pad 1700, and the first semiconductor device 11 can be electrically connected to an external terminal 1600 through the first connection terminal 1610. The first connection terminal 1610 can be substantially the same as or similar to the connection terminal 610 described in reference to Figure 1 and Figure 2A .

[0103] The second semiconductor device 12 can be mounted on the first semiconductor device 11. The second connection terminal 2610 can be provided between the first semiconductor device 11 and the second semiconductor device 12. The second semiconductor device 12 can be electrically connected to the first semiconductor device 11 and the package substrate 1000 through the second connection terminal 2610. The second connection terminal 2610 can be substantially the same as or similar to the connection terminal 610 described in reference to Figure 1 and Figure 2A .

[0104] The third semiconductor device 13 can be mounted on the second semiconductor device 12. The third connection terminal 3610 can be interposed between the second semiconductor device 12 and the third semiconductor device 13. The third semiconductor device 13 can be electrically connected to the first semiconductor device 11, the second semiconductor device 12 or the package substrate 1000 through the third connection terminal 3610. The third connection terminal 3610 can be substantially the same as or similar to the connection terminal 610 described in reference to Figure 1 and Figure 2A .

[0105] The fourth semiconductor device 14 is a top semiconductor device. The fourth semiconductor device 14 can include a fourth semiconductor substrate 4100 and a fourth wiring layer 4200, and can not include a via structure. The fourth connection terminal 4610 can be interposed between the fourth semiconductor device 14 and the third semiconductor device 13. The fourth semiconductor device 14 can be electrically connected to the first semiconductor device 11, the second semiconductor device 12 and the third semiconductor device 13 through the fourth connection terminal 4610, or can be electrically connected to the package substrate 1000. The fourth connection terminal 4610 can be substantially the same as or similar to the connection terminal 610 described in reference to Figure 1 and Figure 2A .

[0106] The number of semiconductor devices 11, 12, 13 and 14 is not limited, and can be more than four or less than four.

[0107] A molding film 5000 (molding layer) can be provided on the package substrate 1000 to cover the first to fourth semiconductor devices 11, 12, 13 and 14. The molding film 5000 can include an insulating polymer such as an epoxy molding compound.

[0108] According to an exemplary embodiment of the inventive concept, an etch stop layer may be formed between a semiconductor substrate and a wiring pattern. A via hole may be formed to expose the wiring pattern by a first etching process, a second etching process, and a third etching process. Since the formation of the via hole may be performed by the first etching process to the third etching process, the etching of the via hole may be better controlled than in a conventional process. Accordingly, unwanted etching of the wiring pattern and / or the separation layer may be prevented and / or suppressed.

[0109] Although the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor device, comprising: a crystalline substrate having a first surface and a second surface facing away from each other in a vertical direction; an insulating layer disposed on the first surface of the crystalline substrate; an etch stop layer interposed between the crystalline substrate and the insulating layer and contacting the crystalline substrate and the insulating layer; Conductive via structure, penetrating the crystal substrate and the insulating layer; as well as an insulating separation layer, arranged horizontally adjacent to the conductive through-hole structure, and having an inner wall and an outer wall facing away from the inner wall, wherein the inner wall contacts the conductive through-hole structure; The insulating separation layer includes a first portion disposed between the conductive via structure and the crystalline substrate and a second portion disposed between the conductive via structure and the etching stop layer, and The outer wall of the second portion protrudes horizontally from the outer wall of the first portion relative to the conductive through-hole structure.

2. The semiconductor device according to claim 1, wherein A first gap between an outer wall of the first portion and the conductive via structure is smaller than a second gap between an outer wall of the second portion and the conductive via structure.

3. The semiconductor device according to claim 1 , further comprising a wiring pattern provided on a bottom surface of the insulating layer, in, The conductive via structure is connected to the wiring pattern.

4. The semiconductor device according to claim 3, wherein The wiring pattern includes a metal pattern and a barrier metal film interposed between the metal pattern and the insulating layer. The semiconductor device according to claim 1 , wherein An insulating separation layer surrounds the conductive via structure. 6 . The semiconductor device according to claim 1 , further comprising a transistor provided in the crystalline substrate and / or on the first surface of the crystalline substrate.

7. The semiconductor device according to claim 1, wherein The height of the conductive via structures is 10µm to 100µm.

8. The semiconductor device according to claim 1, wherein A lower surface of the insulating separation layer is disposed at the same level as an upper surface of the insulating layer.

9. The semiconductor device according to claim 1, wherein The etch stop layer includes a material different from that of the insulating layer.

10. A semiconductor device, comprising: crystalline semiconductor substrate; an etch stop layer disposed on the first surface of the crystalline semiconductor substrate; Conductive via structures penetrating the crystalline semiconductor substrate and the etch stop layer; as well as an insulating separation layer, disposed between the conductive via structure and the crystalline semiconductor substrate, The lower portion of the insulating separation layer contacts a portion of the etch stop layer and protrudes toward a side surface of the etch stop layer. 11 . The semiconductor device according to claim 10 , further comprising a wiring pattern provided below the etch stop layer.

12. The semiconductor device according to claim 11 , further comprising an insulating layer provided between the etch stop layer and the wiring pattern and having an etching selectivity with respect to the etch stop layer, in, The conductive via structure passes through the insulating layer.

13. The semiconductor device according to claim 12, wherein The insulating separation layer includes a first portion disposed between the conductive via structure and the crystalline semiconductor substrate and a second portion disposed between the conductive via structure and the etch stop layer. The second portion is connected to the first portion and corresponds to the lower portion of the insulating separation layer.

14. The semiconductor device according to claim 12, wherein From the cross-sectional view, the insulating separation layer includes a first insulating isolation pattern provided on the first sidewall of the conductive via structure and a second insulating isolation pattern provided on the second sidewall of the conductive via structure. The second side wall is opposite to the first side wall. The first insulating isolation pattern and the second insulating isolation pattern each include: a first portion disposed between the conductive via structure and the crystalline semiconductor substrate; and a second portion disposed between the conductive via structure and the etching stop layer and connected to the first portion, and The second portion of the first insulating isolation pattern and the second portion of the second insulating isolation pattern protrude toward corresponding side surfaces of the etch stop layer.

15. The semiconductor device according to claim 10, wherein The conductive via structure has a height of 10µm to 100µm.

16. The semiconductor device according to claim 12, wherein The maximum width of the conductive via structure in the insulating layer is smaller than the minimum width of the conductive via structure in the crystalline semiconductor substrate.

17. The semiconductor device according to claim 10, further comprising: a wiring layer comprising a plurality of insulating layers and a wiring structure on a bottom surface of the etch stop layer; A connecting terminal is provided below the wiring layer; as well as A conductive pad is provided on the upper surface of the conductive through-hole structure, Wherein, the conductive through-hole structure is electrically connected to the connection terminal.

18. A semiconductor device, comprising: substrate; A first semiconductor device is disposed on a substrate; as well as a second semiconductor device disposed on the first semiconductor device, The first semiconductor device includes: a first crystalline semiconductor substrate; a first etch stop layer, which is arranged on the first surface of the first crystalline semiconductor substrate; a first conductive via structure, which penetrates the first crystalline semiconductor substrate and the first etch stop layer and has a height of 10µm to 100µm; and a first insulating separation layer, which is arranged between the first conductive via structure and the first crystalline semiconductor substrate, wherein the lower portion of the first insulating separation layer contacts a portion of the first etch stop layer and protrudes toward the corresponding side surface of the first etch stop layer.

19. The semiconductor device according to claim 18, wherein The second semiconductor device includes: a second crystalline semiconductor substrate; a second etch stop layer disposed on the second crystalline semiconductor substrate; a second conductive via structure penetrating the second crystalline semiconductor substrate and the second etch stop layer and having a height of 10 μm to 100 μm; and A second insulating separation layer is provided between the second conductive via structure and the second crystalline semiconductor substrate, and The second insulating separation layer contacts a portion of the second etch stop layer.

20. The semiconductor device according to claim 18, wherein The first insulating separation layer comprises: a first portion disposed between the first conductive via structure and the first crystalline semiconductor substrate; and The second portion is disposed between the first conductive via structure and the first etch stop layer, is electrically connected to the first portion, and corresponds to the lower portion of the first insulating separation layer.

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