A semiconductor device including a support pattern on a lower electrode structure

Abstract

A semiconductor device is provided. The semiconductor device includes a first part of a lower electrode structure, and the first part of the lower electrode structure is located on a substrate. The semiconductor device includes a first support pattern that contacts a first part of a sidewall of the first part of the lower electrode structure. The semiconductor device includes a second part of the lower electrode structure, and the second part of the lower electrode structure is located on a second part of the sidewall of the first part of the lower electrode structure. The semiconductor device includes an upper electrode, and the upper electrode is located on the second part of the lower electrode structure and on the first support pattern. In addition, the semiconductor device includes a dielectric layer, and the dielectric layer is located between the upper electrode and the second part of the lower electrode structure.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2019-0106808, filed with the Korean Intellectual Property Office on August 29, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having improved electrical characteristics and reliability and a method of manufacturing the same. Background Art

[0003] In the electronics industry (e.g., cellular phones and laptop computers / tablet computers), there has been an increasing demand for lightweight, small-sized, high-speed, multi-functional, high-performance, high-reliability, and low-cost electronic components. To meet these demands, the integration density of semiconductor memory devices can be increased, and the performance of semiconductor memory devices can be improved.

[0004] The capacitance of a capacitor can be increased to improve the reliability of a highly integrated semiconductor memory device including the capacitor. The capacitance of the capacitor can increase as the dielectric constant of the dielectric layer of the capacitor increases. Accordingly, various studies have been conducted on process technologies for forming a capacitor having a high dielectric constant. Summary of the Invention

[0005] Embodiments of the inventive concept may provide a semiconductor device having improved electrical characteristics and reliability.

[0006] Embodiments of the inventive concept may also provide a method of manufacturing a semiconductor device having improved electrical characteristics and reliability.

[0007] In some embodiments, a semiconductor device may include a first portion of a lower electrode structure positioned on a substrate. The semiconductor device may include a first support pattern in contact with a first portion of a sidewall of the first portion of the lower electrode structure. The semiconductor device may include a second portion of the lower electrode structure positioned on a second portion of the sidewall of the first portion of the lower electrode structure. The semiconductor device may include an upper electrode positioned on the second portion of the lower electrode structure and on the first support pattern. Further, the semiconductor device may include a dielectric layer positioned between the upper electrode and the second portion of the lower electrode structure.

[0008] In some embodiments, a semiconductor device may include a lower electrode structure including a first portion on a substrate and a second portion on a surface of the first portion. The semiconductor device may include a support pattern on a sidewall of the first portion of the lower electrode structure. The semiconductor device may include an upper electrode on the lower electrode structure and on the support pattern. In addition, the semiconductor device may include a dielectric layer between the lower electrode structure and the upper electrode and between the support pattern and the upper electrode. The second portion of the lower electrode structure may include niobium and fluorine, and the second portion of the lower electrode structure may further include at least one of oxygen and nitrogen.

[0009] In some embodiments, a semiconductor device may include a lower electrode structure including a first conductive portion on a substrate and a second conductive portion on a surface of the first conductive portion. The semiconductor device may include a support pattern contacting a sidewall of the lower electrode structure. The second conductive portion of the lower electrode structure may not be present on a surface of the support pattern or may be discontinuous on the surface of the support pattern. The semiconductor device may include an upper electrode on the lower electrode structure and on the support pattern. In addition, the semiconductor device may include a dielectric layer between the lower electrode structure and the upper electrode and between the support pattern and the upper electrode. The second conductive portion of the lower electrode structure may include niobium. The second conductive portion of the lower electrode structure and the dielectric layer may both include a material having a tetragonal structure.

[0010] In some embodiments, a method of manufacturing a semiconductor device may include the steps of: forming an electrode hole by etching a module structure including a module layer and a support layer stacked on a substrate; forming a lower electrode pillar filling the electrode hole; etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through hole exposing a portion of a top surface of the module layer; removing the module layer through the through hole to expose sidewalls of the lower electrode pillars; and selectively forming a lower electrode pattern on the sidewalls and a top surface of the lower electrode pillars.

[0011] In some embodiments, a semiconductor device may include: an etch stop layer on a substrate; a lower electrode pillar penetrating the etch stop layer on the substrate; a first support pattern surrounding a sidewall of a lower portion of the lower electrode pillar, the first support pattern having a first through hole disposed between the lower electrode pillars; a second support pattern surrounding a sidewall of an upper portion of the lower electrode pillar, the second support pattern having a second through hole disposed between the lower electrode pillars and vertically stacked with the first through hole; a lower electrode pattern disposed on the sidewall of the lower electrode pillar exposed by the first support pattern and the second support pattern; an upper electrode covering the lower electrode pillar, the first support pattern, the second support pattern, and the lower electrode pattern on the substrate; and a dielectric layer disposed between the upper electrode and the lower electrode pattern. The lower electrode pattern may include at least one of an oxide containing niobium and fluorine and a nitride containing niobium and fluorine. The lower electrode pattern may have a thickness of 1 angstrom to of thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The inventive concept will become more apparent in view of the drawings and the following detailed description.

[0013] Figure 1 is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0014] Figure 2 is a cross-sectional view taken along line I-I' of Figure 1 for showing a semiconductor device according to some embodiments of the inventive concept.

[0015] Figure 3 is a cross-sectional view taken along line I-I' of Figure 1 for showing a semiconductor device according to some embodiments of the inventive concept.

[0016] Figure 4 is a cross-sectional view taken along line I-I' of Figure 1 for showing a semiconductor device according to some embodiments of the inventive concept.

[0017] Figure 5 is Figure 4 an enlarged cross-sectional view of part “A” of

[0018] Figure 6 is a cross-sectional view taken along line I-I' of Figure 1 for showing a semiconductor device according to some embodiments of the inventive concept.

[0019] Figure 7 is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0020] Figure 8 is a cross-sectional view taken along line I-I' of Figure 7A cross-sectional view of a semiconductor device taken along line II-II' for showing some embodiments according to the inventive concept.

[0021] Figure 9 A plan view of a semiconductor device showing some embodiments according to the inventive concept.

[0022] Figures 10A to 10H Is along Figure 1 A cross-sectional view of a method for manufacturing a semiconductor device taken along line I-I' for showing some embodiments according to the inventive concept. Detailed Description

[0023] Figure 1 A plan view of a semiconductor device showing some embodiments according to the inventive concept. Figure 2 Is along Figure 1 A cross-sectional view of a semiconductor device taken along line I-I' for showing some embodiments according to the inventive concept.

[0024] Referring to Figure 1 And Figure 2 The semiconductor device may include a contact plug 110, a lower electrode structure LE, a first support pattern SL1, a second support pattern SL2, a dielectric layer 130, and an upper electrode UE.

[0025] The contact plug 110 may be disposed on a substrate 100. The substrate 100 may be a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium (SiGe) substrate. For example, when observed in a plan view, the contact plugs 110 may be arranged in a meandering form in a first direction X. The contact plug 110 may include at least one of a doped semiconductor material (e.g., doped polysilicon), a metal semiconductor compound (e.g., tungsten silicide), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), and a metal (e.g., titanium, tungsten, or tantalum).

[0026] An interlayer insulating layer 112 may be disposed on the substrate 100. The interlayer insulating layer 112 may fill the space between the contact plugs 110. For example, the interlayer insulating layer 112 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In some embodiments, word lines and bit lines intersecting the word lines may be formed on and / or in the substrate 100. The interlayer insulating layer 112 may be formed to cover the word lines and the bit lines. Dopant regions may be formed in the substrate 100 on both sides of each of the word lines, and each of the contact plugs 110 may be connected to one of the dopant regions.

[0027] The etch stop layer ES may be provided on the interlayer insulating layer 112. The etch stop layer ES may cover the top surface of the interlayer insulating layer 112 and may expose the top surface of the contact plug 110. The etch stop layer ES may include, for example, a silicon oxide (SiO2) layer.

[0028] The lower electrode post 122 may be provided on the contact plug 110. For example, each of the lower electrode posts 122 may have a solid post shape extending in a direction (e.g., the third direction Z) perpendicular to the top surface of the substrate 100. The lower electrode posts 122 may be arranged in a meandering form along the first direction X on the contact plug 110. The lower electrode posts 122 may include at least one of a metal material (e.g., cobalt, titanium, nickel, tungsten, or molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), or tungsten nitride (WN)), a noble metal (e.g., platinum (Pt), ruthenium (Ru), or iridium (Ir)), a conductive oxide (e.g., PtO, RuO2, IrO2, (strontium (Sr))RuO3 (SRO), (barium (Ba)Sr)RuO3 (BSRO), (calcium (Ca))RuO3 (CRO), or lanthanum strontium cobalt oxide (LSCO)), and a metal silicide.

[0029] The first support pattern SL1 may be provided on the sidewalls of the lower electrode posts 122. The first support pattern SL1 may surround a part of the sidewalls of the lower electrode structure LE. The first support pattern SL1 may be in direct contact with the sidewalls of the lower electrode posts 122. The first support pattern SL1 may have a first through hole H1. For example, each of the first through holes H1 may be formed to penetrate the first support pattern SL1. When observed in a plan view, each of the first through holes H1 may be located in an area between the lower electrode posts 122 adjacent to each other in the first direction X and in an area between the lower electrode posts 122 adjacent to each other in the second direction Y intersecting the first direction X. In other words, each of the first through holes H1 may be provided between four adjacent lower electrode posts 122. The first support pattern SL1 may be provided on the middle part of the sidewalls of the lower electrode posts 122. For example, the first support pattern SL1 may include silicon oxide.

[0030] The second support pattern SL2 may be disposed on the first support pattern SL1 and may be disposed on the sidewall of the lower electrode structure LE. The first support pattern SL1 may be disposed between the etch stop layer ES and the second support pattern SL2. The second support pattern SL2 may surround a portion of the sidewall of the lower electrode post 122. The second support pattern SL2 may be spaced apart from the first support pattern SL1 in the third direction Z. The top surface of the second support pattern SL2 may be coplanar with the top surface of the lower electrode post 122. The second support pattern SL2 may have a second through hole H2. When observed in a plan view, each of the second through holes H2 may be positioned in a region between the lower electrode posts 122 adjacent to each other in the first direction X and in a region between the lower electrode posts 122 adjacent to each other in the second direction Y. In other words, each of the second through holes H2 may be disposed between four adjacent lower electrode posts 122. A portion of the sidewall of the lower electrode post 122 may be exposed by the second through hole H2. The second through hole H2 may be stacked with the first through hole H1 in the third direction Z. Each of the second through holes H2 may extend between adjacent lower electrode posts 122 to connect to a corresponding one of the first through holes H1. Each of the first through holes H1 may extend to the etch stop layer ES between adjacent lower electrode posts 122. For example, the second support pattern SL2 may include silicon oxide. For example, the width of the second through hole H2 may be larger than the width of the first through hole H1. The lower electrode pattern 124 may be disposed on the sidewall and the top surface of the lower electrode post 122 exposed by the first support pattern SL1 and the second support pattern SL2. The lower electrode pattern 124 may be in direct contact with the sidewall and the top surface of the lower electrode post 122 exposed by the first support pattern SL1 and the second support pattern SL2. The lower electrode pattern 124 may be partially disposed on the sidewall and the top surface of the lower electrode post 122 exposed by the first support pattern SL1 and the second support pattern SL2, but may not be disposed on the surfaces of the first support pattern SL1 and the second support pattern SL2 exposed by the lower electrode post 122. The lower electrode pattern 124 may not be disposed on the top surface of the etch stop layer ES. Accordingly, the top and bottom surfaces of the first support pattern SL1 and the second support pattern SL2 and the top surface of the etch stop layer ES may be exposed by the lower electrode pattern 124. Each of the lower electrode patterns 124 may have a thickness of about to about . More specifically, each of the lower electrode patterns 124 may have a thickness of about to about The thickness. The lower electrode pattern 124 can be used as a seed layer in the crystallization of the dielectric layer 130. For example, the lower electrode pattern 124 can include a metal material having a tetragonal structure. The lower electrode pattern 124 can include a metal material having a high work function. The lower electrode pattern 124 can include niobium and fluorine, and can include at least one of oxygen and nitrogen. The lower electrode pattern 124 can include at least one of an oxide containing niobium and fluorine and a nitride containing niobium and fluorine. The lower electrode pattern 124 can include a nitride containing niobium, an oxide containing niobium, or a niobium oxynitride. For example, the lower electrode pattern 124 can include niobium nitride (NbN) containing fluorine, niobium oxide (NbO) containing fluorine, or niobium oxynitride (NbON) containing fluorine. In some embodiments, each of the lower electrode posts 122 and the lower electrode pattern 124 provided on the sidewalls of each of the lower electrode posts 122 can constitute each lower electrode structure in the lower electrode structure LE.

[0031] In addition, the lower electrode posts 122 are not limited to a columnar shape. Instead, each of the lower electrode posts 122 can be any shape that continuously extends through the first support pattern SL1 and contacts the sidewalls of the first support pattern SL1. Therefore, the lower electrode posts 122 and the lower electrode pattern 124 can be generally referred to as the "first part" and the "second part" of the lower electrode structure LE, respectively, herein. In addition, both the lower electrode posts 122 and the lower electrode pattern 124 can include a conductive material (e.g., a metal or a conductive oxide).

[0032] In some embodiments, each of the lower electrode posts 122 may include a first portion P1, a second portion P2, a third portion P3, and a fourth portion P4. The first portion P1 may be horizontally stacked with the second support pattern SL2. The second portion P2 may be horizontally stacked with the first support pattern SL1. The third portion P3 may be disposed between the first portion P1 and the second portion P2 and may not be horizontally stacked with the first support pattern SL1 or the second support pattern SL2. The fourth portion P4 may be disposed between the second portion P2 and each of the contact plugs 110 and may not be horizontally stacked with the first support pattern SL1. The lower electrode pattern 124 may include a first lower electrode pattern 124a and a second lower electrode pattern 124b. The first lower electrode pattern 124a may be located on the sidewalls and the top surface of the first portion P1 and the sidewalls of the third portion P3 (e.g., covering the sidewalls and the top surface of the first portion P1 and the sidewalls of the third portion P3). The second lower electrode pattern 124b may be located on the sidewalls of the fourth portion P4 (e.g., covering the sidewalls of the fourth portion P4). The first lower electrode pattern 124a and the second lower electrode pattern 124b disposed on the same lower electrode post 122 may be physically spaced apart from each other by the first support pattern SL1. In other words, the first lower electrode pattern 124a and the second lower electrode pattern 124b disposed on the same lower electrode post 122 may not be connected to each other. The first lower electrode patterns 124a disposed on the lower electrode posts 122 adjacent to each other along the first direction X and the second direction Y may be physically spaced apart from each other by the second support pattern SL2. The second lower electrode patterns 124b disposed on the lower electrode posts 122 adjacent to each other along the first direction X and the second direction Y may be physically spaced apart from each other by the first support pattern SL1.

[0033] In some embodiments, the first lower electrode pattern 124a and the second lower electrode pattern 124b disposed on the same lower electrode post 122 may be connected to each other. The first lower electrode patterns 124a disposed on the lower electrode posts 122 adjacent to each other along the first direction X and the second direction Y may be physically spaced apart from each other by the second support pattern SL2. The second lower electrode patterns 124b disposed on the lower electrode posts 122 adjacent to each other along the first direction X and the second direction Y may be physically spaced apart from each other by the second support pattern SL2.

[0034] In some embodiments, a first width W1 corresponding to the sum of the width of the third portion P3 of each lower electrode post 122 and twice the thickness of the lower electrode pattern 124 located on the sidewall of the third portion P3 (e.g., covering the sidewall of the third portion P3) may be substantially equal to a second width W2 corresponding to the sum of the width of the fourth portion P4 of each lower electrode post 122 and twice the thickness of the lower electrode pattern 124 located on the sidewall of the fourth portion P4 (e.g., covering the sidewall of the fourth portion P4). A third width W3 of the first portion P1 of each lower electrode post 122 may be substantially equal to a fourth width W4 of the second portion P2 of each lower electrode post 122. The first width W1 and the second width W2 may be larger than the third width W3 and the fourth width W4. For example, each of the first width W1 and the second width W2 may be larger than each of the third width W3 and the fourth width W4 by twice the thickness of the lower electrode pattern 124.

[0035] The upper electrode UE may be disposed on the lower electrode structure LE, the etch stop layer ES, and the first support pattern SL1 and the second support pattern SL2. The upper electrode UE may fill the first space S1, the second space S2, the first through hole H1, and the second through hole H2, where each of the first spaces S1 is defined by the first support pattern SL1 and the second support pattern SL2 between adjacent lower electrode structures LE, and each of the second spaces S2 is defined by the first support pattern SL1 and the etch stop layer ES between adjacent lower electrode structures LE. The upper electrode UE may be formed of at least one of a semiconductor material doped with a dopant, a metal material, a metal nitride, and a metal silicide. In some embodiments, the upper electrode UE may be formed of a refractory metal material such as cobalt, titanium, nickel, tungsten, and / or molybdenum. In some embodiments, the upper electrode UE may be formed of a metal nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), and / or tungsten nitride (WN). In some embodiments, the upper electrode UE may be formed of at least one of platinum (Pt), ruthenium (Ru), and iridium (Ir).

[0036] The dielectric layer 130 may be disposed between the upper electrode UE and the lower electrode structure LE, between the upper electrode UE and the first support pattern SL1, between the upper electrode UE and the second support pattern SL2, and between the upper electrode UE and the etch stop layer ES. The dielectric layer 130 may be disposed on the lower electrode pattern 124, on the top and bottom surfaces of the first support pattern SL1 and the second support pattern SL2, on the sidewalls of the first through hole H1 of the first support pattern SL1, and on the top surface of the etch stop layer ES, and the lower electrode pattern 124 is disposed on the sidewalls and the top surface of the lower electrode pillar 122. The dielectric layer 130 may be physically spaced apart from the lower electrode pillar 122 and may be in direct contact with the lower electrode pattern 124. The dielectric layer 130 may be in direct contact with the top and bottom surfaces of the first support pattern SL1 and the second support pattern SL2 and the sidewalls of the first through hole H1. In some embodiments, portions of the dielectric layer 130 disposed between the upper electrode UE and the top and bottom surfaces of the first support pattern SL1 and the second support pattern SL2 and portions disposed between the upper electrode UE and the sidewalls of the first through hole H1 may have a substantially flat surface. In other words, between the dielectric layer 130 and the top and bottom surfaces of the first support pattern SL1 and the second support pattern SL2 and between the dielectric layer 130 and the sidewalls of the first through hole H1, the first support pattern SL1 and the second support pattern SL2 may not include any layers and / or any patterns. The dielectric layer 130 may include a material having a tetragonal structure. For example, the dielectric layer 130 may be formed of at least one of a metal oxide (e.g., hafnium oxide (HfO2), zirconium oxide (ZrO2), Al2O3, lanthanum oxide (La2O3), Ta2O3, or TiO2)) and a perovskite dielectric material (e.g., SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, or PLZT). The dielectric layer 130 may have a single-layer structure or a multi-layer structure.

[0037] Figure 3 is taken along Figure 1 line I-I' of FIG. for showing a cross-sectional view of a semiconductor device according to some embodiments of the inventive concept.

[0038] Referring to Figure 3, the metal oxide pattern 140 may be locally disposed between the dielectric layer 130 and the lower electrode pattern 124. In other words, the metal oxide pattern 140 may not be disposed between the top and bottom surfaces of the dielectric layer 130 and the first support pattern SL1 and the second support pattern SL2, between the sidewall of the dielectric layer 130 and the first through hole H1, and between the dielectric layer 130 and the etch stop layer ES. The metal oxide pattern 140 may be in direct contact with the dielectric layer 130. The dielectric layer 130 may be physically spaced apart from the lower electrode post 122 and the lower electrode pattern 124 by the metal oxide pattern 140. The metal oxide pattern 140 may include, for example, niobium oxide (NbO). The metal oxide pattern 140 may include fluorine.

[0039] Figure 4 is taken along Figure 1 the line I-I' of a cross-sectional view of a semiconductor device showing some embodiments according to the inventive concept. Figure 5 is Figure 4 an enlarged cross-sectional view of part “A” of

[0040] Referring to Figure 4 and Figure 5 , the metal residue pattern RP may be disposed on the sidewalls, top surfaces, and bottom surfaces of the first support pattern SL1 and the second support pattern SL2 and on the top surface of the etch stop layer ES. The metal residue pattern RP may be disposed between the top and bottom surfaces of the dielectric layer 130 and the first support pattern SL1, between the top and bottom surfaces of the dielectric layer 130 and the second support pattern SL2, between the sidewall of the dielectric layer 130 and the first through hole H1 of the first support pattern SL1, and / or between the top surface of the dielectric layer 130 and the top surface of the etch stop layer ES. The metal residue pattern RP may be in direct contact with the top and bottom surfaces of the first support pattern SL1 and the second support pattern SL2, the sidewall of the first through hole H1, and the top surface of the etch stop layer ES. The metal residue patterns RP may be spaced apart from each other. The metal residue pattern RP may be physically spaced apart from the lower electrode pattern 124. The metal residue patterns RP may not physically connect / electrically connect the adjacent lower electrode structures LE. When observed in a cross-sectional view, the metal residue pattern RP may have a hemispherical shape. The metal residue pattern RP may include the same material as that of the lower electrode pattern 124. For example, the metal residue pattern RP may include a nitride containing niobium, an oxide containing niobium, or a oxynitride containing niobium. For example, the metal residue pattern RP may include niobium nitride (NbN) containing fluorine, niobium oxide (NbO) containing fluorine, or niobium oxynitride (NbON) containing fluorine.

[0041] Figure 6 is taken along Figure 1 the line I-I' of a cross-sectional view of a semiconductor device showing some embodiments according to the inventive concept.

[0042] Referring to Figure 6 , the top surface of the second support pattern SL2 may not be coplanar with the top surface of the lower electrode pillar 122. The height of the top surface of the second support pattern SL2 from the top surface of the substrate 100 may be lower than the height of the top surface of the lower electrode pillar 122 from the top surface of the substrate 100. The upper portion of the first portion P1 of the lower electrode pillar 122 may protrude upward beyond the top surface of the second support pattern SL2 (i.e., above the level of the top surface of the second support pattern SL2). The sidewall of the upper portion of the first portion P1 of the lower electrode pillar 122 may be exposed by the second support pattern SL2, and the sidewall is vertically aligned with the sidewall of the first portion P1 that contacts the second support pattern SL2. Thus, each lower electrode pillar 122 may have a constant width. The lower electrode pattern 124 located on the top surface of the lower electrode pillar 122 (e.g., covering the top surface of the lower electrode pillar 122) may extend onto the sidewall of the upper portion of the first portion P1 of the lower electrode pillar 122 that is exposed by the second support pattern SL2. The top surface and the bottom surface of the second support pattern SL2 may be exposed by the lower electrode pattern 124.

[0043] Figure 7 is a plan view of a semiconductor device showing some embodiments according to the inventive concept. Figure 8 is a cross-sectional view taken along the line II-II' of Figure 7 for showing a semiconductor device according to some embodiments of the inventive concept.

[0044] Referring to Figure 7 and Figure 8, each of the lower electrode posts 122 may include a horizontal portion PP, a first vertical portion V1, and a second vertical portion V2. The horizontal portion PP may be parallel to the top surface of the substrate 100. The horizontal portion PP may be in contact with the top surface of each of the contact plugs 110. The first vertical portion V1 may extend in the third direction Z from a first end of the horizontal portion PP. The first vertical portion V1 may be connected to the first end of the horizontal portion PP. The second vertical portion V2 may extend in the third direction Z from a second end of the horizontal portion PP opposite the first end. The second vertical portion V2 may be connected to the second end. The first vertical portion V1 and the second vertical portion V2 may be spaced apart from each other in the first direction X and may be parallel to each other in the third direction Z. The lower electrode post 122 may have a cylindrical shape. The first support pattern SL1 and the second support pattern SL2 may be provided on a portion of the outer sidewall of the lower electrode post 122. The first support pattern SL1 and the second support pattern SL2 may not be provided on the inner sidewall of the lower electrode post 122. In other words, the first support pattern SL1 and the second support pattern SL2 may not be provided in the internal space surrounded by the lower electrode post 122. Accordingly, the entire inner surface (e.g., the inner sidewall and the bottom surface) of the lower electrode post 122 may be exposed by the first support pattern SL1 and the second support pattern SL2.

[0045] In some embodiments, the first lower electrode pattern 124a may extend onto the inner sidewall and the bottom surface of the lower electrode post 122. The first lower electrode pattern 124a may be in direct contact with the inner sidewall and the bottom surface of the lower electrode post 122.

[0046] Figure 9 is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0047] Referring to Figure 9 , a first through hole H1 of the first support pattern SL1 and a second through hole H2 of the second support pattern SL2 that are stacked on each other in the third direction Z may be provided between three adjacent lower electrode structures LE. The first through hole H1 and the second through hole H2 may pass through between three adjacent lower electrode structures LE.

[0048] Figures 10A to 10H is a cross-sectional view taken along line I-I' of Figure 1 for showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0049] Referring to Figure 10A , an interlayer insulating layer 112 may be formed on the substrate 100. The substrate 100 may be a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium (SiGe) substrate. For example, the interlayer insulating layer 112 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0050] A contact plug 110 may be formed in the interlayer insulating layer 112. A top surface of the contact plug 110 may be exposed by the interlayer insulating layer 112. The contact plug 110 may include at least one of a doped semiconductor material (e.g., doped polysilicon), a metal semiconductor compound (e.g., tungsten silicide), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), and a metal (e.g., titanium, tungsten, or tantalum). In some embodiments, word lines and bit lines intersecting the word lines may be formed on and / or in the substrate 100. An interlayer insulating layer 112 may be formed to cover the word lines and the bit lines. In some embodiments, dopant regions may be formed in the substrate 100 on both sides (i.e., opposite sides) of each of the word lines, and each of the contact plugs 110 may be connected to one of the dopant regions.

[0051] An etch stop layer ES may be formed on the contact plug 110 and the interlayer insulating layer 112. The etch stop layer ES may cover the top surface of the contact plug 110 and the top surface of the interlayer insulating layer 112. The etch stop layer ES may include, for example, a silicon oxide layer.

[0052] A module structure MS may be formed on the etch stop layer ES. The module structure MS may include a first module layer 150, a first support layer 152, a second module layer 154, and a second support layer 156 that are sequentially formed on the etch stop layer ES. The first module layer 150 may include, for example, a silicon nitride layer. The first support layer 152 may include a material having an etch selectivity with respect to the first module layer 150. The first support layer 152 may include, for example, a silicon oxide layer. The second module layer 154 may include a material having an etch selectivity with respect to the first support layer 152. The second module layer 154 may include the same material as the first module layer 150. For example, the second module layer 154 may include a silicon nitride layer. The second support layer 156 may include a material having an etch selectivity with respect to the second module layer 154. The second support layer 156 may include the same material as the first support layer 152. The second support layer 156 may include, for example, a silicon oxide layer.

[0053] A first mask layer 160 and a second mask layer 162 may be sequentially formed on the module structure MS. The first mask layer 160 may cover the second support layer 156. For example, the first mask layer 160 may include at least one of a polysilicon layer, a silicon nitride layer, and a silicon oxynitride layer. The second mask layer 162 may be formed on the first mask layer 160. The second mask layer 162 may have an opening. A portion of the top surface of the first mask layer 160 may be exposed through the opening. For example, the second mask layer 162 may be formed of a spin-on hard mask (SOH) layer or an amorphous carbon layer (ACL).

[0054] Refer to Figure 10B, the second mask layer 162 can be used as an etch mask to anisotropically etch the first mask layer 160, the module structure MS, and the etch stop layer ES. Thus, electrode holes EH can be formed in the module structure MS and the etch stop layer ES. For example, the electrode holes EH can be formed by anisotropically etching the first mask layer 160, the second support layer 156, the second module layer 154, the first support layer 152, the first module layer 150, and the etch stop layer ES in the order presented below. The top surface of the contact plug 110 can be exposed by the electrode holes EH. Portions of the first module layer 150 and the second module layer 154, the first support layer 152 and the second support layer 156, and the etch stop layer ES can be exposed by the sidewalls of the electrode holes EH. For example, the anisotropic etching process can be a dry etching process. The dry etching process can use an etch gas. The etch gas can include an etch gas for etching the first module layer 150 and the second module layer 154 and an etch gas for etching the first support layer 152 and the second support layer 156. In some embodiments, the first mask layer 160 and the second mask layer 162 can be removed during the anisotropic etching process. In some embodiments, the first mask layer 160 and the second mask layer 162 can be removed by an additional etching process after the anisotropic etching process.

[0055] Lower electrode posts 122 can be formed to fill the electrode holes EH, respectively. The formation of the lower electrode posts 122 can include the following steps: forming a lower electrode layer that fills the electrode holes EH and covers the module structure MS; and performing a planarization process on the lower electrode layer until the top surface of the second support layer 156 is exposed. Since the electrode holes EH have a high aspect ratio, the deposition process for forming the lower electrode posts 122 can use a layer formation technique with excellent step coverage properties. For example, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process can be used to form the lower electrode posts 122. A chemical mechanical polishing (CMP) process can be used to perform the planarization process. When the lower electrode layer completely fills the electrode holes EH, the lower electrode posts 122 can have a solid cylindrical shape, as Figure 9 and Figure 10B shown. When the lower electrode layer is formed to conformally cover the sidewalls and the bottom surface of the electrode holes EH, the lower electrode posts 122 can have a cylindrical shape, as Figure 8As shown in. The lower electrode post 122 may be in direct contact with the sidewall of the electrode hole EH. The lower electrode post 122 may include at least one of a metal material (e.g., cobalt, titanium, nickel, tungsten, or molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), or tungsten nitride (WN)), a noble metal (e.g., platinum (Pt), ruthenium (Ru), or iridium (Ir)), a conductive oxide (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), or LSCO), and a metal silicide.

[0056] Referring to Figure 10C , a third mask layer 164 may be formed on the module structure MS in which the lower electrode post 122 is formed. The third mask layer 164 may be formed of a material having an etching selectivity with respect to the second support layer 156. The third mask layer 164 may include, for example, a polysilicon layer. A photoresist layer 166 may be formed on the third mask layer 164. The photoresist layer 166 may have openings 168. Each of the openings 168 may be positioned on a part of the second support layer 156, the part being provided between a pair of lower electrode posts 122 adjacent to each other along the first direction X and between a pair of lower electrode posts 122 adjacent to each other along the second direction Y (see Figure 1 ). The width of each of the openings 168 may be equal to or greater than the distance between the adjacent lower electrode posts 122.

[0057] Referring to Figure 10D , the third mask layer 164 and the second support layer 156 may be sequentially anisotropically etched using the photoresist layer 166 as an etching mask. Accordingly, the portions of the third mask layer 164 and the second support layer 156 exposed by the openings 168 may be etched, and a second support pattern SL2 having a second through hole H2 may be formed. Portions of the top surface of the second module layer 154 and portions of the sidewalls of the lower electrode posts 122 may be exposed by the second through hole H2. The photoresist layer 166 may be removed in the anisotropic etching process. Accordingly, the top surface of the third mask layer 164 may be exposed. For example, the anisotropic etching process may be a dry etching process. The dry etching process may be performed using an etching gas for etching the second support layer 156.

[0058] Referring to Figure 10E , the third mask layer 164 may be removed. Accordingly, the top surface of the second support pattern SL2 may be exposed. The third mask layer 164 may be removed by, for example, a wet etching process or a dry etching process.

[0059] The second module layer 154 exposed by the second through-hole H2 can be removed through an isotropic etching process. Accordingly, the bottom surface of the second support pattern SL2 and the top surface of the first support layer 152 can be exposed. In addition, portions of the sidewall of the lower electrode post 122 exposed by the second through-hole H2 and portions of the sidewall of the lower electrode post 122 disposed between the first support layer 152 and the second support pattern SL2 can also be exposed. The second support pattern SL2 and the first support layer 152 may have an etching selectivity with respect to the second module layer 154. Accordingly, the second support pattern SL2 and the first support layer 152 may not be removed when the second module layer 154 is removed. The first space S1 and the third space S3 can be formed by removing the second module layer 154. Each of the first spaces S1 can be defined by the second support pattern SL2 and the first support layer 152 between adjacent lower electrode posts 122. Each of the third spaces S3 can be defined by the adjacent lower electrode posts 122 between the first support layer 152 and each second through-hole H2. In other words, each of the third spaces S3 can extend from each of the second through-holes H2 to the top surface of the first support layer 152. The first space S1 can expose a portion of the sidewall of the lower electrode post 122 disposed between the second support pattern SL2 and the first support layer 152. The third space S3 can expose a portion of the sidewall of the lower electrode post 122 disposed between the first support layer 152 and the second through-hole H2. The isotropic etching process performed on the second module layer 154 can use phosphoric acid (H3PO4).

[0060] The portion of the first support layer 152 vertically stacked with the second through-hole H2 can be etched to form a first support pattern SL1 having a first through-hole H1. The first through-hole H1 of the first support pattern SL1 can be stacked with the second through-hole H2 of the second support pattern SL2 in the third direction Z. A portion of the top surface of the first module layer 150 can be exposed by the first through-hole H1.

[0061] Referring to Figure 10F, the first module layer 150 exposed by the first through hole H1 can be removed by an isotropic etching process. Phosphoric acid (H3PO4) can be used for the isotropic etching process performed on the first module layer 150. The second space S2 and the fourth space S4 can be formed by removing the first module layer 150. Each of the second spaces S2 can be defined by the top surface of the etch stop layer ES between the adjacent lower electrode posts 122 and the first support pattern SL1. Each of the fourth spaces S4 can be defined by the etch stop layer ES and the adjacent lower electrode posts 122 between each of the first through holes H1. In other words, each of the fourth spaces S4 can extend from each of the first through holes H1 between the adjacent lower electrode posts 122 toward the top surface of the interlayer insulating layer 112. The second space S2 can expose the portion of the sidewall of the lower electrode post 122 disposed between the top surface of the etch stop layer ES and the bottom surface of the first support pattern SL1. The fourth space S4 can expose the portion of the sidewall of the lower electrode post 122 disposed between the top surface of the etch stop layer ES and the first through hole H1. In some embodiments, the etch stop layer ES may not be removed in the isotropic etching process of the first module layer 150. In some embodiments, the etch stop layer ES may be removed in the isotropic etching process of the first module layer 150.

[0062] Referring to Figure 10G , the lower electrode pattern 124 can be selectively formed on the sidewalls and the top surface of the lower electrode post 122 exposed by the first support pattern SL1 and the second support pattern SL2. The deposition process for forming the lower electrode pattern 124 may include the following steps: supplying source gases (e.g., NH3, N2, O2, O3) to adsorb the source gases on the sidewalls and the top surface of the lower electrode post 122; purging the unadsorbed source gases; supplying a precursor to chemically bond the precursor with the source gases on the sidewalls and the top surface of the lower electrode post 122; and purging the unbonded precursor. The supply of the source gases, the purging of the unadsorbed source gases, the supply of the precursor, and the purging of the unbonded precursor may constitute a cycle, and the lower electrode pattern 124 can be formed by repeating this cycle multiple times. The precursor may be, for example, a niobium precursor including fluorine. For example, the precursor may be NbF5 or NbF 5-x . The lower electrode pattern 124 may include a niobium-containing nitride, a niobium-containing oxide, or a niobium-containing oxynitride. For example, the lower electrode pattern 124 may include niobium nitride (NbN) containing fluorine, niobium oxide (NbO) containing fluorine, or niobium oxynitride (NbON) containing fluorine.

[0063] In some embodiments, the formation rate of the layer deposited on the sidewall and top surface of the lower electrode post 122 by chemical combination of a precursor and a source gas may be greater than the formation rate of the layer deposited on the surfaces of the first support pattern SL1, the second support pattern SL2, and the etch stop layer ES by chemical combination of a precursor and a source gas. Accordingly, while forming the lower electrode pattern 124 on the sidewall and top surface of the lower electrode post 122, the lower electrode pattern 124 may not be formed on the sidewalls, top surfaces, and bottom surfaces of the first support pattern SL1 and the second support pattern SL2 and on the top surface of the etch stop layer ES. In some embodiments, a metal residue pattern RP (see Figure 4 ) may be formed on a portion of the surface of the etch stop layer ES and the first support pattern SL1 and the second support pattern SL2. The metal residue patterns RP may be spaced apart from each other on the top surfaces, bottom surfaces, and sidewalls of the first support pattern SL1 and the second support pattern SL2 and on the top surface of the etch stop layer ES. In other words, the metal residue patterns RP may be formed as a discontinuous layer on the top surfaces, bottom surfaces, and sidewalls of the first support pattern SL1 and the second support pattern SL2 and on the top surface of the etch stop layer ES. The metal residue pattern RP may include the same material as the lower electrode pattern 124. The metal residue pattern RP may include a nitride containing niobium. For example, the metal residue pattern RP may include niobium nitride (NbN) containing fluorine.

[0064] In some embodiments, a metal oxide pattern 140 may be formed on the lower electrode pattern 124, as shown in Figure 3 . After forming the lower electrode pattern 124, a source gas including oxygen (e.g., O2 and / or O3) may be provided to oxidize the surface of the lower electrode pattern 124, thereby forming the metal oxide pattern 140. The metal oxide pattern 140 may include, for example, niobium oxide (NbO). The metal oxide pattern 140 may include fluorine.

[0065] According to some embodiments of the inventive concept, the lower electrode pattern 124 may be selectively formed on the sidewalls and the top surface of the lower electrode post 122 by using a niobium precursor including fluorine, and a deposition rate of the niobium precursor including fluorine varies according to a surface material. Accordingly, even when the lower electrode pattern 124 is formed on the substrate 100 having the first support pattern SL1 and the second support pattern SL2 after the first module layer 150 is removed, the lower electrode pattern 124 may not be formed on the top surface, the bottom surface, and the sidewalls of the first support pattern SL1 and the second support pattern SL2 and on the top surface of the etch stop layer ES (i.e., may not exist on the top surface, the bottom surface, and the sidewalls of the first support pattern SL1 and the second support pattern SL2 and on the top surface of the etch stop layer ES), or may be formed as a discontinuous layer on the top surface, the bottom surface, and the sidewalls of the first support pattern SL1 and the second support pattern SL2 and on the top surface of the etch stop layer ES. As a result, adjacent lower electrode posts 122 may not be electrically connected to each other through the lower electrode pattern 124. In addition, when the first module layer 150 and the second module layer 154 are removed, the lower electrode pattern 124 including fluorine may not be etched, and thus reliability of the semiconductor device may be improved.

[0066] According to some embodiments of the inventive concept, the lower electrode pattern 124 may be used as a seed layer capable of growing the dielectric layer 130 in a tetragonal structure corresponding to high-k, and thus electrical characteristics of the semiconductor device may be improved.

[0067] Referring to Figure 10H , the dielectric layer 130 may be formed to conformally cover the top surface and the sidewalls of the lower electrode pattern 124, the top surfaces, the bottom surfaces, and the sidewalls of the first support pattern SL1 and the second support pattern SL2, and the top surface of the etch stop layer ES. The dielectric layer 130 in contact with the lower electrode pattern 124 may be formed to have the same crystal structure as that of the lower electrode pattern 124. For example, the dielectric layer 130 may include a material having a tetragonal structure. The dielectric layer 130 may be formed by a layer formation technique having excellent step coverage properties (e.g., a CVD technique or an ALD technique). For example, the dielectric layer 130 may be formed of at least one of metal oxides (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3, or TiO2) and perovskite dielectric materials (e.g., SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, or PLZT). The dielectric layer 130 may have a single-layer structure or a multi-layer structure.

[0068] Referring again to Figure 2, an upper electrode UE may be formed on the dielectric layer 130. The upper electrode UE may fill the first space to the fourth space S1, S2, S3, and S4 and the first through hole H1 and the second through hole H2, and may cover the top surface of the dielectric layer 130. The upper electrode UE may be formed of at least one of a semiconductor material doped with a dopant, a metal material, a metal nitride, and a metal silicide. In some embodiments, the upper electrode UE may be formed of a refractory metal material such as cobalt, titanium, nickel, tungsten, and / or molybdenum. In some embodiments, the upper electrode UE may be formed of a metal nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), and / or tungsten nitride (WN). In some embodiments, the upper electrode UE may be formed of at least one of platinum (Pt), ruthenium (Ru), and iridium (Ir).

[0069] According to some embodiments of the inventive concept, a stripping process of the module layer may be performed to expose the sidewalls of the lower electrode pillars, and then, a lower electrode pattern may be selectively formed on the exposed sidewalls and the top surface of the lower electrode pillars where the support pattern is located. The lower electrode pattern may not be formed on the surface of the support pattern, or may be formed discontinuously on the surface of the support pattern. Accordingly, even when the lower electrode pattern of the portion serving as the lower electrode is formed after the support pattern is formed, adjacent lower electrode pillars may not be electrically connected to each other through the lower electrode pattern.

[0070] According to some embodiments of the inventive concept, the lower electrode pattern may serve as a seed layer capable of growing the dielectric layer in a tetragonal structure corresponding to high-k, and thus, the electrical characteristics of the semiconductor device may be improved.

[0071] Although the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the scope of the inventive concept. Therefore, it should be understood that the above embodiments are illustrative rather than restrictive. Accordingly, the scope of the inventive concept will be determined by the broadest permissible interpretation of the claims and their equivalents, and should not be restricted or limited by the foregoing description.

Claims

1. A semiconductor device, the semiconductor device comprising: A first portion of a lower electrode structure, located on a substrate; A first support pattern, in contact with a first portion of a sidewall of the first portion of the lower electrode structure; A second portion of the lower electrode structure, located on a second portion of the sidewall of the first portion of the lower electrode structure; An upper electrode, located on the second portion of the lower electrode structure and on the first support pattern; And A dielectric layer, located between the upper electrode and the second portion of the lower electrode structure, Wherein, the first portion of the lower electrode structure and the dielectric layer are physically spaced apart by the second portion of the lower electrode structure, such that the dielectric layer does not include a portion in contact with the first portion of the lower electrode structure, Wherein, both the second portion of the lower electrode structure and the dielectric layer include a material having a tetragonal structure, Wherein, the second portion of the lower electrode structure does not exist on the top surface and the bottom surface of the first support pattern or is discontinuous on the top surface and the bottom surface of the first support pattern, and Wherein, the dielectric layer is in contact with the top surface and the bottom surface of the first support pattern.

2. The semiconductor device according to claim 1, Among them, The first portion of the lower electrode structure includes: an upper portion, protruding upward beyond the top surface of the first support pattern; and a lower portion, located at a level between the substrate and the first support pattern, Wherein, the second portion of the lower electrode structure includes: a first lower electrode pattern, located on the surface of the upper portion; and a second lower electrode pattern, located on the surface of the lower portion, Wherein, the first lower electrode pattern and the second lower electrode pattern are physically spaced apart.

3. The semiconductor device according to claim 1, Among them, The dielectric layer is in contact with the second portion of the lower electrode structure.

4. The semiconductor device according to claim 1, Among them, The dielectric layer extends between the upper electrode and the top surface of the first support pattern, between the upper electrode and the bottom surface of the first support pattern, and between the upper electrode and the sidewall of the first support pattern, and Wherein, the portions of the dielectric layer located on the top surface, sidewall, and bottom surface of the first support pattern have a flat surface.

5. The semiconductor device according to claim 1, the semiconductor device further comprising: A metal residue pattern, located on the top surface, bottom surface, and sidewall of the first support pattern, Wherein, the metal residue pattern is spaced apart from the second portion of the lower electrode structure, and Wherein, when observed in a cross-sectional view, the metal residue pattern has a hemispherical shape.

6. The semiconductor device according to claim 1, the semiconductor device further comprising: A metal residue pattern, located on the top surface, bottom surface, and sidewall of the first support pattern, Wherein, the metal residue patterns are spaced apart from each other.

7. The semiconductor device according to claim 1, Among them, The first portion of the lower electrode structure includes a first metal nitride containing titanium, and Wherein, the second portion of the lower electrode structure includes a second metal nitride containing niobium, a metal oxide containing niobium, or a metal oxynitride containing niobium.

8. The semiconductor device according to claim 1, the semiconductor device further comprising: A metal oxide pattern, located between the second portion of the lower electrode structure and the dielectric layer, Wherein, the metal oxide pattern includes niobium.

9. The semiconductor device according to claim 1, wherein, The first support pattern includes silicon oxide.

10. The semiconductor device according to claim 1, wherein, The second portion of the lower electrode structure includes fluorine.

11. The semiconductor device according to claim 1, wherein the semiconductor device further comprises: a second support pattern located on the first support pattern and in contact with a third portion of a sidewall of a first portion of the lower electrode structure, wherein the second support pattern is vertically spaced apart from the first support pattern, and wherein a top surface of the second support pattern is coplanar with a top surface of the first portion of the lower electrode structure.

12. The semiconductor device according to claim 1, wherein the semiconductor device further comprises: a second support pattern located on the first support pattern and in contact with a third portion of a sidewall of a first portion of the lower electrode structure, wherein the second support pattern is vertically spaced apart from the first support pattern, wherein an upper portion of the first portion of the lower electrode structure protrudes upward beyond a top surface of the second support pattern, and wherein the first portion of the lower electrode structure has a constant width.

13. The semiconductor device according to claim 1, Among them, wherein the first portion of the lower electrode structure comprises: a horizontal portion parallel to a top surface of the substrate; a first vertical portion vertically extending from a first end of the horizontal portion; and a second vertical portion vertically extending from a second end of the horizontal portion, wherein the first vertical portion and the second vertical portion are parallel to each other and spaced apart from each other, and wherein a second portion of the lower electrode structure is located on a top surface of the horizontal portion, inner sidewalls and top surfaces of the first vertical portion, and inner sidewalls and top surfaces of the second vertical portion.

14. A semiconductor device, the semiconductor device comprising: a lower electrode structure comprising: a first portion located on a substrate; and a second portion located on a surface of the first portion; a support pattern located on a sidewall of the first portion of the lower electrode structure; an upper electrode located on the lower electrode structure and on the support pattern; and a dielectric layer located between the lower electrode structure and the upper electrode and between the support pattern and the upper electrode, wherein the first portion of the lower electrode structure is physically spaced apart from the dielectric layer by the second portion of the lower electrode structure such that the dielectric layer does not include a portion in contact with the first portion of the lower electrode structure, wherein the second portion of the lower electrode structure comprises niobium and fluorine, wherein the second portion of the lower electrode structure further comprises at least one of oxygen and nitrogen, wherein the second portion of the lower electrode structure does not exist on a top surface and a bottom surface of the support pattern or is discontinuous on the top surface and the bottom surface of the support pattern, and wherein the dielectric layer is in contact with the top surface and the bottom surface of the support pattern and comprises a material having a tetragonal structure.

15. The semiconductor device according to claim 14, wherein, The support pattern is in contact with a portion of a sidewall of the first portion of the lower electrode structure.

16. The semiconductor device according to claim 14, wherein the semiconductor device further comprises: metal residue patterns located between the support pattern and the dielectric layer, wherein the metal residue patterns are spaced apart from each other, and wherein the metal residue patterns comprise a material the same as that of the second portion of the lower electrode structure.

17. The semiconductor device according to claim 14, wherein the semiconductor device further comprises: metal oxide patterns located between the second portion of the lower electrode structure and the dielectric layer, wherein the metal oxide patterns comprise niobium.

18. The semiconductor device according to claim 14, Among them, The second part of the lower electrode structure is in contact with the dielectric layer.

19. The semiconductor device according to claim 14, Among them, The lower electrode structure includes: an upper region horizontally stacked with the support pattern; and a lower region located between the upper region and the substrate and not horizontally stacked with the support pattern, and wherein the width of the upper region is smaller than the width of the lower region.

20. A semiconductor device, the semiconductor device includes: a lower electrode structure including a first conductive part on the substrate and a second conductive part on the surface of the first conductive part; a support pattern in contact with the sidewall of the lower electrode structure, wherein the second conductive part of the lower electrode structure does not exist on the top surface and the bottom surface of the support pattern or is discontinuous on the top surface and the bottom surface of the support pattern; an upper electrode on the lower electrode structure and the support pattern; and a dielectric layer between the lower electrode structure and the upper electrode and between the support pattern and the upper electrode, wherein the first conductive part of the lower electrode structure is physically spaced from the dielectric layer by the second conductive part of the lower electrode structure such that the dielectric layer does not include a part in contact with the first conductive part of the lower electrode structure, wherein the second conductive part of the lower electrode structure includes niobium, wherein both the dielectric layer and the second conductive part of the lower electrode structure include a material having a tetragonal structure, and wherein the dielectric layer is in contact with the top surface and the bottom surface of the support pattern.

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