Non-volatile memory devices

Abstract

A nonvolatile memory device includes: a first semiconductor layer having a step region and a cell region, the cell region having a memory cell array formed therein; and a second semiconductor layer including a page buffer connected to the memory cell array. The first semiconductor layer includes: a plurality of word lines; a ground selection line in a layer on the word lines; a common source line in a layer on the ground selection line; a plurality of vertical transfer transistors in the step region; and a plurality of drive signal lines in the same layer as the common source line. The word lines are formed in a step shape in the step region, and each vertical transfer transistor is connected between a corresponding word line in the word lines and a corresponding drive signal line in the drive signal lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0108469 filed on September 2, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a memory device, and more particularly, to a nonvolatile memory device having a cell on periphery (COP) structure. Background Art

[0004] With the recent multifunctionalization of information and communication equipment, it is expected that memory devices have high capacity and high integration density. As the memory cell size is reduced to achieve high integration density, the operation circuit and / or interconnection structure included in the memory device for the operation and electrical connection of the memory device becomes complicated. Therefore, a memory device with high integration density and excellent electrical characteristics is expected. In particular, in order to increase the integration density of the memory device, the number of word lines stacked on the substrate in the vertical direction can be increased. The number of transfer transistors connected to the word lines may increase, thereby increasing the chip size. Summary of the invention

[0005] The inventive concept provides a nonvolatile memory device for increasing its integration density and reducing its chip size.

[0006] According to some embodiments of the present invention, there is provided a non-volatile memory device, comprising: a first semiconductor layer, comprising a step region and a cell region, the cell region comprising a memory cell array formed therein; and a second semiconductor layer, on a first side of the first semiconductor layer. The second semiconductor layer comprises a page buffer connected to the memory cell array. The first semiconductor layer may comprise: a plurality of word lines, stacked in a vertical direction perpendicular to the first semiconductor layer. The first semiconductor layer comprises: a ground selection line, in a layer on the plurality of word lines; a common source line, in a layer on the ground selection line; a plurality of vertical transfer transistors, in the step region; and a plurality of drive signal lines, in the same layer as the common source line. The plurality of word lines may form a step shape in the step region, and each of the plurality of vertical transfer transistors may be connected between a corresponding word line among the plurality of word lines and a corresponding drive signal line among the plurality of drive signal lines.

[0007] According to some embodiments of the present invention, there is provided a non-volatile memory device, comprising: a first semiconductor layer, comprising a memory cell array, the memory cell array comprising a vertical channel structure; and a second semiconductor layer, at a first side of the first semiconductor layer in a vertical direction. The second semiconductor layer comprises a page buffer connected to the memory cell array. The first semiconductor layer may comprise: a plurality of word lines, stacked in a vertical direction perpendicular to the first semiconductor layer; a ground selection line, in a layer on the plurality of word lines; a plurality of vertical transfer transistors, in a stepped region of the plurality of word lines. The plurality of vertical transfer transistors each comprise a vertical channel extending in a vertical direction. The first semiconductor layer may comprise a plurality of drive signal lines in a layer on the plurality of vertical transfer transistors. Each of the plurality of vertical transfer transistors may be connected between a corresponding word line among the plurality of word lines and a corresponding drive signal line among the plurality of drive signal lines.

[0008] According to some embodiments of the present invention, a nonvolatile memory device is provided, comprising: a first semiconductor layer; and a second semiconductor layer located on the first semiconductor layer in a vertical direction perpendicular to the first semiconductor layer. The second semiconductor layer includes transistors. The first semiconductor layer may include: a plurality of word lines stacked in a vertical direction; a ground selection line in a layer on the plurality of word lines; a common source line in a layer on the ground selection line; and a plurality of vertical transfer transistors in a stepped region of the plurality of word lines. The plurality of vertical transfer transistors are respectively connected to the plurality of word lines. The first semiconductor layer includes: a plurality of first contacts extending in a vertical direction, connecting the plurality of vertical transfer transistors to the plurality of word lines, and having the same length in the vertical direction. The first semiconductor layer includes a plurality of drive signal lines in the same layer as the common source line. Each of the plurality of vertical transfer transistors may be connected between a corresponding drive signal line in the plurality of drive signal lines and a corresponding word line in the plurality of word lines, and may include a gate configured to receive a block selection signal. The gate may be in the same layer as the ground selection line and may be connected to the transistor in the second semiconductor layer through a second contact and a first bonding pad formed in the first semiconductor layer and through a second bonding pad and a third contact formed in the second semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present invention will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a memory device according to some embodiments;

[0011] Figure 2 is a diagram schematically illustrating a structure of a memory device according to some example embodiments;

[0012] Figure 3 is a diagram showing a memory cell array according to some embodiments;

[0013] Figure 4 is a circuit diagram illustrating an equivalent circuit of a memory block according to some example embodiments;

[0014] Figure 5 is a diagram illustrating a row decoder and a pass transistor circuit according to some example embodiments;

[0015] Figure 6 is a table of voltages applied to word line drive signal lines in each memory operation according to some embodiments;

[0016] Figure 7 According to some example embodiments, Figure 5 A diagram of a memory device having a pass transistor circuit in FIG.

[0017] Figure 8 According to some example embodiments, Figure 7 A cross-sectional view taken along line AA′;

[0018] Fig. 9 According to some example embodiments, Figure 7 A cross-sectional view taken along line BB′;

[0019] FIG. 10A to FIG. 10C According to an example embodiment, Figure 5 A diagram of a memory device including a pass transistor circuit in FIG.

[0020] Fig.11 is a diagram illustrating a row decoder and a pass transistor circuit according to some example embodiments;

[0021] Fig.12 According to some example embodiments, Fig.11 A diagram of a memory device having a pass transistor circuit in FIG.

[0022] Fig.13 is a diagram illustrating a row decoder and a pass transistor circuit according to some example embodiments;

[0023] Fig.14 is a schematic diagram showing a method according to some embodiments including Fig.13 A cross-sectional view of a memory device including a pass transistor circuit in FIG. 1 ; and

[0024] Fig.15 is a block diagram of an example of applying a memory device according to some example embodiments to a solid state drive (SSD) system according to some example embodiments. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram of a memory device 10 according to some embodiments.

[0027] refer to Figure 1 , the memory device 10 may include a memory cell array 100 and a peripheral circuit 200. The peripheral circuit 200 may include a pass transistor circuit 210, a row decoder 220, a control logic 230, and a page buffer 240. Although not shown, the peripheral circuit 200 may also include a voltage generator, a data input / output (I / O) circuit, an I / O interface, a column logic, a pre-decoder, a temperature sensor, a command decoder, and / or an address decoder. In some embodiments, the memory device 10 may be a non-volatile memory device. Hereinafter, the term "memory device" refers to a non-volatile memory device.

[0028] In some example embodiments, at least a portion of the pass transistor circuit 210 and the memory cell array 100 may be formed in an upper semiconductor layer or a first semiconductor layer (eg, Figure 2 300 in the figure), and the row decoder 220, the control logic 230, and the page buffer 240 may be located in the lower semiconductor layer or the second semiconductor layer (eg, Figure 2 400 in . However, the memory device 10 is not limited to the above-described embodiments. In some embodiments, at least some circuits forming the row decoder 220 may be in the upper semiconductor layer together with the memory cell array 100 and the pass transistor circuit 210, and other circuits forming the pass transistor circuit 210, the control logic 230, and the page buffer 240 may be in the lower semiconductor layer.

[0029] In some example embodiments, the pass transistor circuit 210 may include a plurality of vertical pass transistors (eg, Figure 8 For example, a plurality of vertical transfer transistors may be on the upper semiconductor layer.

[0030] In some example embodiments, the pass transistor circuit 210 may include at least one conventional pass transistor (eg, Fig. 10A TRg in). For example, a plurality of vertical transfer transistors may be on the upper semiconductor layer, and a plurality of conventional transfer transistors may be on the lower semiconductor layer. However, the embodiment is not limited thereto, and at least one conventional transfer transistor may be on the first semiconductor layer.

[0031] The memory cell array 100 may be connected to the page buffer 240 through the bit lines BL, and may be connected to the pass transistor circuit 210 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL. In addition, the pass transistor circuit 210 may be connected to the row decoder 220 through the block selection signal line BS, the string selection line drive signal line SS, the word line drive signal line SI, and the ground selection line drive signal line GS. The string selection line drive signal line SS, the word line drive signal line SI, and the ground selection line drive signal line GS may be referred to as "drive signal lines".

[0032] The memory cell array 100 may include a plurality of memory cells. For example, the memory cells may include flash memory cells. Hereinafter, the embodiment will be described using a case where the plurality of memory cells are NAND flash memory cells as an example. However, the embodiment is not limited thereto. In some example embodiments, the plurality of memory cells may be resistive memory cells, such as resistive random access memory (ReRAM) cells, phase change RAM (PRAM) cells, or magnetic RAM (MRAM) cells.

[0033] In some example embodiments, the memory cell array 100 may include a three-dimensional (3D) memory cell array. The 3D memory cell array may include a plurality of NAND strings, each of which may include memory cells connected to word lines respectively stacked vertically on a substrate. Figure 3 and Figure 4 This is described in more detail. However, the embodiments are not limited thereto. In some example embodiments, the memory cell array 100 may include a two-dimensional (2D) memory cell array that may include a plurality of NAND strings in rows and columns.

[0034] The control logic 230 may generate various control signals for programming data to the memory cell array 100, reading data from the memory cell array 100, or erasing data from the memory cell array 100 based on the command CMD, the address ADDR, and the control signal CTRL. For example, the control logic 230 may output a row address X-ADDR sent to the row decoder 220 and / or a column address Y-ADDR sent to the page buffer 240. Thus, the control logic 230 may generally control various operations of the memory device 10.

[0035] The row decoder 220 may output a block selection signal for selecting one of a plurality of memory blocks to a block selection signal line BS in response to a row address X-ADDR. In response to the row address X-ADDR, the row decoder 220 may also output a word line drive signal for selecting one of the word lines WL of the selected memory block to a word line drive signal line SI, a string selection line drive signal for selecting one of the string selection lines SSL to a string selection line drive signal line SS, and a ground selection line drive signal for selecting one of the ground selection lines GSL to a ground selection line drive signal line GS. The page buffer 240 may select some of the bit lines BL in response to the column address Y-ADDR. Depending on the operation mode, the page buffer 240 may operate as a write driver or a sense amplifier.

[0036] As the level of memory cells arranged in the memory cell array 100 (i.e., the number of word lines WL stacked in the vertical direction) increases with the development of semiconductor processes, the number of pass transistors driving the word lines WL increases, and thus the area of ​​the pass transistor circuit 210 may increase. At least a portion of the pass transistor circuit 210 of the memory device 10 may be located in a stepped region (e.g., Figure 2 In some example embodiments, the pass transistor circuit 210 may include a plurality of vertical pass transistors in the step region of the word line WL. Therefore, the area of ​​the pass transistor circuit 210 overlaps with the step region of the word line WL, so even if the number of pass transistors increases as the number of stacked layers of the word line WL increases, the chip size of the memory device 10 can be prevented from increasing. In other words, the overall chip size is reduced by using the overlapping step region SA.

[0037] Figure 2 is a diagram schematically illustrating a structure of a memory device 10 according to some example embodiments.

[0038] refer to Figure 1 and Figure 2 , the memory device 10 may include a first semiconductor layer 300 and a second semiconductor layer 400. The first semiconductor layer 300 may be stacked on top of the second semiconductor layer 400 in the vertical direction VD. In other words, the second semiconductor layer 400 may be located on the bottom of the first semiconductor layer 300 in the vertical direction VD.

[0039] In some example embodiments, the memory cell array 100 and at least some of the pass transistors in the pass transistor circuit 210 may be formed in the first semiconductor layer 300, and the row decoder 220, the control logic 230, and the page buffer 240 may be formed in the second semiconductor layer 400. However, embodiments are not limited thereto, and at least a portion of the circuit of the row decoder 220 may be in the first semiconductor layer 300. Therefore, the memory device 10 may have a cell-on-periphery (COP) structure in which the memory cell array 100 is above a portion of the peripheral circuit 200 including the control logic 230 and / or the page buffer 240. The COP structure may effectively reduce a horizontal area and may increase the integration density of the memory device 10.

[0040] In some example embodiments, the first semiconductor layer 300 and the second semiconductor layer 400 may be formed in different wafers, respectively, and may be bonded to each other using Cu-Cu (C2C) wafer bonding, thereby manufacturing the memory device 10. For example, a plurality of bonding pads may be formed on a first surface of the first semiconductor layer 300, and a plurality of bonding pads may be formed on a first surface of the second semiconductor layer 400. The bonding pads of the first semiconductor layer 300 may be connected to the bonding pads of the second semiconductor layer 400. However, the memory device 10 is not limited thereto, and the first semiconductor layer 300 and the second semiconductor layer 400 may be formed in one wafer.

[0041] In the first semiconductor layer 300, the word line WL may extend in the first horizontal direction HD1, and the bit line BL may extend in the second horizontal direction HD2. The first horizontal direction and the second horizontal direction may be perpendicular to each other. The respective ends of the word line WL may form a step shape. In this specification, the region including the step-shaped word line WL in the first semiconductor layer 300 will be referred to as a "step region SA".

[0042] In the first semiconductor layer 300 , a vertical channel structure may be formed, thereby forming a cell region CA in which memory cells are formed. Therefore, the memory cell array 100 may be located in the cell region CA.

[0043] Figure 3 is a diagram illustrating a memory cell array 100 according to some embodiments.

[0044] refer to Figure 3, the memory cell array 100 may include a plurality of memory blocks BLK1 to BLKi, where "i" may be a positive integer. Each of the memory blocks BLK1 to BLKi may have a 3D structure (or a vertical structure). In detail, each of the memory blocks BLK1 to BLKi may include a plurality of NAND strings extending in a vertical direction VD. At this time, the NAND strings may be separated from each other by a certain distance in a first horizontal direction HD1 and a second horizontal direction HD2. The NAND strings may be connected to each other by a row decoder (e.g., Figure 1 For example, the row decoder 220 may select a memory block corresponding to a block address from among the memory blocks BLK1 to BLKi.

[0045] Figure 4 is a circuit diagram illustrating an equivalent circuit of a memory block BLK according to some example embodiments. For example, the memory block BLK may correspond to Figure 3 One of the memory blocks BLK1 to BLKi.

[0046] refer to Figure 4 , the memory block BLK may include a plurality of NAND strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of first bit lines BL1 to third bit lines BL3, a plurality of ground selection lines GSL1 to GSL3, a plurality of string selection lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may vary with different embodiments.

[0047] The NAND strings NS11, NS21, and NS31 may be disposed between the first bit line BL1 and the common source line CSL. The NAND strings NS12, NS22, and NS32 may be disposed between the second bit line BL2 and the common source line CSL. The NAND strings NS13, NS23, and NS33 may be disposed between the third bit line BL3 and the common source line CSL. Each NAND string (e.g., NS11) may include a string selection transistor SST, a plurality of memory cells MC, and a ground selection transistor GST connected in series.

[0048] The string selection transistor SST may be connected to a corresponding string selection line among the string selection lines SSL1 to SSL3. The memory cells MC may be connected to the word lines WL1 to WL8, respectively. The ground selection transistor GST may be connected to a corresponding ground selection line among the ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to a corresponding bit line among the first bit line BL1 to the third bit line BL3. The ground selection transistor GST may be connected to a common source line CSL.

[0049] exist Figure 4In the memory block BLK of FIG. 1 , word lines (eg, WL1) at the same depth level in the device are commonly connected to each other, string selection lines SSL1 to SSL3 are separated from each other, and ground selection lines GSL1 to GSL3 are also separated from each other. Figure 4 , it is shown that three string selection lines SSL1 to SSL3 share the same horizontal word line, but the embodiment is not limited thereto. For example, two string selection lines may share the same horizontal word line. In another example, four string selection lines may share the same horizontal word line.

[0050] Figure 5 is a diagram illustrating a row decoder 220 a and a pass transistor circuit 210 a according to example embodiments.

[0051] refer to Figure 5 , the memory block BLKa may correspond to Figure 3 The row decoder 220a may be one of the memory blocks BLK1 to BLKi. Figure 1 , and the pass transistor circuit 210a may be Figure 1 An example of a pass transistor circuit 210 in FIG.

[0052] The row decoder 220a may include a block decoder 221 and a drive signal line decoder 222a. The transfer transistor circuit 210a may include a plurality of transfer transistors, for example, a transfer transistor TRs, a first transfer transistor TR1 to an mth transfer transistor TRm, and a transfer transistor TRg, where "m" may be a positive integer. For each memory block (for example, Figure 3 The pass transistor circuit 210a is provided for the memory block (e.g., BLK1 to BLKi) and can be Figure 3 The block decoder 221 and the drive signal line decoder 222a are commonly provided by BLK1 to BLKi.

[0053] The block decoder 221 may be connected to the transfer transistor circuit 210a through a block selection signal line BS. For example, the block selection signal line BS may be connected to the corresponding gates of the transfer transistors, for example, the transfer transistor TRs, the first transfer transistor TR1 to the mth transfer transistor TRm, and the transfer transistor TRg. When a block selection signal provided through the block selection signal line BS is activated, the transfer transistors, for example, the transfer transistor TRs, the first transfer transistor TR1 to the mth transfer transistor TRm, and the transfer transistor TRg are turned on, and thus the memory block BLKa may be selected.

[0054] The driving signal line decoder 222a may be connected to the transfer transistor circuit 210a through the string selection line driving signal line SS, the first word line driving signal line SI1 to the m-th word line driving signal line SIm, and the ground selection line driving signal line GS. In detail, the string selection line driving signal line SS, the first word line driving signal line SI1 to the m-th word line driving signal line SIm, and the ground selection line driving signal line GS may be connected to the corresponding sources of the transfer transistors such as the transfer transistor TRs, the first transfer transistor TR1 to the m-th transfer transistor TRm, and the transfer transistor TRg, respectively. For example, the first word line driving signal line SI1 may be connected to the first transfer transistor TR1, the second word line driving signal line SI2 may be connected to the second transfer transistor TR2, and the m-th word line driving signal line SIm may be connected to the m-th transfer transistor TRm.

[0055] The transfer transistor circuit 210a may be connected to the memory block BLKa through the ground selection line GSL, the first to m-th word lines WL1 to WLm, and the string selection line SSLu. The first to m-th transfer transistors TR1 to TRm may connect the first to m-th word lines WL1 to WLm to the first to m-th word line drive signal lines SI1 to SIm, respectively. For example, the first transfer transistor TR1 may be connected to the first word line WL1, and may connect the first word line WL1 to the first word line drive signal line SI1. The second transfer transistor TR2 may be connected to the second word line WL2, and may connect the second word line WL2 to the second word line drive signal line SI2. The m-th transfer transistor TRm may be connected to the m-th word line WLm, and may connect the m-th word line WLm to the m-th word line drive signal line SIm.

[0056] The transfer transistor TRs may connect the string selection line SSLu to the string selection line drive signal line SS corresponding to the string selection line SSLu. The transfer transistor TRg may connect the ground selection line GSL to the ground selection line drive signal line GS corresponding to the ground selection line GSL. For example, when the block selection signal is activated, the transfer transistor TRs, the first to m-th transfer transistors TR1 to TRm, and the transfer transistor TRg may respectively provide drive signals, which are respectively provided to the string selection line SSLu, the first to m-th word lines WL1 to WLm, and the ground selection line GSL through the string selection line drive signal line SS, the first to m-th word line drive signal lines SI1 to SIm, and the ground selection line drive signal line GS.

[0057] In some example embodiments, the transfer transistor TRs and the first to mth transfer transistors TR1 to TRm may be implemented as vertical transfer transistors. In this specification, the term "vertical transfer transistor" refers to a transistor including a vertical channel. For example, the transfer transistor TRs and the first to mth transfer transistors TR1 to TRm may be provided in a stepped region of a word line (e.g., Figure 2 In some example embodiments, the transfer transistor TRg may be implemented as a conventional transfer transistor. In this specification, the term “conventional transfer transistor” refers to a transistor including a horizontal channel. For example, the transfer transistor TRg may be in the second semiconductor layer (e.g., Figure 2 400). The reference includes Fig. 10A This is described with reference to the accompanying drawings.

[0058] Figure 6 is a diagram illustrating voltages applied to a word line driving signal line in each memory operation according to some embodiments.

[0059] refer to Figure 5 and Figure 6 , the selected word line drive signal line SIa may correspond to the drive signal line connected to the selected word line WLsel, and the unselected word line drive signal line SIb may correspond to the drive signal line connected to the unselected word line WLunsel. In a programming operation, a programming voltage Vpgm (e.g., about 20V) may be applied to the selected word line drive signal line SIa among the first word line drive signal line SI1 to the mth word line drive signal line SIm. A transmission voltage Vpass (e.g., about 9V) may be applied to the unselected word line drive signal line SIb among the first word line drive signal line SI1 to the mth word line drive signal line SIm. In a read operation, a read voltage Vr (e.g., about 0V) may be applied to the selected word line drive signal line SIa, and a read transmission voltage Vread (e.g., about 6V) may be applied to the unselected word line drive signal line SIb. In an erase operation, an erase voltage Ver (eg, about 0 V) ​​may be applied to a selected word line drive signal line SIa and unselected word line drive signal lines SIb.

[0060] Figure 7 According to some example embodiments, Figure 5 FIG. 1 is a diagram of a memory device 10 having a pass transistor circuit 210 a in FIG. Figure 8 According to some example embodiments, Figure 7 A cross-sectional view taken along line AA′. Fig. 9 According to some example embodiments, Figure 7 In detail, Figure 7is a diagram of the first semiconductor layer 300 of the memory device 10 viewed from below in the vertical direction VD.

[0061] refer to Figure 7 and Figure 8 , the first semiconductor layer 300 of the memory device 10 may include a plurality of word lines, for example, first to m-th word lines WL1 to WLm. The first to m-th word lines WL1 to WLm may be sequentially stacked in a direction opposite to the vertical direction VD, and may extend in the first horizontal direction HD1. Although not shown, the first to m-th word lines WL1 to WLm may be electrically insulated by a plurality of insulating layers. The respective ends of the first to m-th word lines WL1 to WLm in the first horizontal direction HD1 may be implemented as a step shape in the step area SA.

[0062] Each of the first to m-th word lines WL1 to WLm may include a conductive region W and an insulating region NT in the step region SA. For example, each of the first to m-th word lines WL1 to WLm may include a conductive region W contacting a contact CP corresponding to each word line and an insulating region NT contacting a contact CP not corresponding thereto (e.g., a contact CP connected to another word line).

[0063] Here, the conductive region W may include a conductive material such as tungsten, but is not limited to tungsten. The insulating region NT may include an insulating material such as nitride, but is not limited to nitride.

[0064] The first word line WL1 may be under the gate GT, and second to m-th word lines WL2 to WLm may be sequentially formed under the first word line WL1 in a direction opposite to the vertical direction VD.

[0065] Each of the first to m-th word lines WL1 to WLm may be connected to a vertical channel VC corresponding thereto through a contact CP corresponding thereto. For example, a vertical channel VC corresponding to the first word line WL1 may be connected to a first word line drive signal line SI1, a vertical channel VC corresponding to the second word line WL2 may be connected to a second word line drive signal line SI2, a vertical channel VC corresponding to the third word line WL3 may be connected to a third word line drive signal line SI3, and a vertical channel VC corresponding to the fourth word line WL4 may be connected to a fourth word line drive signal line SI4. The first to m-th word lines WL1 to WLm may extend in a first horizontal direction HD1, and one horizontal word line may be divided by a word line cutting region WLC.

[0066] The first semiconductor layer 300 of the memory device 10 may include a ground selection line GSL above the first word line WL1 to the mth word line WLm and a common source line CSL above the ground selection line GSL. In some example embodiments, a plurality of drive signal lines, for example, the first word line drive signal line SI1 to the fourth word line drive signal line SI4 and the first string selection line drive signal line SS1 to the fourth string selection line drive signal line SS4 and the common source line CSL may be arranged at the same level (i.e., the same layer). For example, a plurality of drive signal lines, for example, the first word line drive signal line SI1 to the fourth word line drive signal line SI4 and the first string selection line drive signal line SS1 to the fourth string selection line drive signal line SS4 and the common source line CSL may be formed by the same process. In some example embodiments, a plurality of drive signal lines, for example, the first word line drive signal line SI1 to the fourth word line drive signal line SI4 and the first string selection line drive signal line SS1 to the fourth string selection line drive signal line SS4, may extend in the second horizontal direction HD2 and may be separated from each other in the first horizontal direction HD1. In some example embodiments, the common source line CSL may extend in the second horizontal direction HD2 and may be implemented by a metal plate. Figure 7 and Figure 8 Only the first to fourth word line drive signal lines SI1 to SI4 are shown, but the first to m-th word line drive signal lines SI1 to SIm may be included in the memory device 10 to correspond to the first to m-th word lines WL1 to WLm, respectively, thereby providing corresponding word line drive signals to the first to m-th word lines WL1 to WLm, respectively.

[0067] The first semiconductor layer 300 of the memory device 10 may further include a string selection line SSLu below the first to m-th word lines WL1 to WLm. For example, the string selection line SSLu may include a first to fourth string selection line SSLu1 to SSLu4. The first to fourth string selection lines SSLu1 to SSLu4 may be arranged at the same level and may be separated from each other by a string selection line cutting region SSLC. Each of the first to fourth string selection lines SSLu1 to SSLu4 may be connected to a vertical channel VC corresponding thereto via a contact CP corresponding thereto. The vertical channel VC corresponding to the first string selection line SSLu1 may be connected to the first string selection line drive signal line SS1, the vertical channel VC corresponding to the second string selection line SSLu2 may be connected to the second string selection line drive signal line SS2, the vertical channel VC corresponding to the third string selection line SSLu3 may be connected to the third string selection line drive signal line SS3, and the vertical channel VC corresponding to the fourth string selection line SSLu4 may be connected to the fourth string selection line drive signal line SS4.

[0068] Despite Figure 8 1 shows that the memory device 10 includes a layer of string selection lines SSLu, but the embodiment is not limited thereto. In some example embodiments, the memory device 10 may include two string selection lines (eg, Fig. 10A SSLu and SSLd in SSL.

[0069] In some example embodiments, the ground selection line GSL, the string selection line SSLu, and the gate GT may include the same material as the first to mth word lines WL1 to WLm. For example, the ground selection line GSL, the string selection line SSLu, and the gate GT may include the same material as the conductive region W.

[0070] A plurality of vertical channel structures VP may be in the channel region CA of the first semiconductor layer 300, and a memory cell array may be formed in the channel region CA. The plurality of vertical channel structures VP may extend in the vertical direction VD and pass through the first word line WL1 to the mth word line WLm and a plurality of insulating layers formed between the first word line WL1 to the mth word line WLm. The plurality of vertical channel structures VP may be referred to as vertical pillars. In some example embodiments, each of the plurality of vertical channel structures VP may have a first width VPW in the first horizontal direction HD1. For example, each of the plurality of vertical channel structures VP may have a ring shape. At this time, the first width VPW may correspond to the first channel hole size. However, the embodiment is not limited thereto. Each of the plurality of vertical channel structures VP may have an elliptical pillar shape or a quadrilateral pillar shape. The plurality of vertical channel structures VP may be spaced apart from each other in the first horizontal direction HD1 and the second horizontal direction HD2.

[0071] In some example embodiments, each vertical channel structure VP may include a charge storage layer, a channel layer, and an inner layer. The channel layer may include a silicon material having a first type (e.g., P-type) and may be used as a channel region. The inner layer may include an insulating material, such as silicon oxide or an air gap. The charge storage layer may include a gate insulating layer (or referred to as a "tunneling insulating layer"), a charge trap layer, and / or a blocking insulating layer. For example, the charge storage layer may have an oxide-nitride-oxide (ONO) structure.

[0072] The drain or drain contact may be disposed below the vertical channel structure VP, respectively. For example, the drain or drain contact may include a silicon material doped with impurities having a second conductivity type (eg, N-type). The bit line (eg, Figure 2 The BL in the second semiconductor layer 400 may be disposed under the drain contact and may be respectively connected to the drain contact through the bit line contacts. Each bit line may be connected to the page buffer in the second semiconductor layer 400 through a pad.

[0073] A plurality of vertical transfer transistors, for example, first and third vertical transfer transistors TR1 and TR3 and vertical transfer transistors TRs1 and TRs2, may be located in the step area SA. Figure 8 Only the first and third vertical transfer transistors TR1 and TR3 and the vertical transfer transistors TRs1 and TRs2 are shown in FIG. Figure 5 The second transfer transistor TR2 and the fourth transfer transistor TR4 to the mth transfer transistor TRm can be formed in the step area SA as vertical transfer transistors, and the description of the first vertical transfer transistor TR1 and the third vertical transfer transistor TR3 and the vertical transfer transistors TRs1 and TRs2 can also be applied to the second transfer transistor TR2 and the fourth transfer transistor TR4 to the mth transfer transistor TRm.

[0074] Each of the first and third vertical transfer transistors TR1 and TR3 and the vertical transfer transistors TRs1 and TRs2 may be connected to a corresponding line among the first to m-th word lines WL1 to WLm and the string selection line SSLu, and to a corresponding drive signal line among a plurality of drive signal lines, for example, the first to fourth word line drive signal lines SI1 to SI4 and the first to fourth string selection line drive signal lines SS1 to SS4. For example, the first vertical transfer transistor TR1 may be connected between the first word line WL1 and the first word line drive signal line SI1, and the third vertical transfer transistor TR3 may be connected between the third word line WL3 and the third word line drive signal line SI3. The vertical transfer transistor TRs1 may be connected between the first string selection line SSLu1 and the first string selection line drive signal line SS1, and the vertical transfer transistor TRs2 may be connected between the second string selection line SSLu2 and the second string selection line drive signal line SS2.

[0075] Each of the first and third vertical transfer transistors TR1 and TR3 and the vertical transfer transistors TRs1 and TRs2 may include a vertical channel VC extending in the vertical direction VD. In some example embodiments, the plurality of vertical channels VC may have the same height in the vertical direction VD, for example, a first height VCH. In some example embodiments, the bottom level of the vertical channel VC may be higher than the top level of the first word line WL1, where the first word line WL1 is at the top among the first word line WL1 to the m-th word line WLm. For example, the bottom level of the vertical channel VC may be between the first word line WL1 and the ground selection line GSL.

[0076] The vertical channel VC may have a second width VCW in the first horizontal direction HD1. In some example embodiments, the second width VCW may be greater than the first width WPW of the vertical channel structure VP. Therefore, the breakdown problem of the first vertical transfer transistor TR1 and the third vertical transfer transistor TR3 and the vertical transfer transistors TRs1 and TRs2 may be solved. That is, by forming the widths of the vertical transfer transistors TR1, TR3, TRs1, and TRs2 to be relatively wide, the vertical transfer transistors TR1, TR3, TRs1, and TRs2 are formed to withstand high voltage, and the breakdown problem of the vertical transfer transistors TR1, TR3, TRs1, and TRs2 may be solved. For example, the second width VCW may be at least twice the first width VPW. However, the embodiment is not limited thereto. The first width VPW and the second width VCW may vary from embodiment to embodiment.

[0077] In some example embodiments, the vertical channel VC may be formed in the same structure using the same process as the vertical channel structure VP. Therefore, similar to the vertical channel structure VP, the vertical channel VC may include a charge storage layer, a channel layer, and an inner layer. However, the embodiments are not limited thereto. In some example embodiments, the vertical channel VC may include only a channel layer and an inner layer.

[0078] The vertical channels VC respectively included in the first and third vertical transfer transistors TR1 and TR3 and the vertical transfer transistors TRs1 and TRs2 may be commonly connected to the gate GT. In some example embodiments, the gate GT commonly connected to the first and third vertical transfer transistors TR1 and TR3 and the vertical transfer transistors TRs1 and TRs2 may be at the same level as the ground selection line GSL.

[0079] In some example embodiments, the vertical channels VC respectively included in the first and third vertical transfer transistors TR1 and TR3 and the vertical transfer transistors TRs1 and TRs2 may be connected to different gates, respectively. At this time, the different gates may have different lengths in the vertical direction VD, and the first and third vertical transfer transistors TR1 and TR3 and the vertical transfer transistors TRs1 and TRs2 may have different driving performances.

[0080] In some example embodiments, the first length LG1 of the gate GT may be substantially the same as the second length LG2 of the ground selection line GSL in the vertical direction VD. In some example embodiments, the third length LS1 of the insulating layer under the gate GT may be substantially the same as the fourth length LS2 of the insulating layer under the ground selection line GSL in the vertical direction VD. However, embodiments are not limited thereto. The first length LG1 may be different from the second length LG2, and the third length LS1 may be different from the fourth length LS2.

[0081] In some example embodiments, the second length LG2 of the ground selection line GSL may be substantially the same as the length of each of the first to m-th word lines WL1 to WLm in the vertical direction VD, but the embodiment is not limited thereto. In some example embodiments, the second length LG2 may be substantially the same as the length of the string selection line SSLu in the vertical direction VD, but the embodiment is not limited thereto.

[0082] The contact CP may be in each of the first and third vertical transfer transistors TR1 and TR3 and the vertical transfer transistors TRs1 and TRs2. Each of the first and third vertical transfer transistors TR1 and TR3 and the vertical transfer transistors TRs1 and TRs2 may be connected to corresponding lines of the first to m-th word lines WL1 to WLm and the string selection line SSLu through the contact CP corresponding thereto. For example, the first vertical transfer transistor TR1 may be connected to the first word line WL1 through the contact CP corresponding to the first vertical transfer transistor TR1, and the third vertical transfer transistor TR3 may be connected to the third word line WL3 through the contact CP corresponding to the third vertical transfer transistor TR3. The vertical transfer transistor TRs1 may be connected to the first string selection line SSLu1 through the contact CP corresponding to the vertical transfer transistor TRs1, and the vertical transfer transistor TRs2 may be connected to the second string selection line SSLu2 through the contact CP corresponding to the vertical transfer transistor TRs2.

[0083] In some example embodiments, the plurality of contacts CP respectively connected to the vertical channels VC may have the same height, eg, the second height CPH, in the vertical direction VD. Therefore, the contacts CP may be easily formed in the memory device 10.

[0084] refer to Figure 8 and Fig. 9, the second semiconductor layer 400 may include a substrate SUB, a first lower insulating layer IL21, and / or a second lower insulating layer IL22. The first semiconductor layer 300 may be combined with the second semiconductor layer 400 by C2C wafer bonding. At this time, a plurality of bonding pads PD1a and PD1b may be formed on a first surface of the first semiconductor layer 300, and a plurality of bonding pads PD2a and PD2b may be formed on a first surface of the second semiconductor layer 400. The first surface of the first semiconductor layer 300 may be bonded to the first surface of the second semiconductor layer 400. In some example embodiments, an I / O pad formation process and a post-lapping process may be sequentially performed on a second surface opposite to the first surface of the first semiconductor layer 300.

[0085] The gate GT may be connected to the transistor 440 through an interconnection including the first contact 310, the metal pattern 330, and the bonding pad PD1a included in the first semiconductor layer 300, and the bonding pad PD2a, contacts 410 and 430, and the metal pattern 420 included in the second semiconductor layer 400. The first word line drive signal line SI1 may be connected to the transistor 480 through an interconnection including the contact 320 and the bonding pad PD2b included in the first semiconductor layer 300, and the bonding pad PD1b, contacts 450 and 470, and the metal pattern 460 included in the second semiconductor layer 400. Although not shown, each of the plurality of drive signal lines (e.g., SI2 to SI4 and SS1 to SS4) other than the first word line drive signal line SI1 may be connected to the transistor through an interconnection including the contact CP and the bonding pad included in the first semiconductor layer 300, and the bonding pad, the contact, and the metal pattern included in the second semiconductor layer 400.

[0086] In some example embodiments, at least a portion of a row decoder (e.g., Figure 5 220a) in the vertical direction VD may be located below the vertical transfer transistors (eg, TR1, TR3, TRs1, and TRs2). Figure 5 At least one selected from the block decoder 221 and the driving signal line decoder 222 a may be located below the vertical transfer transistors (eg, TR1 , TR3 , TRs1 , and TRs2 ) in the vertical direction VD and may include the transistor 440 .

[0087] FIG. 10A to FIG. 10C According to an example embodiment, Figure 5 FIG. 210 a and 210 b are diagrams of memory devices 10 a, 10 b and 10 c including the pass transistor circuit 210 a in FIG. 210 b and 210 c are diagrams of memory devices 10 a, 10 b and 10 c including the pass transistor circuit 210 a in FIG. Figure 8 , Fig. 9 and FIG. 10A to FIG. 10C Repeated description of the same number in .

[0088] refer to Fig. 10A , the memory device 10a may include an upper string selection line SSLd stacked on the string selection line SSLu. Therefore, the above-mentioned string selection line SSLu may be composed of FIG. 10A to FIG. 10C , and the lower string selection line SSLu in the vertical direction VD. For example, the upper string selection line SSLd may be stacked on the lower string selection line SSLu in the vertical direction VD. The lower string selection line SSLu may include a first lower string selection line SSLul and a second lower string selection line SSLu2 located at the same level. A plurality of vertical channel structures VP may extend in the vertical direction VD and pass through the ground selection line GSL, the first word line WL1 to the mth word line WLm, the upper string selection line SSLd and / or the lower string selection line SSLu.

[0089] In the memory device 10a, some of the plurality of pass transistors (eg, Figure 5 The transmission transistors TRs, TR1 to TRm and TRg in the first semiconductor layer 300a can be formed as vertical transmission transistors in the first semiconductor layer 300a, and the other transmission transistors in the transmission transistors can be formed as conventional transmission transistors in the second semiconductor layer 400a. For example, the transmission transistor TRg connected to the ground selection line GSL can be formed as a conventional transmission transistor in the second semiconductor layer 400a, and the ground selection line GSL among the first word line WL1 to the m-th word line WLm, the upper string selection line SSLd and the lower string selection line SSLu are located in the same layer as the gate GT. The ground selection line GSL can be connected to the transmission transistor TRg through an interconnection including the second contact 311, the metal pattern 331 and the bonding pad PD1c included in the first semiconductor layer 300a and the bonding pad PD2c, the contacts 411 and 431 and the metal pattern 421 included in the second semiconductor layer 400a.

[0090] The second contact 311 may extend in the vertical direction VD to contact the ground selection line GSL, and may pass through the first to m-th word lines WL1 to WLm, the upper string selection line SSLd, and the lower string selection line SSLu. The first to m-th word lines WL1 to WLm, the upper string selection line SSLd, and the lower string selection line SSLu may include an insulating region NT contacting the second contact 311, and thus may be insulated from the second contact 311.

[0091] In the memory device 10a, the gate GT commonly connected to the plurality of vertical transfer transistors (e.g., TR1, TR3, TRs1, and TRs2) is at the same level as the ground selection line GSL, so the transfer transistor TRg connected to the ground selection line GSL may be formed in the second semiconductor layer 400a. However, the embodiment is not limited thereto. The transfer transistor TRg connected to the ground selection line GSL may be formed in the first semiconductor layer 300a as a conventional transistor or a vertical transfer transistor.

[0092] refer to Fig. 10B , the memory device 10b may include a gate GTb that forms a third vertical transfer transistor TR3 and vertical transfer transistors TRs1 and TRs2. In some example embodiments, a first length LG1b of the gate GTb may be different from a second length LG2b of the ground selection line GSL in the vertical direction VD. For example, the first length LG1b of the gate GTb may be greater than the second length LG2b of the ground selection line GSL. In some example embodiments, a third length LS1b of the insulating layer under the gate GTb may be different from a fourth length LS2b of the insulating layer under the ground selection line GSL in the vertical direction VD.

[0093] When the first length LG1b of the gate GTb in the vertical direction VD increases, a high voltage can be applied to the gates of the third vertical transfer transistor TR3 and the vertical transfer transistors TRs1 and TRs2, that is, the gate GTb, and the driving speed of the third vertical transfer transistor TR3 and the vertical transfer transistors TRs1 and TRs2 can be improved. In addition, the breakdown problem of the first vertical transfer transistor TR1 and the third vertical transfer transistor TR3 and the vertical transfer transistors TRs1 and TRs2 can be solved.

[0094] In some example embodiments, the transfer transistor TRg and the first transfer transistor TR1b of the memory device 10b may be in the second semiconductor layer 400b and may be a conventional transfer transistor. For example, the ground selection line GSL may be connected to the transfer transistor TRg through an interconnection including the second contact 311, the metal pattern 331, and the bonding pad PD1c included in the first semiconductor layer 300b, and the bonding pad PD2c, the contacts 411 and 431, and the metal pattern 421 included in the second semiconductor layer 400b. For example, the first word line WL1 may be connected to the first transfer transistor TR1b through an interconnection including the third contact 312, the metal pattern 331, and the bonding pad PD1d included in the first semiconductor layer 300b, and the bonding pad PD2d, the contacts 412 and 432, and the metal pattern 422 included in the second semiconductor layer 400b.

[0095] The third contact 312 may extend in the vertical direction VD to contact the first word line WL1, and may pass through the second word lines WL2 to the m-th word line WLm, the upper string selection line SSLd, and the lower string selection line SSLu. The second word lines WL2 to the m-th word line WLm, the upper string selection line SSLd, and the lower string selection line SSLu may include an insulating region NT in contact with the third contact 312. Therefore, the second word lines WL2 to the m-th word line WLm, the upper string selection line SSLd, and the lower string selection line SSLu may be insulated from the third contact 312.

[0096] Although referenced Fig. 10B The transfer transistor TRg and the first transfer transistor TR1b are described in the second semiconductor layer 400b, but the embodiment is not limited thereto. When a dummy word line (eg, Fig.12 When DWL1 in , the pass transistor connected to the virtual word line (for example, Fig.12 TRd1) in the second semiconductor layer 400b may be in the second semiconductor layer 400b.

[0097] refer to Fig. 10C , the gate GT and the ground selection line GSL formed in the first semiconductor layer 300c may be formed of a material different from the first to m-th word lines WL1 to WLm. For example, the gate GT and the ground selection line GSL may include polysilicon, and the first to m-th word lines WL1 to WLm may include tungsten. However, this is only an example, and the gate GT and the ground selection line GSL may include various materials.

[0098] Since the gate GT and the ground selection line GSL in the memory device 10c are formed of a material different from that of the first to mth word lines WL1 to WLm, when the ground selection line GSL, the second to mth word lines WL2 to WLm, the upper string selection line SSLd and the lower string selection line SSLu are partially etched to form the word line cutting area WLC, the gate GT and the ground selection line GSL can limit the etching and prevent over-etching.

[0099] Fig.11 is a diagram illustrating a row decoder 220 a ′ and a pass transistor circuit 210 a ′ according to some example embodiments.

[0100] refer to Fig.11 , the memory block BLKa may correspond to Figure 3 One of the memory blocks BLK1 to BLKi. Figure 5Compared to the memory block BLKa in the memory block BLKa, the memory block BLKa′ may further include first to fourth dummy word lines DWL1 to DWL4. The first and second dummy word lines DWL1 and DWL2 may be between the ground selection line GSL and the first word line WL1, and the third and fourth dummy word lines DWL3 and DWL4 may be between the mth word line WLm and the string selection line SSLu. In some example embodiments, the memory block BLKa′ may include at least one dummy word line selected from the first to fourth dummy word lines DWL1 to DWL4. The number of dummy word lines of the memory block BLKa′ may vary.

[0101] The row decoder 220a′ may be Figure 5 The row decoder 220a in FIG. 1 is modified, and the pass transistor circuit 210a′ may be a modification of the row decoder 220a in FIG. Figure 5 A modification of the pass transistor circuit 210a in FIG. Figure 5 Compared with the pass transistor circuit 210a in FIG. 2 , the pass transistor circuit 210a′ may further include pass transistors TRd1 to TRd4. The pass transistors TRd1 to TRd4 may respectively connect the first to fourth dummy word lines DWL1 to DWL4 to the first to fourth dummy word line drive signal lines DSI1 to DSI4.

[0102] Fig.12 According to some example embodiments, Fig.11 FIG. 10 is a diagram of a memory device 10d including a pass transistor circuit 210a′ in FIG. Figure 8 and Fig.12 Repeated description of the same number in .

[0103] refer to Fig.12 , the first semiconductor layer 300d of the memory device 10d may include first to m-th word lines WL1 to WLm and first to fourth dummy word lines DWL1 to DWL4. The first and second dummy word lines DWL1 and DWL2 may be between the ground selection line GSL and the first word line WL1, and the third and fourth dummy word lines DWL3 and DWL4 may be between the m-th word line WLm and the string selection line SSLu. However, the memory device 10d is not limited thereto, and the number of dummy word lines may vary.

[0104] Each of the first to fourth dummy word lines DWL1 to DWL4 may be connected to a vertical channel VC corresponding thereto through a contact CP corresponding thereto. For example, a vertical channel VC corresponding to the first dummy word line DWL1 may be connected to a first dummy word line drive signal line DSI1. The vertical channel VC and the gate GT connected to the first dummy word line drive signal line DSI1 may form a transfer transistor TRd1 connected to the first dummy word line DWL1. In some example embodiments, a plurality of vertical transfer transistors (e.g., TRd1, TR1, TRs1, and TRs2) may be commonly connected to the gate GT.

[0105] Fig.13 is a diagram illustrating a row decoder 220 b and a pass transistor circuit 210 b according to some example embodiments.

[0106] refer to Fig.13 , the memory block BLKb may correspond to Figure 3 One of the memory blocks BLK1 to BLKi, where "b" may be a positive integer. The row decoder 220b may be Figure 5 The row decoder 220a in FIG. 1 is modified, and the pass transistor circuit 210b may be a modification of the row decoder 220a in FIG. Figure 5 Modification of the pass transistor circuit 210a in FIG.

[0107] The row decoder 220b may include a block decoder 221 and a driving signal line decoder 222b. The transfer transistor circuit 210b may include a plurality of transfer transistors, for example, transfer transistors TRs, first to mth transfer transistors TR1 to TRm, transfer transistors TRg, and transfer transistors TRgd.

[0108] The driving signal line decoder 222b may be connected to the transfer transistor circuit 210b through the string selection line driving signal line SS, the first word line driving signal line SI1 to the m-th word line driving signal line SIm, the ground selection line driving signal line GS, and the gate induced drain leakage (GIDL) gate driving signal line GDS. In detail, the string selection line driving signal line SS, the first word line driving signal line SI1 to the m-th word line driving signal line SIm, the ground selection line driving signal line GS, and the GIDL gate driving signal line GDS may be connected to corresponding sources of the transfer transistors (e.g., TRs, TR1 to TRm, TRg, and TRgd), respectively.

[0109] The transfer transistor circuit 210b may be connected to the memory block BLKb through the ground selection line GSL, the first word line WL1 to the mth word line WLm, the string selection line SSLu, and the GIDL gate line GIDL. For example, the transfer transistor TRgd may connect the GIDL gate line GIDL to the GIDL gate drive signal line GDS. When the block selection signal is activated, the transfer transistors (e.g., TRs, TR1 to TRm, TRg, and TRgd) may respectively provide drive signals, which are respectively provided to the string selection line SSLu, the first word line WL1 to the mth word line WLm, the ground selection line GSL, and the GIDL gate line GIDL through the string selection line drive signal line SS, the first word line drive signal line S11 to the mth word line drive signal line SIm, the ground selection line drive signal line GS, and the GIDL gate drive signal line GDS.

[0110] In some example embodiments, at least one of the transfer transistors TRs and TRg and the first to m-th transfer transistors TR1 to TRm may be implemented as a vertical transfer transistor. For example, the transfer transistors TRs and TRg and the first to m-th transfer transistors TR1 to TRm may be in a step region (e.g., Figure 8 In some example embodiments, the transfer transistor TRgd may be implemented as a conventional transfer transistor. For example, the transfer transistor TRgd may be in the second semiconductor layer. Fig.14 This is described in detail.

[0111] Fig.14 is a schematic diagram showing a method according to some embodiments including Fig.13 FIG. 2 is a cross-sectional view of a memory device 10e including a transfer transistor circuit 210b in FIG. Figure 8 and Fig.14 Repeated description of the same number in .

[0112] refer to Fig.14 , the first semiconductor layer 300e of the memory device 10e may include a string selection line SSLu, first to m-th word lines WL1 to WLm, a ground selection line GSL, a GIDL gate line GIDL, and a regular source line CSL.

[0113] The string selection line SSLu, the first to m-th word lines WL1 to WLm, the ground selection line GSL, and the GIDL gate line GIDL may be sequentially stacked in a vertical direction and may extend in a first horizontal direction HD1. Each of the string selection line SSLu, the first to m-th word lines WL1 to WLm, the ground selection line GSL, and the GIDL gate line GIDL may be electrically insulated by a plurality of insulating layers.

[0114] A plurality of vertical transfer transistors (eg, TRg, TR2, TRs1, and TRs2) may be provided in a stepped region (eg, Figure 8 The vertical transfer transistor TRg may be connected between the ground selection line GSL and the ground selection line drive signal line GS. The second vertical transfer transistor TR2 may be connected between the second word line WL2 and the second word line drive signal line SI2. The second vertical transfer transistor TR2 may be connected to the second word line WL2 through a contact CP corresponding thereto.

[0115] The vertical transfer transistor TRg may be connected to the ground selection line GSL through a contact CP corresponding thereto. In some example embodiments, different contacts CP respectively connected to different vertical channels VC may have the same height in the vertical direction VD.

[0116] The vertical channels VC of the vertical transfer transistors (e.g., TRg, TR2, TRs1, and TRs2) may be commonly connected to the gate GT. In some example embodiments, the gate GT commonly connected to the vertical channels VC of the vertical transfer transistors (e.g., TRg, TR2, TRs1, and TRs2) may be at the same level as the GIDL gate line GIDL. In some example embodiments, the vertical channels VC may have the same height in the vertical direction VD.

[0117] In some example embodiments, the first length of the gate GT in the vertical direction VD may be substantially the same as the third length of the GIDL gate line GIDL in the vertical direction VD. In some example embodiments, the first length of the gate GT may be different from the third length of the GIDL gate line GIDL. For example, the first length may be greater than the third length.

[0118] In the memory device 10e, some of the plurality of pass transistors (eg, Fig.13The transmission transistors TRs, TR1 to TRm, TRg and TRgd in the first semiconductor layer 300e can be formed as vertical transmission transistors in the first semiconductor layer 300e, and the other transmission transistors in the transmission transistors can be formed as conventional transmission transistors in the second semiconductor layer 400e. For example, the transmission transistor TRgd connected to the GIDL gate line GIDL can be formed as a conventional transmission transistor in the second semiconductor layer 400e, and the GIDL gate line GIDL among the GIDL gate line GIDL, the ground selection line GSL, the first word line WL1 to the m-th word line WLm, the upper string selection line SSLd and the lower string selection line SSLu and the gate GT are located in the same layer. The GIDL gate line GIDL can be connected to the transmission transistor TRgd through an interconnection including the fourth contact 313, the metal pattern 333 and the bonding pad PD1e included in the first semiconductor layer 300e and the bonding pad PD2e, the contacts 413 and 433 and the metal pattern 423 included in the second semiconductor layer 400e.

[0119] The fourth contact 313 may extend in the vertical direction VD to contact the GIDL gate line GIDL, and may pass through the ground selection line GSL, the first to m-th word lines WL1 to WLm, the upper string selection line SSLd, and the lower string selection line SSLu. The ground selection line GSL, the first to m-th word lines WL1 to WLm, the upper string selection line SSLd, and the lower string selection line SSLu may include an insulating region NT contacting the fourth contact 313.

[0120] In the memory device 10e, the gate GT commonly connected to the plurality of vertical transfer transistors (e.g., TRg, TR2, TRs1, and TRs2) is at the same level as the GIDL gate line GIDL, so the transfer transistor TRgd connected to the GIDL gate line GIDL may be formed in the second semiconductor layer 400e. However, the embodiment is not limited thereto. The transfer transistor TRgd connected to the GIDL gate line GIDL may be formed in the first semiconductor layer 300e as a conventional transistor or a vertical transfer transistor.

[0121] Despite Fig.14 1 shows that only the transfer transistor TRgd is located in the second semiconductor layer 400e among the plurality of transfer transistors, but the memory device 10e is not limited thereto. Two or more transfer transistors may be in the second semiconductor layer 400e. For example, when the length of the gate GT in the vertical direction VD is greater than the length of the GIDL gate line GIDL in the vertical direction VD, the transfer transistors TRgd and TRg may be in the second semiconductor layer 400e.

[0122] Fig.151 is a block diagram of an example in which a memory device according to an example embodiment is applied to a solid state drive (SSD) system 1000. Fig.15 , the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may exchange signals with the host 1100 through a signal connector SIG, and may receive power through a power connector PWR. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. Each of the memory devices 1230, 1240, and 1250 may include a plurality of memory chips MEM, and the memory devices 1230, 1240, and 1250 may be connected to the SSD controller 1210 through channels Ch1 to Chn.

[0123] You can use the reference Figures 1 to 14 Memory devices 1230 , 1240 , and 1250 are implemented with any of the embodiments of the described memory devices.

[0124] Although the present invention has been specifically shown and described with reference to the embodiments of the present invention, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims. The elements and / or features of any embodiment may be combined without departing from the scope of the present invention.

Claims

1. A non-volatile memory device, comprising: a first semiconductor layer including a stepped region and a cell region, the cell region including a memory cell array formed therein; as well as a second semiconductor layer on a first side of the first semiconductor layer, the second semiconductor layer comprising a page buffer connected to the memory cell array, Wherein, the first semiconductor layer comprises: A plurality of word lines are stacked in a vertical direction perpendicular to the first semiconductor layer; a ground select line in a layer above the plurality of word lines; a common source line in a layer above the ground select line; a plurality of vertical pass transistors in the stepped region; and A plurality of driving signal lines are in the same layer as the common source line, wherein the plurality of word lines form a staircase shape in the staircase region, and Each of the plurality of vertical transfer transistors is connected between a corresponding word line among the plurality of word lines and a corresponding drive signal line among the plurality of drive signal lines.

2. The nonvolatile memory device according to claim 1, in, The common source line includes a metal plate, and The plurality of driving signal lines are adjacent to each other in a first horizontal direction perpendicular to the vertical direction, extend in a second horizontal direction perpendicular to the first horizontal direction, and are in the same layer as the metal plate.

3. The nonvolatile memory device according to claim 1, wherein: Each of the plurality of vertical pass transistors includes a gate configured to receive a block selection signal.

4. The nonvolatile memory device according to claim 3, wherein: The gate is in the same layer as the ground selection line.

5. The nonvolatile memory device according to claim 4, wherein: A first length of the gate in the vertical direction is equal to a second length of the ground selection line in the vertical direction.

6. The nonvolatile memory device according to claim 4, wherein: A first length of the gate in the vertical direction is greater than a second length of the ground selection line in the vertical direction.

7. The nonvolatile memory device according to claim 4, wherein: The second semiconductor layer also includes a conventional pass transistor connected to the ground select line.

8. The nonvolatile memory device according to claim 3, in, The first semiconductor layer further includes a gate induced drain leakage (GIDL) gate line between the ground selection line and the common source line, and The gate and the GIDL gate line are in the same layer.

9. The nonvolatile memory device according to claim 8, wherein: The second semiconductor layer also includes a conventional pass transistor connected to the GIDL gate line.

10. The nonvolatile memory device according to claim 1, wherein: The ground selection line includes a different material from the plurality of word lines.

11. A non-volatile memory device comprising: A first semiconductor layer includes a memory cell array, wherein the memory cell array includes a vertical channel structure; as well as a second semiconductor layer on a first side of the first semiconductor layer in a vertical direction perpendicular to the first semiconductor layer, the second semiconductor layer including a page buffer connected to the memory cell array, Wherein, the first semiconductor layer comprises: a plurality of word lines stacked in the vertical direction; a ground select line in a layer above the plurality of word lines; a common source line in a layer above the ground select line; a plurality of vertical pass transistors, each of the plurality of vertical pass transistors including a vertical channel extending in the vertical direction in the step regions of the plurality of word lines; and a plurality of drive signal lines in a layer above the plurality of vertical transfer transistors and in the same layer as the common source line, and Each of the plurality of vertical transfer transistors is connected between a corresponding word line among the plurality of word lines and a corresponding drive signal line among the plurality of drive signal lines.

12. The nonvolatile memory device according to claim 11, in, The vertical channel structure has a first width, and Wherein, the vertical channel has a second width greater than the first width.

13. The nonvolatile memory device according to claim 11, wherein: Heights of vertical channels respectively included in the plurality of vertical pass transistors are equal to each other.

14. The nonvolatile memory device according to claim 11, wherein: With respect to the second semiconductor layer, a bottom level of the vertical channel is higher than a top level of a topmost word line of the plurality of word lines.

15. The nonvolatile memory device according to claim 11, wherein: The first semiconductor layer further includes a dummy word line between the plurality of word lines and the ground selection line.

16. The nonvolatile memory device according to claim 11, in, Each of the plurality of vertical pass transistors further includes a gate configured to receive a block selection signal, and The gate is connected to the transistor in the second semiconductor layer through a first contact and a first bonding pad in the first semiconductor layer and through a second bonding pad and a second contact in the second semiconductor layer.

17. The nonvolatile memory device according to claim 11, in, The first semiconductor layer further includes a plurality of contacts extending in the vertical direction, and Each of the plurality of vertical pass transistors is connected to a corresponding word line through a corresponding contact among the plurality of contacts.

18. The nonvolatile memory device according to claim 17, wherein: The lengths of the plurality of contacts are equal to each other.

19. The nonvolatile memory device according to claim 17, in, Each of the plurality of word lines includes a conductive region and an insulating region, and Each of the plurality of word lines contacts a corresponding contact among the plurality of contacts in the conductive region, and contacts other contacts among the plurality of contacts except the corresponding contact in the insulating region.

20. A non-volatile memory device comprising: a first semiconductor layer; as well as a second semiconductor layer on a first side of the first semiconductor layer in a vertical direction perpendicular to the first semiconductor layer, Wherein, the second semiconductor layer includes a transistor, Wherein, the first semiconductor layer comprises: a plurality of word lines stacked in the vertical direction; a ground select line on the plurality of word lines; a common source line on said ground select line; a plurality of vertical pass transistors in the step regions of the plurality of word lines, wherein the plurality of vertical pass transistors are respectively connected to the plurality of word lines; a plurality of first contacts extending in the vertical direction, the plurality of first contacts connecting a vertical pass transistor of the plurality of vertical pass transistors to a word line of the plurality of word lines and having equal lengths in the vertical direction; and A plurality of driving signal lines are in the same layer as the common source line, wherein each of the plurality of vertical transfer transistors is connected between a corresponding drive signal line among the plurality of drive signal lines and a corresponding word line among the plurality of word lines, and includes a gate configured to receive a block selection signal, and The gate is in the same layer as the ground selection line and is connected to the transistor in the second semiconductor layer through a second contact and a first bonding pad formed in the first semiconductor layer and through a second bonding pad and a third contact formed in the second semiconductor layer.

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