Display panel

Abstract

A display panel includes two or more gate layers including a plurality of gate patterns extending in a first direction, and one or more source-drain layers including a plurality of source-drain patterns extending in a second direction intersecting the first direction. The gate patterns of the two or more gate layers are curled or bent along a hole-surrounding region corresponding to a periphery of a hole in an effective region. The source-drain patterns of the one or more source-drain layers are curled or bent along the hole-surrounding region. In the hole-surrounding region, the gate patterns of at least one of the two or more gate layers overlap the source-drain patterns of at least one of the one or more source-drain layers in a thickness direction of the display panel.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present inventive concept relate to a display panel and a display apparatus including the same. More particularly, example embodiments of the present inventive concept relate to a display panel including a hole and a display apparatus including the same. BACKGROUND

[0002] The display panel has a hole having a disposition relationship with other elements such as a camera. Gate lines and data lines disposed adjacent to a hole surrounding area can be curled or bent to bypass the hole. The gate lines and the data lines can create a dead zone near the hole surrounding area. SUMMARY

[0003] Aspects of example embodiments of the present inventive concept relate to a display panel capable of reducing a dead zone adjacent to a hole surrounding area of the display panel.

[0004] Aspects of example embodiments of the present inventive concept relate to a display apparatus including the same.

[0005] In example embodiments of a display panel according to the present inventive concept, the display panel includes two or more gate layers including a plurality of gate patterns extending in a first direction, and one or more source-drain layers including a plurality of source-drain patterns extending in a second direction crossing the first direction. The gate patterns of the two or more gate layers are curled or bent along a hole surrounding area corresponding to a periphery of a hole in an active area. The source-drain patterns of the one or more source-drain layers are curled or bent along the hole surrounding area. In the hole surrounding area, the gate patterns of at least one gate layer of the two or more gate layers overlap the source-drain patterns of at least one source-drain layer of the one or more source-drain layers in a thickness direction of the display panel.

[0006] In example embodiments, the display panel can further include a first gate insulating layer, a second gate insulating layer, and a first passivation layer, and the two or more gate layers can include a first gate layer, a second gate layer, and a third gate layer. The first gate layer is on the first gate insulating layer, the second gate insulating layer is on the first gate layer, the second gate layer is on the second gate insulating layer, the first passivation layer is on the second gate layer, and the third gate layer is on the first passivation layer.

[0007] In example embodiments, in a normal area that is not the hole surrounding area, the second gate layer can overlap the third gate layer in the thickness direction. In the normal area, the first gate layer can not overlap the second gate layer and the third gate layer in the thickness direction.

[0008] In example embodiments, in the hole surrounding area, the first gate layer, the second gate layer, and the third gate layer can overlap each other in the thickness direction.

[0009] In an example embodiment, the display panel can further include an organic insulating layer in the hole surrounding area and between the second gate insulating layer and the second gate layer.

[0010] In an example embodiment, in the hole surrounding area, the second gate layer can overlap the third gate layer in a thickness direction. In the hole surrounding area, the first gate layer can not overlap the second gate layer and the third gate layer in the thickness direction.

[0011] In an example embodiment, the display panel can further include a pixel including a P-type transistor and an N-type transistor.

[0012] In an example embodiment, the first gate layer can include a P-type gate line configured to transmit a P-type gate signal to the P-type transistor. The second gate layer can include a back gate electrode of the P-type transistor or the N-type transistor and a connection line of the back gate electrode. The third gate layer can include an N-type gate line configured to transmit an N-type gate signal to the N-type transistor.

[0013] In an example embodiment, the display panel further includes a first organic insulating layer and a second organic insulating layer, and the one or more source-drain layers can include a first source-drain layer and a second source-drain layer. The first organic insulating layer is on the first source-drain layer, the second source-drain layer is on the first organic insulating layer, and the second organic insulating layer is on the second source-drain layer.

[0014] In an example embodiment, in a normal area that is not the hole surrounding area, the first source-drain layer can not overlap the second source-drain layer in a thickness direction.

[0015] In an example embodiment, in the hole surrounding area, the first source-drain layer can overlap the second source-drain layer in a thickness direction.

[0016] In an example embodiment, the display panel can further include a plurality of pixels in a matrix form. The pixels in a pixel column among the plurality of pixels can be alternately connected to a first data line and a second data line.

[0017] In an example embodiment, the first source-drain layer can include the first data line. The second source-drain layer can include the second data line.

[0018] In an example embodiment, the display panel can include a first gate layer on a first gate insulating layer, a second gate insulating layer on the first gate layer, a second gate layer on the second gate insulating layer, a first passivation layer on the second gate layer, a third gate layer on the first passivation layer, a second passivation layer on the third gate layer, a first source-drain layer on the second passivation layer, a first organic insulating layer on the first source-drain layer, a second source-drain layer on the first organic insulating layer, and a second organic insulating layer on the second source-drain layer.

[0019] In an example embodiment, in the hole-encircling area, the first gate layer, the second gate layer, the third gate layer, the first source-drain layer, and the second source-drain layer can overlap each other in a thickness direction.

[0020] In an example embodiment, the display panel can further include a third organic insulating layer in the hole-encircling area and between the second gate insulating layer and the second gate layer.

[0021] In an example embodiment, in the hole-encircling area, the second gate layer, the third gate layer, the first source-drain layer, and the second source-drain layer can overlap each other in a thickness direction. In the hole-encircling area, the first gate layer can not overlap the second gate layer in the thickness direction.

[0022] In an example embodiment, the display panel can include a first gate layer on a first gate insulating layer, a second gate insulating layer on the first gate layer, a second gate layer on the second gate insulating layer, a first passivation layer on the second gate layer, a third gate layer on the first passivation layer, a second passivation layer on the third gate layer, a source-drain layer on the second passivation layer, and an organic insulating layer on the source-drain layer.

[0023] In an example embodiment, in the hole-encircling area, the first gate layer, the second gate layer, the third gate layer, and the source-drain layer can overlap each other in a thickness direction.

[0024] In an example embodiment of a display device according to the inventive concept, the display device includes a display panel, a gate driver, a data driver, and an emission driver. The display panel includes two or more gate layers including a plurality of gate patterns extending in a first direction, one or more source-drain layers including a plurality of source-drain patterns extending in a second direction crossing the first direction, and a plurality of pixels connected to the plurality of gate patterns and the plurality of source-drain patterns. The gate driver is configured to provide a gate signal to the display panel. The data driver is configured to provide a data voltage to the display panel. The emission driver is configured to provide an emission signal to the display panel. The gate patterns of the two or more gate layers are crimped or bent along a hole-encircling area corresponding to a periphery of a hole in an active area of the display panel. The source-drain patterns of the one or more source-drain layers are crimped or bent along the hole-encircling area. In the hole-encircling area, the gate patterns of at least one of the two or more gate layers overlap the source-drain patterns of at least one of the one or more source-drain layers in a thickness direction of the display panel.

[0025] According to embodiments of a display panel and a display device including the same, when a hole is formed in an active area of the display panel and a pattern on a gate layer and a pattern on a source-drain layer bypass the hole at a hole-encircling area, the pattern on the gate layer and the pattern on the source-drain layer overlap each other in a thickness direction, so that a dead zone adjacent to the hole-encircling area can be reduced. Attached Figure Description

[0026] The above and other features and aspects of the inventive concept will become more apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0027] Figure 1 This is a block diagram illustrating an exemplary embodiment of a display device according to a concept of the present invention;

[0028] Figure 2 It is a diagram. Figure 1 The circuit diagram of the pixels of the display panel;

[0029] Figure 3 The diagram is applied to Figure 2 Timing diagram of the input signal of the pixel;

[0030] Figure 4 It is a diagram. Figure 1 A conceptual diagram of the pixel structure of a display panel;

[0031] Figure 5 It is a diagram. Figure 1 A plan view of the holes, the area around the holes, and the normal area of ​​the display panel;

[0032] Figure 6 It is a diagram. Figure 5 Plan view of the aperture, gate layer, and source-drain layer;

[0033] Figure 7 It is shown in the diagram along Figure 6 A cross-sectional view of the display panel taken by line A-A';

[0034] Figure 8 It is shown in the diagram along Figure 6 A cross-sectional view of the display panel taken by line B-B';

[0035] Figure 9 It is shown in the diagram along Figure 6 A cross-sectional view of the display panel taken by line C-C';

[0036] Figure 10 This is a plan view illustrating a hole, a region surrounding the hole, and a normal region of a display panel according to an exemplary embodiment of the present invention.

[0037] Figure 11 It is shown in the diagram along Figure 10 A cross-sectional view of the display panel taken by line C-C';

[0038] Figure 12 This is a cross-sectional view illustrating the area surrounding the holes in a display panel according to an exemplary embodiment of the present invention;

[0039] Figure 13is a conceptual diagram illustrating a pixel structure of a display panel according to an example embodiment of the present inventive concept; and

[0040] Figure 14 is a cross-sectional view illustrating a hole surrounding area of a display panel. Figure 13 DETAILED DESCRIPTION

[0041] Hereinafter, the present inventive concept will be explained in detail with reference to the accompanying drawings.

[0042] Figure 1 is a block diagram illustrating a display apparatus according to an example embodiment of the present inventive concept.

[0043] Referring to Figure 1 , the display apparatus includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0044] The display panel 100 has a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0045] The display panel 100 includes a plurality of gate lines GWPL, GWNL, GIL, and GBL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels electrically connected to the gate lines GWPL, GWNL, GIL, and GBL, the data lines DL, and the emission lines EL. The gate lines GWPL, GWNL, GIL, and GBL can extend in a first direction D1, the data lines DL can extend in a second direction D2 crossing the first direction D1, and the emission lines EL can extend in the first direction D1.

[0046] The driving controller 200 receives input image data IMG and input control signals CONT from an external apparatus. For example, the input image data IMG can include red image data, green image data, and blue image data. The input image data IMG can include white image data. The input image data IMG can include magenta image data, cyan image data, and yellow image data. The input control signals CONT can include a main clock signal and a data enable signal. The input control signals CONT can further include a vertical synchronization signal and a horizontal synchronization signal.

[0047] The driving controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signals CONT.

[0048] ​The drive controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 can include a vertical start signal and a gate clock signal.

[0049] The drive controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 can include a horizontal start signal and a load signal.

[0050] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0051] The drive controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0052] The drive controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600.

[0053] The gate driver 300 generates gate signals for driving the gate lines GWPL, GWNL, GIL, and GBL in response to the first control signal CONT1 received from the drive controller 200. The gate driver 300 can sequentially output the gate signals to the gate lines GWPL, GWNL, GIL, and GBL.

[0054] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0055] In an example embodiment, the gamma reference voltage generator 400 can be arranged in the drive controller 200 or in the data driver 500.

[0056] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage having an analog type using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0057] The emission driver 600 generates an emission signal for driving the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 can output the emission signal to the emission line EL.

[0058] Figure 2 is a circuit diagram of a pixel in the display panel 100 illustrated in Figure 1 . Figure 3 is a timing chart illustrating input signals applied to a pixel of Figure 2 .

[0059] Referring to Figures 1 to 3 , the display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0060] The pixel receives the data write gate signals GWP and GWN, the data initialization gate signal GI, the organic light emitting element initialization gate signal GB, the data voltage VDATA, and the emission signal EM, and the organic light emitting element OLED of the pixel emits light corresponding to a level of the data voltage VDATA to display an image (e.g., a portion of an image).

[0061] In the illustrated example embodiment, the pixel can include a first type of switching element and a second type of switching element different from the first type. In one or more example embodiments, the first type of switching element can be a polysilicon thin film transistor, and the second type of switching element can be an oxide thin film transistor. In one or more example embodiments, the first type of switching element can be a low temperature polysilicon (LTPS) thin film transistor, and the second type of switching element can be an oxide thin film transistor. In one or more example embodiments, the first type of switching element can be a P-type transistor, and the second type of switching element can be an N-type transistor. Although different types of transistors are described with respect to the illustrated example embodiment, any suitable types can be used such that the pixel includes a first type of switching element and a second type of switching element different from the first type.

[0062] In one or more example embodiments, the data write gate signals GWP and GWN can include a first data write gate signal GWP and a second data write gate signal GWN. The first data write gate signal GWP can be applied to the P-type transistor such that the first data write gate signal GWP has a low level of the start signal corresponding to the data write timing. The second data write gate signal GWN can be applied to the N-type transistor such that the second data write gate signal GWN has a high level of the start signal corresponding to the data write timing.

[0063] At least one of the pixels can include the first to seventh pixel switching elements T1 to T7 (i.e., the first pixel switching element T1, the second pixel switching element T2, the third pixel switching element T3, the fourth pixel switching element T4, the fifth pixel switching element T5, the sixth pixel switching element T6, and the seventh pixel switching element T7), the storage capacitor CST, and the organic light emitting element OLED.

[0064] The first pixel switching element T1 includes a control electrode connected to the first node N1, an input electrode connected to the second node N2, and an output electrode connected to the third node N3.

[0065] In one or more example embodiments, the first pixel switching element T1 can be a polycrystalline silicon thin film transistor. In one or more example embodiments, the first pixel switching element T1 can be a P-type thin film transistor. The control electrode of the first pixel switching element T1 can be a gate electrode, the input electrode of the first pixel switching element T1 can be a source electrode, and the output electrode of the first pixel switching element T1 can be a drain electrode.

[0066] The second pixel switching element T2 includes a control electrode to which the first data write gate signal GWP is applied, an input electrode to which the data voltage VDATA is applied, and an output electrode connected to the second node N2.

[0067] In one or more example embodiments, the second pixel switching element T2 can be a polycrystalline silicon thin film transistor. In one or more example embodiments, the second pixel switching element T2 can be a P-type thin film transistor. The control electrode of the second pixel switching element T2 can be a gate electrode, the input electrode of the second pixel switching element T2 can be a source electrode, and the output electrode of the second pixel switching element T2 can be a drain electrode.

[0068] The third pixel switching element T3 includes a control electrode to which the second data write gate signal GWN is applied, an input electrode connected to the first node N1, and an output electrode connected to the third node N3.

[0069] In one or more example embodiments, the third pixel switching element T3 can be an oxide thin film transistor. In one or more example embodiments, the third pixel switching element T3 can be an N-type thin film transistor. The control electrode of the third pixel switching element T3 can be a gate electrode, the input electrode of the third pixel switching element T3 can be a source electrode, and the output electrode of the third pixel switching element T3 can be a drain electrode.

[0070] The fourth pixel switching element T4 includes a control electrode to which a data initialization gate signal GI is applied, an input electrode to which an initialization voltage VI is applied, and an output electrode connected to the first node N1.

[0071] In one or more example embodiments, the fourth pixel switching element T4 can be an oxide thin film transistor. In one or more example embodiments, the fourth pixel switching element T4 can be an N-type thin film transistor. The control electrode of the fourth pixel switching element T4 can be a gate electrode, the input electrode of the fourth pixel switching element T4 can be a source electrode, and the output electrode of the fourth pixel switching element T4 can be a drain electrode.

[0072] The fifth pixel switching element T5 includes a control electrode to which an emission signal EM is applied, an input electrode to which a high power voltage ELVDD is applied, and an output electrode connected to the second node N2.

[0073] In one or more example embodiments, the fifth pixel switching element T5 can be a polysilicon thin film transistor. In one or more example embodiments, the fifth pixel switching element T5 can be a P-type thin film transistor. The control electrode of the fifth pixel switching element T5 can be a gate electrode, the input electrode of the fifth pixel switching element T5 can be a source electrode, and the output electrode of the fifth pixel switching element T5 can be a drain electrode.

[0074] The sixth pixel switching element T6 includes a control electrode to which an emission signal EM is applied, an input electrode connected to the third node N3, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

[0075] In one or more example embodiments, the sixth pixel switching element T6 can be a polysilicon thin film transistor. In one or more example embodiments, the sixth pixel switching element T6 can be a P-type thin film transistor. The control electrode of the sixth pixel switching element T6 can be a gate electrode, the input electrode of the sixth pixel switching element T6 can be a source electrode, and the output electrode of the sixth pixel switching element T6 can be a drain electrode.

[0076] The seventh pixel switching element T7 includes a control electrode to which an organic light emitting element initialization gate signal GB is applied, an input electrode to which an initialization voltage VI is applied, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

[0077] In one or more example embodiments, the seventh pixel switching element T7 may be an oxide thin-film transistor. In one or more example embodiments, the seventh pixel switching element T7 may be an N-type thin-film transistor. The control electrode of the seventh pixel switching element T7 may be a gate electrode, the input electrode of the seventh pixel switching element T7 may be a source electrode, and the output electrode of the seventh pixel switching element T7 may be a drain electrode.

[0078] Although the seventh pixel switching element T7 is an oxide thin-film transistor in the illustrated example embodiment, the inventive concept is not limited thereto. For example, the seventh pixel switching element T7 could be a polysilicon thin-film transistor. Although the seventh pixel switching element T7 is an N-type thin-film transistor in the illustrated example embodiment, the inventive concept is not limited thereto. For example, the seventh pixel switching element T7 could be a P-type thin-film transistor.

[0079] The storage capacitor CST includes a first electrode to which a high electrical voltage ELVDD is applied and a second electrode connected to a first node N1.

[0080] Organic light-emitting elements (OLEDs) include an anode electrode and a cathode electrode to which a low electrical voltage (ELVSS) is applied.

[0081] exist Figure 3 During the first duration DU1, the first node N1 and the storage capacitor CST are initialized in response to the data initialization gate signal GI (e.g., the data initialization gate signal GI is applied high to the control electrode of the fourth pixel switching element T4). During the second duration DU2, the threshold voltage |VTH| of the first pixel switching element T1 is compensated in response to the first data write gate signal GWP and the second data write gate signal GWN (e.g., the first data write gate signal GWP is applied low to the control electrode of the second pixel switching element T2, and the second data write gate signal GWN is applied high to the control electrode of the third pixel switching element T3), and the data voltage VDATA compensated for the threshold voltage |VTH| is written to the first node N1. During the third duration DU3, the anode electrode of the organic light-emitting element OLED is initialized in response to the organic light-emitting element initialization gate signal GB (e.g., the organic light-emitting element initialization gate signal GB is applied high to the control electrode of the seventh pixel switching element T7). During the fourth duration DU4, the organic light-emitting element OLED emits light in response to the emission signal EM (e.g., the emission signal EM is applied at a low level to the control electrode of the fifth pixel switching element T5 and the control electrode of the sixth pixel switching element T6), causing the display panel 100 to display an image.

[0082] Although, in the illustrated example embodiment, the emission-off duration of the emission signal EM corresponds to the first to third durations (the first duration DU1, the second duration DU2, and the third duration DU3), the present inventive concept is not limited thereto. The emission-off duration of the emission signal EM can be set to include the second duration DU2. In one or more example embodiments, the emission-off duration of the emission signal EM can be longer than the sum of the first to third durations DU1, DU2, and DU3.

[0083] During the first duration DU1, the data initialization gate signal GI can have an active level. For example, the active level of the data initialization gate signal GI can be a high level. When the data initialization gate signal GI has the active level, the fourth pixel switching element T4 is turned on so that the initialization voltage VI can be applied to the first node N1. The data initialization gate signal GI[N] of the current stage can be generated based on the scan signal SCAN[N-1] of the previous stage.

[0084] During the second duration DU2, the first data write gate signal GWP and the second data write gate signal GWN can have active levels. For example, the active level of the first data write gate signal GWP can be a low level, and the active level of the second data write gate signal GWN can be a high level. When the first data write gate signal GWP and the second data write gate signal GWN have the active levels, the second pixel switching element T2 and the third pixel switching element T3 are turned on. In addition, the first pixel switching element T1 is turned on in response to the initialization voltage VI. The first data write gate signal GWP[N] of the current stage can be generated based on the scan signal SCAN[N] of the current stage. The second data write gate signal GWN[N] of the current stage can be generated based on the scan signal SCAN[N] of the current stage.

[0085] A voltage generated by subtracting the absolute value |VTH| of the threshold voltage of the first pixel switching element T1 from the data voltage VDATA can be charged at the first node N1 along a path generated by the first to third pixel switching elements (i.e., the first pixel switching element T1, the second pixel switching element T2, and the third pixel switching element T3).

[0086] During the third duration DU3, the organic light emitting element initialization gate signal GB can have an active level. For example, the active level of the organic light emitting element initialization gate signal GB can be a high level. When the organic light emitting element initialization gate signal GB has the active level, the seventh pixel switching element T7 is turned on so that the initialization voltage VI can be applied to the anode electrode of the organic light emitting element OLED. The organic light emitting element initialization gate signal GB[N] of the current stage can be generated based on the scan signal SCAN[N+1] of the next stage.

[0087] During the fourth duration DU4, the emission signal EM can have an active level. The active level of the emission signal EM can be a low level. When the emission signal EM has the active level, the fifth pixel switching element T5 and the sixth pixel switching element T6 are turned on. In addition, the first pixel switching element T1 is turned on by the data voltage VDATA.

[0088] A drive current flows through the fifth pixel switching element T5, the first pixel switching element T1, and the sixth pixel switching element T6 to drive the organic light emitting element OLED. The strength of the drive current can be determined by the level of the data voltage VDATA. The brightness of the organic light emitting element OLED is determined by the strength (e.g., magnitude) of the drive current applied to the organic light emitting element OLED.

[0089] In the illustrated example embodiment, when the image displayed on the display panel 100 is a static image or the display panel 100 is operated in an always-on mode, the driving frequency of the display panel 100 can be reduced to reduce power consumption. When all of the switching elements of the pixels of the display panel 100 are polycrystalline thin film transistors, flicker can occur due to the leakage current of the pixel switching elements in the low frequency driving mode. Therefore, some of the pixel switching elements can be designed using oxide thin film transistors. In the illustrated example embodiment, the third pixel switching element T3, the fourth pixel switching element T4, and the seventh pixel switching element T7 can be oxide thin film transistors. The first pixel switching element T1, the second pixel switching element T2, the fifth pixel switching element T5, and the sixth pixel switching element T6 can be polycrystalline thin film transistors. Therefore, in the illustrated embodiment, flicker can be reduced or prevented in the low frequency driving mode.

[0090] Although in the illustrated example embodiment, the second data write gate signal GWN is applied to the control electrode of the third pixel switching element T3 and the organic light emitting element initialization gate signal GB is applied to the control electrode of the seventh pixel switching element T7, the inventive concepts are not limited thereto. The control electrode of the third pixel switching element T3 can be connected to the control electrode of the seventh pixel switching element T7 and the second data write gate signal GWN can be applied to both the control electrode of the third pixel switching element T3 and the control electrode of the seventh pixel switching element T7. Therefore, in one or more example embodiments, the separate organic light emitting element initialization gate signal GB can be omitted.

[0091] Figure 4 is a conceptual diagram of a pixel structure of the display panel 100. Figure 1

[0092] Referring to Figures 1 to 4 , the display panel 100 includes a plurality of pixels arranged in a matrix form.​

[0093] In the illustrated example embodiment, the pixels in a pixel column can be alternately connected to adjacent data lines (e.g., two adjacent data lines). For example, the pixels in the pixel column can be alternately connected to odd data lines and even data lines.

[0094] For example, the first pixel P11, the second pixel P21, the third pixel P31, and the fourth pixel P41 are arranged in the first pixel column of the display panel 100 in the order of succession, where the first pixel P11 and the third pixel P31 among the pixels are connected to the first data line DL1 (odd data line), and the second pixel P21 and the fourth pixel P41 among the pixels are connected to the second data line DL2 (even data line). In one or more example embodiments, the first pixel P12 and the third pixel P32 among the pixels arranged in the second pixel column of the display panel 100 can be connected to the third data line DL3, and the second pixel P22 and the fourth pixel P42 among the pixels arranged in the second pixel column can be connected to the fourth data line DL4. In one or more example embodiments, the first pixel P13 and the third pixel P33 among the pixels arranged in the third pixel column of the display panel 100 can be connected to the fifth data line DL5, and the second pixel P23 and the fourth pixel P43 among the pixels arranged in the third pixel column can be connected to the sixth data line DL6. In one or more example embodiments, the first pixel P14 and the third pixel P34 among the pixels arranged in the fourth pixel column of the display panel 100 can be connected to the seventh data line DL7, and the second pixel P24 and the fourth pixel P44 among the pixels arranged in the fourth pixel column can be connected to the eighth data line DL8.

[0095] Figure 5 is a plan view of the hole HL, the hole surrounding area, and the normal area of the display panel 100 of Figure 1 . Figure 6 is a plan view of the hole HL, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 of Figure 5 .

[0096] Referring to Figures 1 to 6 , the display panel 100 includes an active area AA that displays an image and a peripheral area PA surrounding the active area AA.

[0097] The hole HL can be disposed in the active area AA. The hole HL can be formed to correspond to a position of a camera module of the display device. In one or more example embodiments, the hole HL can overlap the camera module of the display device. The hole HL can refer to a hole physically formed in the base substrate of the display panel 100. In one or more example embodiments, only a transparent element is disposed in the hole HL.

[0098] The display panel 100 can include a plurality of gate layers GAT1, GAT2, and GAT3 including gate patterns extending in the first direction D1 and a plurality of source-drain layers SD1 and SD2 including source-drain patterns extending in the second direction D2.

[0099] The gate patterns of the gate layers GAT1, GAT2, and GAT3 that do not pass through the area in which the hole HL is formed (e.g., the area including the hole HL) extend straight in the first direction D1. In one or more example embodiments, when viewed in a plan view as shown in FIG. 1B, the gate patterns of the second gate layer GAT2 and the third gate layer GAT3 that do not pass through the area in which the hole HL is formed do not overlap. Figure 6 The source-drain patterns of the source-drain layers SD1 and SD2 that do not pass through the area in which the hole HL is formed (e.g., the area including the hole HL) extend straight in the second direction D2. In one or more example embodiments, the source-drain patterns of the source-drain layers SD1 and SD2 that pass through the area in which the hole HL is formed (i.e., through the area including the hole HL and the area surrounding the hole HL) extend straight in the second direction D2 in a normal area in which the hole HL is not formed, and the source-drain patterns of the source-drain layers SD1 and SD2 are curled or bent along the outer periphery (e.g., the outer circumference) of the hole HL in the hole surrounding area (i.e., the area surrounding the hole HL).

[0100] In one or more example embodiments, when viewed from the direction of the first direction D1,

[0101] Figure 6 ​When viewed in the plan view shown in the embodiment, the first source-drain layer SD1 and the second source-drain layer SD2 can extend in the normal region along the second direction D2 and be alternately arranged along the first direction D1. In one or more example embodiments, when viewed from... Figure 6 When viewed in the plan view shown in the embodiment, the first gate layer GAT1 and the third gate layer GAT3 can extend in the normal region along the first direction D1 and be alternately arranged along the second direction D2. In one or more example embodiments, when viewed from... Figure 6 When viewed in the plan view shown in the embodiment, the first gate layer GAT1 and the second gate layer GAT2 can extend in the normal region in the first direction D1 and be alternately arranged in the second direction D2.

[0102] The portion of the gate patterns of gate layers GAT1, GAT2, and GAT3, or the source-drain patterns of source-drain layers SD1 and SD2, that is curled or bent due to the via HL, can be defined as the area around the via.

[0103] Figure 7 It is shown in the diagram along Figure 6 The cross-sectional view of the display panel 100 taken by line A-A'. Figure 8 It is shown in the diagram along Figure 6 The cross-sectional view of the display panel 100 taken by line B-B'. Figure 9 It is shown in the diagram along Figure 6 The cross-sectional view of the display panel 100 taken by line C-C'.

[0104] Line A-A' represents the cross-sectional structure of source-drain layers SD1 and SD2 in the normal region where the via HL is not formed. Line B-B' represents the cross-sectional structure of gate layers GAT1, GAT2, and GAT3 in the normal region where the via HL is not formed. Line C-C' represents the cross-sectional structure of gate layers GAT1, GAT2, and GAT3, and source-drain layers SD1 and SD2 in the region surrounding the via (i.e., the region around the via HL).

[0105] refer to Figures 1 to 9The display panel 100 includes a base layer PI, a barrier layer BR disposed on the base layer PI, a first gate insulating layer GI1 disposed on the barrier layer BR, a first gate layer GAT1 disposed on the first gate insulating layer GI1, a second gate insulating layer GI2 disposed on the first gate layer GAT1 and / or the first gate insulating layer GI1, a second gate layer GAT2 disposed on the second gate insulating layer GI2, a first passivation layer ILD1 disposed on the second gate layer GAT2 and / or the second gate insulating layer GI2, a third gate layer GAT3 disposed on the first passivation layer ILD1, a second passivation layer ILD2 disposed on the third gate layer GAT3 and / or the first passivation layer ILD1, a first source-drain layer SD1 disposed on the second passivation layer ILD2, a first organic insulating layer VIA1 disposed on the first source-drain layer SD1 and / or the second passivation layer ILD2, a second source-drain layer SD2 disposed on the first organic insulating layer VIA1, and a second organic insulating layer VIA2 disposed on the second source-drain layer SD2 and / or the first organic insulating layer VIA1.

[0106] The base layer PI can include polyimide. The barrier layer BR can include an inorganic material. The thickness of the barrier layer BR can be between about 800 nm and about 900 nm.

[0107] The first gate insulating layer GI1 and the second gate insulating layer GI2 can include an inorganic material. The thickness of the first gate insulating layer GI1 can be about 150 nm. The thickness of the second gate insulating layer GI2 can be about 150 nm.

[0108] The first passivation layer ILD1 and the second passivation layer ILD2 can include an inorganic material. The thickness of the first passivation layer ILD1 and the thickness of the second passivation layer ILD2 can be greater than the thickness of the first gate insulating layer GI1 and the thickness of the second gate insulating layer GI2. The thickness of the first passivation layer ILD1 can be between about 400 nm and about 500 nm. The thickness of the second passivation layer ILD2 can be between about 400 nm and about 500 nm.

[0109] The first organic insulating layer VIA1 and the second organic insulating layer VIA2 can include an organic insulating material. The thickness of the first organic insulating layer VIA1 and the thickness of the second organic insulating layer VIA2 can be greater than the thickness of the first gate insulating layer GI1 and the thickness of the second gate insulating layer GI2. The thickness of the first organic insulating layer VIA1 and the thickness of the second organic insulating layer VIA2 can be greater than the thickness of the first passivation layer ILD1 and the thickness of the second passivation layer ILD2. The thickness of the first organic insulating layer VIA1 can be between about 1.5 μm and about 2 μm. The thickness of the second organic insulating layer VIA2 can be between about 1.5 μm and about 2 μm.

[0110] In an example embodiment, the first passivation layer ILD1 can be replaced by a third gate insulating layer. In this document, the third gate insulating layer may comprise an inorganic material. The thickness of the third gate insulating layer may be approximately 150 nm.

[0111] like Figure 7 As shown, in the normal region, the first source-drain layer SD1 and the second source-drain layer SD2 may not overlap in the thickness direction.

[0112] The first source-drain layer SD1 may include Figure 4 The pixel structure includes odd-numbered data lines DL1, DL3, DL5, and DL7. The second source-drain layer SD2 may include... Figure 4 The even-numbered data lines DL2, DL4, DL6, and DL8 in the pixel structure. In the normal region, the odd-numbered data lines DL1, DL3, DL5, and DL7 can not overlap with the even-numbered data lines DL2, DL4, DL6, and DL8, so that the first source-drain layer SD1 and the second source-drain layer SD2 can not overlap in the thickness direction in the normal region.

[0113] On the contrary, such as Figure 9 As shown, in the region surrounding the aperture, the first source-drain layer SD1 and the second source-drain layer SD2 may overlap in the thickness direction. In the region surrounding the aperture, the first source-drain layer SD1 and the second source-drain layer SD2 are not connected to pixels. According to one or more example embodiments, the patterns on the first source-drain layer SD1 and the second source-drain layer SD2 are curled or bent in the region surrounding the aperture to bypass the aperture HL.

[0114] In the region surrounding the aperture, the first source-drain layer SD1 and the second source-drain layer SD2 can overlap in the thickness direction, thereby reducing the dead zone caused by (or defined by) the aperture HL.

[0115] The horizontal spacing of adjacent data lines on the first source-drain layer SD1 in the area surrounding the via can be smaller than the horizontal spacing of adjacent data lines on the first source-drain layer SD1 in the normal area. Similarly, the horizontal spacing of adjacent data lines on the second source-drain layer SD2 in the area surrounding the via can be smaller than the horizontal spacing of adjacent data lines on the second source-drain layer SD2 in the normal area. Therefore, the dead zone caused by the via HL can be further reduced in the area surrounding the via.

[0116] like Figure 8 As shown, in the normal region, the second gate layer GAT2 and the third gate layer GAT3 can overlap in the thickness direction, and in the normal region, the first gate layer GAT1 can not overlap with the second gate layer GAT2 and the third gate layer GAT3 in the thickness direction.

[0117] The first gate layer GAT1 may include outputting the P-type gate signal GWP to...Figure 2 P-type gate lines GWPL of the P-type transistors. The second gate layer GAT2 can include back gate electrodes of the P-type transistors or the N-type transistors and connection lines of the back gate electrodes. The third gate layer GAT3 can include N-type gate lines GWNL of the N-type transistors outputting the N-type gate signal GWN to the N-type transistors. Figure 2

[0118] In the normal region, the first gate layer GAT1 and the second gate layer GAT2 can output gate signals having different waveforms, and thus it can be desirable that the first gate layer GAT1 and the second gate layer GAT2 can not overlap in the thickness direction to prevent or reduce coupling of the signals. In other words, the first gate layer GAT1 and the second gate layer GAT2 can not overlap in the thickness direction to prevent or reduce the possibility of coupling of the gate signals.

[0119] On the contrary, as shown in FIG. 1B, in the hole surrounding region, the first gate layer GAT1, the second gate layer GAT2, and the third gate layer GAT3 can overlap with each other in the thickness direction. In the hole surrounding region, the patterns on the first gate layer GAT1, the second gate layer GAT2, and the third gate layer GAT3 are curled or bent to bypass the hole HL. Figure 9

[0120] In the hole surrounding region, the first gate layer GAT1, the second gate layer GAT2, and the third gate layer GAT3 can overlap with each other in the thickness direction, so that a dead zone due to the hole HL can be reduced.

[0121] A horizontal interval of adjacent gate lines on the first gate layer GAT1 in the hole surrounding region can be smaller than a horizontal interval of adjacent gate lines on the first gate layer GAT1 in the normal region. A horizontal interval of adjacent connection lines of the back gate electrodes on the second gate layer GAT2 in the hole surrounding region can be smaller than a horizontal interval of adjacent connection lines of the back gate electrodes on the second gate layer GAT2 in the normal region. A horizontal interval of adjacent gate lines on the third gate layer GAT3 in the hole surrounding region can be smaller than a horizontal interval of adjacent gate lines on the third gate layer GAT3 in the normal region. Thus, a dead zone due to the hole HL can be further reduced in the hole surrounding region.

[0122] In addition, in the example embodiment shown, in the hole surrounding region, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 can overlap with each other in the thickness direction. Thus, a dead zone due to the hole HL can be further reduced in the hole surrounding region.

[0123] Although as shown in FIG. 1B, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 can overlap with each other in the thickness direction in the hole surrounding region, the present disclosure is not limited thereto. For example, as shown in FIG. 1C, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 can not overlap with each other in the thickness direction in the hole surrounding region. Figure 9 ​​As illustrated in FIG. 1, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 can overlap each other in the thickness direction in the hole surrounding area to reduce a dead zone due to the hole HL, but in one or more example embodiments, one or more of the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 can not overlap the other layers.

[0124] According to the illustrated example embodiment, when the hole HL is formed in the active area AA of the display panel 100, and the patterns on the gate layers GAT1, GAT2, and GAT3 and the patterns on the source-drain layers SD1 and SD2 bypass the hole HL at the hole surrounding area, the patterns on the gate layers GAT1, GAT2, and GAT3 and the patterns on the source-drain layers SD1 and SD2 overlap each other in the thickness direction, so that a dead zone adjacent to the hole surrounding area can be reduced.

[0125] Figure 10 is a plan view illustrating a hole, a hole surrounding area, and a normal area of a display panel according to an example embodiment of the present inventive concept. Figure 11 is a cross-sectional view of the display panel taken along Figure 10 line C-C’.

[0126] The display panel according to the illustrated example embodiment and a display device including the same are substantially the same as the display panel and the display device of the previous example embodiment described with reference to Figures 1 to 9 , except for the layer structure of the display panel in the hole surrounding area. Thus, the same reference numerals will be used to refer to parts that are the same as or similar to those described in the previous example embodiment of Figures 1 to 9 , and any repetitive or redundant description regarding the above elements can be omitted.

[0127] With reference to Figures 1 to 5 , Figure 7 , Figure 8 , Figure 10 and Figure 11 , the display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0128] The display panel 100 includes an active area AA to display an image and a peripheral area PA surrounding the active area AA. A hole HL can be disposed in the active area AA. The hole HL can be formed to correspond to a position of a camera module of the display device.

[0129] The display panel 100 may include multiple gate layers GAT1, GAT2 and GAT3 and multiple source-drain layers SD1 and SD2. The multiple gate layers GAT1, GAT2 and GAT3 include gate patterns extending in a first direction D1, and the multiple source-drain layers SD1 and SD2 include source-drain patterns extending in a second direction D2.

[0130] The display panel 100 includes: a substrate layer PI, a barrier layer BR disposed on the substrate layer PI, a first gate insulating layer GI1 disposed on the barrier layer BR, a first gate layer GAT1 disposed on the first gate insulating layer GI1, a second gate insulating layer GI2 disposed on the first gate layer GAT1 and / or the first gate insulating layer GI1, a second gate layer GAT2 disposed on the second gate insulating layer GI2, a first passivation layer ILD1 disposed on the second gate layer GAT2 and / or the second gate insulating layer GI2, a third gate layer GAT3 disposed on the first passivation layer ILD1, a second passivation layer ILD2 disposed on the third gate layer GAT3 and / or the first passivation layer ILD1, a first source-drain layer SD1 disposed on the second passivation layer ILD2, a first organic insulating layer VIA1 disposed on the first source-drain layer SD1 and / or the second passivation layer ILD2, a second source-drain layer SD2 disposed on the first organic insulating layer VIA1, and a second organic insulating layer VIA2 disposed on the second source-drain layer SD2 and / or the first organic insulating layer VIA1.

[0131] like Figure 11 As shown, the display panel 100 may further include a third organic insulating layer VIA3 disposed only in the area around the hole and disposed between the second gate insulating layer GI2 and the second gate layer GAT2.

[0132] The first organic insulating layer VIA1, the second organic insulating layer VIA2, and the third organic insulating layer VIA3 may comprise organic insulating materials. The thicknesses of the first organic insulating layer VIA1, the second organic insulating layer VIA2, and the third organic insulating layer VIA3 may be greater than the thicknesses of the first gate insulating layer GI1 and the second gate insulating layer GI2. The thicknesses of the first organic insulating layer VIA1, the second organic insulating layer VIA2, and the third organic insulating layer VIA3 may be greater than the thicknesses of the first passivation layer ILD1 and the second passivation layer ILD2. The thickness of the first organic insulating layer VIA1 may be between approximately 1.5 μm and approximately 2 μm. The thickness of the second organic insulating layer VIA2 may be between approximately 1.5 μm and approximately 2 μm. The thickness of the third organic insulating layer VIA3 may be between approximately 1.5 μm and approximately 2 μm.

[0133] In the illustrated example embodiment, in the hole surrounding area, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 can overlap each other in the thickness direction. Thus, a dead zone due to the hole HL can be reduced in the hole surrounding area.

[0134] The first gate layer GAT1 and the second gate layer GAT2 can output gate signals having different waveforms. In this case, it can be desirable to reduce or prevent coupling between the first gate layer GAT1 and the second gate layer GAT2. Thus, when the first gate layer GAT1 and the second gate layer GAT2 overlap each other in the thickness direction, coupling between the first gate layer GAT1 and the second gate layer GAT2 can occur. Thus, as illustrated in FIG. 1, the third organic insulating layer VIA3 can be formed between the first gate layer GAT1 and the second gate layer GAT2 so that coupling between the first gate layer GAT1 and the second gate layer GAT2 can be prevented or reduced. In one or more example embodiments, the third organic insulating layer VIA3 has a thickness sufficient to prevent or substantially prevent coupling between the first gate layer GAT1 and the second gate layer GAT2. Figure 11

[0135] According to the illustrated example embodiment, when the hole HL is formed in the active area AA of the display panel 100, and the patterns on the gate layers GAT1, GAT2, and GAT3 and the patterns on the source-drain layers SD1 and SD2 bypass the hole HL at the hole surrounding area, the patterns on the gate layers GAT1, GAT2, and GAT3 and the patterns on the source-drain layers SD1 and SD2 overlap each other in the thickness direction so that a dead zone adjacent to the hole surrounding area can be reduced.

[0136] Figure 12 is a cross-sectional view illustrating a hole surrounding area of a display panel according to an example embodiment of the present inventive concept.

[0137] The display panel according to the illustrated example embodiment and the display device including the same are substantially the same as or similar to the display panel and the display device including the same described with reference to Figures 1 to 9 The display panel and the display device including the same of the previous example embodiment described with reference to Figures 1 to 9 will be used to refer to parts that are the same as or similar to those described in the previous example embodiment, and any repetitive or redundant description regarding the above-described elements can be omitted.

[0138] With reference to Figures 1 to 8 and Figure 12 , the display device includes the display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.​

[0139] The display panel 100 includes an active area AA in which an image is displayed, and a peripheral area PA surrounding the active area AA. The hole HL can be arranged in the active area AA. The hole HL can be formed to correspond to a position of a camera module of the display device.

[0140] The display panel 100 can include a plurality of gate layers GAT1, GAT2, and GAT3 including a gate pattern extending in a first direction D1, and a plurality of source-drain layers SD1 and SD2 including a source-drain pattern extending in a second direction D2.

[0141] The display panel 100 includes a base layer PI, a barrier layer BR arranged on the base layer PI, a first gate insulating layer GI1 arranged on the barrier layer BR, a first gate layer GAT1 arranged on the first gate insulating layer GI1, a second gate insulating layer GI2 arranged on the first gate layer GAT1 and / or the first gate insulating layer GI1, a second gate layer GAT2 arranged on the second gate insulating layer GI2, a first passivation layer ILD1 arranged on the second gate layer GAT2 and / or the second gate insulating layer GI2, a third gate layer GAT3 arranged on the first passivation layer ILD1, a second passivation layer ILD2 arranged on the third gate layer GAT3 and / or the first passivation layer ILD1, a first source-drain layer SD1 arranged on the second passivation layer ILD2, a first organic insulating layer VIA1 arranged on the first source-drain layer SD1 and / or the second passivation layer ILD2, a second source-drain layer SD2 arranged on the first organic insulating layer VIA1, and a second organic insulating layer VIA2 arranged on the second source-drain layer SD2 and / or the first organic insulating layer VIA1.

[0142] As shown in FIG. 1A, the second gate layer GAT2 can overlap the third gate layer GAT3 in the thickness direction in the normal area, and the first gate layer GAT1 can not overlap the second gate layer GAT2 and the third gate layer GAT3 in the thickness direction in the normal area. Figure 8 As shown in FIG. 1A, the second gate layer GAT2 can overlap the third gate layer GAT3 in the thickness direction in the normal area, and the first gate layer GAT1 can not overlap the second gate layer GAT2 and the third gate layer GAT3 in the thickness direction in the normal area.

[0143] As shown in FIG. 1A, the second gate layer GAT2 can overlap the third gate layer GAT3 in the thickness direction in the normal area, and the first gate layer GAT1 can not overlap the second gate layer GAT2 and the third gate layer GAT3 in the thickness direction in the normal area. Figure 12 As shown in FIG. 1A, the second gate layer GAT2 can overlap the third gate layer GAT3 in the thickness direction in the normal area, and the first gate layer GAT1 can not overlap the second gate layer GAT2 and the third gate layer GAT3 in the thickness direction in the normal area.

[0144] In the example embodiment shown, in the hole surrounding area, the second gate layer GAT2, the third gate layer GAT3, the first source-drain layer SD1, and the second source-drain layer SD2 can overlap each other in the thickness direction. Thus, a dead zone due to the hole HL can be reduced in the hole surrounding area.

[0145] The first gate layer GAT1 and the second gate layer GAT2 output gate signals having different waveforms. In this case, it can be desirable to prevent or reduce coupling between the first gate layer GAT1 and the second gate layer GAT2. In the illustrated example embodiment, the pattern on the first gate layer GAT1 and the pattern on the second gate layer GAT2 can be alternately arranged such that a distance between the pattern on the first gate layer GAT1 and the pattern on the second gate layer GAT2 can be greater than a distance between the pattern on the first gate layer GAT1 and the pattern on the second gate layer GAT2 in the vertical overlapping structure in Figure 9 . Thus, coupling between the first gate layer GAT1 and the second gate layer GAT2 can be prevented or reduced.

[0146] According to the illustrated example embodiment, when the hole HL is formed in the active area AA of the display panel 100, and the patterns on the gate layers GAT1, GAT2, and GAT3 and the patterns on the source-drain layers SD1 and SD2 bypass the hole HL at the hole surrounding area, the patterns on the gate layers GAT2 and GAT3 and the patterns on the source-drain layers SD1 and SD2 partially overlap each other in the thickness direction, so that a dead zone adjacent to the hole surrounding area can be reduced.

[0147] Figure 13 is a conceptual view illustrating a pixel structure of a display panel according to an example embodiment of the present inventive concept. Figure 14 is a cross-sectional view illustrating a hole surrounding area of the display panel of Figure 13 .

[0148] The display panel according to the illustrated example embodiment and a display device including the display panel are substantially the same as the display panel and the display device of the previous example embodiment described with reference to Figures 1 to 9 , except for the pixel structure of the display panel and the layer structure of the display panel in the hole surrounding area. Thus, the same reference numerals will be used to refer to parts that are the same as or similar to those described in the previous example embodiment of Figures 1 to 9 , and any repetitive or redundant description regarding the above-described elements can be omitted.

[0149] The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600. Figures 1 to 3 Figure 5 Figure 8 Figure 13 Figure 14 , the display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0150] ​​​​The display panel 100 includes an active area AA in which an image is displayed, and a peripheral area PA surrounding the active area AA. A hole HL can be arranged in the active area AA. The hole HL can be formed to correspond to a position of a camera module of the display device.

[0151] The display panel 100 can include a plurality of gate layers GAT1, GAT2, and GAT3 including a gate pattern extending in a first direction D1, and a source-drain layer SD1 including a source-drain pattern extending in a second direction D2.

[0152] The display panel 100 includes a base layer PI, a barrier layer BR arranged on the base layer PI, a first gate insulating layer GI1 arranged on the barrier layer BR, a first gate layer GAT1 arranged on the first gate insulating layer GI1, a second gate insulating layer GI2 arranged on the first gate layer GAT1 and / or the first gate insulating layer GI1, a second gate layer GAT2 arranged on the second gate insulating layer GI2, a first passivation layer ILD1 arranged on the second gate layer GAT2 and / or the second gate insulating layer GI2, a third gate layer GAT3 arranged on the first passivation layer ILD1, a second passivation layer ILD2 arranged on the third gate layer GAT3 and / or the first passivation layer ILD1, a source-drain layer SD1 arranged on the second passivation layer ILD2, and an organic insulating layer VIA1 arranged on the source-drain layer SD1 and / or the second passivation layer ILD2.

[0153] As shown in FIG. 1A, the display panel 100 includes a plurality of pixels arranged in a matrix form. Figure 13

[0154] In the example embodiment shown, the pixels in a pixel column can be connected to a single data line adjacent to the pixel column.

[0155] For example, the pixels P11, P21, P31, and P41 arranged in a first pixel column of the display panel 100 can be connected to a first data line DL1. For example, the pixels P12, P22, P32, and P42 arranged in a second pixel column of the display panel 100 can be connected to a second data line DL2. For example, the pixels P13, P23, P33, and P43 arranged in a third pixel column of the display panel 100 can be connected to a third data line DL3. For example, the pixels P14, P24, P34, and P44 arranged in a fourth pixel column of the display panel 100 can be connected to a fourth data line DL4.

[0156] Figure 14 The source-drain layer SD1 of the display panel 100 can include the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4.

[0157] ​In the example embodiment shown, in the hole surrounding region, the first gate layer GAT1, the second gate layer GAT2, the third gate layer GAT3, and the source-drain layer SD1 can overlap each other in the thickness direction. Thus, a dead zone due to the hole HL can be reduced in the hole surrounding region.

[0158] According to the example embodiment shown, when the hole HL is formed in the active area AA of the display panel 100, and the patterns on the gate layers GAT1, GAT2, and GAT3 and the pattern on the source-drain layer SD1 bypass the hole HL at the hole surrounding region, the patterns on the gate layers GAT1, GAT2, and GAT3 and the pattern on the source-drain layer SD1 overlap each other in the thickness direction, so that a dead zone adjacent to the hole surrounding region can be reduced.

[0159] According to aspects of the example embodiments of the inventive concepts as described above, a dead zone of a hole surrounding region in an active area of a display panel can be reduced.

[0160] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of example embodiments described herein.

[0161] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0162] It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0163] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0164] Further, the use of "may" when describing example embodiments of the present disclosure relates to "one or more example embodiments of the present disclosure."

[0165] It will be understood that when a component is referred to as being "on" another component, "connected to" another component, or "coupled to" another component, it can be directly on, directly connected, or directly coupled to the other component, or one or more intervening components can also be present. When a component is referred to as being "directly on," "directly connected to," or "directly coupled to" another component, there are no intervening components present.

[0166] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0167] Any numerical range recited herein is intended to include all sub-ranges of the same entire number precision, i.e. one having the same number of decimal places as the numerical range recited. As an example, a range from 1.0 to 10.0 is intended to include from 1.0 to 10.0, 1.1 to 9.9, 1.2 to 9.8 etc. as essentially the same numerical range even though the interval representations are different. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, it is intended that the application be construed broadly and be given a full range of equivalents.

[0168] The term "use" and variations thereof, as used herein, can be taken in its broadest possible context as being synonymous with the term "utilize" and variations thereof, respectively.

[0169] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0170] As used herein, a phrase such as "plan view" can refer to a view from the top or from a direction normal to a display surface of a display panel. A "thickness direction" can refer to a direction normal or perpendicular to a display surface of a display panel.

[0171] The foregoing is a summary of the inventive concept and is not to be construed as limiting the inventive concept. Although certain example embodiments of the inventive concept have been described, it will be apparent to those skilled in the art that many modifications are possible without departing from the inventive concept in its broader aspects. Accordingly, the entire disclosure of the application is intended to include all such modifications and will be construed as such. It is to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments will be apparent to those of skill in the art upon reading the above description. The scope of the application should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with their full scope of equivalents. The inventive concept is defined by the following claims and their equivalents.

Claims

1. A display panel comprising: a first gate layer including a plurality of gate patterns extending in a first direction; a second gate layer including a plurality of gate patterns extending in the first direction; and a first source-drain layer including a plurality of source-drain patterns extending in a second direction intersecting the first direction, wherein the gate patterns of the first gate layer and the gate patterns of the second gate layer are curled or bent along a hole-surrounding region corresponding to a periphery of a hole in an effective region, wherein the source-drain patterns of the first source-drain layer are curled or bent along the hole-surrounding region, and wherein in the hole-surrounding region, the gate patterns of the first gate layer, the gate patterns of the second gate layer, and the source-drain patterns of the first source-drain layer overlap with each other in a thickness direction of the display panel. The display panel further includes a first gate insulating layer, a second gate insulating layer, a first passivation layer, and a third gate layer, wherein:

2. The display panel of claim 1, wherein, the first gate layer is on the first gate insulating layer; the second gate insulating layer is on the first gate layer; the second gate layer is on the second gate insulating layer; the first passivation layer is on the second gate layer; and the third gate layer is on the first passivation layer. In a normal region that is not the hole-surrounding region, the second gate layer overlaps with the third gate layer in the thickness direction, and 3. The display panel of claim 2, wherein, wherein in the normal region, the first gate layer does not overlap with the second gate layer and the third gate layer in the thickness direction. In the hole-surrounding region, the first gate layer, the second gate layer, and the third gate layer overlap with each other in the thickness direction.

4. The display panel of claim 3, wherein, The display panel further includes an organic insulating layer in the hole-surrounding region and between the second gate insulating layer and the second gate layer.

5. The display panel of claim 4, wherein, In the hole-surrounding region, the second gate layer overlaps with the third gate layer in the thickness direction, and 6. The display panel of claim 3, wherein, wherein in the hole-surrounding region, the first gate layer does not overlap with the second gate layer and the third gate layer in the thickness direction. A pixel including a P-type transistor and an N-type transistor.

7. The display panel of claim 3, further comprising: The first gate layer includes a P-type gate line configured to transmit a P-type gate signal to the P-type transistor, 8. The display panel of claim 7, wherein, wherein the second gate layer includes a back gate electrode of the P-type transistor or the N-type transistor and a connection line of the back gate electrode, and wherein the third gate layer includes an N-type gate line configured to transmit an N-type gate signal to the N-type transistor. The display panel further includes a first organic insulating layer, a second organic insulating layer, and a second source-drain layer, wherein:

9. The display panel of claim 1, wherein, the first organic insulating layer is on the first source-drain layer; the second source-drain layer is on the first organic insulating layer; and the second organic insulating layer is on the second source-drain layer. In a normal region that is not the hole-surrounding region, 10. The display panel of claim 9, wherein, the first source-drain layer does not overlap with the second source-drain layer in the thickness direction. ​

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